CN113594254B - LDMOS device structure for improving transconductance - Google Patents
LDMOS device structure for improving transconductance Download PDFInfo
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- CN113594254B CN113594254B CN202110862381.4A CN202110862381A CN113594254B CN 113594254 B CN113594254 B CN 113594254B CN 202110862381 A CN202110862381 A CN 202110862381A CN 113594254 B CN113594254 B CN 113594254B
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- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
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- 206010063385 Intellectualisation Diseases 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
Abstract
The application relates to the technical field of semiconductor integrated circuit manufacturing, in particular to an LDMOS device structure for improving transconductance. The LDMOS device structure for improving transconductance comprises: a substrate layer in which laterally adjacent channel regions and drift regions are formed, the channel regions and the drift regions each extending downward from an upper surface of the substrate layer; the first end part and the second end part of the gate structure are respectively overlapped with the channel region and the drift region; forming a first drain end doping region on one side of the drift region far away from the channel region, forming a first field oxide layer at the position of the drift region between the first drain end doping region and the second end part of the gate structure, wherein the second end part is overlapped with the first field oxide layer; forming a source end doping region in the channel region at a position close to the first end of the gate structure; a voltage-withstand-improving region is formed in the base layer at a position below the drift region, and the voltage-withstand-improving region is in longitudinal contact with the drift region.
Description
Technical Field
The application relates to the technical field of semiconductor integrated circuit manufacturing, in particular to an LDMOS device structure for improving transconductance.
Background
The high-voltage LDMOS (lateral diffusion MOS, lateral Diffuse MOS) device not only has the characteristic of high voltage and high current of a discrete device, but also draws the advantage of high-density intelligent logic control of a low-voltage integrated circuit, and the single chip realizes the function which can be finished by a plurality of chips, so that the area is greatly reduced, the cost is reduced, the energy efficiency is improved, and the device meets the development direction of miniaturization, intellectualization and low energy consumption of modern power electronic devices.
In the related art, in order to improve the withstand voltage of the LDMOS device, a scheme of reducing the doping concentration of the epitaxial layer or increasing the length and depth of the drift region is adopted to increase the on-resistance of the device while improving the breakdown voltage of the device. However, as the depth of the drift region of the device increases, the transconductance of the device is compressed, resulting in the problem of insufficient saturation current of the device.
Disclosure of Invention
The application provides an LDMOS device structure for improving transconductance, which can solve the problem that the saturation current of a device is insufficient due to the fact that the depth of a drift region is large in the related art and the transconductance of the device is compressed.
In order to solve the technical problem described in the background art, the present application provides an LDMOS device structure for improving transconductance, where the LDMOS device structure for improving transconductance includes:
a base layer in which laterally adjacent channel and drift regions are formed, the channel and drift regions each extending downwardly from an upper surface of the base layer;
a gate structure bridging between the channel region and the drift region along the surface of the substrate layer, wherein the first end and the second end of the gate structure overlap with the channel region and the drift region respectively;
forming a first drain doped region on one side of the drift region far away from the channel region, and forming a first field oxide layer at the position of the drift region between the first drain doped region and a second end part of the gate structure, wherein the second end part is overlapped with the first field oxide layer;
forming a source end doping region in the channel region at a position close to the first end of the gate structure;
and a pressure resistance improving region is formed in the substrate layer at a position below the drift region, and the pressure resistance improving region is longitudinally contacted with the drift region.
Optionally, a high voltage isolation region is also formed in the substrate layer;
the high-voltage isolation region is positioned at the other side of the drift region relative to the channel region and is used for isolating the LDMOS device.
Optionally, a second drain doped region is formed in the high voltage isolation region.
Optionally, a second field oxide layer is formed in the substrate layer between the second drain doped region and the first drain doped region.
Optionally, the high-voltage isolation region extends downwards from the upper surface of the substrate layer, and the lower end of the high-voltage isolation region is connected with a buried layer of a first conductivity type;
the first conductivity type buried layer extends laterally in the base layer;
and the laterally extending buried layer of the first conductivity type and the longitudinally extending high-voltage isolation region semi-surround the LDMOS device structure.
Optionally, the high voltage isolation region is of the first conductivity type.
Optionally, the drift region is of the first conductivity type, and the doping concentration in the drift region is in the range of 1e17cm -3 ～1e18cm -3 。
Optionally, the voltage-withstand-voltage-improving region is of the second conductivity type, and the doping concentration in the voltage-withstand-improving region is in the range of 5e17cm -3 ～5e18cm -3 。
Optionally, the drift region is in the base layer and the first depth extending in the longitudinal direction is 0.6 micrometers to 1.0 micrometers.
Optionally, the pressure-resistance improving region is in the base layer at a second depth extending in the longitudinal direction of 1.4 micrometers to 3.0 micrometers.
The technical scheme of the application at least comprises the following advantages: a voltage-resistant improving region is formed in a substrate layer at a position below a drift region, so that the voltage-resistant improving region is in contact with the drift region in the longitudinal direction, the lateral length of the drift region is not changed, the voltage-resistant performance of a device is ensured, the depth of the drift region is thinned in the longitudinal direction, the transconductance of the LDMOS device is improved, and the saturation current of the device is increased.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 illustrates an LDMOS device structure with improved transconductance provided by an embodiment of the present application;
fig. 2 shows a transconductance variation curve of an LDMOS device provided by the related art;
fig. 3 shows a transconductance variation curve of the LDMOS device provided in the present application.
Detailed Description
The following description of the embodiments of the present application will be made apparent and complete in conjunction with the accompanying drawings, in which embodiments described are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
In the description of the present application, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of description of the present application and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, or can be communicated inside the two components, or can be connected wirelessly or in a wired way. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context.
In addition, the technical features described below in the different embodiments of the present application may be combined with each other as long as they do not collide with each other.
Fig. 1 shows an LDMOS device structure for improving transconductance according to an embodiment of the present application, and as can be seen from fig. 1, the LDMOS device structure for improving transconductance includes:
a base layer 100, a laterally adjacent channel region 110 and drift region 120 are formed in the base layer 100, the channel region 110 and drift region 120 each extending downwardly from an upper surface of the base layer 100. The X-direction shown in fig. 1 is lateral and the Y-direction is longitudinal, with the channel region 110 and drift region 120 each extending downward a specified depth in the substrate layer 100 along the Y-direction. Alternatively, the channel region 110 and the drift region 120 may be connected at intervals, i.e., the channel region 110 and the drift region 120 are spaced apart as shown in fig. 1.
A gate structure 130, the gate structure 130 bridging between the channel region 110 and the drift region 120 along the surface of the substrate layer 100, and a first end 131 of the gate structure 130 overlapping the channel region 110, and a second end 132 of the gate structure 130 overlapping the drift region 120. Wherein the first overlapping portion 111 of the first end 131 and the channel region 110 is used to form a conductive channel of the LDMOS device. The gate structure 130 leads out of the gate 230 of the LDMOS device.
In the drift region 120, a first drain doped region 141 is formed on a side away from the channel region 110, i.e., the first drain doped region 141 is formed on a right portion of the drift region 120 as shown in fig. 1, and the channel region 110 is located in the base layer 100 on an X left side of the drift region 120.
A first field oxide layer 151 is formed at the location of the drift region 120 between the first drain doped region 141 and the second end 132 of the gate structure 130, the second end 132 overlapping the first field oxide layer 151. In this embodiment, the first field oxide layer 151 is located in the drift region 120 and extends downward along the Y direction from the upper surface of the drift region 120, and the depth of the first field oxide layer 151 extending longitudinally in the drift region 120 is smaller than the depth of the drift region 120 extending longitudinally in the substrate layer 100. Since the second end portion 132 is partially overlapped with the first field oxide layer 151, the second end portion 132 of the gate structure 130 is connected to the first drain doped region 141 through the first field oxide layer 151.
In the channel region 110 near the first end 131 of the gate structure 130, a source-doped region 160 is formed, optionally, an edge of the first end 131 overlaps an edge of the source-doped region 160, and the overlapping edge serves as a boundary between the first end 131 and the source-doped region 160. So that the source-side doped region 160 laterally adjoins the first overlap 111 between the first end 131 and the channel region 110 at the boundary location. In this embodiment, the source doped region 160 is further adjacent to a body doped region 170, the body doped region 170 and the first overlapping portion 111 are respectively located at two opposite sides of the source doped region 160, and the body doped region 170 is also located in the channel region 110. The source-side doped region 160 and the body-side doped region 170 lead out of the source 210 of the LDMOS device, which is connected to the body and source sides.
In the base layer 100 at a position below the drift region 120, a withstand voltage improving region 180 is formed, and the withstand voltage improving region 180 is in longitudinal contact with the drift region 120.
The drift region in the related art has deeper depth and small doping concentration, so that the transconductance of the device is smaller, and the saturation current is insufficient, if the drift region concentration is increased or the drift region thickness is thinned, the breakdown voltage of the device is not high enough, and the working withstand voltage requirement of the device cannot be met.
In this embodiment, the voltage-withstand-improving region is formed in the substrate layer at a position below the drift region, so that the voltage-withstand-improving region is in contact with the drift region in the longitudinal direction, so that the depth of the drift region is thinned in the longitudinal direction while the lateral length of the drift region is not changed and the voltage-withstand performance of the device is ensured, and the voltage-withstand-improving region is used for improving the transconductance of the LDMOS device and increasing the saturation current of the device.
Alternatively, the drift region 120 extends longitudinally downward from the upper surface of the base layer 100 by a first depth D1 in the range of 0.6 micrometers to 1.0 micrometers, and the withstand voltage improving region 180 extends longitudinally by a second depth D2 in the range of 1.4 micrometers to 3.0 micrometers.
Taking an N-type LDMOS as an example, the first conductivity type is N-type, and the second conductivity type is P-type. So that the conductivity type of the base layer 100 shown in fig. 1 is P-typeThe conductivity type of the channel region 110 is P-type, the conductivity type of the drift region 120 is N-type, the conductivity type of the voltage withstand enhancement region 180 is P-type, the conductivity type of the first drain doped region 141 is N-type, the conductivity type of the source doped region 160 is N-type, and the conductivity type of the body doped region 170 is P-type. Wherein the doping concentration in the drift region 120 is in the range of 1e17cm -3 ～1e18cm -3 The doping concentration in the voltage-withstand voltage-improving region is in the range of 5e17cm -3 ～5e18cm -3 . For the P-type LDMOS, the channel region 110, the drift region 120, the withstand voltage improving region 180, the first drain-side doped region 141, the source-side doped region 160, and the body-side doped region 170 shown in fig. 1 are opposite to the conductivity type of the N-type LDMOS. Wherein the P-type and the N-type are opposite conductive types to each other.
With continued reference to fig. 1, the substrate layer 100 may include a bottom layer 101 and an epitaxial layer 102 sequentially stacked from bottom to top in a longitudinal direction, i.e., a Y direction as shown in fig. 1, and a buried layer 103 may be formed by a doping process at an interface position of the bottom layer 101 and the epitaxial layer 102. Taking an N-type LDMOS as an example, the conductivity type of the buried layer 103 is N-type. The LDMOS device described above is located in the epitaxial layer 102, i.e. the channel region 110, the drift region 120 and the withstand voltage improving region 180 are all located in the epitaxial layer 102.
A high voltage isolation region 190 is also formed in the epitaxial layer 102. The high voltage isolation region 190 is located on the other side of the drift region 120 with respect to the channel region 110 for isolating the LDMOS device. As can be seen in fig. 1, the high voltage isolation region 190 and the channel region 110 are located to the right and left, respectively, of the X of the drift region 120. The high voltage isolation region 190 extends in the longitudinal direction and is in contact with the buried layer 103 in the longitudinal direction such that the high voltage isolation region 190 and the buried layer 103 semi-surround the LDMOS device structure, thereby isolating the LDMOS device structure from adjacent other devices.
In this embodiment, the high voltage isolation region 190 has an N-type conductivity, and may include a first N-type well region 191 and a second N-type well region 192, where the first N-type well region 191 extends downward from the upper surface of the substrate layer 100 to be in contact with the buried layer 103. The second N-type well region 192 is formed in the first N-type well region 191 and extends downward from the upper surface of the first N-type well region 191, and the depth of the second N-type well region 192 in the longitudinal direction is smaller than the depth of the first N-type well region 191 in the longitudinal direction. The second N-type well region 192 is formed with a second drain doped region 142 by heavily doping an N-type impurity, and the second field oxide layer 152 is formed in the base layer 200 between the second drain doped region 142 and the first drain doped region 141. As can be seen from fig. 1, the second field oxide layer 152 sequentially passes through the drift region 120, the first N-type well region 191 and the second N-type well region 192 from the position of the first drain doped region 141 until being in contact with the second drain doped region 142.
The first drain doped region 141 and the second drain doped region 142 collectively lead out of the drain 230 of the LDMOS device.
Fig. 2 shows a transconductance variation curve of an LDMOS device provided by the related art, and it can be seen from fig. 2 that the LDMOS device has a smaller transconductance.
Fig. 3 shows a transconductance variation curve of the LDMOS device provided by the present application, and as can be seen from fig. 3, the transconductance of the LDMOS device provided by the present application is larger, which can solve the problem that the depth of a drift region is larger in the related art, so that the transconductance of the device is compressed, thereby resulting in insufficient saturation current of the device.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While nevertheless, obvious variations or modifications may be made to the embodiments described herein without departing from the scope of the invention.
Claims (6)
1. An LDMOS device structure for improving transconductance, comprising:
a base layer in which laterally adjacent channel and drift regions are formed, the channel and drift regions each extending downwardly from an upper surface of the base layer;
a gate structure bridging between the channel region and the drift region along the surface of the substrate layer, wherein the first end and the second end of the gate structure overlap with the channel region and the drift region respectively;
forming a first drain doped region on one side of the drift region far away from the channel region, and forming a first field oxide layer at the position of the drift region between the first drain doped region and a second end part of the gate structure, wherein the second end part is overlapped with the first field oxide layer;
forming a source end doping region in the channel region at a position close to the first end of the gate structure;
a pressure resistance improving region is formed in the substrate layer at the position below the drift region, and the pressure resistance improving region is in longitudinal contact with the drift region;
the drift region is of a first conductivity type, and the doping concentration in the drift region is in the range of 1e17cm -3 ～1e18cm -3 ；
The voltage-resistant enhancement region is of the second conductivity type, and the doping concentration in the voltage-resistant enhancement region is in the range of 5e17cm -3 ～5e18cm -3 ；
The drift region is in the base layer and has a first depth extending longitudinally of 0.6 microns to 1.0 microns;
the pressure-resistance improving region is in the base layer and has a second depth extending in the longitudinal direction of 1.4 micrometers to 3.0 micrometers.
2. The improved transconductance LDMOS device structure of claim 1, wherein a high voltage isolation region is also formed in said base layer;
the high-voltage isolation region is positioned at the other side of the drift region relative to the channel region and is used for isolating the LDMOS device.
3. The LDMOS device structure of claim 2, wherein the second drain-doped region is formed in the high-voltage isolation region.
4. The LDMOS device structure of claim 3, wherein a second field oxide layer is formed in the substrate layer between the second drain-doped region and the first drain-doped region.
5. The LDMOS device structure of claim 2, wherein the high-voltage isolation region extends downward from the upper surface of the substrate layer, and a buried layer of the first conductivity type is connected to the lower end of the high-voltage isolation region;
the first conductivity type buried layer extends laterally in the base layer;
and the laterally extending buried layer of the first conductivity type and the longitudinally extending high-voltage isolation region semi-surround the LDMOS device structure.
6. The LDMOS device structure of claim 5, wherein the high-voltage isolation region is of a first conductivity type.
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