CN113594254A - LDMOS device structure for improving transconductance - Google Patents
LDMOS device structure for improving transconductance Download PDFInfo
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- CN113594254A CN113594254A CN202110862381.4A CN202110862381A CN113594254A CN 113594254 A CN113594254 A CN 113594254A CN 202110862381 A CN202110862381 A CN 202110862381A CN 113594254 A CN113594254 A CN 113594254A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
Abstract
The application relates to the technical field of semiconductor integrated circuit manufacturing, in particular to an LDMOS device structure for improving transconductance. The LDMOS device structure for improving transconductance comprises: the substrate layer is internally provided with a channel region and a drift region which are transversely adjacent, and the channel region and the drift region both extend downwards from the upper surface of the substrate layer; the gate structure is bridged between the channel region and the drift region along the surface of the substrate layer, and a first end part and a second end part of the gate structure are respectively overlapped with the channel region and the drift region; forming a first drain end doped region on one side, far away from the channel region, of the drift region, forming a first field oxide layer at the position of the drift region between the first drain end doped region and the second end part of the gate structure, wherein the second end part is overlapped with the first field oxide layer; forming a source end doped region in the channel region at a position close to the first end of the gate structure; a withstand voltage improving region is formed in the base layer at a position below the drift region, and the withstand voltage improving region is in longitudinal contact with the drift region.
Description
Technical Field
The application relates to the technical field of semiconductor integrated circuit manufacturing, in particular to an LDMOS device structure for improving transconductance.
Background
The high-voltage LDMOS (laterally diffused MOS) device has the characteristics of high voltage and high current of discrete devices, draws the advantage of high-density intelligent logic control of a low-voltage integrated circuit, realizes the functions which can be completed by a plurality of chips originally by a single chip, greatly reduces the area, reduces the cost, improves the energy efficiency, and accords with the development direction of miniaturization, intellectualization and low energy consumption of modern power electronic devices.
In the related art, in order to improve the withstand voltage of the LDMOS device, a scheme of reducing the doping concentration of an epitaxial layer or increasing the length and the depth of a drift region is adopted to improve the breakdown voltage of the device and increase the on-resistance of the device at the same time. However, as the depth of the drift region of the device is increased, the transconductance of the device is compressed, so that the saturation current of the device is insufficient.
Disclosure of Invention
The application provides an LDMOS device structure capable of improving transconductance, which can solve the problem that in the related technology, the depth of a drift region is large, so that the transconductance of a device is compressed, and the saturation current of the device is insufficient.
In order to solve the technical problems described in the background art, the present application provides an LDMOS device structure with improved transconductance, which includes:
a base layer in which laterally adjacent channel and drift regions are formed, both extending downwardly from an upper surface of the base layer;
the gate structure is bridged between the channel region and the drift region along the surface of the substrate layer, and a first end part and a second end part of the gate structure are respectively overlapped with the channel region and the drift region;
forming a first drain terminal doped region on one side of the drift region far away from the channel region, and forming a first field oxide layer at the position of the drift region between the first drain terminal doped region and a second end part of the gate structure, wherein the second end part is overlapped with the first field oxide layer;
forming a source end doped region in the channel region at a position near a first end of the gate structure;
and a withstand voltage improving region is formed in the substrate layer at a position below the drift region, and the withstand voltage improving region is in longitudinal contact with the drift region.
Optionally, a high voltage isolation region is further formed in the base layer;
the high-voltage isolation region is located on the other side, opposite to the channel region, of the drift region and is used for isolating the LDMOS device.
Optionally, a second drain doped region is formed in the high voltage isolation region.
Optionally, a second field oxide layer is formed in the substrate layer between the second drain doped region and the first drain doped region.
Optionally, the high-voltage isolation region extends downward from the upper surface of the substrate layer, and a lower end of the high-voltage isolation region is connected with a first conductivity type buried layer;
the first-conductivity-type buried layer extends laterally in the base layer;
the laterally extending first conduction type buried layer and the longitudinally extending high-voltage isolation region are used for semi-surrounding the LDMOS device structure.
Optionally, the high voltage isolation region is of a first conductivity type.
Optionally, the drift region is of the first conductivity type, and the doping concentration in the drift region is in a range of 1e17cm-3～1e18cm-3。
Optionally, the withstand voltage improving region is of the second conductivity type, and a doping concentration range in the withstand voltage improving region is 5e17cm-3～5e18cm-3。
Optionally, the drift region is in the base layer and has a first depth extending in the longitudinal direction of 0.6 to 1.0 micron.
Optionally, the withstand voltage improving region is in the base layer, and the second depth extending in the longitudinal direction is 1.4 micrometers to 3.0 micrometers.
The technical scheme at least comprises the following advantages: by forming the withstand voltage improving region in the substrate layer at the position below the drift region, the withstand voltage improving region is in contact with the drift region in the longitudinal direction, so that the transverse length of the drift region is not changed, the withstand voltage performance of the device is guaranteed, and meanwhile, the depth of the drift region is reduced in the longitudinal direction, the transconductance of the LDMOS device is improved, and the saturation current of the device is increased.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 illustrates an LDMOS device structure with improved transconductance according to an embodiment of the present application;
fig. 2 shows a transconductance variation curve of an LDMOS device provided in the related art;
fig. 3 shows a transconductance variation curve of the LDMOS device provided by the present application.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Fig. 1 illustrates an LDMOS device structure with improved transconductance according to an embodiment of the present application, and as can be seen from fig. 1, the LDMOS device structure with improved transconductance includes:
the semiconductor device includes a substrate layer 100, a channel region 110 and a drift region 120 are formed in the substrate layer 100, and the channel region 110 and the drift region 120 extend downward from an upper surface of the substrate layer 100. The channel region 110 and the drift region 120 in the substrate layer 100 each extend downward in the Y direction by a certain depth, with the X direction being the lateral direction and the Y direction being the longitudinal direction as shown in fig. 1. Alternatively, the channel region 110 and the drift region 120 may be connected with a space, that is, the channel region 110 and the drift region 120 are spaced apart from each other as shown in fig. 1.
A gate structure 130, the gate structure 130 bridging between the channel region 110 and the drift region 120 along the surface of the substrate layer 100, wherein a first end 131 of the gate structure 130 overlaps the channel region 110 and a second end 132 of the gate structure 130 overlaps the drift region 120. Wherein the first end portion 131 and the first overlapping portion 111 of the channel region 110 are used for forming a conductive channel of an LDMOS device. The gate structure 130 leads out the gate 230 of the LDMOS device.
In the drift region 120, a first drain doping region 141 is formed on a side of the drift region 120 away from the channel region 110, that is, as shown in fig. 1, the first drain doping region 141 is formed on a right portion of the drift region 120, and the channel region 110 is located in the substrate layer 100 on the X-direction left side of the drift region 120.
A first field oxide layer 151 is formed at the drift region 120 between the first drain-side doped region 141 and the second end 132 of the gate structure 130, and the second end 132 overlaps the first field oxide layer 151. In the embodiment, the first field oxide layer 151 is located in the drift region 120 and extends downward from the upper surface of the drift region 120 along the Y direction, and the depth of the first field oxide layer 151 extending longitudinally in the drift region 120 is smaller than the depth of the drift region 120 extending longitudinally in the substrate layer 100. Since the second end portion 132 is partially overlapped with the first field oxide layer 151, the second end portion 132 of the gate structure 130 is connected to the first drain doped region 141 through the first field oxide layer 151.
A source doped region 160 is formed in the channel region 110 at a position close to the first end 131 of the gate structure 130, and optionally, an edge of the first end 131 overlaps an edge of the source doped region 160, and the overlapped edge serves as a boundary position of the first end 131 and the source doped region 160. Such that the source doped region 160 laterally abuts the first overlap 111 between the first end 131 and the channel region 110 at the interface location. In this embodiment, the source doped region 160 is further adjacent to a body doped region 170, the body doped region 170 and the first overlapping portion 111 are respectively located on two opposite sides of the source doped region 160, and the body doped region 170 is also located in the channel region 110. The source doped region 160 and the body doped region 170 lead out a source 210 connected with the body end and the source end of the LDMOS device.
In the base layer 100 at a position below the drift region 120, a withstand voltage improving region 180 is formed, and the withstand voltage improving region 180 is in longitudinal contact with the drift region 120.
In the related technology, the drift region is deep in depth and small in doping concentration, so that transconductance of the device is small, saturation current is insufficient, and if the concentration of the drift region is increased or the thickness of the drift region is reduced, the breakdown voltage of the device is not high enough, and the working withstand voltage requirement of the device cannot be met.
In this embodiment, the withstand voltage improving region is formed in the substrate layer at the position below the drift region, so that the withstand voltage improving region is in contact with the drift region in the longitudinal direction, thereby reducing the depth of the drift region in the longitudinal direction while ensuring the withstand voltage performance of the device without changing the transverse length of the drift region, and increasing the transconductance of the LDMOS device and the saturation current of the device.
Alternatively, the drift region 120 extends longitudinally downward from the upper surface of the substrate layer 100 by a first depth D1 in a range of 0.6 to 1.0 micrometers, and the withstand voltage improving region 180 extends longitudinally by a second depth D2 in a range of 1.4 to 3.0 micrometers.
Taking an N-type LDMOS as an example, the first conductivity type is N-type and the second conductivity type is P-type as described in this application. Thus, the conductivity type of the substrate layer 100 shown in fig. 1 is P type, the conductivity type of the channel region 110 is P type, the conductivity type of the drift region 120 is N type, the conductivity type of the withstand voltage raising region 180 is P type, the conductivity type of the first drain doping region 141 is N type, the conductivity type of the source doping region 160 is N type, and the conductivity type of the body doping region 170 is P type. Wherein the doping concentration in the drift region 120 is in the range of 1e17cm-3～1e18cm-3The doping concentration range in the withstand voltage raising region is 5e17cm-3～5e18cm-3. For a P-type LDMOS, the channel region 110, the drift region 120, the withstand voltage improving region 180, the first drain-terminal doping region 141, the source-terminal doping region 160, and the body-terminal doping region 170 shown in fig. 1 are opposite to the conductivity type of the N-type LDMOS. Wherein the P-type and the N-type are opposite conductivity types.
With continued reference to fig. 1, the substrate layer 100 may include a bottom layer 101 and an epitaxial layer 102 stacked in sequence from bottom to top in a longitudinal direction, i.e., a Y direction shown in fig. 1, and the buried layer 103 may be formed at a boundary position of the bottom layer 101 and the epitaxial layer 102 through a doping process. Taking an N-type LDMOS as an example, the conductivity type of the buried layer 103 is N-type. The LDMOS device is located in the epitaxial layer 102, i.e., the channel region 110, the drift region 120, and the withstand voltage improving region 180 are all located in the epitaxial layer 102.
A high voltage isolation region 190 is also formed in the epitaxial layer 102. The high voltage isolation region 190 is located on the other side of the drift region 120 opposite to the channel region 110, and is used for isolating the LDMOS device. As can be seen in fig. 1, the high voltage isolation region 190 and the channel region 110 are located on the X-direction right and left sides of the drift region 120, respectively. The high voltage isolation region 190 extends in a longitudinal direction and is in contact with the buried layer 103 in the longitudinal direction, such that the high voltage isolation region 190 and the buried layer 103 semi-surround the LDMOS device structure, thereby isolating the LDMOS device structure from adjacent other devices.
In this embodiment, the high voltage isolation region 190 has an N-type conductivity, and may include a first N-type well 191 and a second N-type well 192, where the first N-type well 191 extends downward from the upper surface of the substrate layer 100 to contact and connect with the buried layer 103. The second N-well 192 is formed in the first N-well 191 and extends downward from the upper surface of the first N-well 191, and the depth of the second N-well 192 in the longitudinal direction is smaller than the depth of the first N-well 191 in the longitudinal direction. The second N-well 192 forms a second drain doping region 142 by heavily doping N-type impurities, and a second field oxide layer 152 is formed in the substrate layer 200 between the second drain doping region 142 and the first drain doping region 141. As shown in fig. 1, the second field oxide layer 152 sequentially passes through the drift region 120, the first N-well 191 and the second N-well 192 from the first drain doping region 141 until contacting the second drain doping region 142.
The first drain-side doped region 141 and the second drain-side doped region 142 jointly lead out the drain 230 of the LDMOS device.
Fig. 2 shows a transconductance variation curve of the LDMOS device provided in the related art, and it can be seen from fig. 2 that the transconductance of the LDMOS device is small.
Fig. 3 shows a transconductance variation curve of the LDMOS device provided by the present application, and as can be seen from fig. 3, the LDMOS device provided by the present application has a larger transconductance, which can solve the problem that the transconductance of the device is compressed due to the larger depth of the drift region in the related art, thereby causing the insufficient saturation current of the device.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (10)
1. An improved transconductance LDMOS device structure, comprising:
a base layer in which laterally adjacent channel and drift regions are formed, both extending downwardly from an upper surface of the base layer;
the gate structure is bridged between the channel region and the drift region along the surface of the substrate layer, and a first end part and a second end part of the gate structure are respectively overlapped with the channel region and the drift region;
forming a first drain terminal doped region on one side of the drift region far away from the channel region, and forming a first field oxide layer at the position of the drift region between the first drain terminal doped region and a second end part of the gate structure, wherein the second end part is overlapped with the first field oxide layer;
forming a source end doped region in the channel region at a position near a first end of the gate structure;
and a withstand voltage improving region is formed in the substrate layer at a position below the drift region, and the withstand voltage improving region is in longitudinal contact with the drift region.
2. The LDMOS device structure with improved transconductance as claimed in claim 1, wherein a high voltage isolation region is further formed in said base layer;
the high-voltage isolation region is located on the other side, opposite to the channel region, of the drift region and is used for isolating the LDMOS device.
3. The LDMOS device structure with improved transconductance as claimed in claim 2, wherein a second drain-side doped region is formed in said high voltage isolation region.
4. The LDMOS device structure with improved transconductance as claimed in claim 3, wherein a second field oxide layer is formed in the base layer between the second drain doped region and the first drain doped region.
5. The LDMOS device structure with improved transconductance as claimed in claim 2, wherein said high voltage isolation region extends downward from the upper surface of said substrate layer, and a first conductivity type buried layer is connected to the lower end of said high voltage isolation region;
the first-conductivity-type buried layer extends laterally in the base layer;
the laterally extending first conduction type buried layer and the longitudinally extending high-voltage isolation region are used for semi-surrounding the LDMOS device structure.
6. The LDMOS device structure with improved transconductance as set forth in claim 5, wherein said high voltage isolation region is of a first conductivity type.
7. The LDMOS device structure with improved transconductance of claim 1, wherein the drift region is of the first conductivity type, and a doping concentration in the drift region ranges from 1e17cm-3～1e18cm-3。
8. The LDMOS device structure with improved transconductance as claimed in claim 1, wherein said withstand voltage raising region is of the second conductivity type, and a doping concentration in said withstand voltage raising region is in a range of 5e17cm-3～5e18cm-3。
9. The LDMOS device structure with improved transconductance as claimed in claim 1, wherein the drift region extends in the base layer along the longitudinal direction by a first depth of 0.6 microns to 1.0 micron.
10. The LDMOS device structure with improved transconductance as claimed in claim 1, wherein said withstand voltage boosting region is in said base layer with a second depth extending in a longitudinal direction of 1.4 microns to 3.0 microns.
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