CN108258051A - LDMOS device and its manufacturing method - Google Patents
LDMOS device and its manufacturing method Download PDFInfo
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- CN108258051A CN108258051A CN201810024868.3A CN201810024868A CN108258051A CN 108258051 A CN108258051 A CN 108258051A CN 201810024868 A CN201810024868 A CN 201810024868A CN 108258051 A CN108258051 A CN 108258051A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 211
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 206
- 239000001301 oxygen Substances 0.000 claims abstract description 206
- 238000000034 method Methods 0.000 claims abstract description 26
- 210000003323 beak Anatomy 0.000 claims abstract description 20
- 230000015556 catabolic process Effects 0.000 claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 19
- 230000003647 oxidation Effects 0.000 claims abstract description 19
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 19
- 230000005684 electric field Effects 0.000 claims abstract description 13
- 230000007547 defect Effects 0.000 claims abstract description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 61
- 229920005591 polysilicon Polymers 0.000 claims description 59
- 239000000758 substrate Substances 0.000 claims description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 19
- 239000004065 semiconductor Substances 0.000 claims description 19
- 229910052710 silicon Inorganic materials 0.000 claims description 19
- 239000010703 silicon Substances 0.000 claims description 19
- 238000002347 injection Methods 0.000 claims description 10
- 239000007924 injection Substances 0.000 claims description 10
- 238000000407 epitaxy Methods 0.000 claims description 7
- 238000006396 nitration reaction Methods 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 238000002955 isolation Methods 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims description 2
- 150000004767 nitrides Chemical class 0.000 claims 1
- 230000002035 prolonged effect Effects 0.000 claims 1
- 230000006872 improvement Effects 0.000 description 14
- 238000010586 diagram Methods 0.000 description 8
- 239000002184 metal Substances 0.000 description 6
- QRSFFHRCBYCWBS-UHFFFAOYSA-N [O].[O] Chemical compound [O].[O] QRSFFHRCBYCWBS-UHFFFAOYSA-N 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000000926 separation method Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 3
- 241000293849 Cordylanthus Species 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- Ceramic Engineering (AREA)
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Abstract
The invention discloses a kind of LDMOS device, drift region oxygen is formed by stacking by first oxygen and second oxygen, and first oxygen is formed using local oxidation technique, and second oxygen is formed using oxide layer deposit plus etching technics；First oxygen forms the beak contact that a beak causes the first side of gate dielectric layer and drift region oxygen in the first side of drift region oxygen, it eliminates when individually using second oxygen the gate dielectric layer and the electric field strength increase of drift region Chang Yang contact positions the defects of, so as to improve the breakdown voltage of device；Second oxygen is superimposed upon the thickness for being used under conditions of the overall thickness for ensureing drift region oxygen remains unchanged reducing by first oxygen on the surface of first oxygen, so as to reduce the distance between the bottom of drift region oxygen and first epi-layer surface, to reduce the conducting resistance of device.The invention also discloses a kind of manufacturing methods of LDMOS device.The present invention can improve the breakdown voltage of device, reduce the conducting resistance and OFF leakage current of device.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing field, more particularly to a kind of LDMOS device；The invention further relates to
A kind of manufacturing method of LDMOS device.
Background technology
Double-diffusion metal-oxide-semiconductor field effect transistor (Double-diffused MOS) is due to having pressure-resistant original text, greatly
It the features such as current driving ability and extremely low power dissipation, is widely adopted in electric power management circuit at present.DMOS includes vertical double expansions
Dispersed metallic oxide semiconductor field effect pipe (VDMOS) and LDMOS (LDMOS), in LDMOS device, conducting resistance is one
Important index.In BCD techniques, although LDMOS and CMOS is integrated in same chip, due to high voltage and low feature electricity
Resistance and the requirement of conducting resistance, LDMOS is before the condition of background device area and drift region and the existing process conditions of CMOS are shared
It puts, there are contradictions and compromise with breakdown voltage (BV) for conducting resistance, can not often meet the requirement of switching tube application, conducting
Resistance generally use featured resistance (Rsp) represents.Therefore identical breakdown voltage (offBV) is being obtained, should reduced as possible
Rsp is to improve the competitiveness of product.
As shown in Figure 1, it is the structure diagram of the first existing LDMOS device；By taking N-type device as an example, it is existing the first
LDMOS device includes：
First epitaxial layer 2 of N-type is formed with drift region 4 and the N of p-type in the selection area of first epitaxial layer 2
Xing Ti areas 5；The drift region 4 and 5 lateral isolation of body area have distance.
The first buried layer 1 of p-type heavy doping is formed in the bottom of first epitaxial layer 2；First buried layer 1 is formed in
Semiconductor substrate surface.In general, the Semiconductor substrate is silicon substrate, first epitaxial layer 2 is silicon epitaxy layer.
It is formed in the selection area of the drift region 4 by drift region oxygen 3.
The grid being formed by stacking by gate dielectric layer such as gate oxide 6 and polysilicon gate 7 is formed on the surface in the body area 5
Structure is used to form raceway groove by 5 surface of body area that the polysilicon gate 7 covers.
First side of the second side of the gate dielectric layer 6 and the drift region oxygen 3 is in contact, the polysilicon gate 7
The second side is extended on the surface of the drift region oxygen 3.
Source region 8a is formed in 5 surface of body area and the second side of the source region 8a and the first side of the polysilicon gate 7
Autoregistration.
Drain region 8b is formed in the second of in the drift region 4 and the first side of the drain region 8b and the drift region oxygen 3
Side autoregistration.
The body draw-out area 9 of N-type heavy doping, the body draw-out area 9 and the source region are also formed on the surface in the body area 5
The side of the first side of 8a is in contact.The body draw-out area 9 and the source region 8a can be connected to by identical contact hole by just
The source electrode of face metal layer composition.
Drain region 8b can then be connected to the drain electrode being made of front metal layer by contact hole, and polysilicon gate 7 then can be by connecing
Contact hole is connected to the grid being made of front metal layer.
In Fig. 1, the drift region oxygen 3 is the structure for the certain depth for being recessed into the first epitaxial layer 2, in general, the drift
Area oxygen 3 is moved to be formed using shallow ditch groove separation process (STI) or using location oxidation of silicon process (LOCOS).Wherein, using STI works
Skill forms the step of drift region oxygen 3 and includes：A) silicon is performed etching to form shallow trench, b) thermal oxide is carried out in shallow ridges
Rooved face forms oxide layer, c) oxide layer filling, d are carried out to groove) form the drift region oxygen 3 through chemical mechanical grinding.
And LOCOS techniques are to carry out oxidation by the silicon to part to form the drift region oxygen 3.In STI and LOCOS techniques, institute
It is thicker to state drift region field oxygen 3, is more conducive to improve the OffBV of device and reduces OFF leakage current (Ioff), but be more unfavorable for
The reduction of the Rsp of device.On the contrary, the drift region oxygen 3 is thinner, Rsp is more advantageously reduced, but OffBV can be caused to reduce
And electric leakage Ioff increases.
Fig. 2 is the structure diagram of existing second of LDMOS device；With the difference of the first existing structure shown in FIG. 1
Part is to have following feature in existing second of LDMOS device：
In Fig. 2, drift region oxygen 3a is formed in the structure of the surface of the first epitaxial layer 2, the drift region oxygen 3a
It is formed using oxide layer deposit plus lithographic etch process.When the shortcomings that existing second of LDMOS is high voltage, easily it is situated between in grid
Matter layer 6 and drift region Chang Yang3a junctions form high electric field, therefore breakdown is frequently experienced in the junction.In order to avoid this existing
As, it has to widen the lateral dimension of device.But widening lateral dimension can cause the Rsp of device to increase rapidly.
Invention content
The technical problems to be solved by the invention are to provide a kind of LDMOS device, can improve the breakdown voltage of device, reduce
The conducting resistance and OFF leakage current of device.For this purpose, the present invention also provides a kind of manufacturing methods of LDMOS device.
In order to solve the above technical problems, LDMOS device provided by the invention includes：
First epitaxial layer of the second conduction type is formed with the first conductive-type in the selection area of first epitaxial layer
The drift region of type and the body area of the second conduction type；Laterally contact or isolation have distance for the drift region and the body area.
It is formed in the selection area of the drift region by drift region oxygen.
The gate structure being formed by stacking by gate dielectric layer and polysilicon gate is formed on the surface in the body area, by described more
The body surface of crystal silicon grid covering is used to form raceway groove.
First side of the second side of the gate dielectric layer and the drift region oxygen is in contact, and the second of the polysilicon gate
Side is extended on the surface of the drift region oxygen.
Source region is formed in the second side of the body surface and the source region and the first side autoregistration of the polysilicon gate.
Drain region is formed in first side in the drift region and drain region and the second side of the drift region oxygen from right
It is accurate.
The drift region oxygen is formed by stacking by first oxygen and second oxygen, and first oxygen uses local oxidation
Technique is formed, and second oxygen is formed using oxide layer deposit plus etching technics.
First oxygen forms a beak in the first side of the drift region oxygen and causes the gate dielectric layer and institute
The beak contact of the first side of drift region oxygen is stated, eliminates when individually using second oxygen gate dielectric layer and described the
Two oxygen are in direct contact the defects of electric field strength increase brought in the gate dielectric layer and the drift region Chang Yang contact positions,
So as to improve the breakdown voltage of device.
Second oxygen is superimposed upon the total thickness being used on the surface of first oxygen ensureing the drift region oxygen
Degree reduces the thickness of first oxygen under conditions of remaining unchanged, so as to reduce the bottom of the drift region oxygen and described the
The distance between one epi-layer surface, to reduce the conducting resistance of device.
A further improvement is that be formed with the first conduction type heavy doping in the bottom of first epitaxial layer first buries
Layer；First buried layer is formed in semiconductor substrate surface.
A further improvement is that the Semiconductor substrate is silicon substrate, first epitaxial layer is silicon epitaxy layer.
A further improvement is that the local oxidation technique of first oxygen is to the consumption of first epitaxial layer
A further improvement is that the thickness of second oxygen is
A further improvement is that the gate dielectric layer is gate oxide.
A further improvement is that the body draw-out area of the second conduction type heavy doping is also formed on the surface in the body area,
The side of the body draw-out area and the first side of the source region is in contact.
A further improvement is that LDMOS is N-type device, the first conduction type is N-type, and the second conduction type is P types；Or
Person, LDMOS are P-type device, and the first conduction type is p-type, and the second conduction type is N-type.
In order to solve the above technical problems, the manufacturing method of LDMOS device provided by the invention includes the following steps：
Step 1: provide the first epitaxial layer of the second conduction type.
Step 2: first oxygen is formed in the selection area of first epitaxial layer using local oxidation technique.
Step 3: second oxygen is formed at the top of first oxygen using oxide layer deposit plus etching technics, by institute
It states first oxygen and second oxygen is superimposed to form drift region oxygen.
Step 4: drift is formed in the selection area of first epitaxial layer using the first conductive type ion injection technology
Area is moved, the drift region oxygen is located in the subregion of the drift region.
Step 5: sequentially form gate dielectric layer and the first polysilicon layer.
Step 6: the lateral location that first time lithographic definition goes out the first side of polysilicon gate is carried out, successively to described first
Polysilicon layer and the gate dielectric layer perform etching the side for the first side to form the polysilicon gate and by the polysilicon gates
The first side side outside first epi-layer surface expose.
Step 7: carrying out forming body area using the second conductive type ion injection technology, the body area is located at the polycrystalline
In first epitaxial layer outside the side of first side of Si-gate, the body area extends to the of the polysilicon gate after annealing
The bottom of side is used to form raceway groove by the body surface that the polysilicon gate covers.
Step 8: the lateral location that second of lithographic definition goes out the second side of polysilicon gate is carried out, to first polycrystalline
Silicon layer performs etching the side for the second side to form the polysilicon gate and forms the polysilicon gate, by the gate dielectric layer and
The polysilicon gate is superimposed to form gate structure；First side of the second side of the gate dielectric layer and the drift region oxygen connects
It touches, the second side of the polysilicon gate is extended on the surface of the drift region oxygen.
Step 9: carrying out the injection of the first conduction type heavy doping ion is formed simultaneously source region and drain region, source region is formed in institute
State the second side of body surface and the source region and the first side autoregistration of the polysilicon gate；Drain region is formed in the drift region
In and first side in the drain region and the second side autoregistration of the drift region oxygen.
First oxygen forms a beak in the first side of the drift region oxygen and causes the gate dielectric layer and institute
The beak contact of the first side of drift region oxygen is stated, eliminates when individually using second oxygen gate dielectric layer and described the
Two oxygen are in direct contact the defects of electric field strength increase brought in the gate dielectric layer and the drift region Chang Yang contact positions,
So as to improve the breakdown voltage of device.
Second oxygen is superimposed upon the total thickness being used on the surface of first oxygen ensureing the drift region oxygen
Degree reduces the thickness of first oxygen under conditions of remaining unchanged, so as to reduce the bottom of the drift region oxygen and described the
The distance between one epi-layer surface, to reduce the conducting resistance of device.
A further improvement is that the first conduction type heavy doping is formed in the bottom of first epitaxial layer in step 1
The first buried layer；First buried layer is formed in semiconductor substrate surface.
A further improvement is that the Semiconductor substrate is silicon substrate, first epitaxial layer is silicon epitaxy layer.
A further improvement is that the local oxidation technique of first oxygen described in step 2 is to first epitaxial layer
Consumption is
A further improvement is that the forming region of first oxygen described in step 2 is using the first oxide layer and the second nitridation
Layer is defined, after second nitration case of the forming region of first oxygen and first oxide layer removal,
Further include first epitaxial layer progress to the forming region of first oxygenOver etching the step of, later
It carries out partial thermal oxidation and forms first oxygen.
A further improvement is that the thickness of second oxygen is
A further improvement is that further include step after step 9：
Step 10: the surface formation body draw-out area that the second conduction type heavy doping ion is infused in the body area is carried out, institute
The side for stating body draw-out area and the first side of the source region is in contact.
The present invention has done the structure of drift region oxygen and has targetedly designed, and predominantly the present invention sets drift region oxygen
Count into first oxygen formed by local oxidation technique and second oxygen by being formed using oxide layer deposit plus etching technics
It is formed by stacking, the different characteristic realizations of first oxygen and second oxygen can be utilized to have complementary functions and overcome mutually respective
Defect individually uses all inaccessiable overall effect of any field oxygen, specially so as to reach：
First oxygen of the present invention has beak structure, in the case of with first oxygen, gate dielectric layer meeting and drift
The beak contact of the first side of area oxygen is moved, it is individually direct using gate dielectric layer during second oxygen and second oxygen so as to eliminate
The defects of contact brings the electric field strength increase in gate dielectric layer and drift region Chang Yang contact positions, so as to improve hitting for device
Voltage namely the independent drift region being made of the second oxygen oxygen relative to same thickness are worn, the present invention can improve device
Breakdown voltage；
Moreover, the present invention is drifted about by reducing the thickness of second oxygen of thickness and increase of first oxygen come entire
The thickness of area oxygen is constant, can reduce the OFF leakage current of device.
The present invention is at the contact position of the first side that gate dielectric layer and drift region oxygen are reduced by first oxygen
Electric field strength, can be by the thickness of second oxygen of thickness and increase of first oxygen of reduction come entire drift region oxygen
Thickness is constant namely the independent drift region that is made of first oxygen oxygen relative to same thickness, drift region of the invention
Field oxygen is since thickness is kept, therefore the breakdown voltage of device can be maintained.
In addition, the structure of the independent drift region being made of the first oxygen oxygen relative to same thickness, the present invention can drop
The thickness of low first oxygen, so the depth that first oxygen is recessed in the first epitaxial layer can be reduced, this is but also drift region
The path that electric current passes through shortens, and can reduce the conducting resistance of device.
Had in short, the present invention can overcome simultaneously using the independent drift region being made of the second oxygen oxygen of same thickness
There is pressure resistance limit by the electric field strength at the oxygen contact position of gate dielectric layer and drift region and that OFF leakage current is larger is scarce
It falls into and overcomes larger using conducting resistance possessed by the independent drift region being made of the first oxygen oxygen of same thickness
Defect, the present invention can improve the breakdown voltage of device, and the conducting resistance of device is reduced under conditions of breakdown voltage is guaranteed
And OFF leakage current.
Description of the drawings
The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments：
Fig. 1 is the structure diagram of the first existing LDMOS device；
Fig. 2 is the structure diagram of existing second of LDMOS device；
Fig. 3 is the structure diagram of LDMOS device of the embodiment of the present invention；
Fig. 4 A- Fig. 4 E are the device architecture schematic diagrames in each step of the manufacturing method of LDMOS device of the embodiment of the present invention.
Specific embodiment
As shown in figure 3, it is the structure diagram of LDMOS device of the embodiment of the present invention；LDMOS device packet of the embodiment of the present invention
It includes：
First epitaxial layer 102 of the second conduction type, first is formed in the selection area of first epitaxial layer 102
The body area 105 of 104 and second conduction type of drift region of conduction type；The drift region 104 and the body area 105 laterally every
With a distance from having.Also can be in other embodiments：The drift region 104 and the laterally contact of the body area 105.
In the embodiment of the present invention, the of the first conduction type heavy doping is formed in the bottom of first epitaxial layer 102
One buried layer 101；First buried layer 101 is formed in semiconductor substrate surface.Preferably, the Semiconductor substrate is silicon substrate,
First epitaxial layer 102 is silicon epitaxy layer.
It is formed in the selection area of the drift region 104 by drift region oxygen 103.
The grid knot being formed by stacking by gate dielectric layer 106 and polysilicon gate 107 is formed on the surface in the body area 105
Structure is used to form raceway groove by 105 surface of body area that the polysilicon gate 107 covers.Preferably, the gate dielectric layer 106
For gate oxide.
First side of the second side of the gate dielectric layer 106 and the drift region oxygen 103 is in contact, the polysilicon gate
107 the second side is extended on the surface of the drift region oxygen 103.
Source region 108a is formed in 105 surface of body area and the second side of the source region 108a and the polysilicon gate 107
The first side autoregistration.
Drain region 108b is formed in the drift region 104 and the first side of the drain region 108b and the drift region oxygen
103 the second side autoregistration.
The body draw-out area 109 of the second conduction type heavy doping is also formed on the surface in the body area 105, the body is drawn
The side of area 109 and the first side of the source region 108a is in contact.The body draw-out area 109 and the source region 108a can pass through
Identical contact hole is connected to the source electrode being made of front metal layer.
Drain region 108b can then be connected to the drain electrode being made of front metal layer by contact hole, and polysilicon gate 107 can then lead to
It crosses contact hole and is connected to the grid being made of front metal layer.
The drift region oxygen 103 is formed by stacking by first oxygen 1032 and second oxygen 1031, first oxygen
1032 are formed using local oxidation technique, and second oxygen 1031 is formed using oxide layer deposit plus etching technics.
First oxygen 1032 forms a beak in the first side of the drift region oxygen 103 and causes the gate medium
The beak contact of first side of layer 106 and the drift region oxygen 103, eliminates and individually uses the second oxygen 1031 when institute
It states gate dielectric layer 106 and second oxygen 1031 is in direct contact and brings in the gate dielectric layer 106 and the drift region
The defects of electric field strength increase of 103 contact position of oxygen, so as to improve the breakdown voltage of device.
Second oxygen 1031, which is superimposed upon on the surface of first oxygen 1032, to be used to ensure the drift region
The overall thickness of oxygen 103 reduces the thickness of first oxygen 1032 under conditions of remaining unchanged, so as to reduce the drift region
The distance between the bottom of oxygen 103 and 102 surface of the first epitaxial layer, to reduce the conducting resistance of device.
Preferably, the local oxidation technique of first oxygen 1032 is to the consumption of first epitaxial layer 102Namely it can obtain the thickness of first oxygen 1032 by the consumption to first epitaxial layer 102
Degree.
First oxygen 1032 in the embodiment of the present invention is used for relative in other regions every the field for going out active area
The thickness of oxygen greatly reduces, and is the local field oxygen (Mini-LOCOS) of a scaled down version.
The thickness of second oxygen 1031 is
In the embodiment of the present invention, LDMOS be N-type device, the first conduction type be N-type, the second conduction type be P types, institute
Semiconductor substrate is stated to adulterate for p-type.Also can be in other embodiments：LDMOS is P-type device, and the first conduction type is p-type,
Second conduction type is N-type.
LDMOS device of the embodiment of the present invention can be integrated in BCD techniques.From the foregoing, it will be observed that, drift different from existing technique
Shifting area oxygen 103 is one by upper and lower structure dimerous.First oxygen 1032 is by the implementation part to silicon face
Thermal oxide forms a very shallow Mini-LOCOS, and meetings of the Mini-LOCOS at both ends forms small and short beak (bird '
S beak), short beak does not interfere with the thickness of gate dielectric layer 106.Shallow Mini-LOCOS can shorten current path, i.e.,
The Rsp of device is substantially reduced, gate dielectric layer 106 and drift region oxygen under high voltage state can be obviously reduced in the beak of LOCOS
The electric field of 103 junctions, therefore the breakdown voltage of device can be improved.Second oxygen 1031 is the top half of field oxygen zone, is
It is formed by other means, the purpose is to improve the breakdown of the OFF state of device to thicken the thickness of entire drift region oxygen 103
Voltage (OffBV), the thickness for the field oxygen zone that wherein Mini-LOCOS is formed cannot be too thick, too thick significantly to increase Rsp, but floats
The thickness for moving area's oxygen 103 cannot be too thin, too thin to reduce OffBV, so the embodiment of the present invention passes through second oxygen 1031
Setting can form thicker drift region oxygen 103 under conditions of ensureing that first oxygen 1032 is relatively thin.As previously mentioned, Mini-
The effect of LOCOS is to form a bird ' s beak in gate dielectric layer 106 and drift region Chang Yang103 junctions to reduce connection
The electric field at place improves the breakdown voltage (BV) of device, which wants small and short compared to the existing LOCOS beaks formed, therefore
Energy device architecture of the embodiment of the present invention can reduce the Rsp of device, improve the performance of device.
Carrying out test can obtain：
Compared to the first existing structure shown in FIG. 1 and existing second of structure shown in Fig. 2, device of the embodiment of the present invention
Part can reduce by 7%~9% Rsp when BV is 29V, and OFF leakage current (Ioff) can reduce an order of magnitude.
As shown in Fig. 4 A to Fig. 4 E, be LDMOS device of the embodiment of the present invention manufacturing method each step in device junction
Structure schematic diagram, the manufacturing method of LDMOS device of the embodiment of the present invention include the following steps：
Step 1: as shown in Figure 4 A, provide the first epitaxial layer 102 of the second conduction type.
In present invention method, the first conduction type heavy doping is formed in the bottom of first epitaxial layer 102
The first buried layer 101；First buried layer 101 is formed in semiconductor substrate surface.
Preferably, the Semiconductor substrate is silicon substrate, and first epitaxial layer 102 is silicon epitaxy layer.
Step 2: as shown in Figure 4 A, using local oxidation technique in the selection area of first epitaxial layer 102 shape
Into first oxygen 1032.In present invention method, the local oxidation technique of first oxygen 1032 is to described first
The consumption of epitaxial layer 102 is
Preferably, the forming region of first oxygen 1032 using the first oxide layer 111 and the second nitration case 110 into
Row definition, removes in second nitration case 110 of the forming region of first oxygen 1032 and first oxide layer 111
Later, it further includes and first epitaxial layer 102 of the forming region of first oxygen 1032 is carried outCross carve
The step of erosion, the etching angle that technique is performed etching to first epitaxial layer 102 are 45 degree~85 degree, carry out part later
Thermal oxide forms first oxygen 1032.
Step 3: as shown in Figure 4 B, etching technics is added in the top shape of first oxygen 1032 using oxide layer deposit
Into second oxygen 1031, drift region oxygen 103 is formed by first oxygen 1032 and second oxygen 1031 superposition.
It needs first to remove the first oxide layer 111 and the second nitration case 110 before oxide layer deposit.Described the formed
The thickness of two oxygen 1031 is
Step 4: as shown in Figure 4 B, using the first conductive type ion injection technology in first epitaxial layer 102
Drift region 104 is formed in selection area, the drift region oxygen 103 is located in the subregion of the drift region 104.
Step 5: as shown in Figure 4 C, sequentially form 106 and first polysilicon layer 107 of gate dielectric layer.Preferably, the grid
Dielectric layer 106 is gate oxide, is formed using thermal oxidation technology.
Step 6: as shown in Figure 4 C, the lateral location that first time lithographic definition goes out the first side of polysilicon gate 107 is carried out,
Successively first polysilicon layer 107 and the gate dielectric layer 106 are performed etching to form the first of the polysilicon gate 107
Simultaneously 102 surface of the first epitaxial layer outside the side of the first side of the polysilicon gate 107 is exposed the side of side.
Step 7: it as shown in Figure 4 C, carries out forming body area 105, the body using the second conductive type ion injection technology
Area 105 is located in first epitaxial layer 102 outside the side of the first side of the polysilicon gate 107, and the body area 105 is being moved back
The bottom of the first side of the polysilicon gate 107 is extended to after fire, 105 table of body area covered by the polysilicon gate 107
Face is used to form raceway groove.
Preferably, it carries out needing to inject using band photoresist during the ion implanting in the body area 105, photoresist is step
The photoresist of the lateral location of first side of the polysilicon gate 107 defined in six.
Step 8: as shown in Figure 4 C, the lateral location that second of lithographic definition goes out the second side of polysilicon gate 107 is carried out,
The side for the second side to form the polysilicon gate 107 is performed etching to first polysilicon layer 107 and forms the polycrystalline
Si-gate 107 forms gate structure by the gate dielectric layer 106 and the superposition of the polysilicon gate 107；The gate dielectric layer 106
First side of the second side and the drift region oxygen 103 is in contact, and the second side of the polysilicon gate 107 extends to the drift
It moves on the surface of area oxygen 103.
Step 9: it as shown in Figure 4 D, carries out the injection of the first conduction type heavy doping ion and is formed simultaneously source region 108a and leakage
Area 108b, source region 108a are formed in the second side on 105 surface of body area and the source region 108a and the polysilicon gate 107
First side autoregistration；Drain region 108b is formed in the drift region 104 and the first side of the drain region 108b and the drift region
The second side autoregistration of field oxygen 103.
Preferably, the body area 105 of adjacent LDMOS device shares, and to be formed the source region 108a and described
The region during ion implanting of drain region 108b between the two neighboring source region 108a in the same body area 105 hinders with photoresist
Gear.The drain region 108b of adjacent LDMOS device is shared, and the both sides of the drain region 108b are all the drift region oxygen 103,
The position of the drain region 108b is directly defined by the drift region of both sides 103 autoregistration of oxygen.
First oxygen 1032 forms a beak in the first side of the drift region oxygen 103 and causes the gate medium
The beak contact of first side of layer 106 and the drift region oxygen 103, eliminates and individually uses the second oxygen 1031 when institute
It states gate dielectric layer 106 and second oxygen 1031 is in direct contact and brings in the gate dielectric layer 106 and the drift region
The defects of electric field strength increase of 103 contact position of oxygen, so as to improve the breakdown voltage of device；
Second oxygen 1031, which is superimposed upon on the surface of first oxygen 1032, to be used to ensure the drift region
The overall thickness of oxygen 103 reduces the thickness of first oxygen 1032 under conditions of remaining unchanged, so as to reduce the drift region
The distance between the bottom of oxygen 103 and 102 surface of the first epitaxial layer, to reduce the conducting resistance of device.
Step 10: carry out the surface formation body draw-out area that the second conduction type heavy doping ion is infused in the body area 105
109, the side of the first side of the body draw-out area 109 and the source region 108a is in contact.When carrying out the body draw-out area 109
It needs first to open the forming region of the body draw-out area 109, other regions stop with photoresist, are carrying out injection formation later
The body draw-out area 109.
In present invention method, LDMOS is N-type device, and the first conduction type is N-type, and the second conduction type is P
Type, the Semiconductor substrate are adulterated for p-type.Also can be in other embodiments：LDMOS is P-type device, and the first conduction type is
P-type, the second conduction type are N-type.
The present invention has been described in detail through specific embodiments, but these not form the limit to the present invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these also should
It is considered as protection scope of the present invention.
Claims (15)
1. a kind of LDMOS device, which is characterized in that including：
First epitaxial layer of the second conduction type is formed with the first conduction type in the selection area of first epitaxial layer
Drift region and the body area of the second conduction type；Laterally contact or isolation have distance for the drift region and the body area；
It is formed in the selection area of the drift region by drift region oxygen；
The gate structure being formed by stacking by gate dielectric layer and polysilicon gate is formed on the surface in the body area, by the polysilicon
The body surface of grid covering is used to form raceway groove；
First side of the second side of the gate dielectric layer and the drift region oxygen is in contact, and the second side of the polysilicon gate is prolonged
On the surface for reaching the drift region oxygen；
Source region is formed in the second side of the body surface and the source region and the first side autoregistration of the polysilicon gate；
Drain region is formed in first side in the drift region and drain region and the second side autoregistration of the drift region oxygen；
The drift region oxygen is formed by stacking by first oxygen and second oxygen, and first oxygen uses local oxidation technique
It is formed, second oxygen is formed using oxide layer deposit plus etching technics；
First oxygen forms a beak in the first side of the drift region oxygen and causes the gate dielectric layer and the drift
The beak contact of the first side of area's oxygen is moved, eliminates when individually using second oxygen gate dielectric layer and second described
Oxygen is in direct contact the defects of electric field strength increase brought in the gate dielectric layer and the drift region Chang Yang contact positions, so as to
The breakdown voltage of device can be improved；
Second oxygen, which is superimposed upon, to be used to protect in the overall thickness for ensureing the drift region oxygen on the surface of first oxygen
Hold it is constant under conditions of reduce the thickness of first oxygen, so as to reduce outside the bottom and described first of the drift region oxygen
Prolong the distance between layer surface, to reduce the conducting resistance of device.
2. LDMOS device as described in claim 1, it is characterised in that：First is formed in the bottom of first epitaxial layer
First buried layer of conduction type heavy doping；First buried layer is formed in semiconductor substrate surface.
3. LDMOS device as claimed in claim 2, it is characterised in that：The Semiconductor substrate is silicon substrate, outside described first
Prolong layer as silicon epitaxy layer.
4. LDMOS device as described in claim 1, it is characterised in that：The local oxidation technique of first oxygen is to institute
The consumption for stating the first epitaxial layer is
5. LDMOS device as described in claim 1, it is characterised in that：The thickness of second oxygen is
6. LDMOS device as described in claim 1, it is characterised in that：The gate dielectric layer is gate oxide.
7. LDMOS device as described in claim 1, it is characterised in that：The second conduction is also formed on the surface in the body area
The side of first side of the body draw-out area of type heavy doping, the body draw-out area and the source region is in contact.
8. the LDMOS device as described in claim any in claim 1 to 7, it is characterised in that：LDMOS be N-type device, first
Conduction type is N-type, and the second conduction type is p-type；Alternatively, LDMOS is P-type device, the first conduction type is p-type, and second leads
Electric type is N-type.
9. a kind of manufacturing method of LDMOS device, which is characterized in that include the following steps：
Step 1: provide the first epitaxial layer of the second conduction type；
Step 2: first oxygen is formed in the selection area of first epitaxial layer using local oxidation technique；
Step 3: second oxygen is formed at the top of first oxygen using oxide layer deposit plus etching technics, by described the
One oxygen and second oxygen are superimposed to form drift region oxygen；
Step 4: drift is formed in the selection area of first epitaxial layer using the first conductive type ion injection technology
Area, the drift region oxygen are located in the subregion of the drift region；
Step 5: sequentially form gate dielectric layer and the first polysilicon layer；
Step 6: the lateral location that first time lithographic definition goes out the first side of polysilicon gate is carried out, successively to first polycrystalline
Silicon layer and the gate dielectric layer perform etching the side for the first side to form the polysilicon gate and by the of the polysilicon gate
First epi-layer surface outside the side of side is exposed；
Step 7: carrying out forming body area using the second conductive type ion injection technology, the body area is located at the polysilicon gate
The first side side outside first epitaxial layer in, the body area extends to the first side of the polysilicon gate after annealing
Bottom, raceway groove is used to form by the body surface that the polysilicon gate covers；
Step 8: the lateral location that second of lithographic definition goes out the second side of polysilicon gate is carried out, to first polysilicon layer
It performs etching the side for the second side to form the polysilicon gate and forms the polysilicon gate, by the gate dielectric layer and described
Polysilicon gate is superimposed to form gate structure；First side of the second side of the gate dielectric layer and the drift region oxygen is in contact,
The second side of the polysilicon gate is extended on the surface of the drift region oxygen；
Step 9: carrying out the injection of the first conduction type heavy doping ion is formed simultaneously source region and drain region, source region is formed in the body
First side autoregistration of area surface and the second side of the source region and the polysilicon gate；Drain region be formed in the drift region and
First side in the drain region and the second side autoregistration of the drift region oxygen；
First oxygen forms a beak in the first side of the drift region oxygen and causes the gate dielectric layer and the drift
The beak contact of the first side of area's oxygen is moved, eliminates when individually using second oxygen gate dielectric layer and second described
Oxygen is in direct contact the defects of electric field strength increase brought in the gate dielectric layer and the drift region Chang Yang contact positions, so as to
The breakdown voltage of device can be improved；
Second oxygen, which is superimposed upon, to be used to protect in the overall thickness for ensureing the drift region oxygen on the surface of first oxygen
Hold it is constant under conditions of reduce the thickness of first oxygen, so as to reduce outside the bottom and described first of the drift region oxygen
Prolong the distance between layer surface, to reduce the conducting resistance of device.
10. the manufacturing method of LDMOS device as claimed in claim 9, it is characterised in that：In first extension in step 1
The bottom of layer is formed with the first buried layer of the first conduction type heavy doping；First buried layer is formed in semiconductor substrate surface.
11. the manufacturing method of LDMOS device as claimed in claim 10, it is characterised in that：The Semiconductor substrate is served as a contrast for silicon
Bottom, first epitaxial layer are silicon epitaxy layer.
12. the manufacturing method of LDMOS device as claimed in claim 9, it is characterised in that：First oxygen described in step 2
Local oxidation technique is to the consumption of first epitaxial layer
13. the manufacturing method of LDMOS device as claimed in claim 12, it is characterised in that：First oxygen described in step 2
Forming region be defined using the first oxide layer and the second nitration case, described the of the forming region of first oxygen
After nitride layer and first oxide layer removal, first extension of the forming region to first oxygen is further included
Layer carries outOver etching the step of, later carry out partial thermal oxidation form first oxygen.
14. the manufacturing method of LDMOS device as claimed in claim 9, it is characterised in that：The thickness of second oxygen is
15. the manufacturing method of LDMOS device as claimed in claim 9, it is characterised in that：Step is further included after step 9：
Step 10: the surface formation body draw-out area that the second conduction type heavy doping ion is infused in the body area is carried out, the body
The side of draw-out area and the first side of the source region is in contact.
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| CN110515017A (en) * | 2019-10-24 | 2019-11-29 | 南京邮电大学 | A kind of hypersensitivity magnetic field sensor |
| CN111785639A (en) * | 2020-08-26 | 2020-10-16 | 上海华虹宏力半导体制造有限公司 | LDMOS transistor and preparation method thereof |
| CN111785640A (en) * | 2020-08-26 | 2020-10-16 | 上海华虹宏力半导体制造有限公司 | Method for adjusting angle of oxide field plate in LDMOS transistor |
| CN113140619A (en) * | 2020-06-09 | 2021-07-20 | 成都芯源系统有限公司 | Manufacturing method of self-aligned DMOS device |
| CN113594254A (en) * | 2021-07-29 | 2021-11-02 | 上海华虹宏力半导体制造有限公司 | LDMOS device structure for improving transconductance |
| CN114429985A (en) * | 2022-04-07 | 2022-05-03 | 广州粤芯半导体技术有限公司 | Transverse power device with grid field plate structure and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110515017A (en) * | 2019-10-24 | 2019-11-29 | 南京邮电大学 | A kind of hypersensitivity magnetic field sensor |
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| CN113140619A (en) * | 2020-06-09 | 2021-07-20 | 成都芯源系统有限公司 | Manufacturing method of self-aligned DMOS device |
| CN111785639A (en) * | 2020-08-26 | 2020-10-16 | 上海华虹宏力半导体制造有限公司 | LDMOS transistor and preparation method thereof |
| CN111785640A (en) * | 2020-08-26 | 2020-10-16 | 上海华虹宏力半导体制造有限公司 | Method for adjusting angle of oxide field plate in LDMOS transistor |
| CN111785639B (en) * | 2020-08-26 | 2024-02-02 | 上海华虹宏力半导体制造有限公司 | LDMOS transistor and preparation method thereof |
| CN113594254A (en) * | 2021-07-29 | 2021-11-02 | 上海华虹宏力半导体制造有限公司 | LDMOS device structure for improving transconductance |
| CN113594254B (en) * | 2021-07-29 | 2024-01-23 | 上海华虹宏力半导体制造有限公司 | LDMOS device structure for improving transconductance |
| CN114429985A (en) * | 2022-04-07 | 2022-05-03 | 广州粤芯半导体技术有限公司 | Transverse power device with grid field plate structure and preparation method thereof |
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