CN103489916A - N type LDMOS of ladder gate oxide layer and active drift region structure and manufacturing method of N type LDMOS - Google Patents

N type LDMOS of ladder gate oxide layer and active drift region structure and manufacturing method of N type LDMOS Download PDF

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CN103489916A
CN103489916A CN201310437804.3A CN201310437804A CN103489916A CN 103489916 A CN103489916 A CN 103489916A CN 201310437804 A CN201310437804 A CN 201310437804A CN 103489916 A CN103489916 A CN 103489916A
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oxide layer
ldmos
drift region
polycrystalline
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聂卫东
朱光荣
易法友
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WUXI JINGYUAN MICROELECTRONICS CO Ltd
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WUXI JINGYUAN MICROELECTRONICS CO Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors

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Abstract

The invention discloses an N type LDMOS of a ladder gate oxide layer and active drift region structure and a manufacturing method of the N type LDMOS. Lightly doped silica-based material is used as a bottommost base; an N well is arranged on the upper layer of the lightly doped silica-based material; the upper layer of the N well comprises a polycrystal constituting a grid electrode of the LDMOS, the N well, drift region doping and a thick N type constitute a drain electrode of the LDMOS, a P type body region constitutes a channel region of the LDMOS, and a thick N type in the P type body region constitutes a source electrode of the LDMOS; a thick P type in the P type body region is doped with the P type body region to constitute a substrate end of the LDMOS; a grid electrode oxide layer is arranged between the polycrystal and the P type body region, a ladder oxide layer is arranged between the polycrystal and the drain electrode of the LDMOS, the thickness of the ladder oxide layer is greater than that of the grid electrode oxide layer, and the ladder oxide layer is automatically aligned to the grid electrode, constituted by the polycrystal, of the LDMOS. The N type LDMOS obviously improves safety operation regions of devices under the circumstances that large currents and large electric fields exist, and on-resistance is not increased basically. Meanwhile, cost is low, and processes are easy to control.

Description

N-type LDMOS of the active drift region structure of step gates oxide layer and preparation method thereof
Technical field
The invention discloses the N-type LDMOS(horizontal dual pervasion field effect pipe of the active drift region structure of a kind of step gates oxide layer) and preparation method thereof, relate to a kind of semiconductor device, belong to technical field of semiconductors.
Background technology
Conventional horizontal dual pervasion field effect pipe is divided into an oxygen drift region structure and active drift region structure, respectively as shown in Figure 1 and Figure 2.Both main differences are that the method that forms of the oxide layer of drift region is different, and the ladder oxide layer of an oxygen drift region structure be partly the thick oxide layer of 0.3-1 μ m, because this part is field oxidation technology making of integrated circuit technology.Polysilicon gate and field oxide will carry out alignment.Field oxygen drift region structure, due to the oxidation bed thickness under polycrystalline, voltage endurance is good; And active drift region structure utilizes the grid polycrystalline to cover the advantage on thin oxide layer, grid polycrystalline and thin oxide layer form autoregistration, can reduce chip size.When conducting, by adding the grid polycrystalline, the impurity concentration of the drift region under thin oxide layer is affected, can effectively reduce conducting resistance, so on state characteristic is better than an oxygen drift region structure.These two kinds of structures have application very widely in integrated circuit technology at present.For the technique platform below 30V, there is very large advantage active drift region.For the technique more than 40V, the inferior position that active drift region is withstand voltage just slowly shows, and not as an oxygen drift region structure is widely used, and what generally adopt is an oxygen drift region structure.
Summary of the invention
Technical problem to be solved by this invention is: for the defect of prior art, a kind of LDMOS that field oxygen drift region structure and active drift region structure are combined together is provided, be thicker than the step gates oxide layer of thin grid oxygen by making the thin grid oxygen of one deck and a layer thickness, effectively reduce the electric field of active drift region structure in the polycrystalline end, obviously improve withstand voltage and breakdown characteristics, the grid polycrystalline, to the autoregistration of step gates oxide layer, does not need the alignment size simultaneously.Its superior on state characteristic is very most reservation still.
The present invention is for solving the problems of the technologies described above by the following technical solutions:
The N-type LDMOS of the active drift region structure of a kind of step gates oxide layer, comprise the dense N-type, P type tagma, the dense P type of inside, P type tagma, dense N-type, field oxide of silica-base material, N trap, drift region doping, ladder oxide layer, polycrystalline, grid oxic horizon, the inside, P type tagma of light doping; The silica-base material of described light doping is bottom basis; The upper strata of the silica-base material of light doping is the N trap; The upper strata of N trap comprises that polycrystalline forms the grid of LDMOS, and N trap, drift region doping and dense N-type form the drain electrode of LDMOS, and the tagma of P type forms the channel region of LDMOS, and the dense N-type of inside, P type tagma forms the source electrode of LDMOS; The dense P type of inside, P type tagma and the doping of P type tagma, the substrate terminal of formation LDMOS; It is characterized in that: described grid oxic horizon is arranged between polycrystalline and P type tagma, described ladder oxide layer is arranged between the drain electrode of polycrystalline and LDMOS, the thickness of ladder oxide layer is thicker than grid oxic horizon, and the grid autoregistration of the LDMOS of ladder oxide layer and described polycrystalline formation.
As the present invention further optimization scheme, described ladder oxide layer and grid oxic horizon are silicon dioxide layer.
As the present invention further optimization scheme, the thickness of described ladder oxide layer is 1.3-10 times of described thickness of grid oxide layer.
As the present invention further optimization scheme, the thickness of described grid oxic horizon is 0.01 μ m-0.04 μ m.
As the present invention further optimization scheme, the thickness of described ladder oxide layer is 0.04 μ m-0.2 μ m.
The invention also discloses the manufacture method of the N-type LDMOS of the active drift region structure of described step gates oxide layer, concrete steps are as follows:
Step 1: make the silica-base material of light doping on n type material or P-type material, resistivity is at 0.3ohmcm-40 ohmcm;
Step 2: form the N trap by injecting N-type impurity, annealing forms the N-type Impurity Distribution;
Step 3: the fabricating yard oxide layer, thickness is 0.3 μ m-1.0 μ m;
Step 4: make the ladder oxide layer, form the oxide layer of thickness between 0.04 μ m-0.2 μ m, by stopping of photoresist and not stopping of exposure position, be etched away the oxide layer of non-staircase areas, remain with the oxide layer that photoresist stops;
Step 5: make grid oxic horizon, form the oxide layer of thickness between 0.01 μ m-0.04 μ m;
Step 6: the grid deposit, the N-type polycrystalline that surface deposition is highly doped, through photoresist, exposure, etching, remove and do not need regional polysilicon, retains the polysilicon that is used for doing grid;
Step 7: make the drift region doping, by photoresist, stop the protection source electrode; By the Self-aligned etching ladder oxide layer of photoresist and polycrystalline, stay the drain electrode oxide layer of 0.02 μ m-0.05 μ m; Phosphorus impurities is injected in the polycrystalline autoregistration, and annealing forms the distribution of N-type impurity, and the concentration of impurity is 3-10 times of impurity concentration in the N trap, and junction depth is less than the junction depth of N trap;
Step 8: at an end of source electrode, by the polycrystalline autoregistration, inject p type impurity, then high temperature advances, and allows impurity form certain horizontal and vertical diffusion;
Step 9: the dense N-type zone that forms LDMOS source electrode and drain electrode by injecting N-type impurity;
Step 10: the dense p type island region territory that forms contact use in P type tagma by injecting p type impurity;
Step 11: the pyroprocess through excess temperature between 800 ℃-1000 ℃, the impurity that allows step 9, step 10 inject fully activates;
Step 12: in the surface deposition layer of oxide layer;
Step 13: the photoetching of contact hole, contact hole etching, expose and form ，Jiang hole, hole internal oxidation layer etching by photoresist, form the position that metal contacts with silicon;
Step 14: surface metalation, corrosion surface metal, at the surface deposition metal level, form electrode source electrode, the contacted place of grid.
The present invention adopts above technical scheme compared with prior art, have following technique effect: device architecture disclosed in this invention can be in the situation that do not change other parameters substantially, effectively weakened the surface field under polycrystalline termination, drain region, original active drift region LDMOS operating voltage has been improved to 20%.And obviously improved the safety operation area in the large electric current of device, large electric field situation, conducting resistance there is no increase.The element manufacturing of this structure only need to increase a photoetching on conventional manufacture craft, and the cost increase seldom.The processing technology of device is all very conventional process simultaneously, and technique is easily controlled, stable between batch.CMOS technique platform for the double grid oxidation of HLV compatible IC, can directly utilize the gate oxide of two kinds of different-thickness in platform to make this device, do not need to increase any operation.
The accompanying drawing explanation
Fig. 1 is the structural representation of a conventional oxygen drift region LDMOS,
Wherein: 1. the silica-base material of light doping, 2. N trap, 3. drift region doping, 4. ladder oxide layer, 5. polycrystalline, 6. grid oxic horizon, 7. dense N-type, 8. tagma, 9. dense P type, 10. dense N-type, 11. field oxides of inside, P type tagma of P type of inside, P type tagma.
Fig. 2 is the structural representation of conventional active drift region LDMOS,
Wherein: 1. the silica-base material of light doping, 2. N trap, 3. drift region doping, 5. polycrystalline, 6. grid oxic horizon, 7. dense N-type, 8. tagma, 9. dense P type, 10. dense N-type, 11. field oxides of inside, P type tagma of P type of inside, P type tagma.
Fig. 3 is the N-type LDMOS structural representation of the active drift region structure of step gates oxide layer of the present invention,
Wherein: 1. the silica-base material of light doping, 2. N trap, 3. drift region doping, 4. ladder oxide layer, 5. polycrystalline, 6. grid oxic horizon, 7. dense N-type, 8. tagma, 9. dense P type, 10. dense N-type, 11. field oxides of inside, P type tagma of P type of inside, P type tagma.
Embodiment
The N-type LDMOS of the active drift region structure of a kind of step gates oxide layer of the present invention has following part: the polycrystalline 5 on surface is the grid of LDMOS.N trap 2, drift region doping 3 and inner dense N-type 10 form the drain electrode of LDMOS.The tagma 8 of P type forms the channel region of LDMOS.The dense N-type 7(N+ of inside, P type tagma) form the source electrode of LDMOS.The dense P type 9(P+ of inside, P type tagma), with the doping of the same type of P type tagma, for P type tagma provides substrate electric potential, form the substrate terminal of LDMOS.Between polycrystalline and P type tagma, the silicon dioxide layer of a layer thickness between 0.01-0.04 μ m arranged, be the thin oxide layer 6 of grid of LDMOS.Under polycrystalline, near LDMOS, drain electrode has the silicon dioxide layer that one deck is thicker, and this layer thickness is between 0.04-0.2 μ m, and this layer of oxide layer is the ladder oxide layer 4 that the present invention introduces.Whole device can be made on the silica-base material of light doping of N-type or P type 1.
The device architecture that the present invention proposes is as Fig. 3, with the difference of the active drift region LDMOS of routine, be that thin gate oxide is become to the step gates oxide layer 4 that thickness is thicker than grid oxygen near the drain electrode part, this layer of oxide layer is thinner than field oxide, in the course of processing, be different from the LDMOS of an oxide structure, after being formed with source region, form, and with the polysilicon gate autoregistration.
Its manufacture method is when the LDMOS manufacturing gate oxide layers of the active drift region of routine, increase the oxidation of ladder oxide layer, then the ladder oxide layer near source terminal is removed in photoetching.Then be exactly the standard technology of conventional active drift region LDMOS.
Below in conjunction with accompanying drawing, technical scheme of the present invention is described in further detail:
The structural representation of a conventional oxygen drift region LDMOS and the structural representation of conventional active drift region LDMOS are respectively as shown in Figure 1 and Figure 2, both main differences are that the method that forms of the oxide layer of drift region is different, zone 4 as Fig. 1, the thick oxide layer that this part is 0.3-1 μ m is (because this part field oxidation technology that is integrated circuit technology is made, so be field oxide, polysilicon gate and field oxide will carry out alignment).Field oxygen drift region structure, due to the oxidation bed thickness under polycrystalline, voltage endurance is good; But active drift region structure, utilize the grid polycrystalline to cover the advantage on thin oxide layer, grid polycrystalline and thin oxide layer form autoregistration, can reduce chip size.When conducting, by adding the grid polycrystalline, the impurity concentration of the drift region under thin oxide layer is affected, can effectively reduce conducting resistance, so on state characteristic is better than an oxygen drift region structure.These two kinds of structures have application very widely in integrated circuit technology at present.For the technique platform below 30V, there is very large advantage active drift region.For the technique more than 40V, the inferior position that active drift region is withstand voltage just slowly shows, and not as an oxygen drift region structure is widely used, and what generally adopt is an oxygen drift region structure.
The N-type LDMOS structural representation of the active drift region structure of step gates oxide layer of the present invention as shown in Figure 3, with the difference of the active drift region LDMOS of routine, be that thin gate oxide is become to the step gates oxide layer 4 that thickness is thicker than grid oxygen near the drain electrode part, this layer of oxide layer is thinner than field oxide, in the course of processing, be different from the LDMOS of an oxide structure, after being formed with source region, form, and with the polysilicon gate autoregistration.Its manufacture method is when the LDMOS manufacturing gate oxide layers of the active drift region of routine, increase the oxidation of ladder oxide layer, then the ladder oxide layer near source terminal is removed in photoetching.Then be exactly the standard technology of conventional active drift region LDMOS.
Form N trap 2 on described substrate 1, first do the thickest oxide layer field oxygen 11 on surface, then make drain-drift region doping NG layer 3, then do ladder oxide layer 4 and gate oxide 6.Then make the polycrystal layer 5 of grid, then be constructed for forming the P type tagma 8 of raceway groove.Finally by the mode of implantation annealing, form the contact area 9 in 10, source region, drain region 7 and P type tagma.
Above-mentioned manufacture method comprises the steps:
1. feed intake: for the N-type LDMOS of source drift region structure, can also can above make at P type silicon materials (can be material piece, can be also the epitaxial loayer of doing on material piece) at n type material, resistivity is at 0.3ohmcm-40 ohmcm.
2.N trap forms: by injecting N-type impurity, then annealing forms the distribution of the N-type impurity of certain junction depth.The degree of depth of N trap greatly about 2 μ m between 15 μ m, make different withstand voltage N trap junction depths corresponding to LDMOS.Withstand voltage higher junction depth requires darker.
3. an oxidation: at the surface deposition silicon nitride, the silicon nitride of the zone that form an oxygen (place) is removed.Through high-temperature oxydation, there is the zone of silicon nitride to form protection, can not be oxidized.Just form the oxide layer of thickness at 0.3-1.0 μ m in place, on the spot the oxygen layer.Then remove silicon nitride, the active area of device area so just occurs doing and do not do device Chang Yang district.
4. the ladder oxide layer is made: the full wafer oxidation forms the oxide layer of thickness between 0.04-0.2 μ m.The thickness of oxide layer should be chosen between 1.3 times to 10 times of thin oxide gate layer thickness.By stopping of photoresist and not stopping of exposure position, be etched away the oxide layer of non-staircase areas again, wherein, have the oxide layer that photoresist stops to be retained.
5. thin gate oxide is made: all oxidations form the oxide layer of thickness between 0.01-0.04 μ m, i.e. thin gate oxide.
6. grid deposit: the polycrystalline that surface deposition is highly doped is generally N-type.Then by photoresist, exposure, etching, remove and do not need regional polysilicon, stay for doing the polysilicon of grid.
7.N type drift region doping: by photoresist, stop, the protection source electrode, by drain electrode and out exposed near the polysilicon of drain electrode.First, by the Self-aligned etching ladder oxide layer of photoresist and polycrystalline, stay the drain electrode oxide layer of 0.02-0.05 μ m.Phosphorus impurities is injected in the polycrystalline autoregistration again, and then annealing forms the distribution of the N-type impurity of certain junction depth.The concentration of impurity is 3-10 times of N trap concentration, and junction depth is less than the junction depth of N trap.The auxiliary N trap layer of this level improves withstand voltage, reduces conducting resistance simultaneously.
8.P the type tagma is injected, diffusion: at source electrode one end, by the polycrystalline autoregistration, inject p type impurity, then high temperature advances, and allows impurity form certain horizontal and vertical diffusion.By horizontal proliferation, P type tagma is deep into the part under polycrystalline, forms channel region.
9.N+ source electrode, drain electrode: the N+ zone that forms LDMOS source electrode and drain electrode by injecting N-type impurity.
10.P+ substrate contact forms: the P+ zone that forms contact use in P type tagma by injecting p type impurity.
11. impurity activation: advanced the pyroprocess of a temperature between 800 ℃-1000 ℃, the impurity that allows step 9, step 10 inject fully activates.
12. surface oxide layer deposit: in the surface deposition layer of oxide layer, purpose is in order to form the hole of step 13.
13. the contact hole photoetching, contact hole etching: by photoresist, exposing, to form ，Jiang hole, hole internal oxidation layer etching clean, forms the position that metal contacts with silicon.
14. surface metalation, the corrosion surface metal: at the surface deposition metal level, purpose is the place that forms electrode source electrode, gate contact.
The foregoing is only preferred embodiment of the present invention, in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of doing, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.

Claims (6)

1. the N-type LDMOS of the active drift region structure of step gates oxide layer, comprise the dense N-type, P type tagma, the dense P type of inside, P type tagma, dense N-type, field oxide of silica-base material, N trap, drift region doping, ladder oxide layer, polycrystalline, grid oxic horizon, the inside, P type tagma of light doping; The silica-base material of described light doping is bottom basis; The upper strata of the silica-base material of light doping is the N trap; The upper strata of N trap comprises that polycrystalline forms the grid of LDMOS, and N trap, drift region doping and dense N-type form the drain electrode of LDMOS, and the tagma of P type forms the channel region of LDMOS, and the dense N-type of inside, P type tagma forms the source electrode of LDMOS; The dense P type of inside, P type tagma and the doping of P type tagma, the substrate terminal of formation LDMOS; It is characterized in that: described grid oxic horizon is arranged between polycrystalline and P type tagma, described ladder oxide layer is arranged between the drain electrode of polycrystalline and LDMOS, the thickness of ladder oxide layer is thicker than grid oxic horizon, and the grid autoregistration of the LDMOS of ladder oxide layer and described polycrystalline formation.
2. the N-type LDMOS of the active drift region structure of a kind of step gates oxide layer as claimed in claim 1, it is characterized in that: described ladder oxide layer and grid oxic horizon are silicon dioxide layer.
3. the N-type LDMOS of the active drift region structure of a kind of step gates oxide layer as claimed in claim 1 is characterized in that: the thickness of described ladder oxide layer be described thickness of grid oxide layer 1.3-10 doubly.
4. the N-type LDMOS of the active drift region structure of a kind of step gates oxide layer as claimed in claim 1, it is characterized in that: the thickness of described grid oxic horizon is 0.01 μ m-0.04 μ m.
5. the N-type LDMOS of the active drift region structure of a kind of step gates oxide layer as claimed in claim 1, it is characterized in that: the thickness of described ladder oxide layer is 0.04 μ m-0.2 μ m.
6. the manufacture method of the N-type LDMOS of the active drift region structure of step gates oxide layer as claimed in claim 1, is characterized in that, concrete steps are as follows:
Step 1: make the silica-base material of light doping on n type material or P-type material, resistivity is 0.3ohmcm to 40 ohmcm;
Step 2: form the N trap by injecting N-type impurity, annealing forms the N-type Impurity Distribution;
Step 3: the fabricating yard oxide layer, thickness is 0.3 μ m-1.0 μ m;
Step 4: make the ladder oxide layer, form the oxide layer of thickness between 0.04 μ m-0.2 μ m, by stopping of photoresist and not stopping of exposure position, be etched away the oxide layer of non-staircase areas, remain with the oxide layer that photoresist stops;
Step 5: make grid oxic horizon, form the oxide layer of thickness between 0.01 μ m-0.04 μ m;
Step 6: the grid deposit, the N-type polycrystalline that surface deposition is highly doped, through photoresist, exposure, etching, remove and do not need regional polysilicon, retains the polysilicon that is used for doing grid;
Step 7: make the drift region doping, by photoresist, stop the protection source electrode; By the Self-aligned etching ladder oxide layer of photoresist and polycrystalline, stay the drain electrode oxide layer of 0.02 μ m-0.05 μ m; Phosphorus impurities is injected in the polycrystalline autoregistration, and annealing forms the distribution of N-type impurity, and the concentration of impurity is 3-10 times of impurity concentration in the N trap, and junction depth is less than the junction depth of N trap;
Step 8: at an end of source electrode, by the polycrystalline autoregistration, inject p type impurity, then high temperature advances, and allows impurity form horizontal and vertical diffusion;
Step 9: the dense N-type zone that forms LDMOS source electrode and drain electrode by injecting N-type impurity;
Step 10: the dense p type island region territory that forms contact use in P type tagma by injecting p type impurity;
Step 11: the high-temperature heating process through excess temperature between 800 ℃-1000 ℃, activate the impurity injected in step 9, step 10;
Step 12: surface deposition oxide layer;
Step 13: the photoetching of contact hole, contact hole etching, expose and form ，Jiang hole, hole internal oxidation layer etching by photoresist, form the position that metal contacts with silicon;
Step 14: surface metalation, corrosion surface metal, at the surface deposition metal level, form the contact point of electrode source electrode, grid.
CN201310437804.3A 2013-09-24 2013-09-24 N type LDMOS of ladder gate oxide layer and active drift region structure and manufacturing method of N type LDMOS Pending CN103489916A (en)

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CN105448988A (en) * 2014-08-22 2016-03-30 无锡华润上华半导体有限公司 LDMOS device and manufacture method thereof
CN105742169A (en) * 2014-12-30 2016-07-06 格罗方德半导体公司 Tapered Gate Oxide In Ldmos Devices
CN110544701A (en) * 2019-08-30 2019-12-06 德淮半导体有限公司 Semiconductor structure and forming method thereof
CN110690290A (en) * 2019-09-18 2020-01-14 华东师范大学 Nano-sheet ring gate field effect transistor with asymmetric gate oxide structure
CN111192916A (en) * 2019-05-31 2020-05-22 深圳方正微电子有限公司 Novel super-barrier power device and manufacturing method thereof
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Application publication date: 20140101