CN108666363B - LDMOS device and manufacturing method thereof - Google Patents

LDMOS device and manufacturing method thereof Download PDF

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CN108666363B
CN108666363B CN201810323121.8A CN201810323121A CN108666363B CN 108666363 B CN108666363 B CN 108666363B CN 201810323121 A CN201810323121 A CN 201810323121A CN 108666363 B CN108666363 B CN 108666363B
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drift region
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silicon epitaxial
epitaxial layer
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CN108666363A (en
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许昭昭
钱文生
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors

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  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention discloses an LDMOS device, which comprises: a drift region and a body region formed in selected regions of the first silicon epitaxial layer; drift region field oxide is formed in selected regions of the drift region. And a germanium-silicon epitaxial layer is formed on the surface of the body region, the germanium-silicon epitaxial layer also extends to the surface of the drift region outside the field oxygen of the drift region, the mobility of carriers is improved by utilizing the germanium-silicon epitaxial layer, so that the channel resistance and the drift region resistance are reduced, and the bottom of the field oxygen of the drift region penetrates through the germanium-silicon epitaxial layer, so that the influence of the germanium-silicon epitaxial layer on the breakdown voltage of the device is eliminated. The invention also discloses a manufacturing method of the LDMOS device. The invention can reduce the on-resistance of the device and simultaneously keep the breakdown voltage of the device.

Description

LDMOS device and manufacturing method thereof
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to an LDMOS device; the invention also relates to a manufacturing method of the LDMOS device.
Background
A Double-diffused MOS (Double-diffused MOS) is widely used in a power management circuit at present because of its characteristics of high voltage resistance, high current driving capability, and extremely low power consumption. DMOS includes vertical double-diffused metal oxide semiconductor field effect transistors (VDMOS) and LDMOS (LDMOS), and in LDMOS devices, on-resistance is an important indicator. In the BCD process, although the LDMOS and the CMOS are integrated in the same chip, due to the requirements of high withstand voltage, low characteristic resistance and on-resistance, on the premise that the conditions of the background region and the drift region of the LDMOS are shared with the existing process conditions of the CMOS, the on-resistance and the Breakdown Voltage (BV) are contradictory and compromised, and often cannot meet the requirements of the application of the switching tube, and the on-resistance is usually expressed by the characteristic resistance (Rsp). Therefore, in order to obtain the same off-state breakdown voltage (offBV), Rsp should be reduced as much as possible to improve the competitiveness of the product.
FIG. 1 is a schematic diagram of a conventional LDMOS device; taking an N-type device as an example, the conventional LDMOS device includes:
the semiconductor device comprises an N-type first silicon epitaxial layer 2, wherein a P-type drift region 4 and an N-type body region 5 are formed in a selected region of the first silicon epitaxial layer 2; the drift region 4 and the body region 5 are laterally separated by a distance.
A P-type heavily doped first buried layer 1 is formed at the bottom of the first silicon epitaxial layer 2; the first buried layer 1 is formed on the surface of the silicon substrate. Typically, the silicon substrate is a silicon substrate and the first silicon epitaxial layer 2 is a silicon epitaxial layer.
Drift region field oxide 3 is formed in selected regions of the drift region 4.
A gate structure formed by overlapping a gate dielectric layer such as a gate oxide layer 6 and a polysilicon gate 7 is formed on the surface of the body region 5, and the surface of the body region 5 covered by the polysilicon gate 7 is used for forming a channel.
The second side of the gate dielectric layer 6 is in contact with the first side of the drift region field oxide 3, and the second side of the polysilicon gate 7 extends to the surface of the drift region field oxide 3.
A source region 8a is formed on the surface of the body region 5 and the second side of the source region 8a and the first side of the polysilicon gate 7 are self-aligned.
A drain region 8b is formed in the drift region 4 and a first side of the drain region 8b and a second side of the drift region field oxide 3 are self-aligned.
An N-type heavily doped body lead-out region 9 is further formed on the surface of the body region 5, and the body lead-out region 9 is in contact with the side face of the first side of the source region 8 a. The body pull-out region 9 and the source region 8a will be connected to a source electrode composed of a front metal layer through the same contact hole.
The drain region 8b is connected to a drain electrode made of a front metal layer through a contact hole, and the polysilicon gate 7 is connected to a gate electrode made of a front metal layer through a contact hole.
In fig. 1, the drift region field oxide 3 is a structure recessed to a certain depth of the first silicon epitaxial layer 2, and typically, the drift region field oxide 3 is formed by a Shallow Trench Isolation (STI) process or a local oxidation process (LOCOS). The step of forming the drift region field oxide 3 by using the STI process comprises the following steps: a) etching silicon to form a shallow trench, b) performing thermal oxidation to form an oxide layer on the surface of the shallow trench, c) filling the oxide layer into the trench, and d) forming the drift region field oxide 3 by chemical mechanical polishing. And the LOCOS process forms the drift region field oxide 3 by oxidizing the local silicon. In the STI and LOCOS processes, the thicker the drift region field oxide 3 is, the more favorable the improvement of OffBV and the reduction of off-state leakage current (Ioff) of the device are, but the more unfavorable the reduction of Rsp of the device is. Conversely, the thinner the drift region field oxide 3, the better the Rsp reduction, but the lower the OffBV and the higher the leakage Ioff.
In the prior device shown in fig. 1, the doping concentration of the drift region 4 has often been optimized to reduce the resistance of the drift region in order to reduce the Rsp of the device. In the low-voltage segment of the LDMOS device, the channel resistance of the device has a large proportion in Rsp, and in order to further reduce the Rsp of the device, the channel resistance of the device needs to be further optimized.
Disclosure of Invention
The invention aims to provide an LDMOS device, which can reduce the on-resistance of the device and simultaneously keep the breakdown voltage of the device. Therefore, the invention also provides a manufacturing method of the LDMOS device.
In order to solve the above technical problem, the LDMOS device provided by the present invention includes:
the semiconductor device comprises a first silicon epitaxial layer of a second conduction type, wherein a drift region of the first conduction type and a body region of the second conduction type are formed in a selected region of the first silicon epitaxial layer; the drift region and the body region are laterally contacted or separated by a distance.
Drift region field oxide is formed in selected regions of the drift region.
And a gate structure formed by overlapping a gate dielectric layer and a polysilicon gate is formed on the surface of the body region, and the surface of the body region covered by the polysilicon gate is used for forming a channel.
And the second side of the gate dielectric layer is contacted with the first side of the drift region field oxide, and the second side of the polysilicon gate extends to the surface of the drift region field oxide.
The source region is formed on the surface of the body region, and the second side of the source region and the first side of the polysilicon gate are self-aligned.
A drain region is formed in the drift region and a first side of the drain region and a second side of the drift region field oxide are self-aligned.
And a germanium-silicon epitaxial layer is formed on the surface of the body region, the germanium-silicon epitaxial layer also extends to the surface of the drift region outside the field oxygen of the drift region, the germanium-silicon epitaxial layer is utilized to improve the mobility of carriers so as to reduce channel resistance and drift region resistance, and the bottom of the field oxygen of the drift region penetrates through the germanium-silicon epitaxial layer so as to eliminate the influence of the germanium-silicon epitaxial layer on the breakdown voltage of the device.
In a further improvement, a first buried layer with heavy doping of a first conductivity type is formed at the bottom of the first silicon epitaxial layer; the first buried layer is formed on the surface of the silicon substrate.
In a further improvement, the drift region field oxide is shallow trench field oxide.
In a further improvement, the junction depth of the source region and the drain region is greater than the thickness of the germanium-silicon epitaxial layer.
The further improvement is that the gate dielectric layer is a gate oxide layer.
In a further improvement, a body lead-out region heavily doped with the second conductivity type is further formed on the surface of the body region, and the body lead-out region is in contact with the side face of the first side of the source region.
The LDMOS device is an N-type device, the first conduction type is an N-type device, and the second conduction type is a P-type device; or the LDMOS device is a P-type device, the first conduction type is a P-type device, and the second conduction type is an N-type device.
In order to solve the above technical problem, the method for manufacturing the LDMOS device provided by the present invention includes the following steps:
step one, providing a first silicon epitaxial layer of a second conduction type, and forming a germanium-silicon epitaxial layer on the surface of the first silicon epitaxial layer.
And secondly, forming drift region field oxide in the selected region, wherein the depth of the drift region field oxide is greater than the thickness of the germanium-silicon epitaxial layer.
And thirdly, forming a drift region in the germanium-silicon epitaxial layer and the first silicon epitaxial layer of the selected region by adopting a first conductive type ion implantation process, wherein the junction depth of the drift region is greater than the thickness of the field oxygen of the drift region, and the field oxygen of the drift region is positioned in a partial region of the drift region.
And step four, sequentially forming a gate dielectric layer and a first polycrystalline silicon layer.
And fifthly, photoetching for the first time to define the side position of the first side of the polysilicon gate, etching the first polysilicon layer and the gate dielectric layer in sequence to form the side of the first side of the polysilicon gate and expose the surface of the germanium-silicon epitaxial layer outside the side of the first side of the polysilicon gate.
And sixthly, forming a body region by adopting a second conductive type ion implantation process, wherein the body region is positioned in the germanium-silicon epitaxial layer and the first silicon epitaxial layer outside the side surface of the first side of the polysilicon gate, the body region extends to the bottom of the first side of the polysilicon gate after annealing, and the surface of the body region covered by the polysilicon gate is used for forming a channel.
Seventhly, photoetching for the second time to define the position of the side face of the second side of the polysilicon gate, etching the first polysilicon layer to form the side face of the second side of the polysilicon gate and form the polysilicon gate, and overlapping the gate dielectric layer and the polysilicon gate to form a gate structure; a second side of the polysilicon gate extends onto a surface of the drift region field oxide.
Eighthly, performing first conductive type heavy doping ion implantation and simultaneously forming a source region and a drain region, wherein the source region is formed on the surface of the body region, and the second side of the source region and the first side of the polysilicon gate are self-aligned; a drain region is formed in the drift region and a first side of the drain region and a second side of the drift region field oxide are self-aligned.
In a further improvement, a first buried layer heavily doped with a first conductivity type is formed at the bottom of the first silicon epitaxial layer in the step one; the first buried layer is formed on the surface of the silicon substrate.
The further improvement is that in the second step, shallow trench isolation technology is adopted to form the drift region field oxide, and the method comprises the following sub-steps:
and 21, sequentially forming hard mask layers on the surfaces of the germanium-silicon epitaxial layers, and defining a forming region of the field oxygen of the drift region by photoetching.
And step 22, removing the hard mask layer in the drift region field oxygen forming region.
And step 23, etching the germanium-silicon epitaxial layer and the first silicon epitaxial layer in the drift region field oxygen forming region by taking the hard mask layer as a mask to form a shallow trench.
And 24, filling an oxidation layer in the shallow trench, removing the oxidation layer outside the shallow trench and the hard mask layer, and forming the field oxygen of the drift region by the oxidation layer filled in the shallow trench.
In a further improvement, in step 21, the hard mask layer is formed by stacking a first oxide layer and a second nitride layer.
In a further improvement, the junction depth of the source region and the drain region is greater than the thickness of the germanium-silicon epitaxial layer.
The further improvement is that the gate dielectric layer is a gate oxide layer.
In a further improvement, the method further comprises the following step after the step eight:
and ninthly, carrying out second conductive type heavy doping ion implantation to form a body extraction region on the surface of the body region, wherein the body extraction region is contacted with the side surface of the first side of the source region.
The LDMOS device is an N-type device, the first conduction type is an N-type device, and the second conduction type is a P-type device; or the LDMOS device is a P-type device, the first conduction type is a P-type device, and the second conduction type is an N-type device.
According to the invention, the germanium-silicon epitaxial layer is formed on the surface of the body region, and the germanium-silicon epitaxial layer is utilized to improve the mobility of carriers, so that the channel resistance can be reduced; meanwhile, the germanium-silicon epitaxial layer also extends to the surface of the drift region, so that the resistance of the drift region can be reduced, and finally the on-resistance can be reduced; meanwhile, the bottom of the field oxygen of the drift region penetrates through the germanium-silicon epitaxial layer, so that the drift region at the bottom of the field oxygen of the drift region is still formed in the first silicon epitaxial layer, the defect that the breakdown critical electric field at the bottom of the field oxygen of the drift region is reduced by the germanium-silicon epitaxial layer can be eliminated, the influence of the germanium-silicon epitaxial layer on the breakdown voltage of the device can be eliminated, and the breakdown voltage of the device can be well maintained.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIG. 1 is a schematic diagram of a conventional LDMOS device;
FIG. 2 is a schematic structural diagram of an LDMOS device according to an embodiment of the invention;
fig. 3A-3D are schematic diagrams of device structures in various steps of a method for manufacturing an LDMOS device according to an embodiment of the invention.
Detailed Description
FIG. 2 is a schematic diagram of an LDMOS device according to an embodiment of the present invention; the LDMOS device of the embodiment of the invention comprises:
a first silicon epitaxial layer 102 of a second conductivity type, wherein a first buried layer 101 heavily doped with a first conductivity type is formed at the bottom of the first silicon epitaxial layer 102; the first buried layer 101 is formed on the surface of the silicon substrate. A drift region 104 of a first conductivity type and a body region 105 of a second conductivity type are formed in selected regions of the first silicon epitaxial layer 102; the drift region 104 and the body region 105 are laterally contacted or separated by a distance.
Drift region field oxide 103 is formed in selected regions of the drift region 104. The drift region field oxide 103 is a shallow trench field oxide.
A gate structure formed by overlapping a gate dielectric layer 106 and a polysilicon gate 107 is formed on the surface of the body region 105, and the surface of the body region 105 covered by the polysilicon gate 107 is used for forming a channel.
The second side of the gate dielectric layer 106 is in contact with the first side of the drift region field oxide 103, and the second side of the polysilicon gate 107 extends to the surface of the drift region field oxide 103. The gate dielectric layer 106 is a gate oxide layer.
A source region 108a is formed on the surface of the body region 105 and a second side of the source region 108a and a first side of the polysilicon gate 107 are self-aligned.
A drain region 108b is formed in the drift region 104 and a first side of the drain region 108b and a second side of the drift region field oxide 103 are self-aligned. The junction depth of the source region 108a and the drain region 108b is greater than the thickness of the silicon germanium epitaxial layer 110.
A body lead-out region 109 heavily doped with the second conductivity type is further formed on the surface of the body region 105, and the body lead-out region 109 is in contact with the side surface of the first side of the source region 108 a.
A silicon germanium epitaxial layer 110 is formed on the surface of the body region 105, the silicon germanium epitaxial layer 110 further extends to the surface of the drift region 104 outside the drift region field oxide 103, the silicon germanium epitaxial layer 110 is utilized to improve the mobility of carriers so as to reduce the channel resistance and the drift region 104 resistance, and the bottom of the drift region field oxide 103 penetrates through the silicon germanium epitaxial layer 110 so as to eliminate the influence of the silicon germanium epitaxial layer 110 on the breakdown voltage of the device.
In the embodiment of the invention, the LDMOS device is an N-type device, the first conduction type is an N type, and the second conduction type is a P type. In other embodiments can also be: the LDMOS device is a P-type device, the first conduction type is a P type, and the second conduction type is an N type.
According to the embodiment of the invention, the germanium-silicon epitaxial layer 110 is formed on the surface of the body region 105, so that the mobility of carriers is improved by utilizing the germanium-silicon epitaxial layer 110, and the channel resistance can be reduced; meanwhile, the germanium-silicon epitaxial layer 110 of the embodiment of the invention also extends to the surface of the drift region 104, so that the resistance of the drift region 104 can be reduced, and finally the on-resistance can be reduced; meanwhile, the bottom of the drift region field oxide 103 of the embodiment of the invention passes through the silicon germanium epitaxial layer 110, so that the drift region 104 at the bottom of the drift region field oxide 103 is still formed in the first silicon epitaxial layer 102, thereby eliminating the defect that the germanium silicon epitaxial layer 110 reduces the breakdown critical electric field at the bottom of the drift region field oxide 103, eliminating the influence of the silicon germanium epitaxial layer 110 on the breakdown voltage of the device, and well maintaining the breakdown voltage of the device.
As shown in fig. 3A to fig. 3D, which are schematic device structures in the steps of the method for manufacturing the LDMOS device according to the embodiment of the present invention, the method for manufacturing the LDMOS device according to the embodiment of the present invention includes the following steps:
step one, as shown in fig. 3A, a first silicon epitaxial layer 102 of a second conductivity type is provided, and a silicon germanium epitaxial layer 110 is formed on a surface of the first silicon epitaxial layer 102.
A first buried layer 101 with a first conductive type heavy doping is formed at the bottom of the first silicon epitaxial layer 102; the first buried layer 101 is formed on the surface of the silicon substrate.
And step two, forming a drift region field oxide 103 in the selected region, wherein the depth of the drift region field oxide 103 is greater than the thickness of the germanium-silicon epitaxial layer 110.
In the embodiment of the present invention, the forming of the drift region field oxide 103 by using a shallow trench isolation process includes the following sub-steps:
step 21, as shown in fig. 3A, sequentially forming a hard mask layer on the surface of the sige epitaxial layer 110, and defining a formation region of the drift region field oxide 103 by photolithography. The hard mask layer is formed by stacking a first oxide layer 111 and a second nitride layer 112.
Step 22, as shown in fig. 3B, the hard mask layer in the drift region field oxide 103 formation region is removed.
Step 23, as shown in fig. 3B, etching the germanium-silicon epitaxial layer 110 and the first silicon epitaxial layer 102 in the formation region of the drift region field oxide 103 with the hard mask layer as a mask to form a shallow trench.
Step 24, as shown in fig. 3B, an oxide layer is filled in the shallow trench.
As shown in fig. 3C, the oxide layer outside the shallow trench and the hard mask layer are removed, and the oxide layer filled in the shallow trench constitutes the drift region field oxide 103. Typically, a Chemical Mechanical Polishing (CMP) process is used to remove the oxide layer and the hard mask layer outside the shallow trench and to make the drift region field oxide 103 and the surface outside the shallow trench even.
Step three, as shown in fig. 3C, a drift region 104 is formed in the germanium-silicon epitaxial layer 110 and the first silicon epitaxial layer 102 in a selected region by using a first conductivity type ion implantation process, a junction depth of the drift region 104 is greater than a thickness of the drift region field oxide 103, and the drift region field oxide 103 is located in a partial region of the drift region 104.
Step four, as shown in fig. 3D, a gate dielectric layer 106 and a first polysilicon layer 107 are sequentially formed. The gate dielectric layer 106 is a gate oxide layer.
Step five, as shown in fig. 3D, performing a first photolithography to define a side position of the first side of the polysilicon gate 107, sequentially etching the first polysilicon layer and the gate dielectric layer 106 to form a side surface of the first side of the polysilicon gate 107, and exposing the surface of the germanium-silicon epitaxial layer 110 outside the side surface of the first side of the polysilicon gate 107.
Step six, as shown in fig. 3D, a second conductive type ion implantation process is adopted to form a body region 105, the body region 105 is located in the germanium-silicon epitaxial layer 110 and the first silicon epitaxial layer 102 outside the side surface of the first side of the polysilicon gate 107, the body region 105 extends to the bottom of the first side of the polysilicon gate 107 after annealing, and the surface of the body region 105 covered by the polysilicon gate 107 is used for forming a channel.
Seventhly, as shown in fig. 3D, performing second photolithography to define the position of the side surface of the second side of the polysilicon gate 107, etching the first polysilicon layer to form the side surface of the second side of the polysilicon gate 107 and form the polysilicon gate 107, and overlapping the gate dielectric layer 106 and the polysilicon gate 107 to form a gate structure; the second side of the polysilicon gate 107 extends onto the surface of the drift region field oxide 103.
Step eight, as shown in fig. 2, performing first conductivity type heavily doped ion implantation while forming a source region 108a and a drain region 108b, where the source region 108a is formed on the surface of the body region 105 and a second side of the source region 108a and a first side of the polysilicon gate 107 are self-aligned; a drain region 108b is formed in the drift region 104 and a first side of the drain region 108b and a second side of the drift region field oxide 103 are self-aligned.
The junction depth of the source region 108a and the drain region 108b is greater than the thickness of the silicon germanium epitaxial layer 110.
Step eight is followed by the step of:
and ninthly, performing second conductive type heavily doped ion implantation to form a body extraction region 109 on the surface of the body region 105, wherein the body extraction region 109 is in contact with the side surface of the first side of the source region 108 a.
In the method of the embodiment of the invention, the LDMOS device is an N-type device, the first conduction type is an N-type device, and the second conduction type is a P-type device. In other embodiments the method can also be: the LDMOS device is a P-type device, the first conduction type is a P type, and the second conduction type is an N type.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.

Claims (11)

1. An LDMOS device, comprising:
the semiconductor device comprises a first silicon epitaxial layer of a second conduction type, wherein a drift region of the first conduction type and a body region of the second conduction type are formed in a selected region of the first silicon epitaxial layer; the drift region and the body region are laterally contacted or separated by a distance;
forming drift region field oxide in selected regions of the drift region;
a grid structure formed by overlapping a grid dielectric layer and a polysilicon grid is formed on the surface of the body region, and the surface of the body region covered by the polysilicon grid is used for forming a channel;
the second side of the gate dielectric layer is in contact with the first side of the drift region field oxide, and the second side of the polysilicon gate extends to the surface of the drift region field oxide;
the source region is formed on the surface of the body region, and the second side of the source region and the first side of the polysilicon gate are self-aligned;
the drain region is formed in the drift region, and a first side of the drain region and a second side of the drift region field oxide are self-aligned;
a germanium-silicon epitaxial layer is formed on the surface of the body region, the germanium-silicon epitaxial layer also extends to the surface of the drift region outside the field oxygen of the drift region, the germanium-silicon epitaxial layer is utilized to improve the mobility of carriers so as to reduce the channel resistance and the drift region resistance, and the bottom of the field oxygen of the drift region penetrates through the germanium-silicon epitaxial layer so as to eliminate the influence of the germanium-silicon epitaxial layer on the breakdown voltage of the device;
a first buried layer with heavily doped first conductivity type is formed at the bottom of the first silicon epitaxial layer; the first buried layer is formed on the surface of the silicon substrate;
the junction depth of the source region and the drain region is larger than the thickness of the germanium-silicon epitaxial layer.
2. The LDMOS device of claim 1, wherein: the drift region field oxygen is shallow trench field oxygen.
3. The LDMOS device of claim 1, wherein: the gate dielectric layer is a gate oxide layer.
4. The LDMOS device of claim 1, wherein: and a body extraction region with a heavily doped second conductivity type is formed on the surface of the body region, and the body extraction region is contacted with the side surface of the first side of the source region.
5. The LDMOS device of any of claims 1-4, wherein: the LDMOS device is an N-type device, the first conduction type is an N type, and the second conduction type is a P type; or the LDMOS device is a P-type device, the first conduction type is a P-type device, and the second conduction type is an N-type device.
6. A method for manufacturing an LDMOS device is characterized by comprising the following steps:
providing a first silicon epitaxial layer of a second conduction type, and forming a germanium-silicon epitaxial layer on the surface of the first silicon epitaxial layer;
a first buried layer with heavily doped first conductivity type is formed at the bottom of the first silicon epitaxial layer; the first buried layer is formed on the surface of the silicon substrate;
secondly, forming drift region field oxide in the selected region, wherein the depth of the drift region field oxide is greater than the thickness of the germanium-silicon epitaxial layer;
forming a drift region in the germanium-silicon epitaxial layer and the first silicon epitaxial layer of the selected region by adopting a first conductive type ion implantation process, wherein the junction depth of the drift region is greater than the thickness of field oxygen of the drift region, and the field oxygen of the drift region is positioned in a partial region of the drift region;
forming a gate dielectric layer and a first polycrystalline silicon layer in sequence;
fifthly, photoetching for the first time to define the position of the side face of the first side of the polysilicon gate, sequentially etching the first polysilicon layer and the gate dielectric layer to form the side face of the first side of the polysilicon gate and expose the surface of the germanium-silicon epitaxial layer outside the side face of the first side of the polysilicon gate;
step six, forming a body region by adopting a second conductive type ion implantation process, wherein the body region is positioned in the germanium-silicon epitaxial layer and the first silicon epitaxial layer outside the side surface of the first side of the polysilicon gate, the body region extends to the bottom of the first side of the polysilicon gate after annealing, and the surface of the body region covered by the polysilicon gate is used for forming a channel;
seventhly, photoetching for the second time to define the position of the side face of the second side of the polysilicon gate, etching the first polysilicon layer to form the side face of the second side of the polysilicon gate and form the polysilicon gate, and overlapping the gate dielectric layer and the polysilicon gate to form a gate structure; a second side of the polysilicon gate extending onto a surface of the drift region field oxide;
eighthly, performing first conductive type heavy doping ion implantation and simultaneously forming a source region and a drain region, wherein the source region is formed on the surface of the body region, and the second side of the source region and the first side of the polysilicon gate are self-aligned; the drain region is formed in the drift region, and a first side of the drain region and a second side of the drift region field oxide are self-aligned;
the junction depth of the source region and the drain region is larger than the thickness of the germanium-silicon epitaxial layer.
7. The method of fabricating the LDMOS device of claim 6, wherein: in the second step, a shallow trench isolation process is adopted to form the drift region field oxide, and the method comprises the following sub-steps:
step 21, sequentially forming hard mask layers on the surfaces of the germanium-silicon epitaxial layers, and defining a formation region of field oxygen in a drift region by photoetching;
step 22, removing the hard mask layer in the drift region field oxygen forming region;
step 23, etching the germanium-silicon epitaxial layer and the first silicon epitaxial layer in the drift region field oxygen forming region by taking the hard mask layer as a mask to form a shallow trench;
and 24, filling an oxidation layer in the shallow trench, removing the oxidation layer outside the shallow trench and the hard mask layer, and forming the field oxygen of the drift region by the oxidation layer filled in the shallow trench.
8. The method of fabricating the LDMOS device of claim 7, wherein: in step 21, the hard mask layer is formed by overlapping a first oxide layer and a second nitride layer.
9. The method of fabricating the LDMOS device of claim 6, wherein: the gate dielectric layer is a gate oxide layer.
10. The method of fabricating the LDMOS device of claim 6, wherein: step eight is followed by the step of:
and ninthly, carrying out second conductive type heavy doping ion implantation to form a body extraction region on the surface of the body region, wherein the body extraction region is contacted with the side surface of the first side of the source region.
11. A method of manufacturing an LDMOS device as claimed in any one of claims 6 to 10, characterized in that: the LDMOS device is an N-type device, the first conduction type is an N type, and the second conduction type is a P type; or the LDMOS device is a P-type device, the first conduction type is a P-type device, and the second conduction type is an N-type device.
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