KR101286707B1 - Tunneling field effect transistor having finfet structure of independent dual gates and fabrication method thereof - Google Patents

Tunneling field effect transistor having finfet structure of independent dual gates and fabrication method thereof Download PDF

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KR101286707B1
KR101286707B1 KR1020120052537A KR20120052537A KR101286707B1 KR 101286707 B1 KR101286707 B1 KR 101286707B1 KR 1020120052537 A KR1020120052537 A KR 1020120052537A KR 20120052537 A KR20120052537 A KR 20120052537A KR 101286707 B1 KR101286707 B1 KR 101286707B1
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gate
semiconductor
semiconductor substrate
region
oxide
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KR1020120052537A
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Korean (ko)
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박병국
김상완
최우영
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서강대학교산학협력단
서울대학교산학협력단
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66931—BJT-like unipolar transistors, e.g. hot electron transistors [HET], metal base transistors [MBT], resonant tunneling transistor [RTT], bulk barrier transistor [BBT], planar doped barrier transistor [PDBT], charge injection transistor [CHINT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/7311—Tunnel transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/737—Hetero-junction transistors
    • H01L29/7371—Vertical transistors
    • H01L29/7376—Resonant tunnelling transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates

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  • General Physics & Mathematics (AREA)
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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE: A tunneling field effect transistor having the FINFET structure of an independent dual gate and a fabrication method thereof are provided to increase the driving current without the loss of a separate area by forming a vertical dual gate structure which is electrically separated from both sides of a semiconductor pin. CONSTITUTION: A semiconductor substrate (10) includes a semiconductor pin (14) at a constant height. A p+ region (62) and an n+ region (64) are formed at both sides of the semiconductor substrate. The semiconductor pin is formed between the p+ region and the n+ region. A first gate (52) is formed between one side of the semiconductor pin and the n+ region. A second gate (54) is formed between the other side of the semiconductor pin and the p+ region. The material of the first gate is different from that of the second gate.

Description

TUNNELING FIELD EFFECT TRANSISTOR HAVING FINFET STRUCTURE OF INDEPENDENT DUAL GATES AND FABRICATION METHOD THEREOF}

The present invention relates to a tunneling field effect transistor, and more particularly, to a tunneling field effect transistor having vertical dual gates separated to operate independently on both sides of a fin and a method of manufacturing the same.

Until now, the trend of semiconductor technology has been to reduce the size of the device to improve its performance and increase the degree of integration. One of the most obstacles to this technological trend is the rapid increase in power consumption. To reduce power consumption, the driving voltage (V dd ) must be lowered. In addition, in order to maintain a high driving current in spite of a low driving voltage, the on / off state must be changed rapidly according to the change of the gate voltage.

Conventional MOSFETs use thermal emission as the basis for current driving, so the subthreshold swing has a physical limit that cannot be lowered below 60 mV / dec at room temperature.

However, since the tunneling field effect transistor (TFET) controls the flow of electrons and holes through the tunneling method, the output current may change significantly due to the minute change in the input voltage. That is, a slope below a low threshold voltage of 60 mV / dec or less, which is a limitation of the conventional MOSFET, is possible. In addition, since tunneling field effect transistors can be manufactured through a process similar to conventional CMOS, they can be used as an existing process infrastructure and are attracting attention as a next generation high energy efficient semiconductor device.

However, conventional tunneling field effect transistors have not yet been able to compare with MOSFETs. An important factor among the various reasons is that it is difficult to realize a sudden change in current due to low driving current and gate voltage.

1 and 3 show a band diagram from the source 130 to the drain 120 in the structure and the off state of the conventional general n-channel tunneling field effect transistor, respectively, FIG. 2 shows the gate 300 in the structure of FIG. When a driving voltage is applied to the channel 122, a channel 122 is formed under the gate insulating layer 200 to form a pn junction between the source 130 and the channel 122, and the tunneling current flowing through the pn junction becomes the driving current 320. FIG. 4 shows a band diagram from the source 130 to the drain 120 when the driving current is applied to the gate 300 as shown in FIG. 2, that is, when the driving current flows.

As can be seen from FIGS. 3 and 4, in the n-channel tunneling field effect transistor, a valence band (Ev) of the source 130 and a conduction band (Vv) of the channel region 110 may be used in order for the driving current by tunneling to flow. The conduction band (Ec) should be lined up, and the narrower the tunneling band width, the higher the probability of tunneling, which can increase the driving current. Therefore, in order to change the current rapidly according to the gate voltage, it is necessary to have a sufficiently small tunneling band width at the moment when the energy bands are arranged in a line.

However, in the conventional general tunneling field effect transistor as shown in FIG. 1, it is difficult to obtain a sudden current change because the tunneling band width gradually decreases according to the gate voltage, and as a result, the reduction of the slope below the threshold voltage is limited. In addition, since the area of the pn junction where tunneling occurs is determined by the depth of the channel 122 affected by the gate, tunneling occurs in a thin region of several nm, and as a result, current driving capability is greatly reduced.

A representative example of the ideas proposed to solve the above problems is a tunneling field effect transistor having a horizontal dual gate structure shown in FIGS. 5 to 7 (Livio Lattanzio, et al., “Electron-Hole Bilayer Tunnel FET for Steep Subthreshold Swing and Improved ON Current, ”Proc., ESSDERC, 2011, pp. 259-262).

In the tunneling field effect transistors illustrated in FIGS. 5 to 7, two independent gates 1 and 2 (610, 612), 620, and 622 are formed vertically with a thin channel region 410 interposed therebetween. A voltage may be applied to the gate to form a pn junction in the extended n + region 422 and the p + region 432, and the thickness of the tunneling barrier may be defined as the thickness of the semiconductor material used as the channel region 410. As a result, the thickness of the tunneling barrier is gradually changed by the gate voltage in the existing structure, thereby obtaining a lower slope below the threshold voltage, and the overlapping portion of the gates 1 and 2 is determined as the tunneling junction area. Therefore, it has many advantages, such as increasing the current driving capability.

However, in the structure shown in FIG. 5, not only the vertical tunneling current 322 between the expanded n + region 422 and the p + region 432, but also between the p + source 430 and the expanded n + region 422. The left and right horizontal tunneling currents 321 and the right horizontal tunneling current 323 generated between the extended p + region 432 and the n + drain 420 exist at the left and right horizontal tunneling currents. The fields 321 and 323 have a problem of acting as off current, that is, leakage current. In order to solve the problem of the off current, as shown in FIG. 6, each gate 612 and 622 should be formed to be separated from the source 430 or the drain 420 by a predetermined distance. On both sides, the underlap regions 412 and 414 of the gates 1 and 2 612 and 622 are alternately present asymmetrically.

Therefore, when manufactured in the structure according to Figure 6, as shown in Figure 7, the effect of suppressing the left and right horizontal tunneling currents acting as a leakage current due to the presence of the asymmetric underlap region (412, 414) However, there is a problem that causes an increase in the overall device area, and there is a problem that the device can not be manufactured in a self-align method due to the asymmetry of the underlap region (412, 414).

SUMMARY OF THE INVENTION The present invention has been proposed to solve a problem of a conventional horizontal dual gate structure, and an object of the present invention is to provide a tunneling field effect transistor having a vertical dual gate structure separated from each other so as to operate independently on both sides of a semiconductor fin and a method of manufacturing the same. It is done.

In order to achieve the above object, the tunneling field effect transistor according to the present invention comprises a semiconductor substrate having a semiconductor fin of a predetermined height; A p + region and an n + region formed in the semiconductor substrate at a predetermined distance from both sides with the semiconductor fin interposed therebetween; A first gate formed between one side of the semiconductor fin and the n + region with a first gate insulating layer interposed therebetween; And a second gate formed to be electrically separated from the first gate with a second gate insulating layer interposed between the other side of the semiconductor fin and the p + region.

Here, the first gate and the second gate may be formed of different materials, and may be formed by doping different impurities into the semiconductor material or different doping concentrations from the same impurities.

More specifically, the first gate may be formed by doping with the same n-type impurity as the impurity doped in the n + region, and the second gate may be formed by doping with the same p-type impurity as the impurity doped in the p + region. have.

The height of the semiconductor fins determines the tunneling junction area.

In addition, the semiconductor fin and the semiconductor substrate may be formed of any one or more of silicon, silicon germanium, germanium, and a group 3-5 compound semiconductor material.

The first gate insulating film and the second gate insulating film may be formed of a silicon oxide film (SiO 2 ), a strontium oxide film (SrO), a silicon nitride film (Si 3 N 4 ), an aluminum oxide film (A1 2 O 3 ), and a magnesium oxide film (MgO). , Scandium oxide (Sc 2 O 3 ), gadolinium oxide (Gd 2 O 3 ), yttrium oxide (Y 2 O 3 ), samarium oxide (Sm 2 O 3 ), hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ) , Tantalum oxide layer Ta 2 O 5 , barium oxide layer BaO, and bismuth oxide layer Bi 2 O 3 .

On the other hand, the method of manufacturing a tunneling field effect transistor according to the present invention comprises a first step of forming a hard mask on a semiconductor substrate; Forming a sidewall spacer on one sidewall of the hard mask; A third step of anisotropically etching the semiconductor substrate by using the hard mask and the sidewall spacers as an etch mask to step toward one side; A fourth step of forming a first gate insulating layer on one side of the semiconductor substrate; Depositing a first gate material on the entire surface of the substrate and etching anisotropically to form a first gate with the first gate insulating layer interposed on one sidewall of the semiconductor substrate; A sixth step of forming a first conductivity type high concentration doped region in the semiconductor substrate to one side of the first gate by doping a first conductivity type impurity on the entire surface of the substrate; Depositing a dummy insulating film on the entire surface of the substrate and flattening the hard mask to be exposed; An eighth step of removing the hard mask and etching the other side of the semiconductor substrate by a predetermined depth using the sidewall spacer and the dummy insulating layer as an etching mask to form a semiconductor fin; A ninth step of forming a second gate insulating film on the other side of the semiconductor substrate on which the semiconductor fin is formed; Depositing a second gate material over the entire surface of the substrate and etching anisotropically to form a second gate with the second gate insulating layer interposed on the other side of the semiconductor substrate; And an eleventh step of forming a second conductivity type high concentration doped region in the semiconductor substrate to one side of the second gate by doping a second conductivity type impurity on the entire surface of the substrate.

Here, the first gate material and the second gate material may be materials having different work functions.

Further, the first gate material and the second gate material are semiconductor materials, and in the sixth step, the doping of the first conductivity type impurity is simultaneously doped into the first gate, and in the eleventh step, the second conductive material is doped. Doping of the type impurity may be simultaneously doped to the second gate.

The etching depths of the semiconductor substrate in the third and eighth steps are the same, and the first gate insulating film is formed in the fourth step and the second gate insulating film is formed in the ninth step. It can be done through.

The buffer layer is first formed on the semiconductor substrate before the first step, the hard mask is formed on the buffer layer, and the hard mask and the sidewall spacer are exposed to one side when the semiconductor substrate is etched in the third step. The buffer layer may be removed by etching first.

The present invention has a vertical dual gate structure in which first and second gates are formed to be electrically separated from both sides of the semiconductor fin, and thus, there is a remarkable difference in the following effects as compared to the conventional horizontal dual gate structure.

First, there is no need for a separate underlap region to suppress leakage current when off between the source / drain and adjacent gates, thus freeing up the device and freeing the process for an underlap region. Since it does not require a separate process for forming, there is an advantage of easy fabrication of the device.

Secondly, in the conventional horizontal dual gate structure, since the tunneling junction area is proportional to the overlapping area between the horizontal gates, the horizontal gate length must be increased to improve the driving current due to tunneling. Although there was a trade-off relationship, the present invention has the advantage that the gate current is formed to face each other vertically, so that the tunneling junction area is proportional to the height of the semiconductor fin, so that the driving current can be improved without any additional area loss. have.

Third, since the conventional horizontal dual gate structure has an asymmetric dual gate structure due to the requirement of an underlap region, self-alignment is difficult during the manufacturing process, and a lot of additional additional processes are required to solve this problem. On the other hand, since the dual gate is formed symmetrically on both sides of the semiconductor fin, there is an advantage that a self-align process is possible.

Fourth, the first and second gates according to the present invention are formed of different materials to form a different work function or doped with different dopants (impurities), thereby causing horizontal band bending between vertical tunneling junction areas. And, by using this actively there is an advantage that can lower the driving voltage during operation of the device.

1 is a cross-sectional view showing the structure of a conventional planar n-channel tunneling field effect transistor.
2 illustrates that when a driving voltage is applied to the gate 300 in the structure of FIG. 1, a channel 122 is formed under the gate insulating layer 200 to generate a pn junction between the source 130 and the channel 122. Sectional view showing that the tunneling current flowing through the drive current 320.
3 and 4 are band diagrams illustrating energy level changes from the source 130 to the drain 120 in the Off state and the On state, respectively, in the structure of FIG. 1.
5 is a cross-sectional view showing the structure of a tunneling field effect transistor having a conventional horizontal dual gate without an underlap region.
6 and 7 are cross-sectional views illustrating a structure of a tunneling field effect transistor having a conventional horizontal dual gate having an underlap region.
8 is a cross-sectional view illustrating a structure of a tunneling field effect transistor having a vertical dual gate finFET structure according to an embodiment of the present invention.
FIG. 9 illustrates an n + region 63 extended below the first and second gate insulating layers 22 and 24 when a driving voltage is applied to the first and second gates 52 and 54, which are dual gates, in the structure of FIG. 8. A channel is formed in the p + region 65 and a sectional view showing that a tunneling current 42 flowing through the pn junction between the channels is generated.
FIG. 10 is a cross-sectional view illustrating that the tunneling current 42 flowing through the pn junction between the channels in FIG. 9 becomes a driving current flowing between the source 64 and the drain 62.
11 and 12 are band diagrams showing energy level changes from the source 64 to the drain 62 in the Off state and the On state, respectively, in the structure of FIG.
FIG. 13 is a simulation result diagram of a band diagram for determining a change in energy level from the second gate 54 to the first gate 52 in the on state in the structure of FIG. 10.
FIG. 14 illustrates HfO 2 for the first and second gate insulating layers 22 and 24, 0V for the source 64 and the second gate 54, and 0.7V for the drain 62. It is a simulation result diagram of the transfer characteristic of drain current according to the gate 52 voltage change.
15 to 24 are cross-sectional views illustrating a manufacturing process of a tunneling field effect transistor having a vertical dual gate finFET structure according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

Tunneling field effect transistor according to an embodiment of the present invention, as shown in Figure 8, basically the semiconductor substrate 10 is formed with a semiconductor fin 14 of a predetermined height; P + region 64 and n + region 62 formed on the semiconductor substrate at predetermined distances from both sides with the semiconductor fin 14 therebetween; A first gate 52 formed between one side of the semiconductor fin 14 and the n + region 62 with a first gate insulating layer 22 therebetween; A second gate 54 formed between the other side of the semiconductor fin 14 and the p + region 64 to be electrically separated from the first gate 52 with a second gate insulating layer 24 interposed therebetween. Characterized in that configured.

In this case, the semiconductor substrate 10 may be a bulk substrate, but as shown in FIG. 8, a substrate having a second semiconductor substrate 1 and a buried insulating film (BOX) 2 on the bottom (eg, the substrate may be silicon). In this case, the SOI substrate is preferable because it can reduce the leakage current.

In addition, the semiconductor fin 14 may be formed of a semiconductor material separate from the semiconductor substrate 10. However, the semiconductor fin 14 may be integrally formed of the same kind of semiconductor material in consideration of a manufacturing process.

As a result, the semiconductor fin 14 and the semiconductor substrate 10 are not limited to silicon (Si), and may be heterologous to at least one of silicon germanium (SiGe), germanium (Ge), and a group 3-5 compound semiconductor material. It may be formed of the same kind of semiconductor.

The semiconductor fins 14 protrude from the semiconductor substrate 10 at a predetermined height such that the dual gates facing each other on both sides and electrically separated from each other may be formed as the first gate 52 and the second gate 54. Has At this time, the protruding height of the semiconductor fin 14 determines the tunneling junction area affecting the driving current.

Accordingly, if the height of the semiconductor fin 14 is sufficiently large without increasing the area of the device, the first gate 52 and the second gate 54 may be formed by vertical dual gates on both sidewalls of the semiconductor fin 14. It is formed to increase the tunneling junction area, thereby there is an advantage that can improve the driving current any number.

In addition, when a predetermined driving voltage is applied to the first gate 52 and the second gate 54, the thickness of the semiconductor fin 14 (the distance between the first gate insulating layer and the second gate insulating layer in FIG. 8) is applied. In the ON state, as seen in FIG. 12, the thickness of the tunneling barrier is determined. In other words, the thickness of the tunneling barrier is proportional to the thickness of the semiconductor fin 14.

However, the smaller the thickness of the tunneling barrier, the greater the tunneling probability of the carrier (electrons or holes). Therefore, according to the present embodiment, the improvement of the driving current by the tunneling current 42 is caused by the semiconductor fin 14. By forming a thin thickness there is an advantage that can be easily achieved.

In addition, the first gate insulating layer 22 and the second gate insulating layer 24 may include a silicon oxide layer (SiO 2 ), a strontium oxide layer (SrO), a silicon nitride layer (Si 3 N 4 ), and an aluminum oxide layer (A1 2 O 3 ). , Magnesium oxide (MgO), scandium oxide (Sc 2 O 3 ), gadolinium oxide (Gd 2 O 3 ), yttrium oxide (Y 2 O 3 ), samarium oxide (Sm 2 O 3 ), hafnium oxide (HfO 2 ), The zirconium oxide layer ZrO 2 , the tantalum oxide layer Ta 2 O 5 , the barium oxide layer BaO, and the bismuth oxide layer Bi 2 O 3 may be formed.

The first gate 52 and the second gate 54 may be formed of a semiconductor material doped with impurities as well as a metal, and may be formed of the same material, but may be formed of different materials for the following reasons. Preferably formed.

The role of the first gate 52 and the second gate 54, as shown in FIG. 12, shifts energy bands in opposite directions to both sides of the semiconductor fin 14 in an ON state, so that the semiconductor fins are shifted. The band bending at 14 causes electrons in the valence band Ev of the channel under the second gate 54 (eg, the extended p + region 65) to be below the first gate 52. The driving current flows by tunneling to the conduction band Ec of the channel (eg, the expanded n + region 65).

Therefore, when the present embodiment is implemented as an n-channel TFET with the p + region 64 as the source and the n + region 62 as the drain, as shown in FIGS. 8 to 10, the ON state of FIG. In order to operate in a state, a negative voltage is applied to the second gate 54 so that the channel energy band under the second gate 54 rises upward, and a positive voltage is applied to the first gate 52. The channel energy band below the first gate 52 goes down.

In this case, the material of the second gate 54 is a material having a higher work function than the material of the semiconductor fin 14, the material of the first gate 52 is a material having a lower work function than the material of the semiconductor fin 14, In each case, the band bending according to the work function difference is further considered, and thus, the driving voltages of the first and second gates 52 and 54 for operating in the ON state can be lowered. .

Means for providing a work function difference between the first and second gates 52 and 54 may be variously implemented. However, different impurities may be doped into the semiconductor material, or different doping concentrations may be implemented using the same impurities. have.

The first gate 52 is the same n-type impurity as the impurity doped in the n + region 62, and the second gate 54 is the same p-type impurity as the impurity doped in the p + region 64. It is advantageous in terms of the manufacturing process to be described later to form each doping with.

FIG. 13 simulates a band diagram from the second gate 54 to the first gate 52 in the ON state with the structure of FIG. 8.

As can be seen in FIG. 13, the region of the semiconductor fin 14 located below the second gate 54 has an energy band upward due to the negative voltage of the second gate 54, and is located below the first gate 52. The region of the semiconductor fin 14 can be seen that the energy band is lowered due to the positive voltage applied to the first gate 52.

Thus, in the region of the semiconductor fin 14, the valence band located below the second gate 54 and the conduction band located below the first gate 52 are arranged to create a condition in which tunneling can occur.

As a result, in the present embodiment, as shown in FIG. 9, when predetermined driving voltages are respectively applied to the first and second gates 52 and 54, the first and second gates 52 and 54 respectively extend below the first and second gates 52 and 54. Each channel is formed of an n + region 63 and an extended p + region 65 so that electrons supplied from the source 64 are transferred to the second gate 54 through the interchannel pn junction formed in the semiconductor fin 14 region. Tunneling toward the first gate 52 at, i.e., tunneling with the conduction of the extended n + region 63 opposite the valence band of the extended p + region 65, exiting back to the drain 62 As shown in FIG. 10, it can be seen that the tunneling current 42 forms a driving current.

FIG. 14 illustrates that the first and second gate insulating layers 22 and 24 are formed of HfO 2 in the structure of FIG. 8, and the first and second gates 52 and 54 are formed in consideration of the material and work function of the semiconductor fin 14. In the case of different formation, even when a negative voltage is not applied to the second gate 54, that is, 0 V (ground) like the source 64 and 0.7 V is applied to the drain 62, the first It is shown that excellent drain current transfer characteristics, that is, switching characteristics, can be obtained according to the gate 52 voltage change.

Next, referring to FIGS. 15 to 23, a method of manufacturing a tunneling field effect transistor according to another embodiment of the present invention will be described. More specifically, a method of manufacturing an n-channel TFET will be described. However, in the case of a p-channel TFET, the roles of the source and drain, and the first and second gates are changed in the n-channel TFET, so the description of the latter is omitted. do.

First, as shown in FIG. 15, the hard mask 30 is formed in the semiconductor substrate 10 (1st step).

Here, the semiconductor substrate 10 is not limited to silicon (Si), and may be formed of a heterogeneous or homogeneous semiconductor made of any one or more of silicon germanium (SiGe), germanium (Ge), and a group 3-5 compound semiconductor material. And a thickness sufficient to form a semiconductor fin having a predetermined height later.

In addition, since the hard mask 30 is to form sidewall spacers to be used as masks in the subsequent formation of semiconductor fins, the hard mask 30 is deposited in consideration of the thickness of semiconductor fins, and before the hard mask 30 is formed according to the material of the semiconductor substrate. As shown in FIG. 15, the buffer layer 20 may be formed first.

When the semiconductor substrate 10 is silicon (Si), the buffer layer 20 may be a silicon oxide layer (SiO 2 ), and the hard mask 30 may be formed of a silicon nitride layer (Si 3 N 4 ).

Next, as shown in FIG. 16, sidewall spacers 40 are formed on one sidewall of the hard mask 30 (second step).

Since the sidewall spacers 40 will be used as masks when forming semiconductor fins later, the degree of anisotropic etching is controlled to determine the size of the sidewall spacers 40 in consideration of the thickness of the semiconductor fins. In addition, the sidewall spacer 40 may be selected as a material having a good etching selectivity between the hard mask 30 and the semiconductor substrate 10.

Next, as shown in FIG. 17, the semiconductor substrate 10 is anisotropically etched to a predetermined depth by using the hard mask 30 and the sidewall spacers 40 as an etching mask (step 3).

In this case, the etching depth of the semiconductor substrate 10 determines the protruding height of the semiconductor fins later, and the protruding height of the semiconductor fins determines the tunneling junction area affecting the driving current of the device as described above. It is preferable to consider the characteristics of the device to be determined.

Thereafter, as shown in FIG. 18, the first gate insulating layer 22 is formed on one side of the semiconductor substrate (step 4), the first gate material is deposited on the entire surface of the substrate, and anisotropically etched to form the semiconductor substrate. A first gate 52 is formed on the one sidewall of the step 10 with the first gate insulating layer 22 therebetween (a fifth step).

Here, when the semiconductor substrate 10 is silicon, the first gate insulating layer 22 may be formed of a silicon oxide layer (SiO 2 ) through a thermal oxidation process. In addition, the first gate insulating layer 22 may include a strontium oxide layer (SrO) and a silicon nitride layer ( Si 3 N 4 ), aluminum oxide (A1 2 O 3 ), magnesium oxide (MgO), scandium oxide (Sc 2 O 3 ), gadolinium oxide (Gd 2 O 3 ), yttrium oxide (Y 2 O 3 ), samarium oxide (Sm 2 O 3 ), hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), tantalum oxide (Ta 2 O 5 ), barium oxide (BaO), and bismuth oxide (Bi 2 O 3 ). have.

In addition, the first gate 52 may be formed of a metal or a semiconductor material. When the first gate 52 is formed of a semiconductor material, conductivity is increased by impurity implantation in a subsequent process.

Since the first gate 52 formed as described above controls a channel to be formed on the drain side, for example, the first gate 52 may be formed of a material having a lower work function than the material of the semiconductor substrate 10 on which semiconductor fins are to be formed.

Next, as shown in FIG. 19, a first conductivity type doped region (eg, n-type impurity) is doped on the entire surface of the substrate to the first gate 52 to one side of the first conductive type high concentration doped region ( For example, n + region, drain 62 is formed (sixth step).

In this case, when the first gate 52 is formed of a semiconductor material in the previous process, the first gate 52 is simultaneously doped with the first gate 52 when doping the first conductivity type impurity, thereby reducing the process steps. 52 and the first conductivity type doped region 62 can be formed. That is, when manufacturing an n-channel TFET, when the n + region (drain) is formed by n-type impurity (ion) implantation, the first gate 52 is doped with the impurity so that the work function is higher than that of the material of the semiconductor substrate 10. There is an advantage that the first gate 52 can be formed low.

Next, as shown in FIG. 20, a dummy insulating film 70 is deposited on the entire surface of the substrate and planarized so that the hard mask 30 is exposed (seventh step).

Next, as shown in FIG. 21, the other side 12 of the semiconductor substrate is anisotropically etched to a predetermined depth by removing the hard mask 30 and using the sidewall spacer 40 and the dummy insulating layer 70 as an etch mask. 22, the semiconductor fin 14 is formed (8th step).

In this case, the etching depth of the other side 12 of the semiconductor substrate may be the same as the etching depth of one side of the semiconductor substrate in the third step, so that the semiconductor fin 14 may protrude to a predetermined height as shown in FIG. 22. Do.

Next, as shown in FIG. 23, a second gate insulating film 24 is formed on the other side of the semiconductor substrate on which the semiconductor fins 14 are formed (ninth step), and a second gate material is deposited on the entire surface of the substrate and is anisotropic. Etching to form a second gate 54 on the other side of the semiconductor substrate with the second gate insulating layer 24 interposed therebetween (step 10).

Here, the second gate insulating film 24 and the second gate 54 may be formed of the same process and material as the first gate insulating film 22 and the first gate 52 in the fourth and fifth steps, respectively. However, since the second gate 54 controls a channel to be formed on the source side, for example, the second gate 54 may be formed of a material having a higher work function than the material of the semiconductor fin 14.

Subsequently, as shown in FIG. 24, a second conductivity type doped region (eg, p-type impurity) is doped on the entire surface of the substrate so that the semiconductor substrate 10 has a second conductivity type doped region (one side of the second gate 54). For example, p + region, source: 64) is formed (11th step).

In this case, when the second gate 54 is formed of a semiconductor material in the previous process, the second gate 54 is simultaneously doped to the second gate 54 when the second conductive dopant is doped, thereby reducing the process steps. And the second conductivity type doped region 64 can be formed. That is, when the n-channel TFET is manufactured, the impurity is also doped into the second gate 54 when the p + region (source) is formed by the p-type impurity (ion) implantation. The second gate 54 can be formed to have a higher work function than the material of 10).

In addition, since the rest of the process is generally required when manufacturing the device, a description thereof will be omitted.

10: semiconductor substrate
14: semiconductor pin
20: buffer layer
22: first gate insulating film
24: second gate insulating film
30: hard mask
40: sidewall spacer
52: first gate
54: second gate
62: first conductivity type doped region, n + region, drain
64: second conductivity type doped region, p + region, source
70: dummy insulating film

Claims (12)

A semiconductor substrate on which semiconductor fins of a predetermined height are formed;
A p + region and an n + region formed in the semiconductor substrate at a predetermined distance from both sides with the semiconductor fin interposed therebetween;
A first gate formed between one side of the semiconductor fin and the n + region with a first gate insulating layer interposed therebetween; And
And a second gate formed to be electrically separated from the first gate with a second gate insulating layer interposed between the other side of the semiconductor fin and the p + region.
The method of claim 1,
The first gate and the second gate tunneling field effect transistor, characterized in that formed of different materials.
The method of claim 1,
And the first gate and the second gate are formed by doping different impurities into a semiconductor material or having different doping concentrations with the same impurities.
The method of claim 3, wherein
The first gate is formed by doping with the same n-type impurities as the impurities doped in the n + region,
And the second gate is doped with the same p-type impurity as the impurity doped in the p + region.
The method according to any one of claims 1 to 4,
And a height of the semiconductor fin determines a tunneling junction area.
The method of claim 5, wherein
And the semiconductor fin and the semiconductor substrate are formed of any one or more of silicon, silicon germanium, germanium, and a group 3-5 compound semiconductor material.
The method according to claim 6,
The first gate insulating layer and the second gate insulating layer may include a silicon oxide layer (SiO 2 ), a strontium oxide layer (SrO), a silicon nitride layer (Si 3 N 4 ), an aluminum oxide layer (A1 2 O 3 ), a magnesium oxide layer (MgO), and scandium Oxide (Sc 2 O 3 ), Gadolinium Oxide (Gd 2 O 3 ), Yttrium Oxide (Y 2 O 3 ), Samarium Oxide (Sm 2 O 3 ), Hafnium Oxide (HfO 2 ), Zirconium Oxide (ZrO 2 ), Tantalum A tunneling field effect transistor, characterized in that formed of any one of an oxide film (Ta 2 O 5 ), barium oxide (BaO) and bismuth oxide (Bi 2 O 3 ).
Forming a hard mask on the semiconductor substrate;
Forming a sidewall spacer on one sidewall of the hard mask;
A third step of anisotropically etching the semiconductor substrate by using the hard mask and the sidewall spacers as an etch mask to step toward one side;
A fourth step of forming a first gate insulating layer on one side of the semiconductor substrate;
Depositing a first gate material on the entire surface of the substrate and etching anisotropically to form a first gate with the first gate insulating layer interposed on one sidewall of the semiconductor substrate;
A sixth step of forming a first conductivity type high concentration doped region in the semiconductor substrate to one side of the first gate by doping a first conductivity type impurity on the entire surface of the substrate;
Depositing a dummy insulating film on the entire surface of the substrate and flattening the hard mask to be exposed;
An eighth step of removing the hard mask and etching the other side of the semiconductor substrate by a predetermined depth using the sidewall spacer and the dummy insulating layer as an etching mask to form a semiconductor fin;
A ninth step of forming a second gate insulating film on the other side of the semiconductor substrate on which the semiconductor fin is formed;
Depositing a second gate material over the entire surface of the substrate and etching anisotropically to form a second gate with the second gate insulating layer interposed on the other side of the semiconductor substrate; And
And an eleventh step of forming a second conductivity type high concentration doped region in the semiconductor substrate to one side of the second gate by doping a second conductivity type impurity on the entire surface of the substrate. .
The method of claim 8,
And wherein the first gate material and the second gate material are materials having different work functions.
The method of claim 8,
The first gate material and the second gate material are semiconductor materials,
In the sixth step, the doping of the first conductivity type impurities is simultaneously doped to the first gate,
And in the eleventh step, the doping of the second conductivity type impurity is simultaneously doped to the second gate.
11. The method according to any one of claims 8 to 10,
In the third and eighth steps, the etching depths of the semiconductor substrates are the same, and
And forming the first gate insulating film in the fourth step and forming the second gate insulating film in the ninth step through a thermal oxidation process.
The method of claim 11,
A buffer layer is first formed on the semiconductor substrate before the first step, and the hard mask is formed on the buffer layer,
And removing the buffer layer exposed to one side of the hard mask and the sidewall spacer by first etching the semiconductor substrate during the etching of the semiconductor substrate.
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KR101827811B1 (en) 2016-08-31 2018-02-12 서강대학교 산학협력단 Tunnel field-effect transistors and fabrication methods of the same
CN107871781A (en) * 2016-09-27 2018-04-03 西安电子科技大学 A kind of silicon carbide MOSFET and its manufacture method
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CN116666436B (en) * 2023-07-24 2023-10-17 西交利物浦大学 Fin type field effect transistor and preparation method thereof

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