CN104347725A - Tunneling field effect transistor and manufacturing method thereof - Google Patents
Tunneling field effect transistor and manufacturing method thereof Download PDFInfo
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- CN104347725A CN104347725A CN201310315534.9A CN201310315534A CN104347725A CN 104347725 A CN104347725 A CN 104347725A CN 201310315534 A CN201310315534 A CN 201310315534A CN 104347725 A CN104347725 A CN 104347725A
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- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 230000005641 tunneling Effects 0.000 title abstract description 10
- 238000002353 field-effect transistor method Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 claims abstract description 77
- 230000005669 field effect Effects 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims description 46
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 18
- 229910052751 metal Inorganic materials 0.000 claims description 16
- 239000002184 metal Substances 0.000 claims description 16
- 230000015572 biosynthetic process Effects 0.000 claims description 14
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 150000004767 nitrides Chemical class 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 4
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical group [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 230000007547 defect Effects 0.000 abstract description 5
- 239000000463 material Substances 0.000 description 14
- 238000005530 etching Methods 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 229910004129 HfSiO Inorganic materials 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 229910010038 TiAl Inorganic materials 0.000 description 1
- 229910010037 TiAlN Inorganic materials 0.000 description 1
- 229910010413 TiO 2 Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- VTGARNNDLOTBET-UHFFFAOYSA-N gallium antimonide Chemical compound [Sb]#[Ga] VTGARNNDLOTBET-UHFFFAOYSA-N 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- -1 silicon nitride Chemical class 0.000 description 1
- OCGWQDWYSQAFTO-UHFFFAOYSA-N tellanylidenelead Chemical compound [Pb]=[Te] OCGWQDWYSQAFTO-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7391—Gated diode structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0895—Tunnel injectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66356—Gated diodes, e.g. field controlled diodes [FCD], static induction thyristors [SITh], field controlled thyristors [FCTh]
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention provides a tunneling field effect transistor. The tunneling field effect transistor comprises a semiconductor layer, a first gate medium layer and a second gate medium layer which are respectively arranged two opposite surfaces of the semiconductor layer, a source electrode region and a drain electrode region which have different doping types, are respectively arranged at two sides of the semiconductor layer and contact with the semiconductor layer, and a first grid electrode and a second grid electrode which are respectively arranged on the first gate medium layer and the second gate medium layer. According to the tunneling field effect transistor, tunneling junctions are controlled through thickness of a channel region, a larger effective tunneling area is realized, the conduction current is further enhanced, moreover, tunneling is generated in the semiconductor layer, namely, the channel; tunneling layers are non-doped or low-doped tunneling layers, so a leakage current caused by defects can be reduced, and thereby sub-threshold characteristics of devices can be improved; dual-gate control is employed, so bipolar conduction characteristics can be better controlled, and on and off control on the devices can be realized.
Description
Technical field
The present invention relates to field of semiconductor devices, particularly one wears field-effect transistor and manufacture method thereof then.
Background technology
Along with constantly reducing of device size, the device count on unit are chip gets more and more, and how to reduce power consumption and becomes the problem become increasingly conspicuous.
The conventional structure of then wearing field-effect transistor (Normal-TFET) mainly comprises the source/drain region of substrate (raceway groove), gate dielectric layer, grid and grid both sides, mainly based on the work of quantum tunneling effect, then field-effect transistor is worn for P type, grid applies negative voltage, the electromotive force of channel region raises, there is quantum to channel region and then wear in source region, electronics and the hole of then wearing generation are flowed out from source region and drain region.
Then wear field-effect transistor for routine, its subthreshold swing (SS) can be less than 60meV/dec, provides a kind of approach for reducing power consumption.But in order to reduce subthreshold swing and improve On current, need then to wear knot more narrow better, but existing structure then wear field-effect transistor, to inject and heat treatment process federation causes the diffusion profile of impurity, be difficult to realize narrow then wear knot.
In addition, then wear in field-effect transistor in routine, source-drain area is all highly doped, and doping certainly will introduce defect, and the leakage current relevant to defect can destroy the reduction of subthreshold swing.And conventional field-effect transistor of then wearing has the dipole characteristic can opened under positive negative gate voltage, and device can be caused to be difficult to turn off completely.
Summary of the invention
Object of the present invention is intended to solve above-mentioned technological deficiency, provides one then to wear field-effect transistor and manufacture method thereof.
The invention provides one and then wear field-effect transistor, comprising:
Semiconductor layer;
First grid dielectric layer and second gate dielectric layer, lay respectively on two relative surfaces of semiconductor layer;
Source area and drain region, have different doping types, lays respectively at the both sides of semiconductor layer and contact with semiconductor layer;
First grid and second grid, lay respectively on first grid dielectric layer and second gate dielectric layer.
Preferably, the thickness of described semiconductor layer is not more than 10nm.
Preferably, described source area and drain region are formed by epitaxial growth.
Preferably, described source area and drain region lay respectively at the both sides of semiconductor layer and part first grid, part second grid, between described source area and described drain region and first grid, second grid, there is separator, do not cover the whole of described semiconductor layer to make first grid, second grid.
Preferably, source and drain contact and first grid, second grid contact draw from the same side.
In addition, present invention also offers above-mentioned manufacture method of then wearing field-effect transistor, comprising:
Step S01, provides the first support substrates;
Step S02, the first support substrates is formed the first removing layer, semiconductor layer, first grid dielectric layer and first grid successively, and formation has different doping types, the source area contacted with semiconductor layer and drain region in the both sides of semiconductor layer;
Step S03, forms the dielectric layer covering source area, drain region and first grid;
Step S04, by dielectric layer and the second support substrates bonding;
Step S05, with the second support substrates for supporting, removes the first support substrates and the first removing layer, and forms second gate dielectric layer and second grid successively on the semiconductor layer;
Step S06, completes the subsequent step of device.
Preferably, described first support substrates is Semiconductor substrate, and described step S02 specifically comprises:
First support substrates is formed with successively the first removing layer, semiconductor layer, first grid dielectric layer, the second removing layer and the first mask layer;
First mask layer described in patterning and the second removing layer, and form the 3rd removing layer at described first mask layer and the second removing layer sidewall;
Under the sheltering of the first mask layer and the 3rd removing layer, remove first grid dielectric layer and lower semiconductor layer thereof and the first removing layer, and again form the second mask layer, remove the first mask layer simultaneously;
Under the sheltering of the second mask layer and the 3rd removing layer, remove the second removing layer and under first grid dielectric layer, semiconductor layer and the first removing layer, and again form source area and the first medium layer on it;
Under the sheltering of first medium layer and the 3rd removing layer, remove the second mask layer, and again form drain region and the second dielectric layer on it, source area and drain region have different doping types, and source area and drain region contact with semiconductor layer;
Remove the 3rd removing layer to form the first opening, form the first separator at the first opening sidewalls, and fill the first opening to form first grid.
Preferably, the first removing layer is silicon dioxide, and semiconductor layer is silicon, and the second removing layer is polysilicon, and the first mask layer and the 3rd removing layer are nitride, and the second mask layer is germanium silicon.
Preferably, the step of step S05 is specially: with the second support substrates for supporting, remove the first support substrates and the first removing layer to form the second opening, form second gate dielectric layer on the semiconductor layer, and form the second separator at the sidewall of the second opening, and fill the second opening to form second grid.
Preferably, the thickness of described semiconductor layer is not more than 10nm.
Preferably, before step S04, also step is comprised: form the first metal layer connecting first grid;
Step S06 comprises: form the second metal level connecting second grid;
Source and drain contact is formed from second grid side, and contacting of being connected with the second metal level with the first metal layer respectively.
What the embodiment of the present invention provided wears field-effect transistor then, in formation source area, both sides and the drain region of semiconductor layer, the two-sided formation grid of semiconductor layer, result in formation of double-gated devices, semiconductor layer is channel region, and the field-effect transistor of then wearing of this structure is do not inject the narrow of diffusion-restricted by impurity then to wear knot, and its thin and thick by channel region controls then to wear knot, and have and larger effectively then wear area, therefore can improve On current.Meanwhile, transistor arrangement of the present invention, it is then worn and betides in semiconductor layer, namely in raceway groove, because tunnel layer is undoped or low-doped, therefore can reduce the leakage current caused by defect, thus improve the Sub-Threshold Characteristic of device.In addition, owing to adopting double grid to control, therefore can better control bipolar-conduction characteristic, realize device and turn off.
Accompanying drawing explanation
The present invention above-mentioned and/or additional aspect and advantage will become obvious and easy understand from the following description of the accompanying drawings of embodiments, wherein:
Fig. 1 shows the structural representation then wearing field-effect transistor according to the embodiment of the present invention;
Fig. 2-Figure 17 shows the schematic cross-section of each formation stages of the semiconductor device according to the embodiment of the present invention.
Embodiment
Be described below in detail embodiments of the invention, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has element that is identical or similar functions from start to finish.Being exemplary below by the embodiment be described with reference to the drawings, only for explaining the present invention, and can not limitation of the present invention being interpreted as.
The present invention be intended to propose a kind of newly then wear field-effect transistor structure, be difficult to realize narrow then wear knot to overcome existing field-effect transistor structure of then wearing, shown in figure 1, described field-effect transistor of then wearing comprises:
Semiconductor layer 104;
First grid dielectric layer 106 and second gate dielectric layer 206, lay respectively on two relative surfaces of semiconductor layer 104;
Source area 120 and drain region 130, have different doping types, lays respectively at the both sides of semiconductor layer 104 and contact with semiconductor layer;
First grid 140 and second grid 240, lay respectively on first grid dielectric layer 106 and second gate dielectric layer 206.
Then wear in field-effect transistor structure of the present invention, in formation source area, both sides and the drain region of semiconductor layer, the two-sided formation grid of semiconductor layer, result in formation of double-gated devices, semiconductor layer is channel region, and upper and lower two grids apply different voltage, and the upper and lower both sides of raceway groove are in different electromotive forces, when this electrical potential difference is greater than the energy gap of channel material, there is quantum between conduction band and valence band and then wear.Then the charge carrier (electronics and hole) wearing generation is flowed out by source and drain, thus forms conducting loop.Then the field-effect transistor of wearing of this structure is do not inject the narrow of diffusion-restricted by impurity then to wear knot, and its thin and thick by channel region controls then to wear knot, and has and larger effectively then wear area (being long-pendingly directly proportional to the long grid width of grid is), therefore can improve On current.In addition, the channel region due to transistor of the present invention can undope or only low-doped, thus significantly reduces the electric current relevant to defect, can realize lower subthreshold swing.
As shown in Figure 1, in an embodiment of the present invention, described source area 120 and drain region 130 lay respectively at the both sides of semiconductor layer 104 and part first grid 140, part second grid 240, have separator 142,242 between described source area 120 and described drain region 130 and first grid 140, second grid 240.The grid that wherein channel region is upper and lower with it, gate dielectric layer and separator autoregistration.
Described source area 120 and described drain region 130 have dissimilar doping, and for N-type device, drain region is N-type heavy doping, and source area is the heavy doping of P type; To P type device, drain region is the heavy doping of P type, and source area is N-type heavy doping.Source and drain contact 172 and first grid, second grid contact 170,174 from the same side draw, draw from second grid 240 side in the present embodiment.Preferably, described source area and drain region can be formed by epitaxial growth.
Described semiconductor layer 104 is preferably the little material of band gap, can be such as monocrystalline silicon, polysilicon, amorphous silicon, germanium, SiGe, indium antimonide, lead telluride, indium arsenide, indium phosphide, GaAs or gallium antimonide, alloy semiconductor or other compound semiconductors, preferably, its thickness can be about 10nm or thinner.This semiconductor layer is the channel region of device, does not carry out adulterating or only carrying out light dope.
Described first or second gate dielectric layer can be silica, silicon oxynitride or high K medium material etc., high K medium material such as hafnium base oxide, HfO
2, HfSiO, HfSiON, HfTaO, HfTiO etc., and other high-g value, such as La
2o
3, TiO
2deng.Described first or second grid can be one or more layers structure, gate electrode can comprise metal gate electrode or polysilicon etc., such as, can comprise: Ti, TiAl
x, TiN, TaN
x, HfN, TiC
x, TaC
x, HfC
x, Ru, TaN
x, TiAlN, WCN, MoAlN, RuO
x, polysilicon or other suitable materials, or their combination.Grid by other metal level 160,260 or directly can be drawn as required.
First grid and second grid and source-drain area are kept apart by described separator, and this makes first grid, second grid not cover the whole of described semiconductor layer, to reduce leakage current further, improves Sub-Threshold Characteristic.Separator can be the material such as nitride or oxide.
Be described structure of then wearing field-effect transistor of the present invention above, in addition, present invention also offers the manufacture method of above-mentioned transistor, described method comprises:
Step S01, provides the first support substrates;
Step S02, the first support substrates is formed the first removing layer, semiconductor layer, first grid dielectric layer and first grid successively, and formation has different doping types, the source area contacted with semiconductor layer and drain region in the both sides of semiconductor layer;
Step S03, forms the dielectric layer covering source area, drain region and first grid;
Step S04, by dielectric layer and the second support substrates bonding;
Step S05, with the second support substrates for supporting, removes the first support substrates and the first removing layer, and forms second gate dielectric layer and second grid successively on the semiconductor layer;
Step S06, completes the subsequent step of device.
For a better understanding of the present invention, below in conjunction with accompanying drawing 2-16, the embodiment of the manufacture method of this structure is described in detail.
In the present embodiment, first, the first support substrates 100 is provided, described in reference diagram 2.
In the present embodiment, the first support substrates 100 is Si substrate, and according to specific needs, the first support substrates 100 can also select other suitable substrates.
Then, the first support substrates 100 is formed with the first removing layer 102, semiconductor layer 104, first grid dielectric layer 106, second removing layer 108 and the first mask layer 110 successively, as shown in Figure 2.
In the present embodiment, the first removing layer 102 is oxide, and as silica, semiconductor layer 104 is Si, and first grid dielectric layer 106 is high-k gate dielectric layer, such as HfSiO, and the second removing layer 108 is polysilicon, and the first mask layer 110 is nitride, as silicon nitride.
In the present embodiment, the first support substrates 100, first removing layer 102 and semiconductor layer are by SOI(silicon-on-insulator) substrate provides, i.e. the bottom silicon of these three layers of corresponding SOI substrate of difference, oxygen buried layer and top layer silicon.In other embodiments, suitable substrate or material can be selected as required to be formed.
Then, the first mask layer 110 and the second removing layer 108 described in patterning, and form the 3rd removing layer 114 at described first mask layer 110 and the second removing layer 108 sidewall, as shown in Figure 3.
In the present embodiment, the first mask layer 110 arranges photosensitive etching agent 112, as shown in Figure 1, under the covering of photosensitive etching agent 112, etch the first mask layer 110, and then, etching the second removing layer 108 further.After patterning, form the 3rd removing layer 114 at the sidewall of the first mask layer 110 and the second removing layer 108, from the optionally consideration of subsequent etching, the 3rd removing layer 114 can be same material with the first mask layer 110, is silicon nitride in the present embodiment.
Then, under the sheltering of the first mask layer 110 and the 3rd removing layer 114, remove first grid dielectric layer 106 and under semiconductor layer 104 and the first removing layer 102, as shown in Figure 4; And again form the second mask layer 116, that is, again position after removal forms the second mask layer, as shown in Figure 6; Remove the first mask layer 110, as shown in Figure 6 simultaneously.
In the present embodiment, described second mask layer 116 is SiGe, can continue grinding by CMP(chemistry) grind, remove described first mask layer 110, until expose the second removing layer 108.
Then, under the sheltering of the second mask layer 116 and the 3rd removing layer 114, remove the second removing layer 108 and under first grid dielectric layer 106, semiconductor layer 104 and the first removing layer 102, and again form source area 120 and the first medium layer 122 on it, as shown in Figure 7, Figure 8.
In the present embodiment, particularly, first etch, remove the second removing layer 108 and under first grid dielectric layer 106, semiconductor layer 104 and the first removing layer 102, until expose the first support substrates 100, then, position after this removes is filled up again the Si of doping by epitaxial growth (epi), certainly, in other embodiments, source area and drain region also can select the material different from channel layer to be formed, as shown in Figure 7, then carry out etching and remove part Si, and form oxide, as silica, thus, form source area 120 and the first medium layer 122 on it, as shown in Figure 8.
Then, under the sheltering of first medium layer 122 and the 3rd removing layer 114, remove the second mask layer 116, and again form drain region 130 and the second dielectric layer 132 on it, source area 120 and drain region 130 have different doping types, source area and drain region contact with semiconductor layer, as shown in Fig. 9,10.
In this embodiment, etching removal second mask layer 116, until expose the first support substrates 100, then, position after this removes can be passed through the Si that another doping is filled up in epitaxial growth (epi) again, as shown in Figure 9, then, carry out the Si etching removal part, and form oxide, as silica, thus, form drain region 130 and the second dielectric layer on it 132, as shown in Figure 10.
Then, remove the 3rd removing layer 114 to form the first opening, form separator 142 at the first opening sidewalls, and fill the first opening to form first grid 140, as shown in figure 11.
In this embodiment, etching removal the 3rd removing layer 114, until expose first medium layer 106, then, form separator 142, separator 142 can be nitride, such as silicon nitride, and fills the formation first grid 140.In the present embodiment, first removing layer is silicon dioxide, semiconductor layer is silicon, second removing layer is polysilicon, first mask layer and the 3rd removing layer are nitride, and the second mask layer is germanium silicon, by selecting different materials, there is different Etch selectivities, thus self aligned formation source area, drain region and grid.Below be only example, different materials and process can be selected as required to form as above structure.
Then, as required, form the first metal layer 160 be connected with first grid 140, the first metal layer can have identical or different material with first grid.
Then, cover the first metal layer 160 and form the 3rd dielectric layer 144, such as silica, as shown in figure 12.
Then, by the second support substrates 200 and the 3rd dielectric layer 144 bonding, to realize the combination of said structure and the second support substrates, as shown in figure 13.Thus, with the second support substrates 200 for supporting, carry out subsequent technique.
Described second support substrates can be the substrate of any appropriate in the present embodiment, such as silicon substrate etc.
Then, remove the first support substrates 100 and the first removing layer 102, and another forms second gate dielectric layer 206 and second grid 240 on the surface successively at semiconductor layer 104 again, as shown in FIG. 14 and 15.
In the present embodiment, remove the first support substrates 100, and etch the first removing layer 102 until another surface of exposed semiconductor layer 104, as shown in figure 14; Then, second gate dielectric layer 206 is formed on the surface at this of semiconductor layer, such as high-k gate dielectric material, and the sidewall of the second opening after removal forms separator 242, separator is such as silicon nitride, and fill up the second opening formation second grid 240, according to the needs that work function is selected, second grid 240 and first grid 140 can be similar and different materials and structures.
Then, as required, form the second metal level 260, second metal level be connected with second grid 240 and can have identical or different material with second grid.
Particularly, first etching removes source area and the drain region of part, and deposit the 4th dielectric material, as silica, to form the 4th dielectric layer 232, as shown in figure 16, then, form the second metal level 260 be connected with second grid, with reference to shown in Figure 17.
Then, continue deposit dielectric material, and form the contact 172 of source-drain area and the contact 174 of first grid, the contact 170 of second grid wherein, in the present embodiment, all contact holes are formed from second grid side, as shown in figure 17.Then, as required, other techniques of device can be completed.
So far, what define the embodiment of the present invention wears field-effect transistor then.
The above is only preferred embodiment of the present invention, not does any pro forma restriction to the present invention.
Although the present invention discloses as above with preferred embodiment, but and be not used to limit the present invention.Any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the Method and Technology content of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or be revised as the Equivalent embodiments of equivalent variations.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (11)
1. then wear a field-effect transistor, it is characterized in that, comprising:
Semiconductor layer;
First grid dielectric layer and second gate dielectric layer, lay respectively on two relative surfaces of semiconductor layer;
Source area and drain region, have different doping types, lays respectively at the both sides of semiconductor layer and contact with semiconductor layer;
First grid and second grid, lay respectively on first grid dielectric layer and second gate dielectric layer.
2. transistor according to claim 1, is characterized in that, the thickness of described semiconductor layer is not more than 10nm.
3. transistor according to claim 1, is characterized in that, described source area and drain region are formed by epitaxial growth.
4. transistor according to claim 1, it is characterized in that, described source area and drain region lay respectively at the both sides of semiconductor layer and part first grid, part second grid, between described source area and described drain region and first grid, second grid, there is separator, do not cover the whole of described semiconductor layer to make first grid, second grid.
5. transistor according to claim 4, is characterized in that, source and drain contact and first grid, second grid contact draw from the same side.
6. then wear a manufacture method for field-effect transistor, it is characterized in that, comprise step:
Step S01, provides the first support substrates;
Step S02, the first support substrates is formed the first removing layer, semiconductor layer, first grid dielectric layer and first grid successively, and formation has different doping types, the source area contacted with semiconductor layer and drain region in the both sides of semiconductor layer; Step S03, forms the dielectric layer covering source area, drain region and first grid;
Step S04, by dielectric layer and the second support substrates bonding;
Step S05, with the second support substrates for supporting, removes the first support substrates and the first removing layer, and forms second gate dielectric layer and second grid successively on the semiconductor layer;
Step S06, completes the subsequent step of device.
7. manufacture method according to claim 6, is characterized in that, described first support substrates is Semiconductor substrate, and described step S02 specifically comprises:
First support substrates is formed with successively the first removing layer, semiconductor layer, first grid dielectric layer, the second removing layer and the first mask layer;
First mask layer described in patterning and the second removing layer, and form the 3rd removing layer at described first mask layer and the second removing layer sidewall;
Under the sheltering of the first mask layer and the 3rd removing layer, remove first grid dielectric layer and under semiconductor layer and the first removing layer, and again form the second mask layer, remove the first mask layer simultaneously;
Under the sheltering of the second mask layer and the 3rd removing layer, remove the second removing layer and under first grid dielectric layer, semiconductor layer and the first removing layer, and again form source area and the first medium layer on it;
Under the sheltering of first medium layer and the 3rd removing layer, remove the second mask layer, and again form drain region and the second dielectric layer on it, source area and drain region have different doping types, and source area and drain region contact with semiconductor layer;
Remove the 3rd removing layer to form the first opening, form the first separator at the first opening sidewalls, and fill the first opening to form first grid.
8. manufacture method according to claim 7, is characterized in that, the first removing layer is silicon dioxide, and semiconductor layer is silicon, and the second removing layer is polysilicon, and the first mask layer and the 3rd removing layer are nitride, and the second mask layer is germanium silicon.
9. manufacture method according to claim 6, it is characterized in that, the step of step S05 is specially: with the second support substrates for supporting, remove the first support substrates and the first removing layer to form the second opening, form second gate dielectric layer on the semiconductor layer, and form the second separator at the sidewall of the second opening, and fill the second opening to form second grid.
10. manufacture method according to claim 6, is characterized in that, the thickness of described semiconductor layer is not more than 10nm.
11. manufacture methods according to claim 6, is characterized in that, before step S03, also comprise step: form the first metal layer connecting first grid;
Step S06 comprises: form the second metal level connecting second grid;
Formation source and drain contacts, and contacting of being connected with the second metal level with the first metal layer respectively.
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