CN108352401A - Tunneling field-effect transistor and preparation method thereof - Google Patents
Tunneling field-effect transistor and preparation method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
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Abstract
A kind of tunneling field-effect transistor and preparation method thereof is provided, technical field of semiconductors is belonged to.The gate capacitance for the gate dielectric layer being located above source region by setting is more than the gate capacitance for the gate dielectric layer being located above channel region, so that under identical grid voltage, grid voltage is better than the ability of regulation and control of line tunnel junctions the ability of regulation and control to tunnel junctions, therefore, the opposite increase of cut-in voltage needed for point tunnel junctions, it can thus delay or postpone the unlatching of a tunnel junctions, the unlatching of entire device can be dominated to ensure that threaded list is worn, ensure that TFEF has the Sub-Threshold Characteristic of steeper so that the lower power consumption of TFET.
Description
The present invention relates to technical field of semiconductors, in particular to a kind of tunneling field-effect transistor and preparation method thereof.
With the rapid development of semiconductor technology, the integration density of transistor is higher and higher in chip.In this case, power consumption becomes the key challenge factor of chip design.The core restraining factors that the key for reducing power consumption is to reduce the supply voltage of transistor, and reduces supply voltage are the subthreshold swing of transistor, the i.e. sharp keen degree that changes from off state to open state of transistor.Precipitous subthreshold value transformation allows the reduction of supply voltage by a larger margin, to realize being greatly reduced for transistor dissipation.TFET (Tunnel Field-Effect Transistor, tunneling field-effect transistor) is a kind of transistor with precipitous Sub-Threshold Characteristic, and therefore, TFET has very big development potentiality in terms of reducing device power consumption.
As shown in Figure 1, it illustrates the structural schematic diagrams of TFET in the prior art a kind of.As shown in Figure 1, source region, drain region, channel region, pocket layer, gate dielectric layer and the grid region being lightly doped in prior art TFET including heavy doping.In Fig. 1,101 indicate source region, and 102 indicate channel region, and 103 indicate drain region, and 104 indicate pocket layer, and 105 indicate gate dielectric layer, and 106 indicate grid region.Wherein, pocket layer is Chong Die with the partial region of the partial region of source region and channel region.Under the action of grid electric field, the carrier accumulation of pocket layer finally forms tunnel junctions with source region, and the carrier tunnelling of source region forms electric current to pocket layer.In TFET shown in FIG. 1, the pocket layer part right above source region and source region constitutes the first tunnel junctions, and on this basis, under the action of grid electric field, carrier can be worn along solid arrow tunnelling, tunnelling direction and grid field parallel for threaded list.Therefore, this kind of tunnelling becomes threaded list and wears knot.In addition, in conjunction with Fig. 1, under this configuration, since the region above channel region is similarly by the regulation of grid electric field, it also will form second of tunnel junctions between the corner and pocket layer of source region, carrier also will do it tunnelling, shown in dotted arrow as shown in figure 1.The tunnelling direction of this kind of tunnelling mode intersects with grid electric field, for a tunnelling.Therefore, this kind of tunnelling becomes a tunnel junctions.In the implementation of the present invention, the inventor finds at least the following defects of the prior art:
Since the cut-in voltage of tunnel junctions is less than the cut-in voltage of line tunnel junctions, it opens invocation point tunnel junctions prior to line tunnel junctions, TFET subthreshold swing is caused to be degenerated, so that TFET is opened slowly, weaken
TFET reduces the ability of operating voltage, causes device to reduce power dissipation capability and degenerates.Therefore, the structure in Fig. 1 makes the power consumption of TFET bigger.
Summary of the invention
Of the existing technology in order to solve the problems, such as, the embodiment of the invention provides a kind of TFET and preparation method thereof.The technical solution is as follows:
In a first aspect, providing a kind of TFET, the TFET includes source region, drain region, channel region, pocket layer, gate dielectric layer and grid region, in which:
The source region and the drain region are separately disposed in inside semiconductor substrate, and the channel region connects the source region and the drain region；
The pocket layer is set to the upper surface of the source region and the channel region, the gate dielectric layer is set to the upper surface of the pocket layer, the grid region is set to the upper surface of the gate dielectric layer, the gate dielectric layer includes first area and second area, the first area is the gate dielectric layer region above the source region, the second area is the gate dielectric layer region above the channel region, and the gate capacitance of the first area is greater than the gate capacitance of the second area；
Wherein, the pocket layer and the source region form the tunnel junctions of the tunneling field-effect transistor.
With reference to first aspect, in the first possible implementation of the first aspect, the gate dielectric layer is made of the first gate dielectric layer and the second gate dielectric layer；The upper surface of the pocket layer is completely covered in first gate dielectric layer, second gate dielectric layer covers the first specified region of first gate dielectric layer upper surface, and the first specified region is the region being located above the channel region in first gate dielectric layer upper surface；
Wherein, the material of first gate dielectric layer is high dielectric material, the material of second gate dielectric layer is dielectric materials, the high dielectric material refers to that relative dielectric constant is greater than the dielectric material of the relative dielectric constant of silica, and the dielectric materials refer to that relative dielectric constant is less than the dielectric material of the relative dielectric constant of silica.
With reference to first aspect, in the second possible implementation of the first aspect, the gate dielectric layer is made of third gate dielectric layer and the 4th gate dielectric layer；The third gate dielectric layer covers the second specified region of pocket layer upper surface, and the second specified region is the region being located above the channel region in pocket layer upper surface；The third of the third gate dielectric layer is completely covered in 4th gate dielectric layer upper surface and pocket layer upper surface specifies region, and it is region of the pocket layer upper surface in addition to the described second specified region that the third, which specifies region,；
Wherein, the material of the third gate dielectric layer is dielectric materials, the material of the 4th gate dielectric layer
For high dielectric material, the dielectric materials refer to that relative dielectric constant is less than the dielectric material of the relative dielectric constant of silica, and the high dielectric material refers to that relative dielectric constant is greater than the dielectric material of the relative dielectric constant of silica.
With reference to first aspect, in a third possible implementation of the first aspect, the thickness of the first area is less than the thickness of the second area, and the material of the first area and the second area is same high dielectric material；
Wherein, the high dielectric material refers to that relative dielectric constant is greater than the dielectric material of the relative dielectric constant of silica.
With reference to first aspect, in a fourth possible implementation of the first aspect, the gate dielectric layer is made of the 5th gate dielectric layer and the 6th gate dielectric layer；The upper surface of the pocket layer is completely covered in 5th gate dielectric layer, the upper surface of the 5th gate dielectric layer is completely covered in 6th gate dielectric layer, and the 6th gate dielectric layer includes third region and the fourth region, the third region is the 6th gate dielectric layer region above the source region, and the fourth region is the 6th gate dielectric layer region above the channel region；
Wherein, the material of 5th gate dielectric layer and the material in the third region are high dielectric material, the material of the fourth region is dielectric materials, the high dielectric material refers to that relative dielectric constant is greater than the dielectric material of the relative dielectric constant of silica, and the dielectric materials refer to that relative dielectric constant is less than the dielectric material of the relative dielectric constant of silica.
With reference to first aspect, in the fifth possible implementation of the first aspect,
The pocket layer, the gate dielectric layer and the grid region two sides are prepared with divider wall；
The specified location of the source region, the grid region and the drain region is prepared with metal source, metal gate electrode and metal leakage pole respectively, and the divider wall is for being isolated the metal source, the metal gate electrode and the metal leakage pole.
Any possible implementation into the 5th kind of possible implementation of first aspect with reference to first aspect, in the sixth possible implementation of the first aspect,
The material of the semiconductor substrate is one of body silicon, the silicon on insulator, germanium silicon, germanium and Group III-V compound semiconductor；
The material of the pocket layer is one of silicon, germanium silicon, germanium and Group III-V compound semiconductor；
The material in the grid region is one of polysilicon, metal and polysilicon and the multi-layer compound structure of metal.
Second aspect, additionally provides the preparation method of TFET a kind of, and the preparation method includes:
According to the type of tunneling field-effect transistor, trap injection is carried out to default substrate, is obtained and the tunnelling
The semiconductor substrate of the type matching of field effect transistor；
It is prepared apart source region and drain region inside the semiconductor substrate, and channel region is made to connect the source region and the drain region；
Pocket layer is prepared in the upper surface of the source region and the channel region, the pocket layer and the source region form the tunnel junctions of the tunneling field-effect transistor；
Gate dielectric layer is prepared in the upper surface of the pocket layer, the gate dielectric layer includes first area and second area, the first area is the gate dielectric layer region above the source region, the second area is the gate dielectric layer region above the channel region, and the gate capacitance of the first area is greater than the gate capacitance of the second area；
Grid region is prepared in the upper surface of the gate dielectric layer.
It is in the first possible implementation of the second aspect, described that source region and drain region are prepared apart inside semiconductor substrate in conjunction with second aspect, comprising:
The default drain region in the semiconductor substrate is protected using photoetching technique, the first ion implanting is carried out to the default source region in the semiconductor substrate；
The source region is protected using photoetching technique, second of ion implanting is carried out to the default drain region；
Rta technique is carried out to the structure for completing ion implanting, generates source region and drain region.
In conjunction with the first possible implementation of second aspect; in a second possible implementation of the second aspect; it is described to protect the default drain region in the semiconductor substrate using photoetching technique, before carrying out the first ion implanting to the default source region in the semiconductor substrate, further includes:
Protective layer is prepared on the semiconductor substrate, it is described protective layer used in when carrying out ion implanting to the default source region and the default drain region, protect the semiconductor substrate；
The sacrificial layer of designated shape is prepared on the protective layer, the sacrificial layer is used to be formed self-aligned the channel region when carrying out ion implanting to the default source region and the default drain region.
In conjunction with second aspect, in the third possible implementation of the second aspect, the upper surface in the pocket layer prepares gate dielectric layer, comprising:
The first gate dielectric layer is deposited in pocket layer upper surface using high dielectric material, the high dielectric material refers to that relative dielectric constant is greater than the dielectric material of the relative dielectric constant of silica；
First specified the second gate dielectric layer of area deposition using dielectric materials in first gate dielectric layer upper surface, the first specified region is the region being located above the channel region in first gate dielectric layer upper surface, and the dielectric materials refer to that relative dielectric constant is less than the dielectric material of the relative dielectric constant of silica；
Wherein, the gate dielectric layer is made of first gate dielectric layer and second gate dielectric layer.
In conjunction with second aspect, in the fourth possible implementation of the second aspect, the upper surface in the pocket layer prepares gate dielectric layer, comprising:
The second specified area deposition third gate dielectric layer using dielectric materials in pocket layer upper surface, the second specified region is the region being located above the channel region in pocket layer upper surface, and the dielectric materials refer to that relative dielectric constant is less than the dielectric material of the relative dielectric constant of silica；
The 4th gate dielectric layer of area deposition is specified in the third of third gate dielectric layer upper surface and pocket layer upper surface using high dielectric material, it is region of the pocket layer upper surface in addition to the described second specified region that the third, which specifies region, and the high dielectric material refers to that relative dielectric constant is greater than the dielectric material of the relative dielectric constant of silica；
Wherein, the gate dielectric layer is made of the third gate dielectric layer and the 4th gate dielectric layer.
In conjunction with second aspect, in a fifth possible implementation of the second aspect, the upper surface in the pocket layer prepares gate dielectric layer, comprising:
Initial gate dielectric layer is deposited in the upper surface of the pocket layer using high dielectric material；
4th specified region of the initial gate dielectric layer is carried out thinned, obtains gate dielectric layer, the 4th specified region is the region being located above the source region in the initial gate dielectric layer.
In conjunction with second aspect, in the sixth possible implementation of the second aspect, the upper surface in the pocket layer prepares gate dielectric layer, comprising:
The 5th gate dielectric layer is deposited in pocket layer upper surface using high dielectric material；
Using high dielectric material in the third region of the 5th specified the 6th gate dielectric layer of area deposition of the 5th gate dielectric layer upper surface, using dielectric materials the 6th specified the 6th gate dielectric layer of area deposition of the 5th gate dielectric layer upper surface the fourth region, the 5th specified region is the region being located above the source region in the 5th gate dielectric layer upper surface, the 6th specified region is the region being located above the channel region in the 5th gate dielectric layer upper surface, the high dielectric material refers to that relative dielectric constant is greater than the dielectric material of the relative dielectric constant of silica, the dielectric materials refer to that relative dielectric constant is less than the dielectric material of the relative dielectric constant of silica；
Wherein, the gate dielectric layer is made of the 5th gate dielectric layer and the 6th gate dielectric layer.
In conjunction with second aspect, in the 7th kind of possible implementation of second aspect, the upper surface in the gate dielectric layer is prepared after grid region, further includes:
Divider wall is prepared in the pocket layer, the gate dielectric layer and the grid region two sides；
Dielectric materials are filled on the outside of the divider wall and the grid region；
Metal source, metal gate electrode and metal leakage pole are prepared respectively in the specified location of the source region, the grid region and the drain region, and the divider wall is for being isolated the metal source, the metal gate electrode and the metal leakage pole.
The beneficial effect of technical solution provided in an embodiment of the present invention is:
Gate capacitance by the way that the gate dielectric layer being located above source region is arranged is greater than the gate capacitance for the gate dielectric layer being located above channel region, so that grid voltage is better than the ability of regulation and control to tunnel junctions to the ability of regulation and control of line tunnel junctions under identical grid voltage.Therefore, cut-in voltage needed for putting tunnel junctions is opposite to be increased, it is thus possible to delay or postpone the unlatching of some tunnel junctions, to guarantee that threaded list wears the unlatching that can dominate entire device, it is ensured that TFEF has the Sub-Threshold Characteristic of steeper, so that the lower power consumption of TFET.
To describe the technical solutions in the embodiments of the present invention more clearly, the accompanying drawings required for describing the embodiments of the present invention are briefly described below, apparently, drawings in the following description are only some embodiments of the invention, for those of ordinary skill in the art, without creative efforts, it is also possible to obtain other drawings based on these drawings.
Fig. 1 is the structural schematic diagram of TFET in the prior art a kind of；
Fig. 2 be another embodiment of the present invention provides a kind of TFET structural schematic diagram；
Fig. 3 be another embodiment of the present invention provides a kind of TFET structural schematic diagram；
Fig. 4 be another embodiment of the present invention provides a kind of TFET structural schematic diagram；
Fig. 5 be another embodiment of the present invention provides a kind of TFET structural schematic diagram；
Fig. 6 be another embodiment of the present invention provides a kind of TFET preparation method flow chart；
Fig. 7 be another embodiment of the present invention provides a kind of TFET preparation method flow chart；
Fig. 8 be another embodiment of the present invention provides a kind of semiconductor substrate schematic diagram；
Fig. 9 be another embodiment of the present invention provides a kind of protective layer and sacrificial layer schematic diagram；
Figure 10 be another embodiment of the present invention provides a Provenance Region and drain region schematic diagram；
Figure 11 be another embodiment of the present invention provides a kind of initial pocket layer, initial first gate dielectric layer and initial second gate dielectric layer schematic diagram；
Figure 12 be another embodiment of the present invention provides a kind of etching after initial second gate dielectric layer schematic diagram；
Figure 13 be another embodiment of the present invention provides a kind of initial pocket layer, initial first gate dielectric layer, initial second gate dielectric layer and initial grid region after etching schematic diagram；
Figure 14 be another embodiment of the present invention provides a kind of divider wall schematic diagram；
Figure 15 be another embodiment of the present invention provides a kind of TFET preparation method flow chart；
Figure 16 be another embodiment of the present invention provides a kind of TFET preparation method flow chart；
Figure 17 be another embodiment of the present invention provides a kind of TFET preparation method flow chart.
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing, embodiment of the present invention is described further in detail.
It include source region, drain region, channel region, pocket layer, gate dielectric layer and grid region the embodiment of the invention provides a kind of TFET, the TFET, in which:
Source region and drain region are separately disposed in inside semiconductor substrate, and channel region connection source region and drain region；Pocket layer is set to the upper surface of source region and channel region, and gate dielectric layer is set to the upper surface of pocket layer, and grid region is set to the upper surface of gate dielectric layer.
It is not especially limited about pocket layer, gate dielectric layer and the thickness in grid region, the embodiment of the present invention, pocket layer, gate dielectric layer and the thickness in grid region may be the same or different.In an alternative embodiment, pocket layer, gate dielectric layer and the thickness in grid region can be set to any value in 1 nanometer to 5 nanometers.
Wherein, gate dielectric layer includes first area and second area, and first area is the gate dielectric layer region above source region, and second area is the gate dielectric layer region above channel region, and the gate capacitance of first area is greater than the gate capacitance of second area.Grid voltage passes through second area control point tunnel junctions by first area control line tunnel junctions.Gate capacitance refers to when constituting capacitor by grid region, gate dielectric layer and source region and drain region, the capacitance size on gate dielectric layer surface.
Pocket layer at least covering part source region and part channel region.Wherein, the doping concentration of pocket layer is less than the doping concentration of source region.The tunnel junctions of pocket layer and source region composition tunneling field-effect transistor.In the TFET, grid region is used to determine the open and close of TFET.When the gate control voltage of TFET is less than threshold voltage, TFET is in close state；When the gate control voltage of TFET is greater than threshold voltage, TFET is in the open state.Under the action of grid electric field, the carrier accumulation of pocket layer finally forms tunnel junctions with source region, and the carrier tunnelling of source region forms electric current to pocket layer.
In embodiments of the present invention, the material of semiconductor substrate can be one of silicon (SOI, Silicon-on-insulator), germanium silicon, germanium and the Group III-V compound semiconductor on body silicon, insulator.The material of pocket layer can be one of silicon, germanium silicon, germanium and Group III-V compound semiconductor.The material in grid region can
Think one of the multi-layer compound structure of polysilicon, metal and polysilicon and metal.The material of semiconductor substrate and pocket layer may be the same or different.Channel region is conductive path of the carrier from source region to drain region.Since channel region is the partial region inside semiconductor substrate, the material of channel region and the material of semiconductor substrate are identical.
In embodiments of the present invention, when the gate capacitance for making gate dielectric layer first area is greater than the gate capacitance of gate dielectric layer second area, it can be met certain condition by control gate dielectric layer in the material and/or composed structure of first area and second area to realize, material and structure about gate dielectric layer will elaborate in subsequent each embodiment, wouldn't repeat herein.In addition, the content of TFET described in the embodiment of the present invention is suitable for following each embodiments, it will not remake and repeat for identical content in subsequent each embodiment.
TFET provided in an embodiment of the present invention, gate capacitance by the way that the gate dielectric layer being located above source region is arranged is greater than the gate capacitance for the gate dielectric layer being located above channel region, so that under identical grid voltage, grid voltage is better than the ability of regulation and control to tunnel junctions to the ability of regulation and control of line tunnel junctions, therefore, cut-in voltage needed for point tunnel junctions is opposite to be increased, it can thus delay or postpone the unlatching of a tunnel junctions, to guarantee that threaded list wears the unlatching that can dominate entire device, ensure that TFEF has the Sub-Threshold Characteristic of steeper, so that the lower power consumption of TFET.
In conjunction with the content of above-described embodiment, Fig. 2 be another embodiment of the present invention provides a kind of TFET structural schematic diagram.Embodiment corresponding to Fig. 2 makes the gate capacitance of gate dielectric layer first area be greater than the gate capacitance of gate dielectric layer second area by controlling composed structure and the material of gate dielectric layer.
As shown in Fig. 2, source region 201 and drain region 203 are separately disposed in inside semiconductor substrate 200 in TFET provided in an embodiment of the present invention；Channel region 202 connects source region 201 and drain region 203.Pocket layer 204 is set to the partial region of 200 upper surface of semiconductor substrate, and pocket layer 204 at least covering part source region 201 and part channel region 202.
Wherein, pocket layer 204 can not be contacted with drain region 203.Pocket layer 204 does not contact a possibility that capable of reducing TFET electric leakage with drain region 203, so as to improve the performance of TFET.
In embodiments of the present invention, as shown in Fig. 2, gate dielectric layer 205 is set on pocket layer 204, and gate dielectric layer 205 is made of the first gate dielectric layer 205.1 and the second gate dielectric layer 205.2.Wherein, the upper surface of pocket layer 204 is completely covered in first gate dielectric layer 205.1, second gate dielectric layer 205.2 covers the first specified region of 205.1 upper surface of the first gate dielectric layer, which is the region for being located at 202 top of channel region in 205.1 upper surface of the first gate dielectric layer.
It can be obtained by Fig. 2, in embodiments of the present invention, the first area of gate dielectric layer 205 is the first gate medium
Layer 205.1 is located at the region of 201 top of source region, and the second area of gate dielectric layer 205 is region and the second gate dielectric layer 205.2 that the first gate dielectric layer 205.1 is located at 202 top of channel region.In Fig. 2, the corresponding gate dielectric layer in region of label " one " is the first area of gate dielectric layer 205, and the corresponding gate dielectric layer in region of label " two " is the second area of gate dielectric layer 205.
Wherein, the relative dielectric constant of the material of the first gate dielectric layer 205.1 is greater than the relative dielectric constant of the material of the second gate dielectric layer 205.2.For example, the material of the first gate dielectric layer 205.1 can be high dielectric material, the material of the second gate dielectric layer 205.2 can be dielectric materials.High dielectric material refers to that relative dielectric constant is greater than the dielectric material of the relative dielectric constant of silica, and dielectric materials refer to that relative dielectric constant is less than the dielectric material of the relative dielectric constant of silica.Wherein, relative dielectric constant refers to that the dielectric constant of relative vacuum, the dielectric constant of silica relative vacuum are 3.9.
In conjunction with Fig. 2, in embodiments of the present invention, it is the region that the first gate dielectric layer 205.1 is located at 201 top of source region by setting 205 first area of gate dielectric layer, second area is region and the second gate dielectric layer 205.2 that the first gate dielectric layer 205.1 is located at 202 top of channel region, so that thickness of the gate dielectric layer 205 in first area is obviously smaller than the thickness of second area, and the gate capacitance of gate dielectric layer 205 and the thickness of gate dielectric layer 205 are inversely proportional, so that gate capacitance of the gate dielectric layer 205 in first area is greater than the gate capacitance of second area.Further, in embodiments of the present invention, material by the way that the first gate dielectric layer 205.1 is arranged is high dielectric material, the material of second gate dielectric layer 205.2 is dielectric materials, so that the relative dielectric constant of 205.1 material of the first gate dielectric layer is greater than the relative dielectric constant of 205.2 material of the second gate dielectric layer, so that the average relative dielectric constant of 205 first area of gate dielectric layer is greater than the average relative dielectric constant of second area, and the gate capacitance of gate dielectric layer 205 is directly proportional to the relative dielectric constant of 205 material of gate dielectric layer, so that the gate capacitance of 205 first area of gate dielectric layer is greater than the gate capacitance of second area.
In conjunction with Fig. 2, in an alternative embodiment, pocket layer 204, gate dielectric layer 205 and 206 two sides of grid region are prepared with divider wall 207.The material of divider wall 207 is that insulating materials, the shapes of divider wall 207 such as silicon nitride can be sickle shaped as shown in Figure 2, or rectangle etc..206 periphery of grid region and 207 periphery of divider wall can be filled with dielectric materials 208, such as silicon nitride (Si3N4) etc..In addition, the specified location of source region 201, grid region 206 and drain region 203 is prepared with metal source 209, metal gate electrode 211 and metal leakage pole 210 respectively.
It should be noted that " designated position " as described in the examples is the pre-set position for being used to prepare metal source 209, metal gate electrode 211 and metal leakage pole 210.For example, designated position can not be isolated any position of the covering of wall 207 for 201 upper surface of source region, any position of 206 upper surface of grid region, 203 upper surface of drain region is not isolated any position of the covering of wall 207.
Wherein, since divider wall 207 is insulating materials, it can be used for isolating metal source electrode 209, metal gate electrode 211 and metal leakage pole 210, to avoid the occurrence of short circuit phenomenon.In addition, the material based on divider wall 207 is capable of fixing the shape in grid region 206, pocket layer 204 and gate dielectric layer 205 so that the mechanical performance of divider wall 207 is relatively good.
By filling dielectric materials 208, the parasitic capacitance of TFET can be prevented excessive.In addition, the mechanical support to metal source 209, metal gate electrode 211 and metal leakage pole 210 can be played the role of by dielectric materials.
TFET provided in an embodiment of the present invention, it is that the first gate dielectric layer is located at the region above source region by setting gate dielectric layer first area, second area is that the first gate dielectric layer is located at region and the second gate dielectric layer above channel region, so that thickness of the gate dielectric layer in first area is obviously smaller than the thickness of second area, and the material by the way that the first gate dielectric layer is arranged is high dielectric material, the material of second gate dielectric layer is dielectric materials, so that the average relative dielectric constant of gate dielectric layer first area is greater than the average relative dielectric constant of second area, and the gate capacitance of gate dielectric layer is inversely proportional to the thickness, and it is directly proportional to the relative dielectric constant of its material, so that the gate capacitance of gate dielectric layer first area is greater than the gate capacitance of second area, it is located above channel region so that the gate capacitance for the gate dielectric layer being located above source region is greater than Gate dielectric layer gate capacitance, make under identical grid voltage, grid voltage is better than the ability of regulation and control to tunnel junctions to the ability of regulation and control of line tunnel junctions, therefore, cut-in voltage needed for point tunnel junctions is opposite to be increased, it is thus possible to delay or postpone the unlatching of some tunnel junctions, to guarantee that threaded list wears the unlatching that can dominate entire device, ensure that TFEF has the Sub-Threshold Characteristic of steeper, so that the lower power consumption of TFET.
In conjunction with the content of above-described embodiment, Fig. 3 be another embodiment of the present invention provides a kind of TFET structural schematic diagram, embodiment corresponding to Fig. 3 makes the gate capacitance of gate dielectric layer first area be greater than the gate capacitance of gate dielectric layer second area by controlling composed structure and the material of gate dielectric layer.
As shown in figure 3, source region 301 and drain region 303 are separately disposed in inside semiconductor substrate 300 in TFET provided in an embodiment of the present invention；Channel region 302 connects source region 301 and drain region 303.Pocket layer 304 is set to the partial region of 300 upper surface of semiconductor substrate, and pocket layer 304 at least covering part source region 301 and part channel region 302, pocket layer 304 are not contacted with drain region 303.Pocket layer 304 does not contact a possibility that capable of reducing TFET electric leakage with drain region 303, so as to improve the performance of TFET.
In embodiments of the present invention, as shown in figure 3, gate dielectric layer 305 is set on pocket layer 304, and gate dielectric layer 305 is made of third gate dielectric layer 305.3 and the 4th gate dielectric layer 305.4.Wherein, third gate dielectric layer 305.3 covers the second specified region of the upper surface of pocket layer 304, the second specified region
For the region for being located at 302 top of channel region in 304 upper surface of pocket layer.The third that 304 upper surface of upper surface and pocket layer of third gate dielectric layer 305.3 is completely covered in 4th gate dielectric layer 305.4 specifies region, and it is region of 304 upper surface of pocket layer in addition to the second specified region which, which specifies region,.
It can be obtained by Fig. 3, in embodiments of the present invention, the first area of gate dielectric layer 305 is the region that the 4th gate dielectric layer 305.4 is located at 301 top of source region, and the second area of gate dielectric layer 305 is the region that third gate dielectric layer 305.3 and the 4th gate dielectric layer 305.4 are located at 302 top of channel region.In Fig. 3, the corresponding gate dielectric layer in region of label " one " is the first area of gate dielectric layer 305, and the corresponding gate dielectric layer in region of label " two " is the second area of gate dielectric layer 305.
Wherein, relative dielectric constant of the relative dielectric constant of 305.3 material of third gate dielectric layer less than 305.4 material of the 4th gate dielectric layer.For example, the material of third gate dielectric layer 305.3 can be dielectric materials, the material of the 4th gate dielectric layer 305.4 can be high dielectric material.
In conjunction with Fig. 3, in embodiments of the present invention, it is the region that the 4th gate dielectric layer 305.4 is located at 301 top of source region by setting 305 first area of gate dielectric layer, the second area of gate dielectric layer 305 is the region that third gate dielectric layer 305.3 and the 4th gate dielectric layer 305.4 are located at 302 top of channel region, so that thickness of the gate dielectric layer 305 in first area is obviously smaller than the thickness of second area, and the gate capacitance of gate dielectric layer 305 and the thickness of gate dielectric layer 305 are inversely proportional, so that gate capacitance of the gate dielectric layer 305 in first area is greater than the gate capacitance of second area.Further, in embodiments of the present invention, material by the way that third gate dielectric layer 305.3 is arranged is dielectric materials, the material of 4th gate dielectric layer 305.4 is high dielectric material, so that relative dielectric constant of the relative dielectric constant of 305.3 material of third gate dielectric layer less than 305.4 material of the 4th gate dielectric layer, so that the average relative dielectric constant of 305 first area of gate dielectric layer is greater than the average relative dielectric constant of second area, and the gate capacitance of gate dielectric layer 305 is directly proportional to the relative dielectric constant of 305 material of gate dielectric layer, so that the gate capacitance of 305 first area of gate dielectric layer is greater than the gate capacitance of second area.
In conjunction with Fig. 3, in an alternative embodiment, pocket layer 304, gate dielectric layer 305 and 306 two sides of grid region are prepared with divider wall 307, the periphery of grid region 306 and 307 periphery of divider wall can be filled with dielectric materials 308 (dielectric materials are not shown in Fig. 3), and the specified location of source region 301, grid region 306 and drain region 303 be prepared with metal source 309, metal gate electrode 311 and metal leakage pole 310 (metal source 309, metal gate electrode 311 and metal leakage pole 310 are not shown in Fig. 3) respectively.
About being illustrated in divider wall 307, dielectric materials 308, metal source 309, metal gate electrode 311 and the contents such as the material of metal leakage pole 310 and the effect embodiment corresponding to above-mentioned Fig. 2, particular content can be found in the content in embodiment corresponding to above-mentioned Fig. 2, and details are not described herein again.
TFET provided in an embodiment of the present invention, the first area by the way that gate dielectric layer is arranged are the 4th gate medium
Layer is located at the region above source region, the second area of gate dielectric layer is that third gate dielectric layer and the 4th gate dielectric layer are located at the region above channel region, so that thickness of the gate dielectric layer in first area is obviously smaller than the thickness of second area, and the material by the way that third gate dielectric layer is arranged is dielectric materials, the material of 4th gate dielectric layer is high dielectric material, so that the average relative dielectric constant of gate dielectric layer first area is greater than the average relative dielectric constant of second area, and the gate capacitance of gate dielectric layer is inversely proportional to the thickness, and it is directly proportional to the relative dielectric constant of its material, so that the gate capacitance of gate dielectric layer first area is greater than the gate capacitance of second area, so that the gate capacitance for the gate dielectric layer being located above source region is greater than the gate capacitance for the gate dielectric layer being located above channel region, make under identical grid voltage, tune of the grid voltage to line tunnel junctions Control ability is better than the ability of regulation and control to tunnel junctions.Therefore, cut-in voltage needed for putting tunnel junctions is opposite to be increased, it is thus possible to delay or postpone the unlatching of some tunnel junctions, to guarantee that threaded list wears the unlatching that can dominate entire device, it is ensured that TFEF has the Sub-Threshold Characteristic of steeper, so that the lower power consumption of TFET.
In conjunction with the content of above-described embodiment, Fig. 4 be another embodiment of the present invention provides a kind of TFET structural schematic diagram, embodiment corresponding to Fig. 4 makes the gate capacitance of gate dielectric layer first area be greater than the gate capacitance of gate dielectric layer second area by control gate dielectric layer in the thickness of different zones.
As shown in figure 4, source region 401 and drain region 403 are separately disposed in inside semiconductor substrate 400 in TFET provided in an embodiment of the present invention；Channel region 402 connects source region 401 and drain region 403.Pocket layer 404 is set to the partial region of 400 upper surface of semiconductor substrate, and pocket layer 404 at least covering part source region 401 and part channel region 402, pocket layer 404 are not contacted with drain region 403.Pocket layer 404 does not contact a possibility that capable of reducing TFET electric leakage with drain region 403, so as to improve the performance of TFET.
In embodiments of the present invention, as shown in figure 4, gate dielectric layer 405 is set on pocket layer 404, and the thickness of 305 first area of gate dielectric layer is less than the thickness of second area, and the material of first area and second area is same high dielectric material.Wherein, first area is the region above source region 401, and second area is the region above channel region 402.In Fig. 4, the corresponding gate dielectric layer in region of label " one " is the first area of gate dielectric layer 405, and the corresponding gate dielectric layer in region of label " two " is the second area of gate dielectric layer 405.
In embodiments of the present invention, in conjunction with Fig. 4, since the thickness of 405 first area of gate dielectric layer is less than the thickness of second area, and the gate capacitance of gate dielectric layer 405 and the thickness of gate dielectric layer 405 are inversely proportional, so that gate capacitance of the gate dielectric layer 305 in first area is greater than the gate capacitance of second area.
In conjunction with Fig. 4, in an alternative embodiment, pocket layer 404, gate dielectric layer 405 and 406 two sides of grid region are prepared with divider wall 40, and 406 periphery of grid region and 407 periphery of divider wall can be filled with dielectric materials
408 (dielectric materials are not shown in Fig. 4), the specified location of source region 401, grid region 406 and drain region 403 are prepared with metal source 409, metal gate electrode 411 and metal leakage pole 410 (metal source 409, metal gate electrode 411 and metal leakage pole 410 are not shown in Fig. 4) respectively.
About being illustrated in divider wall 407, dielectric materials 408, metal source 409, metal gate electrode 411 and the contents such as the material of metal leakage pole 410 and the effect embodiment corresponding to above-mentioned Fig. 2, particular content can be found in the content in embodiment corresponding to above-mentioned Fig. 2, and details are not described herein again.
TFET provided in an embodiment of the present invention, thickness by the way that the first area of gate dielectric layer is arranged is less than the thickness of second area, and the gate capacitance of gate dielectric layer is inversely proportional to the thickness, so that the gate capacitance of gate dielectric layer first area is greater than the gate capacitance of second area, so that grid voltage is better than the ability of regulation and control to tunnel junctions to the ability of regulation and control of line tunnel junctions under identical grid voltage.Therefore, cut-in voltage needed for putting tunnel junctions is opposite to be increased, it is thus possible to delay or postpone the unlatching of some tunnel junctions, to guarantee that threaded list wears the unlatching that can dominate entire device, it is ensured that TFEF has the Sub-Threshold Characteristic of steeper, so that the lower power consumption of TFET.
In conjunction with the content of above-described embodiment, Fig. 5 be another embodiment of the present invention provides a kind of TFET structural schematic diagram, embodiment corresponding to Fig. 5 makes the gate capacitance of gate dielectric layer first area be greater than the gate capacitance of gate dielectric layer second area by controlling the composition material of gate dielectric layer.
As shown in figure 5, source region 501 and drain region 503 are separately disposed in inside semiconductor substrate 500 in TFET provided in an embodiment of the present invention；Channel region 502 connects source region 501 and drain region 503.Pocket layer 504 is set to the partial region of 500 upper surface of semiconductor substrate, and pocket layer 504 at least covering part source region 501 and part channel region 502, pocket layer 504 are not contacted with drain region 503.Pocket layer 504 does not contact a possibility that capable of reducing TFET electric leakage with drain region 503, so as to improve the performance of TFET.
In embodiments of the present invention, as shown in figure 5, gate dielectric layer 505 is set on pocket layer 504, and gate dielectric layer 505 is made of the 5th gate dielectric layer 505.5 and the 6th gate dielectric layer 505.6.Wherein, the upper surface of pocket layer 504 is completely covered in 5th gate dielectric layer 505.5, the upper surface of the 5th gate dielectric layer 505.5 is completely covered in 6th gate dielectric layer 505.6, and the 6th gate dielectric layer 505.6 include third region and the fourth region, third region is the region that the 6th gate dielectric layer 505.6 is located at 501 top of source region, and the fourth region is the region that the 6th gate dielectric layer 505.6 is located at 502 top of channel region.
It can be obtained in conjunction with Fig. 5, in embodiments of the present invention, the first area of gate dielectric layer 505 is the region that the region that the 5th gate dielectric layer 505.5 is located above source region 501 and the 6th gate dielectric layer 505.6 are located at 501 top of source region, and the second area of gate dielectric layer 505 is the region that the region that the 5th gate medium 505.5 is located above channel region 502 and the 6th gate dielectric layer 505.6 are located at 502 top of channel region.In Fig. 5, mark " one "
The corresponding gate dielectric layer in region be gate dielectric layer 505 first area, label " two " the corresponding gate dielectric layer in region be gate dielectric layer 505 second area.
Wherein, the relative dielectric constant of 505.6 third region material of 505.5 material of the 5th gate dielectric layer and the 6th gate dielectric layer is greater than the relative dielectric constant of the material of 505.6 the fourth region of the 6th gate dielectric layer.For example, the material in the 505.6 third region of material and the 6th gate dielectric layer of the 5th gate dielectric layer 505.5 is high dielectric material, the material of 505.6 the fourth region of the 6th gate dielectric layer is dielectric materials.
In conjunction with Fig. 5, in embodiments of the present invention, material by the 505.6 third region of material and the 6th gate dielectric layer that the 5th gate dielectric layer 505.5 is arranged is high dielectric material, the material of 6th gate dielectric layer, 505.6 the fourth region is dielectric materials, so that the average relative dielectric constant of 505 first area of gate dielectric layer is greater than the average relative dielectric constant of second area, and the gate capacitance of gate dielectric layer 505 is directly proportional to the relative dielectric constant of 505 material of gate dielectric layer, so that the gate capacitance of 505 first area of gate dielectric layer is greater than the gate capacitance of second area.
In conjunction with Fig. 5, in an alternative embodiment, pocket layer 504, gate dielectric layer 505 and 506 two sides of grid region are prepared with divider wall 507, the periphery of grid region 506 and 507 periphery of divider wall can be filled with dielectric materials 508 (dielectric materials are not shown in Fig. 5), and the specified location of source region 501, grid region 506 and drain region 503 be prepared with metal source 509, metal gate electrode 511 and metal leakage pole 510 (metal source 509, metal gate electrode 511 and metal leakage pole 510 are not shown in Fig. 5) respectively.
About being illustrated in divider wall 507, dielectric materials 508, metal source 509, metal gate electrode 511 and the contents such as the material of metal leakage pole 510 and the effect embodiment corresponding to above-mentioned Fig. 2, particular content can be found in the content in embodiment corresponding to above-mentioned Fig. 2, and details are not described herein again.
TFET provided in an embodiment of the present invention, it is high dielectric material by the material of the 5th gate dielectric layer of setting and the material in the 6th gate dielectric layer third region, the material of 6th gate dielectric layer the fourth region is dielectric materials, so that the average relative dielectric constant of gate dielectric layer first area is greater than the average relative dielectric constant of second area, and the gate capacitance of gate dielectric layer is directly proportional to the relative dielectric constant of its material, so that the gate capacitance of gate dielectric layer first area is greater than the gate capacitance of second area, so that the gate capacitance for the gate dielectric layer being located above source region is greater than the gate capacitance for the gate dielectric layer being located above channel region, so that under identical grid voltage, grid voltage is better than the ability of regulation and control to tunnel junctions to the ability of regulation and control of line tunnel junctions.Therefore, cut-in voltage needed for putting tunnel junctions is opposite to be increased, it is thus possible to delay or postpone the unlatching of some tunnel junctions, to guarantee that threaded list wears the unlatching that can dominate entire device, it is ensured that TFEF has the Sub-Threshold Characteristic of steeper, so that the lower power consumption of TFET.
The content of the embodiment in conjunction with corresponding to above-mentioned Fig. 2 to Fig. 5, the embodiment of the invention also provides the preparation method of TFET a kind of, which can be used for preparing the TFET of the offer of embodiment corresponding to above-mentioned Fig. 2 to Fig. 5.Fig. 6 be another embodiment of the present invention provides a kind of TFET preparation method flow chart.As shown in fig. 6, the preparation method of TFET provided in an embodiment of the present invention includes:
601, according to the type of tunneling field-effect transistor, trap injection is carried out to default substrate, obtains the semiconductor substrate with the type matching of tunneling field-effect transistor.
602, it is prepared apart source region and drain region inside semiconductor substrate, and makes channel region connection source region and drain region.
603, pocket layer is prepared in the upper surface of source region and channel region, wherein the tunnel junctions of pocket layer and source region composition tunneling field-effect transistor.
604, gate dielectric layer is prepared in the upper surface of pocket layer, wherein, gate dielectric layer includes first area and second area, first area is the gate dielectric layer region above source region, second area is the gate dielectric layer region above channel region, and the gate capacitance of first area is greater than the gate capacitance of second area.
605, grid region is prepared in the upper surface of gate dielectric layer.
The preparation method of TFET provided in an embodiment of the present invention, gate capacitance by the way that the gate dielectric layer being located above source region is arranged is greater than the gate capacitance for the gate dielectric layer being located above channel region, so that under identical grid voltage, grid voltage is better than the ability of regulation and control to tunnel junctions to the ability of regulation and control of line tunnel junctions, therefore, cut-in voltage needed for point tunnel junctions is opposite to be increased, it can thus delay or postpone the unlatching of a tunnel junctions, to guarantee that threaded list wears the unlatching that can dominate entire device, ensure that TFEF has the Sub-Threshold Characteristic of steeper, so that the lower power consumption of TFET.
In another embodiment, source region and drain region are prepared apart inside semiconductor substrate, comprising:
Using the default drain region in photoetching technique protection semiconductor substrate, the first ion implanting is carried out to the default source region in semiconductor substrate；
Source region is protected using photoetching technique, second of ion implanting is carried out to default drain region；
Rta technique is carried out to the structure for completing ion implanting, generates source region and drain region.
In another embodiment, using the default drain region in photoetching technique protection semiconductor substrate, before carrying out the first ion implanting to the default source region in semiconductor substrate, further includes:
Protective layer is prepared on a semiconductor substrate, wherein it is protective layer used in when carrying out ion implanting to default source region and default drain region, protect semiconductor substrate；
The sacrificial layer of designated shape is prepared on the protection layer, wherein sacrificial layer is used to be formed self-aligned channel region when carrying out ion implanting to default source region and default drain region.
In another embodiment, gate dielectric layer is prepared in the upper surface of pocket layer, comprising:
The first gate dielectric layer is deposited in pocket layer upper surface using high dielectric material, wherein high dielectric material refers to that relative dielectric constant is greater than the dielectric material of the relative dielectric constant of silica；
First specified the second gate dielectric layer of area deposition using dielectric materials in the first gate dielectric layer upper surface, wherein, first specified region is the region being located above channel region in the first gate dielectric layer upper surface, and dielectric materials refer to that relative dielectric constant is less than the dielectric material of the relative dielectric constant of silica；
Wherein, gate dielectric layer is made of the first gate dielectric layer and the second gate dielectric layer.
In another embodiment, gate dielectric layer is prepared in the upper surface of pocket layer, comprising:
The second specified area deposition third gate dielectric layer using dielectric materials in pocket layer upper surface, wherein, second specified region is the region being located above channel region in pocket layer upper surface, and dielectric materials refer to that relative dielectric constant is less than the dielectric material of the relative dielectric constant of silica；
The 4th gate dielectric layer of area deposition is specified in the third of third gate dielectric layer upper surface and pocket layer upper surface using high dielectric material, wherein, it is region of the pocket layer upper surface in addition to the second specified region that third, which specifies region, and high dielectric material refers to that relative dielectric constant is greater than the dielectric material of the relative dielectric constant of silica；
Wherein, gate dielectric layer is made of third gate dielectric layer and the 4th gate dielectric layer.
In another embodiment, gate dielectric layer is prepared in the upper surface of pocket layer, comprising:
Initial gate dielectric layer is deposited in the upper surface of pocket layer using high dielectric material；
4th specified region of initial gate dielectric layer is carried out thinned, obtain gate dielectric layer, wherein the 4th specified region is the region being located above source region in initial gate dielectric layer.
In another embodiment, gate dielectric layer is prepared in the upper surface of pocket layer, comprising:
The 5th gate dielectric layer is deposited in pocket layer upper surface using high dielectric material；
Using high dielectric material in the third region of the 5th specified the 6th gate dielectric layer of area deposition of the 5th gate dielectric layer upper surface, using dielectric materials the 6th specified the 6th gate dielectric layer of area deposition of the 5th gate dielectric layer upper surface the fourth region, wherein, 5th specified region is the region being located above source region in the 5th gate dielectric layer upper surface, 6th specified region is the region being located above channel region in the 5th gate dielectric layer upper surface, high dielectric material refers to that relative dielectric constant is greater than the dielectric material of the relative dielectric constant of silica, dielectric materials refer to that relative dielectric constant is less than the dielectric material of the relative dielectric constant of silica；
Wherein, gate dielectric layer is made of the 5th gate dielectric layer and the 6th gate dielectric layer.
In another embodiment, after the upper surface of gate dielectric layer prepares grid region, further includes:
Divider wall is prepared in pocket layer, gate dielectric layer and grid region two sides；
Metal source, metal gate electrode and metal leakage pole are prepared respectively in source region, grid region and the specified location in drain region, and divider wall is used for isolating metal source electrode, metal gate electrode and metal leakage pole.
It should be noted that all the above alternatives, can form alternative embodiment of the invention using any combination, this is no longer going to repeat them.
The content of the embodiment in conjunction with corresponding to above-mentioned Fig. 6, in order to make it easy to understand, the embodiment of the present invention for preparing TFET shown in Fig. 2, is described in detail the preparation method of TFET provided in an embodiment of the present invention.As shown in fig. 7, the preparation method of the TFET the following steps are included:
701, according to the type of tunneling field-effect transistor, trap injection is carried out to default substrate, obtains the semiconductor substrate with the type matching of tunneling field-effect transistor.
Wherein, presetting substrate is intrinsic semiconductor.When the type difference of tunneling field-effect transistor, when carrying out trap injection to default substrate, the type of the impurity of injection is also different.For example, when carrying out trap injection to default substrate, the doping type of injection is p type impurity, such as B (boron) or Ga (gallium), to obtain p-type trap, i.e. P-type semiconductor substrate if TFET is N-type.If TFET is p-type, when carrying out trap injection to default substrate, the doping type of injection is N-type impurity, such as P (phosphorus) or As (arsenic), to obtain N-type trap, i.e. N-type semiconductor substrate.
As shown in figure 8, it illustrates a kind of schematic diagrames of semiconductor substrate.The material of the semiconductor substrate is illustrated in above-mentioned each embodiment, and for details, reference can be made to the contents in above-mentioned each embodiment, and details are not described herein again.
702, protective layer is prepared on a semiconductor substrate, prepares the sacrificial layer of designated shape on the protection layer.
It is protective layer used when forming source region and drain region by way of ion implanting in the semiconductor substrate, protect semiconductor substrate.Sacrificial layer is for being formed self-aligned channel region when forming source region and drain region by way of ion implanting in the semiconductor substrate.Wherein, designated shape can be rectangle etc..
It should be noted that the ion for injecting source region and drain region diffuses in channel region when subsequent ion injects in order to prevent, the length of sacrificial layer on the protection layer is greater than the length of default channel region.For example, the length of default channel region is 200 nanometers, then the length of sacrificial layer can be 250 nanometers etc..As shown in figure 9, it illustrates the schematic diagrames of a kind of protective layer and sacrificial layer.In conjunction with Fig. 9, corresponding semiconductor regions are the region where default channel region below sacrificial layer.
Specifically, about the mode for preparing protective layer and sacrificial layer, can there are many kinds of.For example, protective layer can be prepared on a semiconductor substrate by way of deposition growing, sacrificial layer can be prepared on the protection layer by lithography and etching technology, and define the shape of sacrificial layer.Wherein, the material of protective layer can be titanium dioxide
The material of silicon etc., sacrificial layer can be α silicon etc..
It should be noted that the step is optional step, for protecting semiconductor substrate in the subsequent ion implanting of progress in the semiconductor substrate.Certainly, herein only for generating protective layer and sacrificial layer to protection semiconductor substrate in the way of be illustrated, however, in the specific implementation, can also be realized using other way.
703, using the default drain region in photoetching technique protection semiconductor substrate, the first ion implanting is carried out to the default source region in semiconductor substrate；Source region is protected using photoetching technique, second of ion implanting is carried out to default drain region；Rta technique is carried out to the structure for completing ion implanting, generates source region and drain region.
When carrying out the first ion implanting and second of ion implanting, the type for the ion being injected separately into and the type of TFET are related.For example, the ion injected in source region is P-type ion when TFET is N-type, the ion injected in drain region is N-type ion；When TFET is p-type, the ion injected in source region is N-type ion, and the ion injected in drain region is P-type ion.
As shown in Figure 10, it illustrates the schematic diagrames of a Provenance Region and drain region.In Figure 10, the left half of doped region of semiconductor substrate indicates source region, and right one side of something doped region indicates drain region.
704, protective layer and sacrificial layer are removed by lithographic technique, surface prepares initial pocket layer on a semiconductor substrate, and performs etching to initial pocket layer, obtains pocket layer.
The tunnel junctions of pocket layer and source region composition tunneling field-effect transistor.Principle when about pocket layer and source region composition tunnel junctions, is illustrated, details are not described herein again in the above-described embodiments.Material about pocket layer has also been illustrated in above-mentioned each embodiment, also repeats no more herein.
Wherein, initial pocket layer is performed etching, obtained pocket layer at least covering part source region and part channel region.Optionally, pocket layer not with drain contact, with can reduce TFET electric leakage a possibility that, so as to improve the performance of TFET.
705, the first gate dielectric layer is deposited in pocket layer upper surface using high dielectric material, first specified the second gate dielectric layer of area deposition using dielectric materials in the first gate dielectric layer upper surface forms gate dielectric layer by the first gate dielectric layer and the second gate dielectric layer.
Wherein, the upper surface of pocket layer is completely covered in the first gate dielectric layer, and the second gate dielectric layer covers the first specified region of the first gate dielectric layer upper surface, which is that the first gate dielectric layer upper surface is located at the region above channel region.
Specifically, it is including but not limited to being realized by the following two kinds mode using dielectric materials in first specified the second gate dielectric layer of area deposition of the first gate dielectric layer upper surface using high dielectric material in pocket layer upper surface the first gate dielectric layer of deposition:
First way: the initial pocket layer upper surface prepared in step 704 is deposited using high dielectric material
Initial first gate dielectric layer deposits initial second gate dielectric layer in initial first gate dielectric layer upper surface using dielectric materials.As shown in figure 11, it illustrates a kind of initial pocket layers, the schematic diagram of initial first gate dielectric layer and initial second gate dielectric layer.It can be obtained by Figure 11, the upper surface of semiconductor substrate is completely covered in initial pocket layer, and initial pocket layer is completely covered in initial first gate dielectric layer, and initial first gate dielectric layer is completely covered in initial second gate dielectric layer.Then, initial second gate dielectric layer is performed etching using lithography and etching technology, is defined with the shape to the second gate dielectric layer, etch away the region that initial second gate dielectric layer upper surface is located above source region, initial second gate dielectric layer after being etched.Wherein, the edge of initial second gate dielectric layer after etching is aligned or slightly be overlapped with source region, which can be between 1 nanometer to 5 nanometer.As shown in figure 12, it illustrates a kind of schematic diagrames of initial second gate dielectric layer after etching.Finally, according to the shape, the shape of default first gate dielectric layer and the shape for presetting the second gate dielectric layer for presetting pocket layer, initial second gate dielectric layer after initial pocket layer, initial first gate dielectric layer and etching is carried out after further etching, available pocket layer, the first gate dielectric layer and the second gate dielectric layer.In addition, the pocket layer being prepared in step 705 to initial pocket layer in this step by performing etching to obtain, i.e., step 705 only needs to prepare initial pocket layer under this kind of mode.
The second way: directly depositing the first gate dielectric layer using high dielectric material in pocket layer upper surface, and pre-set first specified region uses dielectric materials the second gate dielectric layer of deposition on the first gate dielectric layer.
When preparing the first gate dielectric layer and the second gate dielectric layer by this kind of mode, etching technics can be saved, so as to save process flow.
706, grid region is prepared in the upper surface of gate dielectric layer.
Material about grid region is illustrated in the above-described embodiments, and details are not described herein again.
It, can also be there are two types of mode when gate dielectric layer upper surface prepares grid region in conjunction with the two ways for preparing the first gate dielectric layer and the second gate dielectric layer in above-mentioned steps 705:
First way: this kind of mode is corresponding with the first way in step 705.
Specifically, after etching initial second gate dielectric layer upper surface and the initial first gate dielectric layer upper surface of the initial second gate dielectric layer covering after not being etched prepare initial grid region.As shown in figure 13, it illustrates the schematic diagrames of initial second gate dielectric layer and initial grid region after a kind of initial pocket layer, initial first gate dielectric layer, etching.Then, according to the shape of default pocket layer, the shape of default first gate dielectric layer, the shape of default second gate dielectric layer and the shape in default grid region, to after initial pocket layer, initial first gate dielectric layer, etching initial second gate dielectric layer and initial grid region perform etching, respectively obtain pocket layer, the first gate dielectric layer, the second gate dielectric layer and grid region.
Specifically, to after initial pocket layer, initial first gate dielectric layer, etching initial second gate dielectric layer and initial grid region perform etching when, can in conjunction with photoetching and anisotropic etching technology, successively to after initial pocket layer, initial first gate dielectric layer, etching initial second gate dielectric layer and initial grid region perform etching.
In addition, the pocket layer being prepared in step 705 to initial pocket layer in this step by performing etching to obtain, i.e., step 705 only needs to prepare initial pocket layer under this kind of mode.First gate dielectric layer and the second gate dielectric layer are also by performing etching respectively to initial second gate dielectric layer after initial first gate dielectric layer and etching in the step, i.e., step 706 only needs to be prepared into initial second gate dielectric layer after initial first gate dielectric layer and etching.
The second way: this kind of mode is corresponding with the second way in step 705.
Specifically, this kind of mode directly deposits grid region in gate dielectric layer upper surface, which is completely covered the upper surface of gate dielectric layer.
707, divider wall is prepared in pocket layer, gate dielectric layer and grid region two sides.
Wherein, the material of divider wall is insulating materials, such as silicon nitride.Specifically, divider wall can be prepared in pocket layer, gate dielectric layer and grid region two sides by anisotropic etching technology.The divider wall is used to be isolated the metal source, metal gate electrode and metal leakage pole of subsequent preparation, to avoid short circuit.As shown in figure 14, it illustrates a kind of schematic diagrames of divider wall.
708, dielectric materials are filled on the outside of divider wall and grid region, and prepare metal source, metal gate electrode and metal leakage pole respectively in source region, grid region and the specified location in drain region.
Wherein, dielectric materials can be silica or silicon nitride etc..By filling dielectric materials, the parasitic capacitance of TFET can be prevented bigger.In addition, by dielectric materials good mechanical support can be played the role of to metal source, metal gate electrode and metal leakage pole.
In addition, the content about designated position is illustrated in the above embodiments, for details, reference can be made to the contents in above-described embodiment, and details are not described herein again.
The preparation method of TFET provided in an embodiment of the present invention, it is that the first gate dielectric layer is located at the region above source region by setting gate dielectric layer first area, second area is that the first gate dielectric layer is located at region and the second gate dielectric layer above channel region, so that thickness of the gate dielectric layer in first area is obviously smaller than the thickness of second area, and the material by the way that the first gate dielectric layer is arranged is high dielectric material, the material of second gate dielectric layer is dielectric materials, so that the average relative dielectric constant of gate dielectric layer first area is greater than the average relative dielectric constant of second area, and the gate capacitance of gate dielectric layer is inversely proportional to the thickness, and it is directly proportional to the relative dielectric constant of its material, so that the gate capacitance of gate dielectric layer first area is greater than the gate capacitance of second area, so that the gate capacitance for the gate dielectric layer being located above source region is greater than The grid of gate dielectric layer above channel region
Capacitor, so that grid voltage is better than the ability of regulation and control to tunnel junctions to the ability of regulation and control of line tunnel junctions under identical grid voltage.Therefore, cut-in voltage needed for putting tunnel junctions is opposite to be increased, it is thus possible to delay or postpone the unlatching of some tunnel junctions, to guarantee that threaded list wears the unlatching that can dominate entire device, it is ensured that TFEF has the Sub-Threshold Characteristic of steeper, so that the lower power consumption of TFET.
The content of the embodiment in conjunction with corresponding to above-mentioned Fig. 6, in order to make it easy to understand, the embodiment of the present invention for preparing TFET shown in Fig. 3, is described in detail the preparation method of TFET provided in an embodiment of the present invention.As shown in figure 15, the preparation method the following steps are included:
1501, according to the type of tunneling field-effect transistor, trap injection is carried out to default substrate, obtains the semiconductor substrate with the type matching of tunneling field-effect transistor.
The principle of the step is consistent with the principle in step 701, and for details, reference can be made to the contents in step 701, and details are not described herein again.
1502, protective layer is prepared on a semiconductor substrate, prepares the sacrificial layer of designated shape on the protection layer.
The principle of the step is consistent with the principle in step 702, and for details, reference can be made to the contents in step 702, and details are not described herein again.
1503, using the default drain region in photoetching technique protection semiconductor substrate, the first ion implanting is carried out to the default source region in semiconductor substrate；Source region is protected using photoetching technique, second of ion implanting is carried out to default drain region；Rta technique is carried out to the structure for completing ion implanting, generates source region and drain region.
The principle of the step is consistent with the principle in step 703, and for details, reference can be made to the contents in step 703, and details are not described herein again.
1504, protective layer and sacrificial layer are removed by lithographic technique, surface prepares initial pocket layer on a semiconductor substrate, and performs etching to initial pocket layer, obtains pocket layer.
The principle of the step is consistent with the principle in step 704, and for details, reference can be made to the contents in step 704, and details are not described herein again.
1505, the second specified area deposition third gate dielectric layer using dielectric materials in pocket layer upper surface, the 4th gate dielectric layer of area deposition is specified in the third of third gate dielectric layer upper surface and pocket layer upper surface using high dielectric material, gate dielectric layer is formed by third gate dielectric layer and the 4th gate dielectric layer.
Wherein, the second specified region of third gate dielectric layer covering pocket layer upper surface, the second specified region are the region being located above channel region in pocket layer upper surface.The third that 4th gate dielectric layer covering third gate dielectric layer and pocket layer upper surface are not covered by third gate dielectric layer specifies region, and it is region of the pocket layer upper surface in addition to the second specified region which, which specifies region,.
Specifically, in the second specified area deposition third gate dielectric layer using dielectric materials in pocket layer upper surface, using high dielectric material when the third of third gate dielectric layer upper surface and pocket layer upper surface specifies four gate dielectric layer of area deposition, including but not limited to realized by the following two kinds mode:
First way: the initial pocket layer upper surface prepared in step 1504 deposits initial third gate dielectric layer using dielectric materials, which is completely covered the initial pocket layer in step 1505；Then, lithography and etching technology performs etching initial third gate dielectric layer, is defined with the shape to third gate dielectric layer, etches away the region that initial third gate dielectric layer upper surface is located above source region, the third gate dielectric layer after being etched.Wherein, the edge of the third gate dielectric layer after etching is aligned or slightly be overlapped with source region, which can be between 1 nanometer to 5 nanometer.Next, initial third gate dielectric layer surface after etching and the pocket layer upper surface of the initial third gate dielectric layer covering after not being etched deposit initial 4th gate dielectric layer.Finally, according to the shape of default pocket layer, the shape of the shape of default third gate dielectric layer and default 4th gate dielectric layer, to after initial pocket layer, etching third gate dielectric layer and initial 4th gate dielectric layer carry out further etch after, obtain pocket layer, third gate dielectric layer and the 4th gate dielectric layer.In addition, the pocket layer being prepared in step 1105 to initial pocket layer in this step by performing etching to obtain, i.e., step 1105 only needs to prepare initial pocket layer under this kind of mode.
The second way: third gate dielectric layer directly is deposited using dielectric materials in the pocket layer upper surface being located above channel region, and specifies the 4th gate dielectric layer of area deposition in the third that third gate dielectric layer and pocket layer upper surface are not covered by third dielectric layer using high dielectric material.
When preparing third gate dielectric layer and four gate dielectric layers by this kind of mode, etching technics can be saved, so as to save process flow.
1506, grid region is prepared in the upper surface of gate dielectric layer.
It, can also be there are two types of mode when gate dielectric layer upper surface prepares grid region in conjunction with the two ways for preparing third gate dielectric layer and the 4th gate dielectric layer in above-mentioned steps 1105:
First way: this kind of mode is corresponding with the first way in step 1105.
Specifically, third gate dielectric layer upper surface after etching prepares initial grid region；Then, according to the shape of default pocket layer, the shape of default third gate dielectric layer, the shape of default 4th gate dielectric layer and the shape in default grid region, initial third gate dielectric layer, initial 4th gate dielectric layer and initial grid region after initial pocket layer, etching is performed etching, pocket layer, third gate dielectric layer, the 4th gate dielectric layer and grid region are respectively obtained.
Specifically, when being performed etching to initial third gate dielectric layer, initial 4th gate dielectric layer and the initial grid region after initial pocket layer, etching, successively initial third gate dielectric layer, the two or four gate dielectric layer and the initial grid region after initial pocket layer, etching can be performed etching in conjunction with photoetching and anisotropic etching technology.
In addition, the pocket layer being prepared in step 1105 to initial pocket layer in this step by performing etching to obtain, i.e., step 1105 only needs to prepare initial pocket layer under this kind of mode.Third gate dielectric layer and the 4th gate dielectric layer be also in the step by respectively to after etching initial third gate dielectric layer and initial 4th gate dielectric layer perform etching, i.e., step 1106 only needs to be prepared into initial second gate dielectric layer after initial first gate dielectric layer and etching.
The second way: this kind of mode is corresponding with the second way in step 1105.
Specifically, this kind of mode directly deposits grid region in gate dielectric layer upper surface, which is completely covered the upper surface of gate dielectric layer.
1507, divider wall is prepared in pocket layer, gate dielectric layer and grid region two sides.
The principle of the step is consistent with the principle in step 707, and for details, reference can be made to the contents in step 707, and details are not described herein again.
1508, dielectric materials are filled on the outside of divider wall and grid region, and prepare metal source, metal gate electrode and metal leakage pole respectively in source region, grid region and the specified location in drain region.
The principle of the step is consistent with the principle in step 708, and for details, reference can be made to the contents in step 708, and details are not described herein again.
The preparation method of TFET provided in an embodiment of the present invention, first area by the way that gate dielectric layer is arranged is that the 4th gate dielectric layer is located at the region above source region, the second area of gate dielectric layer is that third gate dielectric layer and the 4th gate dielectric layer are located at the region above channel region, so that thickness of the gate dielectric layer in first area is obviously smaller than the thickness of second area, and the material by the way that third gate dielectric layer is arranged is dielectric materials, the material of 4th gate dielectric layer is high dielectric material, so that the average relative dielectric constant of gate dielectric layer first area is greater than the average relative dielectric constant of second area, and the gate capacitance of gate dielectric layer is inversely proportional to the thickness, and it is directly proportional to the relative dielectric constant of its material, so that the gate capacitance of gate dielectric layer first area is greater than the gate capacitance of second area, so that under identical grid voltage, grid voltage wears threaded list The ability of regulation and control of knot is better than the ability of regulation and control to tunnel junctions.Therefore, cut-in voltage needed for putting tunnel junctions is opposite to be increased, it is thus possible to delay or postpone the unlatching of some tunnel junctions, to guarantee that threaded list wears the unlatching that can dominate entire device, it is ensured that TFEF has the Sub-Threshold Characteristic of steeper, so that the lower power consumption of TFET.
The content of the embodiment in conjunction with corresponding to above-mentioned Fig. 6, in order to make it easy to understand, the embodiment of the present invention for preparing TFET shown in Fig. 4, is described in detail the preparation method of TFET provided in an embodiment of the present invention.As shown in figure 16, the preparation method the following steps are included:
1601, according to the type of tunneling field-effect transistor, trap injection is carried out to default substrate, is obtained and tunnel
Wear the semiconductor substrate of the type matching of field effect transistor.
The principle of the step is consistent with the principle in step 701, and for details, reference can be made to the contents in step 701, and details are not described herein again.
1602, protective layer is prepared on a semiconductor substrate, prepares the sacrificial layer of designated shape on the protection layer.
The principle of the step is consistent with the principle in step 702, and for details, reference can be made to the contents in step 702, and details are not described herein again.
1603, using the default drain region in photoetching technique protection semiconductor substrate, the first ion implanting is carried out to the default source region in semiconductor substrate；Source region is protected using photoetching technique, second of ion implanting is carried out to default drain region；Rta technique is carried out to the structure for completing ion implanting, generates source region and drain region.
The principle of the step is consistent with the principle in step 703, and for details, reference can be made to the contents in step 703, and details are not described herein again.
1604, protective layer and sacrificial layer are removed by lithographic technique, surface prepares initial pocket layer on a semiconductor substrate, and performs etching to initial pocket layer, obtains pocket layer.
The principle of the step is consistent with the principle in step 704, and for details, reference can be made to the contents in step 704, and details are not described herein again.
1605, initial gate dielectric layer is deposited in the upper surface of pocket layer using high dielectric material, and the 4th specified region of initial gate dielectric layer is carried out thinned, obtain gate dielectric layer.
Wherein, pocket layer is completely covered in initial gate dielectric layer, and the 4th specified region is that initial gate dielectric layer is located at the region above source region.Specifically, it when the 4th specified region to beginning gate dielectric layer carries out thinned, can be realized in conjunction with lithography and etching technology.
In embodiments of the present invention, it when depositing initial gate dielectric layer in the upper surface of pocket layer using high dielectric material, can be realized by the following two kinds mode:
First way: the initial pocket layer upper surface being prepared in step 1604 deposits original gate dielectric layer using high dielectric material；Then, according to the shape of the shape of default pocket layer and default gate dielectric layer, initial pocket layer and original gate dielectric layer is performed etching, pocket layer and initial gate dielectric layer are obtained.
The second way；Directly in the initial gate dielectric layer of pocket layer disposed thereon specified thickness.
1606, grid region is prepared in the upper surface of gate dielectric layer.
Wherein, the whole region of grid region covering gate dielectric layer upper surface.
1607, divider wall is prepared in pocket layer, gate dielectric layer and grid region two sides.
The principle of the step is consistent with the principle in step 707, and for details, reference can be made to the contents in step 707, and details are not described herein again.
1608, dielectric materials are filled on the outside of divider wall and grid region, and prepare metal source, metal gate electrode and metal leakage pole respectively in source region, grid region and the specified location in drain region.
The principle of the step is consistent with the principle in step 708, and for details, reference can be made to the contents in step 708, and details are not described herein again.
The preparation method of TFET provided in an embodiment of the present invention, thickness by the way that the first area of gate dielectric layer is arranged is less than the thickness of second area, and the gate capacitance of gate dielectric layer is inversely proportional to the thickness, so that the gate capacitance of gate dielectric layer first area is greater than the gate capacitance of second area, so that the gate capacitance for the gate dielectric layer being located above source region is greater than the gate capacitance for the gate dielectric layer being located above channel region, so that there is the case where identical gate voltage with the gate dielectric layer on channel region relative to source region, grid is reduced for the ability of regulation and control of tunnel junctions, and then cut-in voltage needed for increasing the point tunnelling formed as source region and pocket layer, it can thus delay or postpone the unlatching of a tunnelling, so that threaded list wears the unlatching for dominating entire device, ensure that TFEF has the Sub-Threshold Characteristic of steeper, so that TFET Power consumption it is smaller.
The content of the embodiment in conjunction with corresponding to above-mentioned Fig. 6, in order to make it easy to understand, the embodiment of the present invention for preparing TFET shown in fig. 5, is described in detail the preparation method of TFET provided in an embodiment of the present invention.As shown in figure 17, the preparation method the following steps are included:
1701, according to the type of tunneling field-effect transistor, trap injection is carried out to default substrate, obtains the semiconductor substrate with the type matching of tunneling field-effect transistor.
The principle of the step is consistent with the principle in step 701, and for details, reference can be made to the contents in step 701, and details are not described herein again.
1702, protective layer is prepared on a semiconductor substrate, prepares the sacrificial layer of designated shape on the protection layer.
The principle of the step is consistent with the principle in step 702, and for details, reference can be made to the contents in step 702, and details are not described herein again.
1703, using the default drain region in photoetching technique protection semiconductor substrate, the first ion implanting is carried out to the default source region in semiconductor substrate；Source region is protected using photoetching technique, second of ion implanting is carried out to default drain region；Rta technique is carried out to the structure for completing ion implanting, generates source region and drain region.
The principle of the step is consistent with the principle in step 703, and for details, reference can be made to the contents in step 703, and details are not described herein again.
1704, protective layer and sacrificial layer are removed by lithographic technique, surface prepares initial pocket layer on a semiconductor substrate, and performs etching to initial pocket layer, obtains pocket layer.
The principle of the step is consistent with the principle in step 704, for details, reference can be made to the content in step 704,
Details are not described herein again.
1705, the 5th gate dielectric layer is deposited in pocket layer upper surface using high dielectric material, using high dielectric material in the third region of the 5th specified the 6th gate dielectric layer of area deposition of the 5th gate dielectric layer upper surface, using dielectric materials the 6th specified the 6th gate dielectric layer of area deposition of the 5th gate dielectric layer upper surface the fourth region, 6th gate dielectric layer is formed by third region and the fourth region, gate dielectric layer is formed by the 5th gate dielectric layer and the 6th gate dielectric layer.
Wherein, the 5th specified region is the region being located above source region in the 5th gate dielectric layer upper surface, and the 6th specified region is the region being located above channel region in the 5th gate dielectric layer upper surface.
Specifically, the 5th gate dielectric layer is being deposited in pocket layer upper surface using high dielectric material, using high dielectric material in the third region of the 5th specified the 6th gate dielectric layer of area deposition of the 5th gate dielectric layer upper surface, using dielectric materials in the fourth region of the 6th specified the 6th gate dielectric layer of area deposition of the 5th gate dielectric layer upper surface, including but not limited to realized by the following two kinds mode:
First way: the initial pocket layer upper surface prepared in step 1604 deposits initial 5th gate dielectric layer using high dielectric material, using high dielectric material in the third region of the 5th specified initial 6th gate dielectric layer of area deposition of initial 5th gate dielectric layer upper surface, using using dielectric materials to form initial 6th gate dielectric layer by the third region of initial 6th gate dielectric layer and the fourth region of initial 6th gate dielectric layer in the fourth region of the 6th specified initial 6th gate dielectric layer of area deposition of initial 5th gate dielectric layer upper surface.Then, initial pocket layer, initial 5th gate dielectric layer and initial 6th gate dielectric layer are performed etching using lithography and etching technology, obtains pocket layer, the 5th gate dielectric layer and the 6th gate dielectric layer.Under this kind of mode, the pocket layer being prepared in step 1705 to initial pocket layer in this step by performing etching to obtain, i.e., step 1705 only needs to prepare initial pocket layer.
The second way: the 5th gate dielectric layer directly is deposited using high dielectric material in pocket layer upper surface, the third region of the 5th specified the 6th gate dielectric layer of area deposition on the 5th gate dielectric layer, using use dielectric materials in the fourth region of the 6th specified the 6th gate dielectric layer of area deposition of initial 5th gate dielectric layer upper surface.
1706, grid region is prepared in the upper surface of gate dielectric layer.
It, can also be there are two types of mode when gate dielectric layer upper surface prepares grid region in conjunction with the two ways for preparing the 5th gate dielectric layer and the 6th gate dielectric layer in above-mentioned steps 1705:
First way: this kind of mode is corresponding with the first way in step 1705.
Specifically, initial grid region is deposited in initial 6th gate dielectric layer upper surface；Then, the shape of pocket layer, the shape of default 5th gate dielectric layer, the shape of default 6th gate dielectric layer and the shape in default grid region are preset,
Initial pocket layer, initial one or five gate dielectric layer, initial 6th gate dielectric layer and initial grid region are performed etching, pocket layer, the 5th gate dielectric layer, the 6th gate dielectric layer and grid region are respectively obtained.
Specifically, when being performed etching to initial pocket layer, initial one or five gate dielectric layer, initial 6th gate dielectric layer and initial grid region, successively initial pocket layer, initial one or five gate dielectric layer, initial 6th gate dielectric layer and initial grid region can be performed etching in conjunction with photoetching and anisotropic etching technology.
In addition, the pocket layer being prepared in step 1705 to initial pocket layer in this step by performing etching to obtain, i.e., step 1705 only needs to prepare initial pocket layer under this kind of mode.5th gate dielectric layer and the 6th gate dielectric layer are also by performing etching respectively to initial 5th gate dielectric layer and initial 6th gate dielectric layer in the step, i.e., step 1706 only needs to be prepared into initial 5th gate dielectric layer and initial 6th gate dielectric layer.
The second way: this kind of mode is corresponding with the second way in step 1705.
This kind of mode directly deposits grid region on the 6th gate dielectric layer surface.
It should be noted that the embodiment is only illustrated so that the 5th gate dielectric layer is located at the lower section of the 6th gate dielectric layer as an example.However, in the specific implementation, the 5th gate dielectric layer can also be located at the top of the 6th gate dielectric layer.
1707, divider wall is prepared in pocket layer, gate dielectric layer and grid region two sides.
The principle of the step is consistent with the principle in step 707, and for details, reference can be made to the contents in step 707, and details are not described herein again.
1708, dielectric materials are filled on the outside of divider wall and grid region, and prepare metal source, metal gate electrode and metal leakage pole respectively in source region, grid region and the specified location in drain region.
The principle of the step is consistent with the principle in step 708, and for details, reference can be made to the contents in step 708, and details are not described herein again.
The preparation method of TFET provided in an embodiment of the present invention, it is high dielectric material by the material of the 5th gate dielectric layer of setting and the material in the 6th gate dielectric layer third region, the material of 6th gate dielectric layer the fourth region is dielectric materials, so that the average relative dielectric constant of gate dielectric layer first area is greater than the average relative dielectric constant of second area, and the gate capacitance of gate dielectric layer is directly proportional to the relative dielectric constant of its material, so that the gate capacitance of gate dielectric layer first area is greater than the gate capacitance of second area, so that the gate capacitance for the gate dielectric layer being located above source region is greater than the gate capacitance for the gate dielectric layer being located above channel region, so that under identical grid voltage, grid voltage is better than the ability of regulation and control to tunnel junctions to the ability of regulation and control of line tunnel junctions.Therefore, cut-in voltage needed for putting tunnel junctions is opposite to be increased, it is thus possible to delay or postpone the unlatching of some tunnel junctions, to guarantee that threaded list wears the unlatching that can dominate entire device, it is ensured that and TFEF has the Sub-Threshold Characteristic of steeper,
So that the lower power consumption of TFET.
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, and all within the spirits and principles of the present invention, any modification, equivalent replacement, improvement and so on should all be included in the protection scope of the present invention.
Claims (15)
- A kind of tunneling field-effect transistor, which is characterized in that the tunneling field-effect transistor includes source region, drain region, channel region, pocket layer, gate dielectric layer and grid region, in which:The source region and the drain region are separately disposed in inside semiconductor substrate, and the channel region connects the source region and the drain region；The pocket layer is set to the upper surface of the source region and the channel region, the gate dielectric layer is set to the upper surface of the pocket layer, the grid region is set to the upper surface of the gate dielectric layer, the gate dielectric layer includes first area and second area, the first area is the gate dielectric layer region above the source region, the second area is the gate dielectric layer region above the channel region, and the gate capacitance of the first area is greater than the gate capacitance of the second area；Wherein, the pocket layer and the source region form the tunnel junctions of the tunneling field-effect transistor.
- Tunneling field-effect transistor according to claim 1, which is characterized in that the gate dielectric layer is made of the first gate dielectric layer and the second gate dielectric layer；The upper surface of the pocket layer is completely covered in first gate dielectric layer, second gate dielectric layer covers the first specified region of first gate dielectric layer upper surface, and the first specified region is the region being located above the channel region in first gate dielectric layer upper surface；Wherein, the material of first gate dielectric layer is high dielectric material, the material of second gate dielectric layer is dielectric materials, the high dielectric material refers to that relative dielectric constant is greater than the dielectric material of the relative dielectric constant of silica, and the dielectric materials refer to that relative dielectric constant is less than the dielectric material of the relative dielectric constant of silica.
- Tunneling field-effect transistor according to claim 1, which is characterized in that the gate dielectric layer is made of third gate dielectric layer and the 4th gate dielectric layer；The third gate dielectric layer covers the second specified region of pocket layer upper surface, and the second specified region is the region being located above the channel region in pocket layer upper surface；The third of the third gate dielectric layer is completely covered in 4th gate dielectric layer upper surface and pocket layer upper surface specifies region, and it is region of the pocket layer upper surface in addition to the described second specified region that the third, which specifies region,；Wherein, the material of the third gate dielectric layer is dielectric materials, and the material of the 4th gate dielectric layer is high dielectric material, and the dielectric materials refer to that relative dielectric constant is normal less than the opposite dielectric of silica Several dielectric materials, the high dielectric material refer to that relative dielectric constant is greater than the dielectric material of the relative dielectric constant of silica.
- Tunneling field-effect transistor according to claim 1, which is characterized in that the thickness of the first area is less than the thickness of the second area, and the material of the first area and the second area is same high dielectric material；Wherein, the high dielectric material refers to that relative dielectric constant is greater than the dielectric material of the relative dielectric constant of silica.
- Tunneling field-effect transistor according to claim 1, which is characterized in that the gate dielectric layer is made of the 5th gate dielectric layer and the 6th gate dielectric layer；The upper surface of the pocket layer is completely covered in 5th gate dielectric layer, the upper surface of the 5th gate dielectric layer is completely covered in 6th gate dielectric layer, and the 6th gate dielectric layer includes third region and the fourth region, the third region is the 6th gate dielectric layer region above the source region, and the fourth region is the 6th gate dielectric layer region above the channel region；Wherein, the material of 5th gate dielectric layer and the material in the third region are high dielectric material, the material of the fourth region is dielectric materials, the high dielectric material refers to that relative dielectric constant is greater than the dielectric material of the relative dielectric constant of silica, and the dielectric materials refer to that relative dielectric constant is less than the dielectric material of the relative dielectric constant of silica.
- Tunneling field-effect transistor according to claim 1, which is characterized in thatThe pocket layer, the gate dielectric layer and the grid region two sides are prepared with divider wall；The specified location of the source region, the grid region and the drain region is prepared with metal source, metal gate electrode and metal leakage pole respectively, and the divider wall is for being isolated the metal source, the metal gate electrode and the metal leakage pole.
- According to claim 1 to tunneling field-effect transistor described in any claim in 6, which is characterized in thatThe material of the semiconductor substrate is one of body silicon, the silicon on insulator, germanium silicon, germanium and Group III-V compound semiconductor；The material of the pocket layer is one of silicon, germanium silicon, germanium and Group III-V compound semiconductor；The material in the grid region is one of polysilicon, metal and polysilicon and the multi-layer compound structure of metal.
- A kind of preparation method of tunneling field-effect transistor, which is characterized in that the preparation method includes:According to the type of tunneling field-effect transistor, trap injection is carried out to default substrate, obtains the semiconductor substrate with the type matching of the tunneling field-effect transistor；It is prepared apart source region and drain region inside the semiconductor substrate, and channel region is made to connect the source region and the drain region；Pocket layer is prepared in the upper surface of the source region and the channel region, the pocket layer and the source region form the tunnel junctions of the tunneling field-effect transistor；Gate dielectric layer is prepared in the upper surface of the pocket layer, the gate dielectric layer includes first area and second area, the first area is the gate dielectric layer region above the source region, the second area is the gate dielectric layer region above the channel region, and the gate capacitance of the first area is greater than the gate capacitance of the second area；Grid region is prepared in the upper surface of the gate dielectric layer.
- Preparation method according to claim 8, which is characterized in that described that source region and drain region are prepared apart inside semiconductor substrate, comprising:The default drain region in the semiconductor substrate is protected using photoetching technique, the first ion implanting is carried out to the default source region in the semiconductor substrate；The source region is protected using photoetching technique, second of ion implanting is carried out to the default drain region；Rta technique is carried out to the structure for completing ion implanting, generates source region and drain region.
- Preparation method according to claim 9, which is characterized in that it is described to protect the default drain region in the semiconductor substrate using photoetching technique, before carrying out the first ion implanting to the default source region in the semiconductor substrate, further includes:Protective layer is prepared on the semiconductor substrate, it is described protective layer used in when carrying out ion implanting to the default source region and the default drain region, protect the semiconductor substrate；The sacrificial layer of designated shape is prepared on the protective layer, the sacrificial layer is used to be formed self-aligned the channel region when carrying out ion implanting to the default source region and the default drain region.
- Preparation method according to claim 8, which is characterized in that the upper surface in the pocket layer prepares gate dielectric layer, comprising:The first gate dielectric layer is deposited in pocket layer upper surface using high dielectric material, the high dielectric material refers to that relative dielectric constant is greater than the dielectric material of the relative dielectric constant of silica；First specified the second gate dielectric layer of area deposition using dielectric materials in first gate dielectric layer upper surface, the first specified region is the region being located above the channel region in first gate dielectric layer upper surface, and the dielectric materials refer to that relative dielectric constant is less than the dielectric material of the relative dielectric constant of silica；Wherein, the gate dielectric layer is made of first gate dielectric layer and second gate dielectric layer.
- Preparation method according to claim 8, which is characterized in that the upper surface in the pocket layer prepares gate dielectric layer, comprising:The second specified area deposition third gate dielectric layer using dielectric materials in pocket layer upper surface, the second specified region is the region being located above the channel region in pocket layer upper surface, and the dielectric materials refer to that relative dielectric constant is less than the dielectric material of the relative dielectric constant of silica；The 4th gate dielectric layer of area deposition is specified in the third of third gate dielectric layer upper surface and pocket layer upper surface using high dielectric material, it is region of the pocket layer upper surface in addition to the described second specified region that the third, which specifies region, and the high dielectric material refers to that relative dielectric constant is greater than the dielectric material of the relative dielectric constant of silica；Wherein, the gate dielectric layer is made of the third gate dielectric layer and the 4th gate dielectric layer.
- Preparation method according to claim 8, which is characterized in that the upper surface in the pocket layer prepares gate dielectric layer, comprising:Initial gate dielectric layer is deposited in the upper surface of the pocket layer using high dielectric material；4th specified region of the initial gate dielectric layer is carried out thinned, obtains gate dielectric layer, the 4th specified region is the region being located above the source region in the initial gate dielectric layer.
- Preparation method according to claim 8, which is characterized in that the upper surface in the pocket layer prepares gate dielectric layer, comprising:The 5th gate dielectric layer is deposited in pocket layer upper surface using high dielectric material；Using high dielectric material in the third region of the 5th specified the 6th gate dielectric layer of area deposition of the 5th gate dielectric layer upper surface, using dielectric materials the 6th specified the 6th gate dielectric layer of area deposition of the 5th gate dielectric layer upper surface the fourth region, the 5th specified region is the region being located above the source region in the 5th gate dielectric layer upper surface, the 6th specified region is the region being located above the channel region in the 5th gate dielectric layer upper surface, the high dielectric material refers to that relative dielectric constant is greater than the dielectric material of the relative dielectric constant of silica, the dielectric materials refer to that relative dielectric constant is less than the dielectric material of the relative dielectric constant of silica；Wherein, the gate dielectric layer is made of the 5th gate dielectric layer and the 6th gate dielectric layer.
- Preparation method according to claim 8, which is characterized in that the upper surface in the gate dielectric layer prepares after grid region, further includes:Divider wall is prepared in the pocket layer, the gate dielectric layer and the grid region two sides；Dielectric materials are filled on the outside of the divider wall and the grid region；Metal source, metal gate electrode and metal leakage pole are prepared respectively in the specified location of the source region, the grid region and the drain region, and the divider wall is for being isolated the metal source, the metal gate electrode and the metal leakage pole.
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| CN102751325A (en) * | 2011-04-21 | 2012-10-24 | 中国科学院微电子研究所 | Tunneling field effect transistor and manufacturing method thereof |
| US20140054657A1 (en) * | 2012-08-23 | 2014-02-27 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing same |
| CN104952917A (en) * | 2015-07-03 | 2015-09-30 | 电子科技大学 | SiC VDMOS (vertical double-diffused metal oxide semiconductor) device |
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| JP5404671B2 (en) * | 2011-02-14 | 2014-02-05 | 株式会社東芝 | Semiconductor device |
| CN102623495B (en) * | 2012-04-09 | 2014-04-30 | 北京大学 | Tunneling field effect transistor with multi-doping pocket structure and manufacturing method for tunneling field effect transistor |
| CN104617137B (en) * | 2015-01-19 | 2018-09-21 | 华为技术有限公司 | A kind of fieldtron and preparation method thereof |
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| CN102751325A (en) * | 2011-04-21 | 2012-10-24 | 中国科学院微电子研究所 | Tunneling field effect transistor and manufacturing method thereof |
| US20140054657A1 (en) * | 2012-08-23 | 2014-02-27 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing same |
| CN104952917A (en) * | 2015-07-03 | 2015-09-30 | 电子科技大学 | SiC VDMOS (vertical double-diffused metal oxide semiconductor) device |
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