WO2018170770A1

WO2018170770A1 - Tunnel field effect transistor and method for fabrication thereof

Info

Publication number: WO2018170770A1
Application number: PCT/CN2017/077619
Authority: WO
Inventors: 杨喜超; 张臣雄
Original assignee: 华为技术有限公司
Priority date: 2017-03-22
Filing date: 2017-03-22
Publication date: 2018-09-27

Abstract

Provided are a tunnel field effect transistor (TFET) and method for fabricating a TFET, said TFET comprising: a source region; a trench; a work function layer; the material of the work function layer is titanium nitride, and the work function layer is located above the source region and the trench; the work function layer contains a first region and a second region; the first region is a region which is in the work function layer and which acts on a line tunneling junction; the second region is a region which is in the work function layer and which acts on a point tunneling junction; the second region is doped with aluminum ions. The invention is capable of improving the swing attribute of a sub-threshold of a TFET component.

Description

Tunneling field effect transistor and manufacturing method thereof

Technical field

The present application relates to the field of semiconductors and, more particularly, to a tunneling field effect transistor and a method of fabricating the same.

Background technique

With the development of integrated circuits, power consumption has gradually become a bottleneck in chip development. How to reduce power consumption has become the key to chip design. For a chip composed of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), the power consumption of the MOSFET can be reduced by reducing the operating voltage of the MOSFET, thereby reducing the power consumption of the chip. However, due to thermodynamic limitations, the subthreshold swing of the MOSFET has a lower limit (60mV/dec), which limits the magnitude of the MOSFET's operating voltage reduction. Therefore, the effect of reducing the power consumption by reducing the operating voltage is limited.

For a chip composed of a Tunnel Field Effect Transistor (TFET), the TFET can break through the thermodynamic limit by using the inter-band tunneling mechanism to achieve a subthreshold swing of less than 60mV/dec. So that the operating voltage of the TFET can be reduced by a larger amplitude. Therefore, for TFETs, the effect of reducing power consumption by lowering the operating voltage is more pronounced.

However, the TFET has a problem that the driving current is low. To solve this problem, the prior art uses a line tunneling technique to increase the driving current. However, when the line tunneling technique is used to increase the driving current, the point tunneling carriers will interfere with the subthreshold swing, resulting in sub-threshold swing of the device (sub-threshold swing becomes larger), which ultimately weakens the device and reduces power consumption. Performance. Therefore, there is a need to provide a new TFET device to better reduce power consumption.

Summary of the invention

The present application provides a TFET and a method of fabricating the same to improve subthreshold swing characteristics of a TFET.

In a first aspect, a TFET is provided, the TFET comprising: a source region; a channel; a work function layer, the material of the work function layer is titanium nitride, and the work function layer is located in the source region and the trench Above the track, the work function layer includes a first region and a second region, wherein the first region is a region of the work function layer acting on a wire tunneling junction, and the second region is in the work function layer Acting on a region of the point tunneling junction, the second region is doped with aluminum ions.

It should be understood that the above TFET may include a line tunneling junction and a point tunneling junction, wherein the line tunneling junction is composed of a source region and a pocket layer directly above it, and the point tunneling junction is formed by a source layer and a pocket layer above the channel region. The composition, the line tunneling junction and the point tunneling junction are all controlled by the static electricity of the gate region. The area of the work function layer above the source region for regulating the turn-on voltage of the line tunneling junction is the first region, and the region of the work function layer above the channel for adjusting the turn-on voltage of the tunneling junction is the second region. region.

Since the region of the work function layer acting on the point tunneling junction is doped with aluminum ions, the work function of the region of the work function layer acting on the point tunneling is greater than the work function of the work function layer acting on the line tunneling region, It can delay or suppress the opening of the point tunneling junction, thereby avoiding the interference caused by the subthreshold swing after the point tunneling is turned on, and improving the subthreshold swing characteristic of the TFET device, so that the TFET device can reduce the power consumption by reducing the voltage. Better results.

In conjunction with the first aspect, in some implementations of the first aspect, the TFET further includes: a gate dielectric layer under the work function layer; a pocket layer under the gate dielectric layer; the isolation wall, located at the Around the pocket layer, the gate dielectric layer, and the work function layer, the height of the isolation wall is equal to a thickness of the pocket layer, a thickness of the gate dielectric layer, a thickness of the work function layer, and The sum of the lengths of the first regions.

The height of the above-mentioned partition wall can be set such that when aluminum ions are injected into the work function layer from a horizontal direction of 45 degrees, aluminum ions are only injected into the second region of the work function layer, that is, only injected into the work function layer. The point tunnels through the junction such that the work function of the second region is greater than the work function of the first region.

In conjunction with the first aspect, in some implementations of the first aspect, the source region and the channel surface are etched with a first trench, the pocket layer being located within the first trench.

In conjunction with the first aspect, in some implementations of the first aspect, the pocket layer is comprised of at least one of silicon, germanium, germanium silicon, and a III-V compound semiconductor material.

In conjunction with the first aspect, in some implementations of the first aspect, the TFET further includes: a drain region; wherein the doping type of the drain region is N-type, and the doping type of the source region is P-type Or, the doping type of the drain region is N-type, and the doping type of the source region is P-type.

It should be understood that the doping type of the drain region and the source region are different, and in addition, the above doping may be either lightly doped or heavily doped.

In conjunction with the first aspect, in some implementations of the first aspect, the source region, the drain region, and the channel are fabricated from a semiconductor substrate material, the semiconductor substrate material being a bulk silicon material, At least one of a silicon material, a germanium material, and a III-V compound semiconductor material on the insulating substrate.

In conjunction with the first aspect, in some implementations of the first aspect, the work function layer has a thickness of less than 10 nanometers.

In a second aspect, a method of fabricating a TFET is provided, the method comprising: fabricating a source region and a channel on a semiconductor substrate; fabricating a work function layer above the source region and the channel, the work function layer The material is titanium nitride, and the work function layer includes a first region and a second region, wherein the first region is a region of the work function layer that acts on a wire tunneling junction, and the second region is the A region of the work function layer that acts on the point tunneling junction; and implants aluminum ions into the second region.

By doping aluminum ions in a region of the work function layer acting on the point tunneling junction, the work function of the region in the work function layer acting on the point tunneling is greater than the work function acting on the line tunneling region in the work function layer, It can delay or suppress the opening of the point tunneling junction, thereby avoiding the interference caused by the subthreshold swing after the point tunneling is turned on, and improving the subthreshold swing characteristic of the TFET device, so that the TFET device can reduce the power consumption by reducing the voltage. Better results.

In conjunction with the second aspect, in some implementations of the second aspect, prior to implanting the aluminum ions into the second region, the method further comprises: forming a pocket layer and a gate over the source region and the channel a dielectric layer; a spacer wall is formed around the pocket layer, the gate dielectric layer, and the work function layer; and the injecting aluminum ions into the second region includes: a direction at a first angle to a horizontal direction Aluminum ions are implanted into the work function layer such that aluminum ions are implanted only into the second region.

Due to the barrier wall existing around the work function layer, when aluminum ions are implanted into the work function layer at an appropriate angle, aluminum ions can be injected only into the second region due to the barrier effect of the partition wall, so that the work function layer acts on The work function of the region where the point is tunneled is larger than the work function of the work function layer acting on the line tunneling region.

It should be understood that the first angle here is related to the height of the wall. Assuming that the height of the partition wall is the first value, the sum of the thickness of the pocket layer, the thickness of the gate dielectric layer, the thickness of the work function layer, and the length of the first region is a second value, then, when the first value is equal to the second value The first angle is 45 degrees. When the first value is greater than the second value, the first angle is greater than 45 degrees and less than 90 degrees. When the first value is less than the second value, the first angle is less than 45 degrees.

In conjunction with the second aspect, in some implementations of the second aspect, the height of the partition wall is equal to a thickness of the pocket layer, a thickness of the gate dielectric layer, a thickness of the work function layer, and the In the case of the sum of the lengths of a region, the first angle is 45 degrees.

DRAWINGS

FIG. 1 is a schematic structural view of a conventional TFET.

2 is a schematic structural view of a conventional TFET.

FIG. 3 is a schematic structural diagram of a TFET according to an embodiment of the present application.

4 is a schematic structural view of a TFET according to an embodiment of the present application.

FIG. 5 is a schematic structural diagram of a TFET according to an embodiment of the present application.

FIG. 6 is a schematic flowchart of a method of fabricating a TFET according to an embodiment of the present application.

FIG. 7 is a flow chart for fabricating a method of fabricating a TFET according to an embodiment of the present application.

FIG. 8 is a flow chart for fabricating a method of fabricating a TFET according to an embodiment of the present application.

FIG. 9 is a flow chart for fabricating a method of fabricating a TFET according to an embodiment of the present application.

FIG. 10 is a flow chart showing the fabrication of a method of fabricating a TFET according to an embodiment of the present application.

FIG. 11 is a flow chart showing the fabrication of a method of fabricating a TFET according to an embodiment of the present application.

FIG. 12 is a flow chart showing the fabrication of a method of fabricating a TFET according to an embodiment of the present application.

FIG. 13 is a flow chart for fabricating a method of fabricating a TFET according to an embodiment of the present application.

FIG. 14 is a flow chart for fabricating a method of fabricating a TFET according to an embodiment of the present application.

detailed description

The technical solutions in the present application will be described below with reference to the accompanying drawings. In order to better understand the tunneling field effect transistor of the present application and its fabrication method, a conventional TFET will be described in detail below with reference to FIGS. 1 and 2.

As shown in FIG. 1, the existing TFET includes a source layer, a channel, a drain region, a partition wall, and a pocket layer, a gate dielectric layer, a metal layer, and a polysilicon layer (the polysilicon layer and the metal layer may also be collectively called For the gate). The source region and the pocket layer above it form a line tunneling junction, and the source layer and the pocket layer above the channel form a point tunneling junction, so there are two mechanisms of line tunneling and point tunneling in carrier tunneling. The gate can generate an electric field through the gate dielectric layer to modulate the energy band distribution of the line tunneling junction and the point tunneling junction (the tunneling turn-on voltage is determined by the work function of the metal layer in the gate), and the energy of the tunnel tunneling junction When the band with the point tunneling junction overlaps, the carrier begins to tunnel. The carrier direction of the line tunneling (shown by the solid arrow in Figure 1) is consistent with the direction of the gate electric field. The gate electric field has a gain effect on the carrier, has a high carrier tunneling efficiency, and has a tunnel. The magnitude of the through current is proportional to the tunnel junction area and can form a steep subthreshold swing (the value of the subthreshold swing is small). Compared with line tunneling, the point tunneling (shown by the dashed arrow in Figure 1) has lower carrier tunneling efficiency, the current is difficult to adjust directly, and the subthreshold swing is relatively flat (sub-threshold pendulum) The value of the width is larger). In the TFET of Figure 1, the line tunneling and point tunneling mechanisms coexist, but under the control of the same gate, the turn-on voltage of the point tunneling is lower than the line tunneling. Therefore, the point tunneling precedes the line. Tunneling is turned on, resulting in degradation of the subthreshold swing of the entire device (ie, resulting in an increase in subthreshold swing). This in turn results in a TFET device that is less effective at reducing power consumption by lowering the voltage.

In order to solve the "interference" problem of the point tunneling to the line tunneling of the TFET device in FIG. 1, different metal work functions can be set by the line tunneling junction and the point tunneling junction (taking the N-type device as an example, at the point The metal layer at the tunneling is set up with a large work function to delay its turn-on). Specifically, as shown in FIG. 2, a metal layer 1 and a metal layer 2 are respectively deposited over the on-line tunneling junction and the point tunneling junction. The metal layer 2 has a larger work function than the metal layer 1, and can delay point tunneling. Opened.

However, for the TFET in Figure 2, the metal work function of the point tunneling junction and the line tunneling junction is very small, and it is very important to find two kinds of work functions that are very close to each other (generally only less than 1 eV). difficult. In addition, the TFET device of FIG. 2 requires two photolithography, etching, and deposition of the metal layer during fabrication, which requires a high manufacturing process and a large cost.

FIG. 3 is a schematic structural view of a TFET of an embodiment of the present application. The TFET of Figure 3 includes:

Source region, channel and work function layer.

Wherein, the work function layer is composed of a titanium nitride (TiN) material, and the work function layer is located above the source region and the channel, and further, the work function layer includes the first region and the second region, wherein the first region is a work function The region in the layer acts on the line tunneling junction, the second region is the region of the work function layer acting on the point tunneling junction, and the second region is doped with aluminum ions.

It should be understood that in FIG. 3, the first region is a region above the source region in the work function layer, and the second region is a region above the channel in the work function layer.

In the present application, since the region of the work function layer acting on the point tunneling junction is doped with aluminum ions, the work function of the region of the work function layer acting on the point tunneling is greater than the work function layer interacting with the line tunneling region. The work function can delay or suppress the opening of the point tunneling junction, thereby avoiding the interference caused by the subthreshold swing after the point tunneling is turned on, and improving the subthreshold swing characteristic of the TFET device, so that the TFET device can reduce the voltage by Reduce power consumption for better results.

In particular, since line tunneling is not disturbed by point tunneling, TFET devices can have better subthreshold characteristics, that is, the voltage required to reduce the current of the TFET by an order of magnitude is smaller, thus TFET devices can be operated at lower voltages, which can better reduce the power consumption of TFET devices.

The first region and the second region of the work function layer of the TFET in the present application are both based on titanium nitride, and do not require any treatment for the first region, and only need to be titanium nitride for the second region. It is only necessary to inject aluminum ions on the basis of the same, and it is necessary to separately fabricate two metal layers having different work functions, as shown in Fig. 2. The TFET of the present application is easy to implement and simple to manufacture.

In addition, the TFET of FIG. 3 may further include a drain region, a gate dielectric layer, a pocket layer, and a partition wall. Wherein, the drain region is adjacent to the channel, and the source region and the channel are sequentially a pocket layer, a gate dielectric layer and a work function layer, and the isolation wall is located around the pocket layer, the gate dielectric layer and the work function layer, and the height of the isolation wall is equal to The thickness of the pocket layer, the thickness of the gate dielectric layer, the thickness of the work function layer, and the length of the first region.

Optionally, the thickness of the work function layer is less than 10 nanometers and the thickness of the gate dielectric layer is less than 5 nanometers.

As shown in FIG. 4, the TFET of the present application further includes polysilicon, which is located above the work function layer. The polysilicon may form a gate with a work function layer and a gate dielectric layer.

In Figures 3 and 4, the pocket layers are both located above the surface of the source region and the channel, and the pocket layer is in contact with the source region and the surface of the channel.

Alternatively, the pocket layer may be located not only on the surface of the unetched source region and the channel but also in the trench formed after etching the source region and the channel surface. As shown in FIG. 5, the source region and the channel are etched with a first trench, and the pocket layer is located within the first trench. The depth of the first groove is the same as the height of the pocket layer, so that the pocket layer is filled in After a trench, it is in a plane with the unetched surface of the source region and the channel.

The above pocket layer may be composed of at least one of silicon, germanium, germanium silicon, and a group III-V compound semiconductor material.

Optionally, the doping type of the source region is P-type, the doping type of the drain region is N-type, or the doping type of the source region is N-type, and the doping type of the drain region is P-type. That is to say, the source region and the drain region belong to different doping types, respectively. In addition, the above doping may be either lightly doped or heavily doped.

Optionally, when the doping type of the source region or the drain region is P-type, the doping concentration of the impurity after annealing is higher than 1×10 ²⁰ cm ⁻³ .

Optionally, when the doping type of the source region or the drain region is N-type, the doping concentration of the impurity after annealing is between 5×10 ¹⁸ and 1×10 ²⁰ cm ⁻³ .

Optionally, the source region, the drain region, and the channel are made of a semiconductor substrate material, and the semiconductor substrate is at least one of a bulk silicon material, a silicon on insulator, a germanium material, and a III-V compound semiconductor material. Kind.

The TFET of the embodiment of the present application is described in detail above with reference to FIG. 1 to FIG. 5. The method for fabricating the TFET of the embodiment of the present application will be described in detail below with reference to FIG. 6 to FIG.

FIG. 6 is a schematic flowchart of a method of fabricating a TFET according to an embodiment of the present application. The method of Figure 6 includes:

610. Fabricating a source region and a channel on a semiconductor substrate.

The semiconductor substrate material may specifically be at least one of a bulk silicon material, a silicon on insulator, a germanium material, and a III-V compound semiconductor material.

620. Create a work function layer above the source region and the channel.

Wherein, the material of the work function layer is titanium nitride, and the work function layer comprises a first region and a second region, wherein the first region is a region of a work function layer acting on a line tunneling junction, and the second region is a work function layer The area that acts on the point tunneling junction.

630. Inject aluminum ions into the second region.

In the present application, by doping aluminum ions in a region of the work function layer acting on the point tunneling junction, the work function of the region acting on the point tunneling in the work function layer is greater than the work functioning on the line tunneling region in the work function layer. The work function can delay or suppress the opening of the point tunneling junction, thereby avoiding the interference caused by the subthreshold swing after the point tunneling is turned on, and improving the subthreshold swing characteristic of the TFET device, so that the TFET device can reduce the voltage by Reduce power consumption for better results.

Optionally, as an embodiment, before injecting aluminum ions into the second region, the method of FIG. 6 further includes:

Making a pocket layer and a gate dielectric layer over the source region and the channel;

Making a partition wall around the pocket layer, the gate dielectric layer, and the work function layer;

Injecting aluminum ions into the second region, including:

Aluminum ions are implanted into the work function layer in a direction at a first angle to the horizontal direction such that aluminum ions are implanted only into the second region.

Specifically, when the height of the partition wall is equal to the thickness of the pocket layer, the thickness of the gate dielectric layer, the sum of the thickness of the work function layer and the length of the first region, the first angle is 45 degrees.

It should be understood that the first angle here is related to the height of the wall. Assume that the height of the wall is the first value, the mouth The sum of the thickness of the bag layer, the thickness of the gate dielectric layer, the thickness of the work function layer and the length of the first region is a second value, then, when the first value is equal to the second value, the first angle is 45 degrees, when the first When a value is greater than the second value, the first angle is greater than 45 degrees and less than 90 degrees, and when the first value is less than the second value, the first angle is less than 45 degrees.

The complete process of the tunneling field effect transistor of the embodiment of the present application will be described in detail below with reference to FIG. 7 to FIG. 14 using an N-type TFET as an example.

S710, providing a semiconductor substrate (as shown in FIG. 7), and forming a first dummy gate on the surface of the semiconductor substrate by using deposition, photolithography, and etching techniques.

The semiconductor substrate may be a bulk silicon material, a silicon-on-insulator (SOI), a germanium material, a III-V compound semiconductor material, or the like.

The material of the first dummy gate may be a material different from the semiconductor substrate material such as polysilicon or silicon dioxide. In addition, the height of the first dummy gate needs to be equal to the length of the first dummy gate and the thickness of the pocket layer produced in the subsequent step, The sum of the thickness of the gate dielectric layer and the thickness of the first work function layer.

It should be understood that the photoresist of FIG. 7 can ensure that the first dummy gate is not etched away during the photolithography process.

S720, isotropic deposition material film, anisotropically depositing the film to form a second dummy gate and a third dummy gate on both sides of the first dummy gate (as shown in FIG. 8).

Wherein, the thickness of the deposited film is the same as the width of the first dummy gate, and thus the widths of the second dummy gate and the third dummy gate are the same as the width of the first dummy gate. In addition, the materials of the second dummy gate and the third dummy gate may be polysilicon, silicon dioxide or other materials, and the materials of the second dummy gate and the third dummy gate are different from those of the first dummy gate and the semiconductor substrate. .

S730, using a photolithography technique, removing the second dummy gate, and doping the exposed semiconductor substrate on the left side with a P-type impurity (as shown in FIG. 9).

Wherein, when doping is performed using a P-type impurity in step S703, it is ensured that the doping concentration after annealing is higher than 1 × 10 ²⁰ cm ^-3 .

S740, the resultant structure isotropically deposited dielectric film, and then anisotropically etched to form a partition wall on both sides of the gate;

The source region is protected by photolithography, and the drain region is doped with an N-type impurity (as shown in FIG. 10).

The material of the partition wall may be a dielectric material such as silicon dioxide or silicon nitride, and the material of the partition wall is different from the first dummy gate and the second dummy gate. The wall has a thickness of less than 20 nanometers. Further, when doping with an N-type impurity in step S704, it is ensured that the impurity doping concentration after annealing is between 5 × 10 ¹⁸ and 1 × 10 ²⁰ cm ^-3 .

S750, removing the first dummy gate and doping with P-type impurities (the doping concentration after annealing is higher than 1×10 ²⁰ cm ⁻³ ), rapidly annealing the generated structure, and activating the implanted impurity ions ( As shown in Figure 11).

S760, removing the third dummy gate, and thereby depositing a pocket layer, a gate dielectric layer and a titanium nitride layer on the exposed gate region (as shown in FIG. 12), and rapidly annealing the generated structure.

The pocket layer has a thickness of less than 10 nanometers, and the pocket layer may be composed of at least one of silicon, germanium silicon, germanium, and a group III-V material.

The thickness of the above gate dielectric layer is less than 5 nm. The material constituting the gate dielectric layer may be a high dielectric constant material such as silicon dioxide, silicon nitride, or hafnium oxide, or a multilayer dielectric layer composed of silicon dioxide and a high dielectric constant material.

An epitaxial growth process can be employed in depositing the above pocket layer. In addition, after the pocket layer is formed, the pocket layer is also doped in situ with a doping concentration of 1 × 10 ¹⁵ to 1 × 10 ¹⁸ cm ^-3 .

The titanium nitride layer described above is used to determine the device gate work function and has a thickness of less than 10 nanometers.

S770, on the formed structure, the titanium nitride layer is subjected to aluminum ion dip angle implantation (as shown in FIG. 13), and the formed structure is subjected to low temperature annealing to activate aluminum ions.

The titanium nitride layer adjacent to the drain end can implant aluminum ions, and the titanium nitride adjacent to the source region is not subjected to aluminum ion implantation due to the barrier of the isolation wall, that is, the aluminum ion dip angle is injected into the self-aligned layer to the work above the channel region. The work function of the function layer is adjusted.

S780, the source, the gate and the drain are respectively fabricated on the source region, the gate region and the drain region (as shown in FIG. 14).

The fabrication of the TFET is completed through the above steps S710-S780, and the fabricated TFET is as shown in FIG. In addition, before depositing the pocket layer on the gate region in the above step S760, the semiconductor trench may be etched in advance, the filling pocket layer is deposited, and then the gate dielectric layer and the metal layer are grown, and other process steps are identical, and the structure of the obtained TFET is as follows. Figure 5 shows.

Those of ordinary skill in the art will appreciate that the elements and algorithm steps of the various examples described in connection with the embodiments disclosed herein can be implemented in electronic hardware or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the solution. A person skilled in the art can use different methods to implement the described functions for each particular application, but such implementation should not be considered to be beyond the scope of the present application.

A person skilled in the art can clearly understand that for the convenience and brevity of the description, the specific working process of the system, the device and the unit described above can refer to the corresponding process in the foregoing method embodiment, and details are not described herein again.

In the several embodiments provided by the present application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the device embodiments described above are merely illustrative. For example, the division of the unit is only a logical function division. In actual implementation, there may be another division manner, for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.

The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

The functions may be stored in a computer readable storage medium if implemented in the form of a software functional unit and sold or used as a standalone product. Based on such understanding, the technical solution of the present application, which is essential or contributes to the prior art, or a part of the technical solution, may be embodied in the form of a software product, which is stored in a storage medium, including The instructions are used to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like. .

The foregoing is only a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto, and any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present application. It should be covered by the scope of protection of this application. Therefore, the scope of protection of the present application should be determined by the scope of the claims.

Claims

A tunneling field effect transistor TFET, comprising:

Source area

Channel

a work function layer, the material of the work function layer is titanium nitride, the work function layer is located above the source region and the channel, and the work function layer includes a first region and a second region, the first An area is a region of the work function layer that acts on a line tunneling junction, and the second region is a region of the work function layer that acts on a point tunneling junction, the second region being doped with aluminum ions.
The TFET of claim 1 wherein said TFET further comprises:

a gate dielectric layer under the work function layer;

a pocket layer located below the gate dielectric layer;

a partition wall surrounding the pocket layer, the gate dielectric layer, and the work function layer, the height of the partition wall being equal to a thickness of the pocket layer, a thickness of the gate dielectric layer, and a work function layer The sum of the thickness and the length of the first region.
The TFET of claim 2, said source region and said channel surface being etched with a first trench, said pocket layer being located within said first trench.
The TFET according to claim 2 or 3, wherein the pocket layer is composed of at least one of silicon, germanium, germanium silicon, and a group III-V compound semiconductor material.
The TFET of any of claims 1 to 4, wherein the TFET further comprises:

Leakage zone

Wherein the doping type of the drain region is N-type, and the doping type of the source region is P-type, or

The doping type of the drain region is N-type, and the doping type of the source region is P-type.
The TFET according to claim 5, wherein said source region, said drain region, and said channel are made of a semiconductor substrate material, said semiconductor substrate material being a bulk silicon material, an insulating substrate At least one of a silicon material, a germanium material, and a III-V compound semiconductor material.
The TFET of any of claims 1-6, wherein the work function layer has a thickness of less than 10 nanometers.
A method of fabricating a TFET, comprising:

Making a source region and a channel on a semiconductor substrate;

Forming a work function layer above the source region and the channel, the material of the work function layer being titanium nitride, the work function layer comprising a first region and a second region, wherein the first region is a region of the work function layer that acts on the line tunneling junction, and the second region is a region of the work function layer that acts on the point tunneling junction;

Aluminum ions are implanted into the second region.
The method of claim 8 wherein prior to injecting aluminum ions into said second region, said method further comprising:

Forming a pocket layer and a gate dielectric layer over the source region and the channel;

Forming a partition wall around the pocket layer, the gate dielectric layer, and the work function layer;

The injecting aluminum ions into the second region comprises:

Aluminum ions are implanted into the work function layer in a direction at a first angle to the horizontal direction such that aluminum ions are implanted only into the second region.
The method according to claim 9, wherein a height of said partition wall is equal to a thickness of said pocket layer, a thickness of said gate dielectric layer, a thickness of said work function layer, and said first region In the case of a sum of lengths, the first angle is 45 degrees.