JP2008028263A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that includes a field effect transistor, capable of attaining a high Ion/Ioff ratio by optimizing the structure of the source/drain region. <P>SOLUTION: In the semiconductor device that includes a field effect transistor, a first gate electrode 107 and a second gate electrode 108 are formed via a first gate insulating film 103 and a second gate insulating film 104, facing on both sides of a channel region 101, respectively. The source region 111 and the drain region 121 are formed on opposite sides of the first gate electrode 107 and the second gate electrode 108, sandwiching the channel region 101 therebetween. The thickness of the source region 111 (TSis) perpendicular to the interface between the first gate insulating film 103 and the channel region 104 is larger than the thickness of the channel region 101 (TSic) in the same direction. Furthermore, the source region 111 and the first and second gate electrodes 107, 108 are separated in the gate lengthwise direction. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a field effect transistor having a multi-gate electrode and having a source / drain region structure optimized.

In order to improve the performance of a semiconductor integrated circuit, it is essential to improve the performance of a field effect transistor that is a component thereof. The guiding principle for improving the performance of devices is miniaturization, and so far, device performance has been improved by miniaturization. In terms of the gate length of the transistor, the research level has reached 10 nm or less (Non-Patent Document 1).
In such an ultrafine field effect transistor, the gate length is shortened and the distance between the source region and the drain region is shortened, so that the non-scattering carrier component in the drain current is increased, and the drain current when the field effect transistor is ON, That is, Ion becomes high. However, at the same time, there is a trade-off in that the current when the field effect transistor is turned off, that is, Ioff is also increased due to the short channel effect.
In order to obtain clear switching characteristics as a high-performance field effect transistor, it is essential to increase the relative ratio (Ion / Ioff ratio) of Ion and Ioff. Here, Ioff means the drain current value when the drain voltage is set to the power supply voltage (Vdd) and the source and gate voltages are set to 0 V (Vss), taking an n-channel field effect transistor as an example. To do. Ion means the drain current value when the drain voltage is set to the power supply voltage (Vdd), the source voltage is set to 0 V (Vss), and the gate voltage is set to the power supply voltage (Vdd).

By the way, the short channel effect is suppressed and the Ioff is reduced by using a multi-gate electrode surrounding the channel region with a plurality of electrodes, for example, a double gate structure in which the channel region is sandwiched between upper and lower gate electrodes (Non-patent Document 2). It is conventionally known that this is possible. That is, according to such a field effect transistor having a multi-gate electrode, the dominance over the channel region of the gate is increased, and DIIn (Drain Induced Barrier Lowering), which is one of the short channel effects, is suppressed, thereby reducing Ioff. descend.
On the other hand, in the ultrafine field effect transistor, the non-scattering carrier component in the drain current increases as described above. For this reason, it is expected that the incident speed of carriers at the end of the source region determines the drain current (Non-Patent Document 3). In addition to the incident speed, the amount of incident carriers naturally limits the drain current.
Therefore, in order to increase the Ion / Ioff ratio in the ultrafine field effect transistor, it is considered effective to modulate the incident velocity and the incident amount of the carrier into the channel region after forming a multi-gate electrode.
Wakabayashi et al. , IEDM Tech. Dig. , P981,2003 Liu et al. , IEEE EDL 25, p510, 2004 Natori, J. et al. Appl. Phys. 76, p4879, 1994

As described above, in the ultrafine field effect transistor, as one guideline for increasing the Ion / Ioff ratio, a decrease in Ioff due to the use of a multi-gate electrode, and Ion due to modulation of the incident velocity and incident amount of the carrier into the channel region. , Ioff control can be considered.
However, in a field effect transistor having a multi-gate electrode, there is a problem that the optimum device structure for improving the Ion / Ioff ratio is not necessarily clarified by the modulation of the incident velocity and the incident amount of the carrier into the channel region. there were.

  The present invention has been made in view of the above circumstances, and its object is to include a field effect transistor capable of obtaining a high Ion / Ioff ratio by optimizing the source / drain region structure. It is to provide a semiconductor device.

A semiconductor device of one embodiment of the present invention includes:
A semiconductor device including a field effect transistor comprising a channel region, a first gate electrode, a second gate electrode, a source region, and a drain region,
The first gate electrode and the second gate electrode are respectively formed through a first gate insulating film and a second gate insulating film so as to face both sides of the channel region,
The source region and the drain region are formed on both sides of the first gate electrode and the second gate electrode with the channel region interposed therebetween,
A thickness (TSis) of the source region in a direction perpendicular to an interface between the first gate insulating film and the channel region is larger than a thickness (TSic) of the channel region in the direction; and
The source region, the first gate electrode, and the second gate electrode are separated in the gate length direction.

  Here, it is desirable that the separation distance is 1 nm or more and 3.5 nm or less.

  Here, it is preferable that a thickness (TSid) of the drain region in a direction perpendicular to an interface between the first gate insulating film and the channel region is equal to or less than a thickness (TSic) of the channel region.

Here, it is desirable that the impurity concentration of the channel region is 1E19 atoms / cm ³ or more and 1E20 atoms / cm ³ or less.

A semiconductor device of one embodiment of the present invention includes:
A semiconductor device including a field effect transistor comprising a channel region, a first gate electrode, a second gate electrode, a source region, and a drain region,
The first gate electrode and the second gate electrode are respectively formed through a first gate insulating film and a second gate insulating film so as to face both sides of the channel region,
The source region and the drain region are formed on both sides of the first gate electrode and the second gate electrode with the channel region interposed therebetween,
A thickness (TSis) of the source region in a direction perpendicular to an interface between the first gate insulating film and the channel region is smaller than a thickness (TSic) of the channel region in the direction. .

  Here, it is preferable that the source region, the first gate electrode, and the second gate electrode are not separated in the gate length direction.

  Here, the field effect transistor is preferably formed on an insulating film substrate.

  According to the present invention, it is possible to provide a semiconductor device including a field effect transistor capable of obtaining a high Ion / Ioff ratio by optimizing the structure of the source / drain regions.

In the field effect transistor having a multi-gate electrode, the inventors have made the incident speed and the incident amount of the carrier into the channel region by making the source region thicker or thinner than the channel region. It was found that the Ion / Ioff ratio of the transistor was improved.
The greatest feature of the present invention is that, in a field effect transistor having a multi-gate electrode, the thickness of the source region is made thicker or thinner than the thickness of the channel region.
Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a cross-sectional view in the channel length direction showing the element structure of the field effect transistor of the first embodiment. 2A is a perspective view showing the entire structure of the element structure of the field effect transistor according to the first embodiment, and FIG. 2B is a sectional view of the drain region perpendicular to the channel length. 2C is a cross-sectional view of the channel region, and FIG. 1D is a cross-sectional view of the source region. In the perspective view, the insulating films 103, 104, 115 and 210 in the cross-sectional view are omitted for simplification of the drawing.
As will be described in detail later, the field effect transistor of the present embodiment is a Fin-type transistor having a pair of side gate electrodes (double gates), the source region is thicker than the channel region, and The source region is separated (offset) from the gate electrode in the gate length direction.

More specifically, as shown in FIGS. 1 and 2, a silicon substrate 100 having an impurity concentration is 5E15atoms / cm ³ order of p-type impurity concentration of the channel region 101 of the p-type of about 5E19atoms / cm ^3, For example, a field effect transistor having a first gate electrode 107 and a second gate electrode 108 made of n-type polysilicon, an n-type source region 111 and a drain region 121 having an impurity concentration of about 2E20 atoms / cm ³ is formed. ing. Then, the first gate electrode 107 and the second gate electrode 108 are formed through the first gate insulating film 103 and the second gate insulating film 104 so as to face both sides of the channel region 101, respectively. ing. The source region 111 and the drain region 121 are formed on both sides of the first gate electrode 107 and the second gate electrode 108 with the channel region 101 interposed therebetween, and the source region 111 and the drain region 121 are insulated from each other. It is covered with a film 115.

In the present embodiment, as shown in FIGS. 1 and 2, the thickness (TSis) of the source region 111 in the direction perpendicular to the interface between the first gate insulating film 103 and the channel region 101 is the same. Thickness (TSis> TSic) of the channel region 101 as viewed in the direction (TSis> TSic), and the source region 111, the first gate electrode 107, and the second gate electrode 108 are separated by a distance d in the gate length direction. It is characterized by being separated (offset) (FIG. 1).

  By making the thickness of the source region thicker than that of the channel region and separating the source region and the gate electrode in this way, a remarkable effect of improving the Ion / Ioff ratio as compared with the prior art is achieved. Is obtained.

FIG. 3 shows the result of simulating the relationship between the distance d between the source region and the gate electrode and the Ion / Ioff ratio.
In the simulation, gate length (L) = 10 nm, EOT (Equivalent Oxide Thickness) = 1 nm, channel region thickness (TSic) = 3 nm, source region thickness (TSis) = 3.8 nm, channel impurity concentration 5E19atoms / cm ³ in the region, the impurity concentration 2E20atoms / cm ³ of the source and drain regions, was calculated as the drain voltage (Vd) = 0.8V. This condition corresponds to condition A in Table 1 below.
FIG. 37 is a cross-sectional view in the channel length direction showing the element structure of a conventional field effect transistor, and FIG. 38A is a perspective view showing the entire structure of the element structure of the conventional field effect transistor. FIG. 38B is a cross-sectional view of the drain region perpendicular to the channel length, FIG. 38C is a cross-sectional view of the channel region, and FIG. 38D is a cross-sectional view of the source region. In the perspective view, the insulating films 103, 104, 115 and 210 in the cross-sectional view are omitted for simplification of the drawing. 37 and 38, the field effect transistor of the related art in which the thickness (TSis) of the source region 111 and the thickness (TSic) of the channel region 101 are equal (TSis = TSic) is also used as a comparative example. Was calculated. At this time, the thickness of the channel region (TSic) and the thickness of the source region (TSis) are both set to 3.0 nm, and the separation distance d is 0 nm, that is, the present embodiment (the present embodiment) except that no offset is set. The calculation was performed under the same conditions as in the case of the invention.

  As is clear from FIG. 3, in this embodiment (the present invention), the Ion / Ioff ratio is improved as compared with the conventional technique (comparative example). In particular, the separation distance d = 2.5 nm to 3 nm has a maximum value, and in this case, about 15% Ion / Ioff ratio is improved as compared with the prior art (comparative example).

FIG. 4 compares the gate voltage (Vg) -drain current (Id) characteristics between the case of the separation distance d = 2.5 nm in the present embodiment (the present invention) and the case of the conventional technique (comparative example). FIG. The drain current (Id) is shown in linear and logarithmic representation.
From FIG. 4, in the present embodiment (the present invention), there is no significant change in Ioff from the prior art (comparative example), and the Ion / Ioff ratio is improved as a result of increasing Ion. Is clear.

以上のように、ソース領域の厚さを変化させることにより、ドレイン電流の変調が可能であることを発明者らは見出し、この作用を本実施の形態で利用することにより、Ｉｏｎ／Ｉｏｆｆ比を向上させることを可能とした。 The operation and effect that the Ion / Iff ratio is improved in the present embodiment will be described using the band diagram of FIG.
FIG. 5A is a band diagram in the case where the thickness of the source region and the channel region in the prior art is equal, and FIG. 5B is a diagram showing the thickness of the source region in this embodiment is the thickness of the channel region. It is a band figure in case it is thicker than this.
First, in general, the drain current density J is approximately equal to the following formula J = qnv where q is the elementary charge.
And is proportional to the electron injection amount n from the source region to the channel region and the average incident velocity v of electrons from the source region to the channel region.
Then, by making the thickness of the source region thicker than that of the channel region, the base subband of the source region is lowered and the barrier is reduced as shown in FIG. n increases.
For this reason, the drain current density J is increased, that is, Ion is increased, and the Ion / Ioff ratio is improved.
In addition, when the thickness of the source region is made larger than the thickness of the channel region, the base subband of the source region is lower than that of the channel region. This is because the energy E of the base subband of the wave function of the electrons in the semiconductor confined in the semiconductor is inversely proportional to the square of the semiconductor thickness TSi if the leakage of the electron wave function to the insulator is ignored.

As described above, the inventors have found that the drain current can be modulated by changing the thickness of the source region. By utilizing this action in the present embodiment, the Ion / Ioff ratio is increased. It was possible to improve.

In this embodiment, the impurity concentration of the channel region is 5E19 atoms / cm ³ , but in order to improve the Ion / Ioff ratio with certainty, the impurity concentration of the channel region is 1E19 atoms / cm ³ or more and 1E20 atoms / cm ^3. It is desirable to be in the range of ³ or less. This is because if it is lower than this, an increase in Ioff due to a decrease in the base subband of the source region may degrade the Ion / Ioff ratio. Conversely, if it is higher, the inversion voltage of the channel region becomes too high, and the device This is because there is a possibility that the structure cannot withstand actual use.

Next, FIGS. 6 to 9 show the results of further investigation on the dependence of the Ion / Ioff ratio on the separation distance d seen in FIG. Here, the simulation was performed by setting the impurity concentrations of the source / drain regions and the channel region, which are considered to have the greatest influence on the distance d dependency from the viewpoint of the barrier height, as the variables in the conditions shown in Table 1 below. The conditions in FIG. 3 correspond to condition A in Table 1. In conditions B to E, conditions other than the impurity concentration were the same as those in FIG.

6 to 9, as in the case of FIG. 3, the Ion / Ioff ratio tends to have a maximum value in a region where the gate electrode and the source region are separated (offset) to some extent.
This tendency can be explained as follows. First, if the separation distance d between the gate electrode and the source region becomes too large, the channel resistance of the separation (offset) portion where the gate does not dominate increases, and therefore the channel resistance is more than the reduction in Ioff due to the increase in channel resistance. The decrease in Ion due to the increase becomes significant, and the Ion / Ioff ratio decreases. On the other hand, if the separation distance d is too small, the channel resistance of the separation (offset) portion where the dominating force of the electric field of the gate electrode does not decrease. The increase in Ioff becomes significant, and again the Ion / Ioff ratio decreases. Therefore, the maximum value of Ion / Ioff can be obtained in a region where the gate electrode and the source region are separated (offset) to some extent.

  From the above results, in this embodiment, the distance d between the gate electrode and the source region is preferably in the range of 1 nm to 3.5 nm where Ion / Iff has a maximum value.

Next, a first modification of the present embodiment will be described.
FIG. 10 is a cross-sectional view in the channel length direction showing the element structure of the field effect transistor of the first modification, and FIG. 11A shows the entire element structure of the field effect transistor of the first modification. FIG. 11B is a cross-sectional view of the drain region perpendicular to the channel length, FIG. 11C is a cross-sectional view of the channel region, and FIG. 11D is a cross-sectional view of the source region. In the perspective view, the insulating films 103, 104, 115 and 210 in the cross-sectional view are omitted for simplification of the drawing. In the present invention, as shown in FIGS. 10 and 11, the drain region 121 may have a thickness (TSid) that is greater than the thickness (TSic) of the channel region 101 (TSid> TSic).
In this case, by increasing the thickness of the drain region 121, the barrier against electrons on the drain side is also lowered, and there is a concern that electrons from the drain region may affect the transistor characteristics by entering the channel portion.
However, in the case of an element in which the source and the drain are interchanged in terms of circuit operation, since the thickness of both the source region and the drain region is larger than the thickness of the channel region, the Ion / Ioff ratio under all circuit operation conditions. Is desirable because it improves. Furthermore, from the viewpoint of circuit design and ease of manufacture, it is more desirable that the source and drain regions on both sides of the channel region are symmetrically thick.

Further, as a second modification of the present embodiment, a configuration (TSid <TSic) in which the thickness (TSid) of the drain region 121 is made thinner than the thickness (TSic) of the channel region 101 may be adopted.
In this case, by reducing the thickness of the drain region 121, as will be described later in detail in the second embodiment, there is a barrier against electrons on the drain side, and electrons from the drain region enter the channel portion. By effectively preventing this, there is an advantage that adverse effects such as an increase in Ioff can be suppressed in the transistor characteristics.

  Next, a method for manufacturing a semiconductor device including the field effect transistor of this embodiment will be described with reference to FIGS.

  First, as shown in FIG. 12 which is a plan view of FIG. 12, FIG. 13 which is a cross-sectional view in the AA direction of FIG. 12, and FIG. 14 which is a cross-sectional view in the BB direction of FIG. After depositing an insulating film 210 serving as a mask material such as a silicon nitride film of about 50 to 100 nm on the type silicon substrate 100, the insulating film 210 and silicon are etched by lithography techniques and etching techniques such as reactive ion etching (hereinafter also referred to as RIE). The substrate 100 is etched to form a trench that becomes an element region 201 and an element isolation region. At this time, a mask pattern is used in which the thickness of the portion that will later become the source region becomes larger than the thickness of the channel region. Thereafter, introduction of p-type impurities into the channel region for threshold adjustment can be performed using, for example, an oblique ion implantation technique.

Next, as shown in FIG. 15 which is a plan view of FIG. 15, FIG. 16 which is a cross-sectional view in the CC direction of FIG. 15, and FIG. 17 which is a cross-sectional view in the DD direction of FIG. An insulating film 215 such as a silicon oxide film is deposited, and the insulating film 215 is flattened to the upper surface of the insulating film 210 by a chemical mechanical polishing method (hereinafter also referred to as CMP) to form an element isolation region. . At this time, a p-type impurity may be introduced under the element isolation region by ion implantation or the like in order to improve the element isolation breakdown voltage and reduce the leakage current of the parasitic transistor.
Thereafter, a part of the insulating film 215 is removed, and a groove 205 is formed so that the side surface of the element region 201 is exposed.

  Next, as shown in FIG. 18 which is a plan view of FIG. 18, FIG. 19 which is a cross-sectional view in the EE direction of FIG. 18, and FIG. 20 which is a cross-sectional view in the FF direction of FIG. Gate insulating films 103 and 104 are formed. The gate insulating films 103 and 104 may be, for example, a silicon oxide film formed by a thermal oxidation method, or a high dielectric film formed by a CVD (Chemical Vapor Deposition) method or an ALD (Atomic Layer Deposition) method. It doesn't matter.

  Next, a conductive material to be the gate electrodes 107 and 108 is deposited on the gate insulating films 103 and 104 to fill the trenches 205. Thereafter, the buried conductive material and the gate insulating film are planarized by CMP until the upper surface of the insulating film 210 is exposed. Here, the conductive material to be the gate electrodes 107 and 108 is made of, for example, a material such as (doped) polysilicon, silicide, or metal.

Next, as shown in the plan view of FIG. 21, FIG. 22 which is a cross-sectional view in the GG direction of FIG. 21, and FIG. 23 which is a cross-sectional view in the HH direction of FIG. Is deposited, and a gate wiring 109 is formed so as to physically and electrically connect the first gate electrode 107 and the second gate electrode 108 by lithography and RIE. Here, the gate wiring 109 is made of, for example, a material such as (doped) polysilicon, silicide, or metal.
Thereafter, sidewall insulating films 220 made of, for example, a silicon nitride film are formed on both sides of the gate wiring 109.
Then, n-type impurities are introduced into the source region 111 and the drain region 121 by ion implantation or the like using the gate wiring 109 and the sidewall insulating film 220 as a mask.

Next, as shown in FIG. 24, which is a plan view of FIG. 24, FIG. 25 which is a cross-sectional view in the II direction of FIG. 24, and FIG. 26 which is a cross-sectional view in the JJ direction of FIG. After that, contact holes are opened by lithography and RIE so that the side surfaces of the source region 111 and the drain region 121 are exposed. The contact hole is filled with a conductive material, whereby the contact electrode 131 on the source region side and the contact electrode 133 on the drain side are formed.
As described above, the semiconductor device of the present embodiment is formed.

(Second Embodiment)
FIG. 27 is a cross-sectional view in the channel length direction showing the element structure of the field effect transistor of the second embodiment. FIG. 28A is a perspective view showing the entire structure of the element structure of the field effect transistor according to the second embodiment, and FIG. 28B is a cross-sectional view of the drain region perpendicular to the channel length. FIG. 28C is a cross-sectional view of the channel region, and FIG. 28D is a cross-sectional view of the source region. In the perspective view, the insulating films 103, 104, 115 and 210 in the cross-sectional view are omitted for simplification of the drawing.
The field effect transistor of this embodiment is a Fin-type transistor having a pair of side gate electrodes (double gates) as will be described in detail later, and the thickness of the source region is thinner than the thickness of the channel region. It is characterized by that.

More specifically, as shown in FIGS. 27 and 28, the silicon substrate 100 having an impurity concentration is 5E15atoms / cm ³ order of p-type impurity concentration of the channel region 101 of the p-type of about 5E19atoms / cm ^3, For example, a field effect transistor having a first gate electrode 107 and a second gate electrode 108 made of n-type polysilicon, an n-type source region 111 and a drain region 121 having an impurity concentration of about 1E19 atoms / cm ³ is formed. ing. Then, the first gate electrode 107 and the second gate electrode 108 are formed through the first gate insulating film 103 and the second gate insulating film 104 so as to face both sides of the channel region 101, respectively. ing. The source region 111 and the drain region 121 are formed on both sides of the first gate electrode 107 and the second gate electrode 108 with the channel region 111 interposed therebetween. The source region 111 and the drain region 121 are insulated from each other. It is covered with a film 115.

  In this embodiment, as shown in FIGS. 27 and 28, the thickness (TSis) of the source region 111 in the direction perpendicular to the interface between the first gate insulating film 103 and the channel region 101 is the same. It is characterized by being thinner (TSis <TSic) than the thickness (TSic) of the channel region as viewed in the direction.

  Thus, by making the thickness of the source region thinner than the thickness of the channel region, a remarkable effect that the Ion / Ioff ratio is improved as compared with the prior art can be obtained.

FIG. 29 shows the result of simulating the relationship between the distance d between the source region and the gate electrode and the Ion / Ioff ratio.
In the simulation, the gate length (L) = 10 nm, the gate insulating film EOT (Equivalent Oxide Thickness) = 1 nm, the channel region thickness (TSic) = 3 nm, the source region thickness (TSis) = 2.2 nm, the channel impurity concentration 5E15atoms / cm ³ in the region, the impurity concentration of 1E19 atoms / cm ³ of the source and drain regions, was calculated as the drain voltage (Vd) = 0.8V.
In addition, as a comparative example, the Ion / Ioff ratio of the conventional field effect transistor in which the thickness (TSis) of the source region 111 and the thickness (TSic) of the channel region 101 shown in the schematic diagrams of FIGS. Was calculated. At this time, the thickness of the channel region (TSic) and the thickness of the source region (TSis) are both set to 3.0 nm, and the separation distance d is 0 nm, that is, the present embodiment (the present embodiment) except that no offset is set. The calculation was performed under the same conditions as in the case of the invention.

As is clear from FIG. 29, in this embodiment (the present invention), the Ion / Ioff ratio is remarkably improved as compared with the conventional technique (comparative example). Unlike the first embodiment, the Ion / Iff ratio becomes maximum when the separation distance d = 0 nm between the gate electrode and the source region, that is, when there is no separation (offset). In this case, the Ion / Ioff ratio is about 200 times that of the prior art (comparative example).
Therefore, in this embodiment mode, it is desirable that the source region and the gate electrode are not separated (offset) in the gate length direction.

FIG. 30 is a diagram comparing the gate voltage (Vg) -drain current (Id) characteristics between d = 0 nm in the present embodiment (the present invention) and the conventional technique (comparative example). The drain current (Id) is shown in logarithmic display.
From FIG. 30, in this embodiment (the present invention), Ion is slightly inferior to the prior art (comparative example), but Ion / Ioff ratio is improved as a result of Ioff being significantly reduced. It is clear.

With reference to the band diagram of FIG. 31, the operation and effect of improving the Ion / Iff ratio in the present embodiment will be described.
FIG. 31A is a band diagram in the case where the thickness of the source region and the channel region in the prior art are equal, and FIG. 31B shows the thickness of the source region in the present embodiment is the thickness of the channel region. It is a band figure in case it is thinner than this.
First, in general, the drain current density J is approximately equal to the following formula J = qnv where q is the elementary charge.
As described above, it is proportional to the electron injection amount n from the source region to the channel region and the average incident velocity v of electrons from the source region to the channel region.
Then, by making the thickness of the source region thinner than that of the channel region, the base subband of the source region rises and a barrier is raised as shown in FIG. For this reason, when the transistor is in the off state, the probability that electrons will get over the barrier is greatly reduced, and Ioff is greatly reduced. On the other hand, also for Ion, the electron flow amount n from the source region to the channel region decreases. However, since the electrons over the barrier have high energy, the average incident velocity v of the electrons is increased. Therefore, since these two actions cancel each other, as a result, the decrease in Ion is not as significant as the decrease in Ioff.
For this reason, it is considered that the Ion / Ioff ratio is improved.
Note that the ground subband of the source region rises because the energy E of the ground subband of the wave function of the electrons in the semiconductor confined by the insulator is, as shown by using (Equation 1). By being inversely proportional to the square of the semiconductor thickness (TSi).

  As described above, unlike the first embodiment, Ion / Ioff is maximum in a region where there is no separation (offset) between the gate electrode and the source region. This is because, in the case of this embodiment, Ioff has already been sufficiently suppressed by the increase of the base subband of the source region, and the channel resistance increase in the separated (offset) portion is reduced by reducing Ion rather than by reducing Ioff. It can be understood that it contributes greatly to

  As a modification of this embodiment, for the same reason as described in the first modification and the second modification in the first embodiment, the thickness (TSid) of the drain region 121 is the channel region. A configuration (TSid <TSic) that is thinner than the thickness (TSic) of 101 or a configuration that is thicker (TSic <TSid) may be employed.

(Third embodiment)
FIG. 32 is a perspective view showing an element structure of a field effect transistor included in a semiconductor device according to the third embodiment of the present invention and a sectional view perpendicular to the channel length. FIG. 32A is a perspective view showing the entire structure of the element structure of the field effect transistor according to the third embodiment, FIG. 32B is a sectional view of the drain region perpendicular to the channel length, and FIG. Is a cross-sectional view of the channel region, and FIG. 32D is a cross-sectional view of the source region. In the perspective view, the insulating films 103, 104, 115 and 210 in the cross-sectional view are omitted for simplification of the drawing.
Except that a buried insulating layer (insulating film substrate) 180 is formed on the p-type semiconductor substrate 100 and an element is formed on the SOI (Silicon on Insulator) layer, the same as in the first embodiment. Therefore, the description is omitted.
Since the field effect transistor according to the present embodiment has elements formed in the SOI layer, in addition to the operation and effect of the first embodiment, the junction leakage from the bottom of the source / drain and the junction capacitance are greatly reduced. Can be achieved. Therefore, low power consumption of the semiconductor device can be realized. In addition, since isolation between elements is completely performed by the buried insulating layer (insulating film substrate) 180, there is an advantage that it is not necessary to consider the element isolation withstand voltage and the manufacturing process can be simplified.

  In the present embodiment, the element of the first embodiment is formed on the SOI layer. However, the power consumption can be reduced by forming the element of the second embodiment on the SOI layer. In addition, the manufacturing process can be simplified.

(Fourth embodiment)
FIG. 33 is a perspective view showing an element structure of a field effect transistor included in a semiconductor device according to the fourth embodiment of the present invention and a sectional view perpendicular to the channel length. FIG. 33A is a perspective view showing the entire structure of the field effect transistor according to the fourth embodiment, FIG. 33B is a sectional view of the drain region perpendicular to the channel length, and FIG. Is a cross-sectional view of the channel region, and FIG. 33D is a cross-sectional view of the source region. In the perspective view, the insulating films 103, 104, and 115 in the cross-sectional view are omitted for simplification of the drawing.
Except for the so-called tri-gate structure having a third gate electrode 145 over the channel region 101 in addition to the gate electrodes 107 and 108 via a third gate insulating film 141, the same as in the first embodiment Therefore, the description is omitted.
Since the field effect transistor of this embodiment has a tri-gate structure, in addition to the operation and effect of the first embodiment, the dominance by the gate is increased, and punch-through between the source / drain regions is suppressed. The drain current is also improved.

  In the present embodiment, the first embodiment has a tri-gate structure, but punch-through suppression between the source / drain regions can also be achieved by using the tri-gate structure for the element of the second embodiment. In addition, the drain current can be improved.

(Fifth embodiment)
FIG. 34 is a perspective view showing an element structure of a field effect transistor included in a semiconductor device according to the fifth embodiment of the present invention and a sectional view perpendicular to the channel length. FIG. 34 (a) is a perspective view showing the entire structure of the element structure of the field effect transistor of the fifth embodiment, FIG. 34 (b) is a sectional view of the drain region perpendicular to the channel length, and FIG. 34 (c). Is a cross-sectional view of the channel region, and FIG. 34D is a cross-sectional view of the source region. In the perspective view, the insulating films 141, 142, and 115 in the cross-sectional view are omitted for simplification of the drawing.
The element structure is not the Fin type, but has a first gate electrode 145 on the channel region 101 via the first gate insulating film 141 and a second gate insulating film 142 below the channel region 101. Except for the so-called planar double gate structure having the second gate electrode 146, the description is omitted because it is the same as the first embodiment.
The field effect transistor of the present embodiment has a planar double gate structure, so that in addition to the operation and effect of the first embodiment, the channel region is formed by film deposition with respect to the Fin structure. There is an advantage that the device characteristics are easy to control and the device characteristics are more stable.

  In this embodiment, the first embodiment has a planar double gate structure. However, the device characteristics of the second embodiment can also be stabilized by using a planar double gate structure. Is possible.

(Sixth embodiment)
FIG. 35 is a perspective view showing an element structure of a field effect transistor included in a semiconductor device according to the sixth embodiment of the present invention and a cross-sectional view perpendicular to the channel length. FIG. 35A is a perspective view showing the entire structure of the element structure of the field effect transistor according to the sixth embodiment, FIG. 35B is a sectional view of the drain region perpendicular to the channel length, and FIG. Is a cross-sectional view of the channel region, and FIG. 35D is a cross-sectional view of the source region.
The element structure is not the Fin type, but has a first gate electrode 145 on the channel region 101 via the first gate insulating film 141 and a second gate insulating film 142 below the channel region 101. The second embodiment is the same as that of the first embodiment except that it has a second gate electrode 146 and is a planar double gate structure in which a gate voltage is independently applied to each gate electrode. Omitted.
The field effect transistor of this embodiment has a planar double gate structure to which a gate voltage is independently applied, so that the threshold of the transistor can be made variable in addition to the operation and effect of the first embodiment. Thus, there is an advantage that the degree of freedom in circuit design increases.

In the present embodiment, the first embodiment has a planar double gate structure in which a gate voltage can be applied independently. However, the device in the second embodiment can have a planar type in which a gate voltage can be applied independently. The double gate structure can also increase the degree of freedom in circuit design.
(Seventh embodiment)
FIG. 36 is a longitudinal sectional view in the direction perpendicular to the channel length showing the element structure of the field effect transistor included in the semiconductor device according to the seventh embodiment of the invention. Since the element structure is the same as that of the first embodiment except that the element structure is not a Fin type but a vertical transistor structure, the description is omitted.
Since the field effect transistor of this embodiment has a vertical transistor structure, in addition to the operations and effects of the first embodiment, a source / drain region, a channel region, and the like can be arranged in the vertical direction. There is an advantage that the degree of integration can be improved.

  In this embodiment, the first embodiment has a vertical transistor structure. However, the degree of integration can also be improved by making the element of the second embodiment a vertical transistor structure. It becomes possible.

  In addition, this invention is not limited to each embodiment mentioned above. Although an n-type channel field effect transistor has been described in the embodiment, the present invention can also be applied to a p-type channel field effect transistor. Although silicon is used as a semiconductor substrate material, it is not necessarily limited to silicon, but silicon germanium (SiGe), germanium (Ge), silicon carbide (SiC), gallium arsenide (GaAs), aluminum nitride (AlN), etc. It is possible to use. Further, the plane orientation of the substrate material is not necessarily limited to the (100) plane, and the (110) plane or the (111) plane can be appropriately selected. In addition, various modifications can be made without departing from the scope of the present invention.

FIG. 3 is a cross-sectional view in the channel length direction showing the element structure of the field effect transistor of the first embodiment. The perspective view which shows the element structure of the field effect transistor of 1st Embodiment, and sectional drawing of a perpendicular direction to channel length. The figure which shows the separation distance dependence of Ion / Ioff ratio of the field effect transistor of 1st Embodiment. The figure which compared the gate voltage (Vg) -drain current (Id) characteristic of 1st Embodiment and the field effect transistor of a prior art. The band figure explaining the effect | action and effect of 1st Embodiment. The figure which shows the separation distance dependence of Ion / Ioff ratio of the field effect transistor of 1st Embodiment. The figure which shows the separation distance dependence of Ion / Ioff ratio of the field effect transistor of 1st Embodiment. The figure which shows the separation distance dependence of Ion / Ioff ratio of the field effect transistor of 1st Embodiment. The figure which shows the separation distance dependence of Ion / Ioff ratio of the field effect transistor of 1st Embodiment. Sectional drawing of the channel length direction which shows the element structure of the field effect transistor of the modification of 1st Embodiment. The perspective view which shows the element structure of the field effect transistor of the modification of 1st Embodiment, and sectional drawing of a perpendicular direction to channel length. FIG. 3 is a plan view showing the method for manufacturing the semiconductor device of the first embodiment. Sectional drawing along the AA line of FIG. Sectional drawing along the BB line of FIG. FIG. 13 is a plan view illustrating the method for manufacturing the semiconductor device according to the first embodiment following FIG. 12; Sectional drawing along CC line of FIG. FIG. 16 is a cross-sectional view taken along line DD of FIG. FIG. 16 is a plan view illustrating the method for manufacturing the semiconductor device according to the first embodiment following FIG. 15; FIG. 19 is a cross-sectional view taken along line EE in FIG. 18. Sectional drawing along the FF line of FIG. FIG. 19 is a plan view illustrating the method for manufacturing the semiconductor device according to the first embodiment following FIG. 18; Sectional drawing along the GG line of FIG. FIG. 22 is a sectional view taken along line HH in FIG. 21. FIG. 22 is a plan view illustrating the method for manufacturing the semiconductor device according to the first embodiment following FIG. 21; FIG. 25 is a cross-sectional view taken along the line II of FIG. 24. FIG. 25 is a sectional view taken along line JJ in FIG. 24. Sectional drawing of the channel length direction which shows the element structure of the field effect transistor of 2nd Embodiment. The perspective view which shows the element structure of the field effect transistor of 2nd Embodiment, and sectional drawing of a perpendicular direction to channel length. The figure which shows the separation distance dependence of Ion / Ioff ratio of the field effect transistor of 2nd Embodiment. The figure which compared the gate voltage (Vg) -drain current (Id) characteristic of 2nd Embodiment and the field effect transistor of a prior art. The band figure explaining the effect | action and effect of 2nd Embodiment. The perspective view which shows the element structure of the field effect transistor of 3rd Embodiment, and sectional drawing of a perpendicular direction to channel length. The perspective view which shows the element structure of the field effect transistor of 4th Embodiment, and sectional drawing of a perpendicular direction to channel length. The perspective view which shows the element structure of the field effect transistor of 5th Embodiment, and sectional drawing of a perpendicular direction to channel length. The perspective view which shows the element structure of the field effect transistor of 6th Embodiment, and sectional drawing of a perpendicular direction to channel length. The longitudinal cross-sectional view of a perpendicular | vertical direction to the channel length which shows the element structure of the field effect transistor of 7th Embodiment. Sectional drawing of the channel length direction which shows the element structure of the field effect transistor of a prior art. The perspective view which shows the element structure of the field effect transistor of a prior art, and sectional drawing of a perpendicular direction to channel length.

Explanation of symbols

100 silicon substrate 101 channel region 103 first gate insulating film 104 second gate insulating film 107 first gate electrode 108 second gate electrode 109 gate wiring 111 source region 115 insulating film 121 drain region 131 contact on the source region side Electrode 133 Contact electrode on the drain region side

Claims (7)

A semiconductor device including a field effect transistor comprising a channel region, a first gate electrode, a second gate electrode, a source region, and a drain region,
The first gate electrode and the second gate electrode are respectively formed through a first gate insulating film and a second gate insulating film so as to face both sides of the channel region,
The source region and the drain region are formed on both sides of the first gate electrode and the second gate electrode with the channel region interposed therebetween,
A thickness (TSis) of the source region in a direction perpendicular to an interface between the first gate insulating film and the channel region is larger than a thickness (TSic) of the channel region in the direction; and
The semiconductor device, wherein the source region, the first gate electrode, and the second gate electrode are separated in a gate length direction.   2. The semiconductor device according to claim 1, wherein the separation distance is not less than 1 nm and not more than 3.5 nm.   2. The thickness (TSid) of the drain region in a direction perpendicular to the interface between the first gate insulating film and the channel region is equal to or less than the thickness (TSic) of the channel region. The semiconductor device described. The semiconductor device according to claim 1, wherein an impurity concentration of the channel region is 1E19 atoms / cm ³ or more and 1E20 atoms / cm ³ or less. A semiconductor device including a field effect transistor comprising a channel region, a first gate electrode, a second gate electrode, a source region, and a drain region,
The first gate electrode and the second gate electrode are respectively formed through a first gate insulating film and a second gate insulating film so as to face both sides of the channel region,
The source region and the drain region are formed on both sides of the first gate electrode and the second gate electrode with the channel region interposed therebetween,
A thickness (TSis) of the source region in a direction perpendicular to an interface between the first gate insulating film and the channel region is smaller than a thickness (TSic) of the channel region in the direction. Semiconductor device.   6. The semiconductor device according to claim 5, wherein the source region, the first gate electrode, and the second gate electrode are not separated in the gate length direction. 6. The semiconductor device according to claim 1, wherein the field effect transistor is formed on an insulating film substrate.

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