JP2008192819A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device comprising a field-effect transistor capable of improving a driving current by having a structure for suppressing pinch-off. <P>SOLUTION: The semiconductor device comprises the field-effect transistor equipped with a source region 111 and a drain region 121, a channel region 101 existing between the source region 111 and the drain region 121 while having opposed principal surfaces and a pair of gate electrodes 107, 108 provided on the principal surfaces through gate insulating films 103, 104 while a space between the opposed principal surfaces is larger in the drain region 121 side than that in the source region 111 side. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device including a field effect transistor, and more particularly to a semiconductor device including a so-called Fin-type channel transistor.

  In order to improve the performance of a semiconductor integrated circuit, it is essential to improve the performance of a field effect transistor that is a component thereof. Up to now, improvement of device performance has been promoted by miniaturization of the device, but the limit is pointed out in the future. In particular, the suppression of the short channel effect is considered a serious issue. According to the International Semiconductor Roadmap (ITRS Roadmap), after the 45 nm generation, multiple new breakthroughs are required to solve these problems. ing.

In such a situation, since resistance to the short channel effect is high, an FD (Fully-Depleted) device in which the channel region is completely depleted is expected as a next-generation basic element structure. Of particular interest are transistors using thin film SOI (Silicon On Insulator) substrates and so-called Fin-type channel transistors (hereinafter also referred to as FinFETs).
A Fin-type channel transistor is a kind of multi-gate transistor having a plate-like channel rising in a direction perpendicular to a substrate. And it is called a Fin-type channel transistor because of the shape of the channel region. This Fin-type channel transistor has a very strong gate dominance, and thus can suppress a drop in the barrier at the source end due to the drain electric field (Drain Induced Barrier Lowering, hereinafter also referred to as DIBL), and is characterized by a strong short channel effect. (For example, refer nonpatent literature 1).

  As described above, the Fin-type channel transistor has a very promising structure for suppressing the short channel effect, but in order to increase the gate control power, the gate interval is very narrow, and the drive current (drain current) is reduced. There is a problem. This problem can be solved by widening the source end while keeping the gate distance between the drain ends narrow, thereby reducing the parasitic resistance of the source region while suppressing the penetration of the drain electric field and securing the amount of drive current. It is possible (Patent Document 1).

JP 2003-298063 A Y. K. Choi et al. “FinFET Process Definitions for Improved Mobility and Gate Work Function Engineering”, Technical Digest of International Electron Meeting.

  However, there are other factors that cause the drive current to decrease in the Fin-type channel transistor. That is, when scaling the parameters of the field effect transistor, since the power supply voltage cannot be scaled as it is, a large drain electric field is applied to the channel in the short channel device. In the Fin-type channel transistor, since the gate dominating force is strong, the drain electric field hardly penetrates into the channel and concentrates on the drain end of the channel. This electric field causes pinch-off and the drive current immediately reaches the saturation current, so that the drive current is suppressed.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device including a field effect transistor capable of improving drive current by having a structure that suppresses pinch-off. There is to do.

A semiconductor device of one embodiment of the present invention includes:
A source region and a drain region;
A channel region present between the source region and the drain region and having an opposing main surface;
Comprising a pair of gate electrodes provided on the main surface via a gate insulating film;
The field effect transistor is characterized in that a distance between the opposing main surfaces is larger on the drain region side than on the source region side.

  Here, it is desirable that an interval between the opposing main surfaces gradually increases from the source region side to the drain region side.

  Here, a region surrounded by the opposing main surface, a plane including the source region side ends of the pair of gate electrodes, and a plane including the drain region side ends of the pair of gate electrodes An isosceles trapezoidal columnar shape, and an angle θ between a height direction of the isosceles trapezoid and a side included in the principal surface of the isosceles trapezoid has a relationship of 0.03 <sin θ <0.27. It is desirable to be satisfied.

  Here, it is preferable that the distance between the opposing main surfaces on the source region side is not more than half of the gate length of the field effect transistor.

  Here, it is desirable that the distance between the opposing main surfaces on the source region side is 10 nm or less.

  Here, it is preferable that the end portion of the gate electrode is located in the center direction of the channel region, rather than the end portion of the region where the interval between the opposing main surfaces changes.

  Here, it is preferable that the end portion of the gate electrode is in an opposite direction to the center of the channel region, rather than the end portion of the region where the interval between the opposing main surfaces changes.

  Here, it is preferable that the gate insulating film and the gate electrode extend to a plane perpendicular to the main surface, and the gate insulating film and the gate electrode exist on at least three surfaces of the channel region.

  The gate insulating film preferably has a dielectric constant higher than that of the silicon oxide film.

  According to the present invention, it is possible to provide a semiconductor device including a field effect transistor capable of improving a drive current by having a structure that suppresses pinch-off.

The inventors of the present invention can obtain a larger driving current compared to the prior art by widening the channel region interval (thickness) on the drain region side of the FinFET than the channel region interval (thickness) on the source region side. I found. This is because the gate electric field has a component opposite to the drain electric field, so that a rapid potential drop due to the drain electric field is suppressed and the pinch-off voltage is increased.
The present invention is characterized in that, in a field effect transistor (FinFET) having a Fin structure included in a semiconductor device, the channel region interval on the drain region side is larger than the channel region interval on the source region side.
Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a perspective view of an n-type field effect transistor included in the semiconductor device according to the first embodiment of the present invention. As shown in FIG. 1, a channel region 101 formed in a wedge shape is formed on a silicon substrate 100. This channel region 101 is formed of a semiconductor such as silicon. In the channel region 101, carriers of the field effect transistor move.

The channel region 101 includes a pair of channel surfaces that are two opposing main surfaces. On these channel surfaces, a pair of gate electrodes 107 and 108 are provided on respective main surfaces via a gate insulating film (not shown) made of, for example, a silicon oxide film.
A source region 111 and a drain region 121 are formed apart from each other so as to sandwich the channel region 101. The source region 111 and the drain region 121 are provided at positions that sandwich the channel region in the direction in which the channel region 101 extends. That is, a channel region 101 having a channel surface that is a main surface facing each other between the source region 111 and the drain region 121 is formed. The source region 111 and the drain region 121 are formed of a semiconductor such as silicon and are doped with, for example, an n-type impurity such as arsenic (As) or phosphorus (P).

  The channel region 101 is a wall-like convex portion formed so as to protrude with respect to the silicon substrate 100, and its shape is such that the interval (thickness) on the drain region 121 side is larger than the interval (thickness) on the source region 111 side. Also has a wide wedge shape. Since the thickness of the gate insulating film is substantially constant, the distance between the pair of gate electrodes 107 and 108 is larger on the drain region 121 side than on the source region 111 side. Also, the distance between the opposing main surfaces (channel region thickness). The size gradually increases from the source region 111 side to the drain region 121 side.

  FIG. 2 is a cross-sectional view of an n-type FinFET (hereinafter referred to as “FinFET of this embodiment”) included in the semiconductor device of this embodiment in a direction parallel to the silicon substrate 100. As described above, the source region 111 and the drain region 121 are formed apart from each other so as to sandwich the channel region 101, and an interval (channel) between the channel surfaces (interfaces between the gate insulating films 103 and 104 and the channel region 101) is formed. The thickness of the region 101) is larger on the drain region 121 side than on the source region 111 side. That is, the distance (channel region thickness) W2 between the channel surfaces on the drain region 121 side of the channel region 101 is larger than the interval (channel region thickness) W1 between the channel surfaces on the source region 111 side. . Further, the gate electrodes 107 and 108 are formed on the channel surfaces, which are the main surfaces facing each other in the channel region 101, via the gate insulating films 103 and 104, respectively. Then, the shape of the channel region 101, that is, the opposing channel surface, the plane including the end portion on the source region 111 side of each of the gate electrodes 107 and 108, and the end on the drain region 121 side of each of the gate electrodes 107 and 108 The shape of the region surrounded by the plane including the part has an isosceles trapezoidal columnar shape. The shape of the channel region 101 is an isosceles trapezoid as shown in FIG. 2 when viewed in a cross section parallel to the silicon substrate 100.

  In FIG. 2, the cross-sections of the two opposing channel surfaces are both represented by straight lines. However, in practice, even if there is some unevenness on both or one of the channel surfaces, it is possible to obtain the operation and effect of this embodiment described later.

  Further, a contact electrode 131 on the source region side and a contact electrode 132 on the drain region side that are respectively connected to the upper layer wiring are formed so as to be electrically connected to the source region 111 and the drain region 121.

Specific dimensions of the FinFET of the present embodiment include, for example, a gate length Lg (channel direction component of the gate electrode, see FIG. 2) of about 20 nm, and an interval between the channel surfaces on the source region 111 side (channel region thickness). ) W1 is about 10 nm, and the distance between the channel surfaces on the drain region 121 side (channel region thickness) W2 is about 20 nm.
Generally, the DIBL suppression effect by FinFET is obtained when the interval W1 on the source region 111 side of the channel surface is less than or equal to half of the gate length Lg, and this relationship is also satisfied in this embodiment. It is desirable to do.
Even in the case where the above relationship is satisfied, since the DIBL suppression effect is further improved in the region where the distance W1 on the source region 111 side of the channel surface is 10 nm or less, the distance on the source region 111 side of the channel surface is 10 nm. The following is more desirable.

FIG. 3 shows the drain voltage-drain current characteristics obtained by simulation of the FinFET of this embodiment. The drain of the FinFET (hereinafter referred to as a conventional FinFET) in which the channel region has a constant thickness from the source region to the drain region. It is a figure shown in comparison with a voltage-drain current characteristic.
In the simulation, the distance between the channel surfaces on the source region 111 side (channel region thickness) W1 = 10 nm, the distance between the channel surfaces on the drain region 121 side (channel region thickness) W2 = 20 nm, and the cross section of the channel region. The shape was an isosceles trapezoid, the gate length Lg was 22 nm, the impurity concentration of the channel region was Nsub = 1E19 atoms / cm ³ , Vg = 1.0 V, and Ioff = 0.1 μA / μm.
As for the conventional FinFET, the channel region has the same thickness as the source region side of the FinFET of the present embodiment (hereinafter referred to as a thin conventional FinFET) and the same thickness as the drain region side. Two types of devices (hereinafter referred to as thick conventional FinFETs) are shown by simulation.

As is clear from FIG. 3, in the FinFET of the present embodiment (indicated as the present invention in FIG. 3), current saturation does not occur up to a higher drain voltage than in the conventional FinFET. Therefore, a large driving current (drain current) can be obtained as compared with the conventional FinFET.
This is because, as will be described in detail later, by increasing the thickness of the channel region in the direction of the drain, a component of the gate electric field facing the drain electric field is generated and the drain electric field is weakened.

  FIG. 4 is a diagram showing gate voltage-drain current characteristics of the FinFET of the present embodiment and the conventional FinFET. The value is obtained by simulation under the same conditions as in FIG. 3 except that the gate voltage Vg is changed while fixing Vd = 0.8V.

As is clear from FIG. 4, in the FinFET of the present embodiment (indicated as the present invention in FIG. 4), the drain current in the subthreshold region (region where the gate voltage is equal to or lower than the threshold value) is larger than that of the thick conventional FinFET. The characteristics are improved. And the good drain current characteristic close | similar to thin conventional FinFET is shown. This is an effect of suppressing DIBL at the source end by reducing the channel region thickness on the source region side. For this reason, it can be seen that the FinFET of this embodiment has a short channel effect resistance comparable to that of a thin conventional FinFET.
Further, in the saturation region where the gate voltage is high, the FinFET of this embodiment can obtain a larger driving current (drain current) than the thin conventional FinFET and the thick conventional FinFET as in the case shown in FIG.
Thus, it can be seen that the FinFET of this embodiment has an advantage over the conventional FinFET from the viewpoint of the short channel effect tolerance and the drain current value.

The effects of the FinFET of the present embodiment as described above will be examined in more detail below.
First, in the channel region of the isosceles trapezoidal shape shown in FIG. 2, the height direction (gate length direction or channel direction) of the isosceles trapezoid and the sides included in the principal surface (channel surface) of the isosceles trapezoid The angle between them is defined as θ as shown in FIG.
FIG. 5 is an explanatory diagram in which the gate electric field of the present embodiment is decomposed into components. As shown in FIG. 5, when the gate electric field generated in the channel by the gate voltage is Eg, the drain direction component is Eg · sin θ. If the drain electric field generated in the channel due to the drain voltage is Ed, the effective electric field in the drain direction inside the channel of the FinFET of the present embodiment is Ed−Eg · sin θ.
In general, when the drain voltage is small, Ed is sufficiently smaller than Eg inside the channel, and the charge sheet approximation is established. However, pinch-off occurs when the drain voltage reaches a certain level. At the pinch-off point, Ed≈Eg, and charge sheet approximation breaks down.

  In the present embodiment, as described above, the effective drain direction electric field inside the channel is Ed−Eg · sin θ. However, at a pinch-off point where Ed≈Eg, when sin θ is about several percent, Eg The sin θ becomes large enough to affect the electric field in the drain direction. On the other hand, if sin θ becomes too large due to an increase in θ, the gate dominance at the edge of the source region is weakened, so that the short channel effect resistance is reduced and the off current (Ioff: drain current of Vg = 0 V) increases. . Then, the ratio (Ion / Ioff ratio) of the on-current (Ion: Vg, Vd = drain current in the case of the operating voltage) to Ioff decreases. Therefore, the switching characteristics of the FinFET are deteriorated.

FIG. 6 is a diagram showing a result of simulating a change in on-current (Ion) when the off-current (Ioff) is made constant with respect to sin θ. The simulation was performed under the same conditions as in FIG. 3 except that the gap (channel region thickness) W2 between the channel surfaces (channel region thickness) on the drain region 121 side was used as a variable. The on-current (Ion) for the conventional FinFET is shown as 1.
As is apparent from FIG. 6, the on-current (Ion) increases in the range of 0 <sin θ <0.3 compared to the conventional FinFET, and in particular, in the range of 0.03 <sin θ <0.27, 10% The above increase in the on-current (Ion) is seen and good. As described above, in the range of 0.03 <sin θ, the term of Eg · sin θ has an influence on the effective drain direction electric field inside the channel, but the range of 0.3 ≦ sin θ. Then, the increase in the off-state current becomes remarkable, and the on-state current is substantially reduced. Therefore, the range of sin θ is preferably 0 <sin θ <0.3, and more preferably 0.03 <sin θ <0.27.

Further, in the FinFET of this embodiment, since the channel surface is inclined with respect to the conventional FinFET, there is a concern that the bulk mobility of the carrier is deteriorated and the action / effect on the conventional type is offset. There is.
It is considered that the bulk mobility deteriorates to about 1/3 at maximum due to the change of the plane orientation. Therefore, assuming that the bulk mobility deteriorates to 1/3, a simulation was performed on how the drain current changes as compared with the case where the mobility deterioration is not considered. The result is shown in FIG. 7 as the gate voltage dependence of the gate voltage-drain current ratio (ratio of drain current when mobility is reduced to 1/3 and drain current when mobility degradation is not considered). In this simulation, the simulation was performed under the same conditions as the FinFET of the present embodiment in the case of FIG. 3 except that the bulk mobility was changed. As is apparent from FIG. 7, even when the deterioration is maximized, the drain current ratio does not fall below 85%. In FIG. 3, the saturation current of the thin conventional FinFET is about 81% of the saturation current of the FinFET of the present embodiment (the present invention in FIG. 3). Therefore, the FinFET of this embodiment can be said to have a sufficient advantage over the conventional FinFET even when the bulk mobility of carriers due to changes in the plane orientation is taken into consideration.

  Furthermore, according to the present embodiment, the occurrence of hot carriers is suppressed by suppressing the pinch-off. Therefore, the function and effect of suppressing the characteristic deterioration due to the occurrence of hot carriers in the FinFET can also be obtained.

  Next, an example of a method for manufacturing a semiconductor device including the field effect transistor of this embodiment will be described with reference to FIGS.

  First, as shown in FIG. 8 which is a plan view of FIG. 8, FIG. 9 which is a cross-sectional view in the AA direction of FIG. 8, and FIG. 10 which is a cross-sectional view in the BB direction of FIG. After depositing an insulating film 210 serving as a mask material such as a silicon nitride film of about 50 to 100 nm on the type silicon substrate 100, the insulating film 210 and silicon are etched by lithography techniques and etching techniques such as reactive ion etching (hereinafter also referred to as RIE). The substrate 100 is etched to form a trench that becomes an element region 201 and an element isolation region. At this time, a mask pattern is used in which the channel region on the side to be the drain region later is thicker than the channel region on the side to be the source region later, and the channel region has an isosceles trapezoidal shape. Thereafter, introduction of p-type impurities into the channel region for threshold adjustment can be performed using, for example, an oblique ion implantation technique.

Next, as shown in FIG. 11 which is a plan view of FIG. 11, FIG. 12 which is a cross-sectional view in the CC direction of FIG. 11, and FIG. 13 which is a cross-sectional view in the DD direction of FIG. An insulating film 215 such as a silicon oxide film is deposited, and the insulating film 215 is flattened to the upper surface of the insulating film 210 by a chemical mechanical polishing method (hereinafter also referred to as CMP) to form an element isolation region. . At this time, a p-type impurity may be introduced under the element isolation region by ion implantation or the like in order to improve the element isolation breakdown voltage and reduce the leakage current of the parasitic transistor.
Thereafter, a part of the insulating film 215 is removed, and a groove 205 is formed so that the side surface of the element region 201 is exposed.

  Next, as shown in FIG. 14 which is a plan view of FIG. 14, FIG. 15 which is a cross-sectional view in the EE direction of FIG. 14 and FIG. 16 which is a cross-sectional view in the FF direction of FIG. Gate insulating films 103 and 104 are formed. The gate insulating films 103 and 104 may be, for example, a silicon oxide film formed by a thermal oxidation method, or a high dielectric film formed by a CVD (Chemical Vapor Deposition) method or an ALD (Atomic Layer Deposition) method. It doesn't matter.

  Next, a conductive material to be the gate electrodes 107 and 108 is deposited on the gate insulating films 103 and 104 to fill the trenches 205. Thereafter, the buried conductive material and the gate insulating film are planarized by CMP until the upper surface of the insulating film 210 is exposed. Here, the conductive material to be the gate electrodes 107 and 108 is made of, for example, a material such as (doped) polysilicon, silicide, or metal.

Next, as shown in FIG. 17 which is a plan view of FIG. 17, FIG. 18 which is a sectional view in the GG direction in FIG. 17, and FIG. 19 which is a sectional view in the HH direction in FIG. Is deposited, and a gate wiring 109 is formed so as to physically and electrically connect the first gate electrode 107 and the second gate electrode 108 by lithography and RIE. Here, the gate wiring 109 is made of, for example, a material such as (doped) polysilicon, silicide, or metal.
At this time, for example, sidewall insulating films made of a silicon nitride film may be formed on both sides of the gate wiring 109.
Then, n-type impurities are introduced into the source region 111 and the drain region 121 by ion implantation or the like using the gate wiring 109 as a mask.

Next, as shown in a plan view of FIG. 20, FIG. 21 which is a cross-sectional view in the II direction in FIG. 20, and FIG. 22 which is a cross-sectional view in the JJ direction in FIG. After that, contact holes are opened by lithography and RIE so that the side surfaces of the source region 111 and the drain region 121 are exposed. The contact hole is filled with a conductive material, whereby the contact electrode 131 on the source region side and the contact electrode 133 on the drain side are formed.
As described above, the semiconductor device of the present embodiment is formed.

Note that the structure and shape of the source / drain regions and the structure and shape of the contact electrode do not directly affect the operation and effect of the present embodiment. Therefore, the junction of the source / drain regions may be a pn junction as described above or a Schottky junction. The source / drain regions may have a structure having an extension diffusion layer, or may have a structure having a metal silicide such as NiSi or CoSi ₂ on the diffusion.

Further, the source / drain regions 111 and 121 are not necessarily formed horizontally on the silicon substrate 100 as shown in FIG.
For example, as shown in a modification of the present embodiment in FIG. 23, a structure in which a part of the source / drain regions 111 and 121 is recessed, a so-called recess structure may be used.
As described above, the recess structure facilitates uniform introduction of source / drain impurities into the source / drain regions in the depth direction, and can stabilize and improve FinFET characteristics.

In addition, the channel region is not necessarily formed on the bulk silicon substrate as shown in FIG. 22, but is formed on the SOI (Silicon On Insulator) layer on the insulating layer 150 as in the modification of the present embodiment shown in FIG. It may be formed.
As described above, by forming the semiconductor device of the present embodiment on the SOI substrate, it is possible to suppress the leakage current due to the parasitic element formed in the bulk portion under the base of the FinFET. Therefore, higher performance of the semiconductor device can be achieved.

  In the present embodiment, as shown in FIG. 25, the distance between the opposing main surfaces, that is, the thickness of the channel region is changed so as to be larger on the drain region side than on the source region side. Here, the end portion (broken line in the figure) of the region where the interval (thickness) changes does not necessarily coincide with the end portions of the gate electrodes 107 and 108.

For example, as shown in the modification of the present embodiment in FIG. 26, the end portions of the gate electrodes 107 and 108 are more than the end portions (broken lines in the drawing) of the regions where the distance between the opposing main surfaces changes. It may be in the center of the channel region. That is, the gate length is shorter than the length in the channel length direction of the region where the interval between the main surfaces changes, and the gate electrodes 107 and 108 exist inside the region where the interval between the main surfaces changes. It doesn't matter.
Further, for example, as shown in the modification of the present embodiment in FIG. 27, the end portions of the gate electrodes 107 and 108 are from the end portions (broken lines in the drawing) of the region where the distance between the opposing main surfaces changes. However, the direction may be opposite to the center of the channel region. In other words, the gate length is longer than the length in the channel length direction of the region where the interval between the main surfaces changes, and the gate electrodes 107 and 108 exist outside the region where the interval between the main surfaces changes. It doesn't matter.
As described above, the end portions of the gate electrodes 107 and 108 and the end portions (broken lines in the figure) where the distance between the main surfaces facing each other is changed in design, and a certain alignment margin is obtained. Even if a misalignment occurs between the gate electrode and the channel region shape in the manufacturing process, it is possible to suppress a rapid change in the characteristic variation of the FinFET. Because, even if misalignment occurs, the relative relationship between the gate electrode end and the channel region shape is kept constant to some extent, so that the change in effective drain direction electric field inside the channel due to misalignment is suppressed, This is because a rapid change in the characteristic variation of the FinFET can be suppressed.

(Second Embodiment)
FIG. 28 is a sectional view of an n-type FinFET, which is an n-type field effect transistor included in the semiconductor device according to the second embodiment of the present invention, in a direction parallel to the silicon substrate.
The n-type FinFET of the present embodiment has a structure in which the opposing main surface of the channel region 101, that is, the channel surface is substantially parallel on the source region 111 side and expands toward the drain region 121 side. Since other than that is the same as the first embodiment, the description is omitted.

  Such a shape of the channel region can be easily formed by changing the shape of the mask pattern when the element region is formed by etching the silicon substrate during the manufacturing method described in the first embodiment. Is possible.

  According to the present embodiment, since the channel surface spreads outward in the drain direction, the drain electric field is weakened by the gate electric field and pinch-off is suppressed as in the first embodiment. In addition, since the channel surface is substantially parallel on the source region side, the dominant power of the gate electric field is increased as compared with the first embodiment, and DIBL is more effectively suppressed. You can get the action and effect.

(Third embodiment)
FIG. 29 is a cross-sectional view in the direction perpendicular to the silicon substrate and the channel length direction of the channel region of an n-type FinFET that is an n-type field effect transistor included in the semiconductor device of the third embodiment of the present invention. is there.
In the n-type FinFET according to the present embodiment, as shown in FIG. 29, the gate insulating films 103 and 104 and the gate electrodes 107 and 108 extend to the opposing main surface of the channel region 101, that is, a surface perpendicular to the channel surface. The description is omitted because it is the same as that of the first embodiment except that the gate insulating film and the gate electrode exist on at least three surfaces of the channel region. Thus, in the FinFET, a structure in which the gate electrode is provided on the side surface and the upper surface of the channel region via the gate insulating film is referred to as a TriGate structure.

  Such a TriGate structure can be formed by previously removing the mask material on the upper surface of the channel region before forming the gate insulating film in the manufacturing method described in the first embodiment.

  According to the present embodiment, in addition to the operation and effect of the first embodiment, the gate dominance is increased by the gate electric field from the upper surface, so that the operation and effect of further suppressing the short channel effect is obtained. It becomes possible.

(Fourth embodiment)
FIG. 30 is a cross-sectional view of a channel region of an n-type FinFET, which is an n-type field effect transistor included in a semiconductor device according to the fourth embodiment of the present invention, in a direction perpendicular to the silicon substrate and the channel length direction. is there.
In the n-type FinFET of the present embodiment, as shown in FIG. 30, the gate insulating films 103 and 104 and the gate electrodes 107 and 108 extend to the opposing main surface of the channel region 101, that is, the surface perpendicular to the channel surface. The base of the channel region on the substrate side is constricted, and the gate insulating films 103 and 104 and the gate electrodes 107 and 108 extend to the constricted region so as to surround the channel region. Since it is the same as that of the first embodiment except that the film and the gate electrode exist, the description is omitted. Thus, in the FinFET, a structure in which the gate electrode is provided on the side surface, the upper surface, and the constricted lower surface of the channel region via the gate insulating film is referred to as an Ω-Gate structure.

  Such an Ω-Gate structure has a strong anisotropy in the first step in the manufacturing method described in the first embodiment, for example, when an element region is formed by etching a silicon substrate. It can be formed by switching under conditions that are strongly isotropic in the second stage.

  According to the present embodiment, in addition to the operation and effect of the first embodiment, the gate dominance is increased by the gate electric field from all directions of the side surface, the upper surface, and the lower surface, so that the suppressive power against the short channel effect is remarkably increased. It is possible to obtain the effect of improving.

  Here, the both side surfaces of the channel region are two opposing main surfaces. Furthermore, it is possible to adopt a structure in which the upper and lower surfaces of the channel region are newly formed as two opposing main surfaces, and the main surfaces also expand toward the drain region. According to this structure, the suppressing power against the further short channel effect is improved.

(Fifth embodiment)
FIG. 31 shows a channel region of an n-type FinFET, which is an n-type field effect transistor included in a semiconductor device according to the fifth embodiment of the present invention, perpendicular to the silicon substrate and parallel to the channel length direction. FIG.
In the n-type FinFET of this embodiment, as shown in FIG. 31, the height of the channel region 101 is higher on the drain region 121 side than on the source region 111 side, and the third embodiment Similar to the embodiment, except for the TriGate structure in which the gate insulating film 103 and the gate wiring 109 connected to the gate electrode exist also on the upper surface of the channel region 101, the description is omitted because it is the same as the first embodiment.

  In the manufacturing method described in the first embodiment, the structure in which the upper surface of the channel region is inclined is, for example, a region in which the channel region is previously formed before etching the silicon substrate to form the element region. It can be formed by combining the LOCal Oxidation of Silicon) method and oxide film peeling to provide an inclination on the wafer surface.

  According to the present embodiment, since the upper surface of the channel region also widens at an angle θ toward the drain side, the drain electric field is further weakened by the gate electric field from the upper surface as compared with the first embodiment. In addition, pinch-off is further suppressed. Therefore, in addition to the operation and effect of the first embodiment, the operation and effect of increasing the drive current more effectively can be obtained.

(Sixth embodiment)
The n-type field effect transistor included in the semiconductor device of the sixth embodiment of the present invention is the same as the first embodiment except that the dielectric constant of the gate insulating film is higher than the dielectric constant of the silicon oxide film. Therefore, the description is omitted.

In general, a high dielectric film is suitable for reducing the effective film thickness (equivalent silicon oxide film thickness) of a gate insulating film, but there is a tendency that performance degradation due to hot carriers is more severe than that of a silicon oxide film.
Therefore, according to the present embodiment, in addition to the operations and effects of the first embodiment, even in a FinFET having a high dielectric film as a gate insulating film, hot carrier deterioration of the high dielectric film is suppressed. Therefore, the effect | action and effect of implement | achieving high hot carrier tolerance are acquired.

In addition, this invention is not limited to each embodiment mentioned above. Although an n-type channel field effect transistor has been described in the embodiment, the present invention can also be applied to a p-type channel field effect transistor.
Although silicon is used as a semiconductor substrate material, it is not necessarily limited to silicon, but silicon germanium (SiGe), germanium (Ge), silicon carbide (SiC), gallium arsenide (GaAs), aluminum nitride (AlN), etc. It is possible to use.
Further, the plane orientation of the substrate material is not necessarily limited to the (100) plane, and the (110) plane or the (111) plane can be appropriately selected. In addition, various modifications can be made without departing from the scope of the present invention.

1 is a perspective view of an n-type field effect transistor included in a semiconductor device according to a first embodiment. 1 is a cross-sectional view of an n-type FinFET (hereinafter referred to as a FinFET of this embodiment) included in a semiconductor device of a first embodiment in a direction parallel to a silicon substrate 100. FIG. The drain voltage-drain current characteristic obtained by the simulation of the FinFET of the first embodiment is the same as the drain voltage of a FinFET whose channel region has a constant thickness from the source region to the drain region (hereinafter referred to as a conventional FinFET)- The figure shown in comparison with drain current characteristics. The figure which shows the gate voltage-drain current characteristic of FinFET of 1st Embodiment, and conventional FinFET. Explanatory drawing which decomposed | disassembled the gate electric field of 1st Embodiment into components. The figure which shows the result of having simulated the change of ON current (Ion) when OFF current (Ioff) was arrange | equalized uniformly with respect to sin (theta) of 1st Embodiment. The figure which shows gate voltage dependence of the gate voltage-drain current ratio (ratio of the drain current when mobility is set to 1/3, and drain current when mobility degradation is not considered) of 1st Embodiment. FIG. 3 is a plan view showing the method for manufacturing the semiconductor device of the first embodiment. Sectional drawing along the AA line of FIG. Sectional drawing along the BB line of FIG. FIG. 9 is a plan view illustrating the method for manufacturing the semiconductor device according to the first embodiment following FIG. 8; Sectional drawing along CC line of FIG. Sectional drawing along the DD line | wire of FIG. FIG. 12 is a plan view illustrating the method for manufacturing the semiconductor device according to the first embodiment following FIG. 11; Sectional drawing along the EE line of FIG. Sectional drawing along the FF line of FIG. FIG. 15 is a plan view illustrating the method for manufacturing the semiconductor device according to the first embodiment following FIG. 14; Sectional drawing along the GG line of FIG. FIG. 18 is a cross-sectional view taken along line HH in FIG. 17. FIG. 18 is a plan view illustrating the method for manufacturing the semiconductor device according to the first embodiment following FIG. 17; Sectional drawing along the II line | wire of FIG. Sectional drawing along the JJ line | wire of FIG. The figure which shows the modification of 1st Embodiment. The figure which shows the modification of 1st Embodiment. The figure which shows 1st Embodiment. The figure which shows the modification of 1st Embodiment. The figure which shows the modification of 1st Embodiment. Sectional drawing of the direction parallel to a silicon substrate of n-type FinFET which is an n-type field effect transistor contained in the semiconductor device of 2nd Embodiment. Sectional drawing of the direction perpendicular | vertical with respect to a silicon substrate and a channel length direction of the channel region of n-type FinFET which is an n-type field effect transistor contained in the semiconductor device of 3rd Embodiment. Sectional drawing of the direction perpendicular | vertical with respect to a silicon substrate and a channel length direction of the channel region of n-type FinFET which is an n-type field effect transistor contained in the semiconductor device of 4th Embodiment. Sectional drawing of the channel area | region of n-type FinFET which is an n-type field effect transistor contained in 5th Embodiment semiconductor device of a direction perpendicular | vertical to a silicon substrate and parallel to a channel length direction.

Explanation of symbols

100 silicon substrate 101 channel region 103 first gate insulating film 104 second gate insulating film 107 first gate electrode 108 second gate electrode 109 gate wiring 111 source region 115 insulating film 121 drain region 131 contact on the source region side Electrode 133 Contact electrode on the drain region side

Claims (9)

A source region and a drain region;
A channel region present between the source region and the drain region and having an opposing main surface;
Comprising a pair of gate electrodes provided on the main surface via a gate insulating film;
A semiconductor device comprising a field effect transistor in which a distance between the opposing main surfaces is larger on the drain region side than on the source region side.   The semiconductor device according to claim 1, wherein a distance between the opposing main surfaces gradually increases from the source region side to the drain region side.   A region surrounded by the opposing main surface, a plane including the source region side ends of the pair of gate electrodes, and a plane including the drain region side ends of the pair of gate electrodes is an equal leg It has a trapezoidal columnar shape, and an angle θ between the height direction of the isosceles trapezoid and the side included in the principal surface of the isosceles trapezoid satisfies the relationship 0.03 <sin θ <0.27. 3. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device.   4. The semiconductor device according to claim 1, wherein a distance between the opposing main surfaces on the source region side is not more than half of a gate length of the field effect transistor.   5. The semiconductor device according to claim 1, wherein an interval between the opposing main surfaces on the source region side is 10 nm or less.   6. The semiconductor device according to claim 1, wherein an end portion of the gate electrode is located in a center direction of the channel region rather than an end portion of the region where the interval between the opposing main surfaces is changed. .   6. The gate electrode according to claim 1, wherein an end portion of the gate electrode is in an opposite direction with respect to the center of the channel region, rather than an end portion of the region where the interval between the opposing main surfaces changes. Semiconductor device.   2. The gate insulating film and the gate electrode extend to a plane perpendicular to the main surface, and the gate insulating film and the gate electrode exist on at least three surfaces of the channel region. The semiconductor device according to claim 7.   9. The semiconductor device according to claim 1, wherein a dielectric constant of the gate insulating film is higher than a dielectric constant of the silicon oxide film.

Images