CN108767011A - A kind of double grids MOSFET structure - Google Patents
A kind of double grids MOSFET structure Download PDFInfo
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- 230000000750 progressive effect Effects 0.000 claims abstract description 6
- 239000000463 material Substances 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910002601 GaN Inorganic materials 0.000 claims description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 3
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 3
- 229910052732 germanium Inorganic materials 0.000 claims description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 3
- 239000011810 insulating material Substances 0.000 claims description 3
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 230000005684 electric field Effects 0.000 abstract description 17
- 230000000694 effects Effects 0.000 abstract description 13
- 230000008859 change Effects 0.000 description 17
- 238000010586 diagram Methods 0.000 description 8
- 239000013078 crystal Substances 0.000 description 5
- 238000009826 distribution Methods 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000005728 strengthening Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 208000032750 Device leakage Diseases 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000001803 electron scattering Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A kind of double grids MOSFET structure, including：In the channel region of progressive thickness, the side that the thickness of channel region is small is equipped with source region, and the big side of thickness is equipped with drain region, and side of the source region far from channel region is equipped with source electrode, and side of the drain region far from channel region is equipped with drain electrode；Connected channel region, source region and the upper and lower surface in drain region is covered each by the first grid oxide layer and the second grid oxide layer, the upper surface that first grid oxide layer covers the part of channel region is equipped with first grid, the lower surface that second grid oxide layer covers the part of channel region is equipped with second grid, and first grid and second grid constitute double-gate structure.Device architecture provided by the present invention can effectively inhibit short-channel effect and improve current driving ability, reduce the peak electric field in drain region；And processing step is relatively easy, it can be mutually compatible with existing CMOS technology.
Description
Technical field
The invention belongs to technical field of semiconductor device, and in particular to a kind of double grids MOSFET structure.
Background technology
With the fast development of integrated circuit, the performance and density of chip are continuously increased therewith, this requires device size not
It is disconnected to reduce, however when the size reduction of device to a certain extent when will cause short-channel effect.Short-channel effect will lead to device
The control ability of part grid declines, and effect is reduced so as to cause the drift of threshold voltage and drain induced barrier, so as to cause device
Quiescent dissipation increases.At the same time, the device size of diminution will cause the electric field of device inside to increase, and increase hot carrier
It generates, reduces the reliability of device.
According to the applicant understood, in order to improve the short-channel effect of MOSFET, researcher proposes various measures.Document 1,
Such as Long W, Ou H, Kuo J M, et al. Dual-material gate (DMG) field effect
transistor[J]. IEEE Transactions on Electron Devices, 1999, 46(5):865-870 is carried
A kind of MOSFET with double section grid structures is gone out.As shown in Figure 1,1 is first segment grid metal, 2 be second segment grid metal, and 3 are
Grid oxide layer, 4 be source electrode, and 5 be source region, and 6 be substrate, and 7 be drain region, and 8 be drain electrode, and 9 be underlayer electrode.The structure is by using two
The characteristic of material of the kind with different work functions, improves the control ability of grid, and enhance the transportation characterization of electronics.But
It is since the manufacturing process of double sections of grid is very complicated, cost is higher, is not suitable for being applied in super large-scale integration.
Document 2, such as Zhang Zhecheng, Chinese patent, 201710288728.2, it is proposed that a kind of MOS crystal of FinFET structure
Pipe.As shown in Fig. 2, 1 is grid, 2 be grid oxide layer, and 3 be source region, and 4 be channel region, and 5 be drain region, and 6 be substrate.The device increases
The quantity of grid, and by raceway groove three dimensional stress so that effective channel width of device improves the control of grid while increase
Ability, therefore current driving ability is increased, and restrained effectively short-channel effect.However due under channel dimensions
Drop, increases the electric field strength of device inside, to reduce the reliability of device.
Document 3, such as United States Patent (USP) Colinge JP.Junctionless metal-oxide-semiconductor
transistor:U.S.Patent8,178,862 [P] .2012-5-15 proposes a kind of no junction field effect transistor.Such as Fig. 3
Shown, 1 is first grid, and 2 be the first grid oxide layer, and 3 be source electrode, and 4 be source region, and 5 be channel region, and 6 be drain region, and 7 be drain electrode, and 8 are
Second grid oxide layer, 9 be second grid.The characteristic that depletion region is utilized in the invention carrys out being switched on and off for control device.Due to not
There are PN junction, manufacturing process is relatively simple.The raceway groove and source-drain area of the structure all need doping same type and dense
Impurity, however carrier fluctuating effect so that device inside carrier concentration profile is inconsistent, limits the extensive of the device
Using.
Invention content
It is an object of the invention to：A kind of double grids MOSFET structure, can effectively control short-channel effect, improve electric current
Driving capability, and the peak electric field of device inside can be reduced, improve the reliability of device.
In order to reach object above, a kind of double grids MOSFET structure, including：In the channel region of progressive thickness, channel region
The small side of thickness is equipped with source region, and the big side of thickness is equipped with drain region, and side of the source region far from channel region is equipped with source electrode, drain region
Side far from channel region is equipped with drain electrode；Connected channel region, source region and the upper and lower surface in drain region is covered each by the first grid oxide layer
With the second grid oxide layer, the upper surface that the first grid oxide layer covers the part of channel region is equipped with first grid, and the second grid oxide layer covers ditch
The lower surface of the part in road area is equipped with second grid, and first grid and second grid constitute double-gate structure.
The present invention preferred embodiment be：The elongated surfaces on upper and lower two surface of channel region must intersect.
Preferably, channel region, source region and the material in drain region are silicon or germanium, germanium silicon, GaAs, gallium nitride.
Preferably, channel region, source region and the doping type in drain region are p-type or N-type.
Preferably, the material of the first grid oxide layer and the second grid oxide layer is the insulating materials of oxide or nitride.
Preferably, the material of source electrode, drain electrode, first grid and second grid is polysilicon or metal.
The present invention has the beneficial effect that：In the structure grid control can be effectively provided by the smaller raceway groove of the thickness of source area
Ability processed, to reduce short-channel effect；And the larger raceway groove of thickness close to drain region can effectively reduce electric field strength, simultaneously
The oblique PN junction generated due to the variation of channel thickness can reduce electric field strength, and the peak electric field in drain region is minimized；
Finally since the gradual change of channel thickness, the scattering process of device inside are improved, the device architecture is enable effectively to enhance
Current driving ability.
Description of the drawings
The present invention will be further described below with reference to the drawings.
Fig. 1 is the schematic diagram for double section grid structures that background technology Literature 1 uses；
Fig. 2 is the schematic diagram for the FinFET structure that background technology Literature 1 uses；
Fig. 3 is the schematic diagram without node MOSFET structure that background technology Literature 1 uses；
Fig. 4 is the schematic cross-section of the double grids MOSFET structure of the present invention；
Fig. 5 is the double grids MOSFET structure three-dimensional schematic diagram of the embodiment of the present invention one；
Fig. 6 is the double grids MOSFET structure three-dimensional schematic diagram of the embodiment of the present invention two；
Fig. 7 is the schematic diagram that the present invention improves groove potential distribution；
Fig. 8 is the schematic diagram that the present invention improves surface distribution；
Fig. 9 is the schematic diagram that the present invention improves mutual conductance.
Specific implementation mode
As shown in figure 4, a kind of double grids MOSFET structure, including：In the channel region 5 of progressive thickness, the thickness of channel region 5 is small
Side be equipped with source region 4, the big side of thickness be equipped with drain region 6, side of the source region 4 far from channel region be equipped with source electrode 3, drain region 6
Side far from channel region is equipped with drain electrode 7；Connected channel region 5, source region 4 and the upper and lower surface in drain region 6 is covered each by the first grid
Oxygen layer 2 and the second grid oxide layer 8, the upper surface that the first grid oxide layer 2 covers the part of channel region are equipped with first grid 1, the second grid oxygen
The lower surface that layer 8 covers the part of channel region is equipped with second grid 9, and first grid 1 and second grid 9 constitute double-gate structure.
The elongated surfaces on upper and lower two surface of channel region 5 must intersect.
The material of channel region 5, source region 4 and drain region 6 is silicon or germanium, germanium silicon, GaAs, gallium nitride.
The doping type of channel region 5, source region 4 and drain region 6 is p-type or N-type.
The material of first grid oxide layer 2 and the second grid oxide layer 8 is the insulating materials of oxide or nitride.
Source electrode 3, drain electrode 7, first grid 1 and second grid 9 material be polysilicon or metal.
As shown in figs. 7 to 9, three kinds of gradual change channel thickness double-gate structures are chosen and carry out performance pair with conventional double grids MOSFET
Than respectively（The sources t=5nm, t leakages=10nm）,（The sources t=5nm, t leakages=15nm）With（The sources t=10nm, t leakages=15nm）, the wherein sources t table
Show that the channel thickness by source area 4, t leakages indicate the channel thickness close to drain region 6.The channel thickness of conventional double grids MOSFET is arranged
For 10nm.
Wherein, Fig. 7 is the groove potential of conventional double-gate structure and gradual change channel thickness double-gate structure proposed by the invention
Comparison.Fig. 8 is that the surface field of conventional double-gate structure and gradual change channel thickness double-gate structure proposed by the invention compares.Fig. 9
It is the mutual conductance comparison of conventional double-gate structure and gradual change channel thickness double-gate structure proposed by the invention.
Raceway groove electricity of the conventional double-gate structure with gradual change channel thickness double-gate structure proposed by the invention is compared in the figure 7
Gesture is distributed.When device channel length shortens, the potential in drain region 6 will influence the Potential Distributing of channel region 5, usually, with
The shortening of channel length, groove potential will be lifted, therefore device is opened required threshold voltage and will be reduced.And potential
Raising will lead to the reduction of the potential barrier between source region 4 and channel region 5, to influence the Sub-Threshold Characteristic of device, device leakage
Electricity increases, and then quiescent dissipation increases.As shown in Figure 7, the groove potential of gradual change channel thickness double-gate structure is than conventional double grid knot
The groove potential of structure is lower.This means that gradual change channel thickness double-gate structure can effectively inhibit short-channel effect so that device
Part threshold voltage is more stablized, and leakage current is reduced, and reduces quiescent dissipation.
Surface electricity of the conventional double-gate structure with gradual change channel thickness double-gate structure proposed by the invention is compared in fig. 8
Field distribution.With the diminution of device size, internal electric field strength gradually rises, and device reliability is caused to decline.From Fig. 8
It is found that the drain region peak electric field of gradual change channel thickness double-gate structure is lower than the drain region peak electric field of conventional double-gate structure.This meaning
Taste, which gradual change channel thickness double-gate structure, can effectively reduce drain region peak electric field, to reduce the breakdown voltage of device, inhibit
The generation of hot carrier improves the reliability of device.
Compare in fig.9 the mutual conductance of conventional double-gate structure and gradual change channel thickness double-gate structure proposed by the invention with
The situation of change of gate voltage.Mutual conductance is a key parameter of device, and mutual conductance is bigger, it is meant that the operating rate of device is got over
Soon.From Fig. 9 it is not difficult to find that the mutual conductance of gradual change channel thickness double-gate structure than conventional double-gate structure mutual conductance higher, therefore gradually
Become operating rate higher of the operating rate than conventional double-gate structure of channel thickness double-gate structure.This is because gradual change channel thickness
Double-gate structure can reduce the electron scattering effect of inversion layer, to improve the mobility of electronics, and then improve the mutual conductance of device.
Embodiment one
As shown in figure 5, the faces XY are defined as parallel with crystal column surface in the present embodiment, Z-direction is defined as the normal of crystal column surface
Direction,
Channel region 5 is set as progressive thickness in z-direction, and lower surface is level, and upper surface takes the form of inclined plane state, thickness it is small one
Side is equipped with source region 4, and the big side of thickness is equipped with drain region 6, and side of the source region 4 far from channel region is equipped with source electrode 3, and drain region 6 is separate
The side of channel region is equipped with drain electrode 7；Connected channel region 5, source region 4 and the upper and lower surface in drain region 6 is covered each by the first grid oxide layer
2 and second grid oxide layer 8, the upper surface that the first grid oxide layer 2 covers the part of channel region be equipped with first grid 1, the second grid oxide layer 8 covers
The lower surface of the part of lid channel region is equipped with second grid 9, and first grid 1 and second grid 9 constitute double-gate structure.
In this configuration, thickness of the channel region 5 in 4 side of source region is smaller than the thickness in 6 side of drain region, is set by this
It sets, the raceway groove smaller by the thickness of source area 4 can effectively provide grid control ability, to reduce short-channel effect；And
The larger raceway groove of thickness close to drain region 6 can effectively reduce electric field strength, simultaneously because the variation of channel thickness and generate
Oblique PN junction can reduce electric field strength, therefore the peak electric field in drain region 6 is minimized；Finally due to the gradual change of channel thickness, device
Scattering process inside part is improved, and causes the device architecture being capable of effectively strengthening electric current driving capability.
Embodiment two
As shown in fig. 6, the faces XY are defined as parallel with crystal column surface in the present embodiment, Z-direction is defined as the normal of crystal column surface
Direction, channel region 5 is set as progressive thickness on the faces XY in the structure；Source region 4 and drain region 6 is respectively set in the both sides of channel region 5；
Grid oxide layer 2 is covered in front and rear surfaces and the upper surface of channel region 5；Grid 1, which is set to, is covered in 2 surface of grid oxide layer；Grid oxide layer 2 exists
The thickness of the top of channel region 5 is set as much larger than the thickness in 5 front and rear surfaces of channel region.By this set, grid 1 is in ditch
Part above road will not provide control ability, and double-gate structure is constituted to the front and rear part of grid 1
In this configuration, thickness of the channel region 5 in 4 side of source region is smaller than the thickness in 6 side of drain region, by this set,
The raceway groove smaller by the thickness of source area 4 can effectively provide grid control ability, to reduce short-channel effect；And it is close
The raceway groove that the thickness in drain region 6 is larger can effectively reduce electric field strength, simultaneously because the variation of channel thickness and the oblique PN that generates
Knot can reduce electric field strength, therefore the peak electric field in drain region 6 is minimized；Finally due to the gradual change of channel thickness, in device
The scattering process in portion is improved, and causes the device architecture being capable of effectively strengthening electric current driving capability.
In addition to the implementation, the present invention can also have other embodiment.It is all to use equivalent substitution or equivalent transformation shape
At technical solution, fall within the scope of protection required by the present invention.
Claims (6)
1. a kind of double grids MOSFET structure, which is characterized in that including：In the channel region of progressive thickness, the thickness of the channel region
Small side is equipped with source region, and the big side of thickness is equipped with drain region, and side of the source region far from channel region is equipped with source electrode, described
Side of the drain region far from channel region is equipped with drain electrode；The connected channel region, the source region and the upper and lower surface in the drain region point
Do not cover the first grid oxide layer and the second grid oxide layer, the upper surface that first grid oxide layer covers the part of the channel region is equipped with the
One grid, second grid oxide layer cover the part of the channel region lower surface be equipped with second grid, the first grid and
The second grid constitutes double-gate structure.
2. a kind of double grids MOSFET structure according to claim 1, which is characterized in that upper and lower two table of the channel region
The elongated surfaces in face must intersect.
3. a kind of double grids MOSFET structure according to claim 1, which is characterized in that the channel region, the source region and
The material in the drain region is silicon or germanium, germanium silicon, GaAs, gallium nitride.
4. a kind of double grids MOSFET structure according to claim 1, which is characterized in that the channel region, the source region and
The doping type in the drain region is p-type or N-type.
5. a kind of double grids MOSFET structure according to claim 1, which is characterized in that first grid oxide layer and described
The material of two grid oxide layers is the insulating materials of oxide or nitride.
6. a kind of double grids MOSFET structure according to claim 1, which is characterized in that the source electrode, it is described drain electrode, it is described
The material of first grid and the second grid is polysilicon or metal.
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|---|---|---|---|
| CN201810398766.8A CN108767011A (en) | 2018-04-28 | 2018-04-28 | A kind of double grids MOSFET structure |
| PCT/CN2018/111908 WO2019205537A1 (en) | 2018-04-28 | 2018-10-25 | Dual-gate mosfet structure |
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| CN201810398766.8A CN108767011A (en) | 2018-04-28 | 2018-04-28 | A kind of double grids MOSFET structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110416288A (en) * | 2019-08-01 | 2019-11-05 | 南京邮电大学 | A kind of dual-grate tunneling transistor structure |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5461250A (en) * | 1992-08-10 | 1995-10-24 | International Business Machines Corporation | SiGe thin film or SOI MOSFET and method for making the same |
| JP2008192819A (en) * | 2007-02-05 | 2008-08-21 | Toshiba Corp | Semiconductor device |
| KR20120066150A (en) * | 2010-12-14 | 2012-06-22 | 서강대학교산학협력단 | Tunneling field effect transistor with asymmetrical active region |
| CN105826391A (en) * | 2016-05-19 | 2016-08-03 | 杭州电子科技大学 | Novel asymmetric double-gate junctionless field effect transistor |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| ATE467908T1 (en) * | 2006-08-04 | 2010-05-15 | Nxp Bv | METHOD FOR PRODUCING A DOUBLE GATE TRANSISTOR |
| US8299547B2 (en) * | 2011-01-03 | 2012-10-30 | International Business Machines Corporation | Lateral extended drain metal oxide semiconductor field effect transistor (LEDMOSFET) with tapered dielectric plates |
-
2018
- 2018-04-28 CN CN201810398766.8A patent/CN108767011A/en active Pending
- 2018-10-25 WO PCT/CN2018/111908 patent/WO2019205537A1/en active Application Filing
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5461250A (en) * | 1992-08-10 | 1995-10-24 | International Business Machines Corporation | SiGe thin film or SOI MOSFET and method for making the same |
| JP2008192819A (en) * | 2007-02-05 | 2008-08-21 | Toshiba Corp | Semiconductor device |
| KR20120066150A (en) * | 2010-12-14 | 2012-06-22 | 서강대학교산학협력단 | Tunneling field effect transistor with asymmetrical active region |
| CN105826391A (en) * | 2016-05-19 | 2016-08-03 | 杭州电子科技大学 | Novel asymmetric double-gate junctionless field effect transistor |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110416288A (en) * | 2019-08-01 | 2019-11-05 | 南京邮电大学 | A kind of dual-grate tunneling transistor structure |
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Address after: 226000 Room 8319, Building 11, Happy New Town, Gangzha District, Nantong City, Jiangsu Province Applicant after: Nanjing Post & Telecommunication Univ. Applicant after: Nanjing University of Posts and Telecommunications Nantong Institute Limited Address before: 210003 new model road 66, Gulou District, Nanjing, Jiangsu Applicant before: Nanjing Post & Telecommunication Univ. Applicant before: Nanjing University of Posts and Telecommunications Nantong Institute Limited |
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| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20181106 |