CN110416288A - A kind of dual-grate tunneling transistor structure - Google Patents
A kind of dual-grate tunneling transistor structure Download PDFInfo
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- CN110416288A CN110416288A CN201910705903.2A CN201910705903A CN110416288A CN 110416288 A CN110416288 A CN 110416288A CN 201910705903 A CN201910705903 A CN 201910705903A CN 110416288 A CN110416288 A CN 110416288A
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- 230000005641 tunneling Effects 0.000 title claims abstract description 61
- 239000000463 material Substances 0.000 claims description 11
- 150000004767 nitrides Chemical class 0.000 claims description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910002601 GaN Inorganic materials 0.000 claims description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 3
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 3
- 229910052732 germanium Inorganic materials 0.000 claims description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 239000011810 insulating material Substances 0.000 claims description 2
- 239000004744 fabric Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 9
- 230000008859 change Effects 0.000 description 5
- 239000013078 crystal Substances 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7391—Gated diode structures
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Abstract
A kind of dual-grate tunneling transistor structure, channel region 5 including being incremented by distribution in stepped thickness, the small side of the thickness of channel region 5 is equipped with source region 9, the big side of its thickness is equipped with source region 4, source region 9 is equipped with source electrode 8 far from the side of channel region, drain region is equipped with drain electrode 3 far from the side of channel region, the upper and lower surfaces of channel region 5 are covered each by the first gate dielectric layer 2 and the second gate dielectric layer 6, the upper surface of first gate dielectric layer 2 covers first grid 1, the lower surface of second gate dielectric layer 6 covers second grid 7, and first grid 1 and second grid 7 constitute double-gate structure.Device architecture provided by the present invention can effectively improve ON state tunnelling probability and on-state current and reduce bipolar state tunnelling probability and bipolar current.
Description
Technical field
The invention belongs to technical field of semiconductor device, and in particular to a kind of dual-grate tunneling transistor structure.
Background technique
With the development of semiconductor integrated circuit, basic unit of the transistor as integrated circuit, size is continuous
Ground reduces, and performance is also improved constantly.It is short however when the size reduction of transistor is to deep-submicron even nanoscale
Channelling effect will become one of the resistance for restricting transistor and persistently reducing.Short-channel effect can weaken grid to internal charge
Control ability, to cause a series of problems, such as leakage current increases, sub-threshold slope increases, threshold voltage shift.Therefore, it studies
Seem particularly necessary if new device structure such as performance of the tunneling transistor to improve transistor.The characteristics of tunneling transistor is remote low
It is lower than 60 mV/dec in the sub-threshold slope of the sub-threshold slope of conventional MOSFET, usual tunneling transistor.Additionally due to tunnelling
The working characteristics of transistor, it is smaller for the more conventional MOSFET of leakage current, therefore tunneling transistor is expected to be applied to nanometer ruler
In very little lower ultra-low power consumption integrated circuit.However tunneling transistor, due to the limitation of itself tunneling mechanism, on-state current is relatively low, and
And there is bipolar current effects.
According to the applicant understood, in order to improve the on-state current and bipolar current of tunneling transistor, researcher is proposed respectively
Kind measure.Document 1, such as K. Boucart, A. M. Ionescu, Double-Gate Tunnel FET With High-k
Gate Dielectric[J]. IEEE transactions on electron devices, 2007, 54(7): 1725-
1733. propose a kind of dual-grate tunneling transistor with high-k gate dielectric.As shown in Figure 1,1 is first grid, 2 be the first grid
Dielectric layer, 3 be drain electrode, and 4 be drain region, and 5 be the second gate dielectric layer, and 6 be second grid, and 7 be source electrode, and 8 be source region, and 9 be channel region.
The structure improves equivalent gate width, to improve grid control ability by the characteristic using double-gate structure.Secondly the knot
Structure uses the gate dielectric layer of high k, effectively improves band curvature degree, to improve tunnelling probability, and then improves tunnel
Wear electric current.However the defect of the structure is that the raising of its tunnelling probability is global, that is to say, that bipolar current similarly
Increase, improves the design difficulty of circuit.
Document 2, such as Zhang Xuefeng, Chinese patent, 201310083020.5, the tunnelling for proposing a kind of vertical tunneling structure is brilliant
Body pipe.As shown in Fig. 2, 1 is drain electrode, 2 be drain region, and 3 be grid, and 4 be gate dielectric layer, and 5 be source region, and 6 be channel region, and 7 be source electrode.
Grid is placed in source region by the effective length of extension grid to increase effective tunnelling region area by the device.Work as device
When part is opened, inversion layer will be will form below grid, so that the energy band of source region bends, thus form vertical tunnel region
Domain.However due to being the semiconductor regions of heavy doping below grid, to make the region transoid, then the voltage that grid is applied must
Must be higher than conventional structure, therefore the threshold voltage of the structure and tunnelling cut-in voltage necessarily increase.In addition, the structure only improves
On-state current, do not optimize for bipolar current.
Document 3, such as United States Patent (USP) Anne Verhulst, Drain Extension Region for Tunnel
Fet:U.S.Patent, 15/337,728 [P] .2016-10-28 propose the tunneling transistor that layer is expanded with drain region.Such as Fig. 3
Shown, 1 is grid, and 2 be gate dielectric layer, and 3 be that layer is expanded in drain region, and 4 be drain region, and 5 be drain electrode, and 6 be source electrode, and 7 be source region, and 8 be ditch
Road area.Layer is expanded to form depletion region, so that tunnelling probability be effectively reduced in the drain region that high-dopant concentration is utilized in the invention.It is closing
When state, drain region expands layer and is capable of forming the depletion region opposite with drain region carrier type, so that the bending journey of energy band be effectively reduced
Degree, and then reduce bipolar current.However the structure process is complex, and can not improve on-state current.
Summary of the invention
The technical problem to be solved by the present invention is to overcome the deficiencies of the prior art and provide a kind of dual-grate tunneling transistor knot
Structure obtains relatively high on-state current and lower bipolar current by changing the thickness distribution of channel region, to reduce
The shutdown power consumption of device.
The present invention provides a kind of dual-grate tunneling transistor structure, the channel region 5 including being incremented by distribution in stepped thickness, ditch
The small side of the thickness in road area 5 is equipped with source region 9, and the big side of thickness is equipped with source region 4, and source region 9 is set far from the side of channel region
Source 8, drain region are equipped with drain electrode 3 far from the side of channel region, and the upper and lower surfaces of channel region 5 are covered each by the first gate dielectric layer 2
With the second gate dielectric layer 6, the upper surface of the first gate dielectric layer 2 covers first grid 1, the lower surface covering of the second gate dielectric layer 6
Second grid 7, first grid 1 and second grid 7 constitute double-gate structure.
As further technical solution of the present invention, it is greater than in the step number that stepped thickness is incremented by the channel region 5 of distribution
0, the position of ladder can be located at the arbitrary region in channel region 5.
Further, the material of channel region 5, source region 9 and drain region 4 is silicon or germanium, germanium silicon, GaAs, gallium nitride.
Further, the doping type of channel region 5, source region 9 and drain region 4 is p-type or N-type, wherein source region 9 and drain region 4
Doping type is opposite.
Further, the material of the first gate dielectric layer 2 and the second gate dielectric layer 6 is the insulation material of oxide or nitride
Material.
Further, the material of source electrode 8, drain electrode 3, first grid 1 and second grid 7 is polysilicon or metal.
The present invention is by changing the thickness distribution of channel region, even if the channel region thickness of source area is leaned on to be less than close to drain region
Channel region thickness, to obtain relatively high on-state current and lower bipolar current.
Detailed description of the invention
Fig. 1 is that having for the use of background technique Literature 1 is highkThe dual-grate tunneling transistor schematic diagram of gate medium；
Fig. 2 is a kind of tunneling transistor schematic diagram for vertical tunneling structure that background technique Literature 2 uses；
Fig. 3 is the tunneling transistor schematic diagram that layer is expanded with drain region that background technique Literature 3 uses；
Fig. 4 is the schematic cross-section of dual-grate tunneling transistor structure of the invention；
Fig. 5 is a kind of structural schematic diagram of the dual-grate tunneling transistor of the embodiment of the present invention one；
Fig. 6 is the dual-grate tunneling transistor structure three-dimensional schematic diagram of the embodiment of the present invention one；
Fig. 7 is the dual-grate tunneling transistor structure three-dimensional schematic diagram of the embodiment of the present invention two；
Fig. 8 is the schematic diagram that the present invention improves transfer characteristic；
Fig. 9 is the schematic diagram that the present invention improves ON state tunnelling probability；
Figure 10 is the schematic diagram that the present invention improves bipolar state tunnelling probability.
Specific embodiment
Referring to Fig. 4, the present embodiment provides a kind of dual-grate tunneling transistor structures, including it is incremented by distribution in stepped thickness
Channel region 5, the small side of the thickness of channel region 5 be equipped with source region 9, the big side of thickness be equipped with source region 4, source region 9 is far from ditch
The side in road area is equipped with source electrode 8, and drain region is equipped with drain electrode 3 far from the side of channel region, and the upper and lower surfaces of channel region 5 are covered each by
The upper surface of first gate dielectric layer 2 and the second gate dielectric layer 6, the first gate dielectric layer 2 covers first grid 1, the second gate dielectric layer 6
Lower surface cover second grid 7, first grid 1 and second grid 7 constitute double-gate structure.
It is greater than 0 in the step number that stepped thickness is incremented by the channel region 5 of distribution, the position of ladder can be located at channel region 5
Interior arbitrary region.
The material of channel region 5, source region 9 and drain region 4 is silicon or germanium, germanium silicon, GaAs, gallium nitride.
The doping type of channel region 5, source region 9 and drain region 4 is p-type or N-type, wherein the doping type of source region 9 and drain region 4
On the contrary.
The material of first gate dielectric layer 2 and the second gate dielectric layer 6 is the insulating materials of oxide or nitride.
Source electrode 8, drain electrode 3, first grid 1 and second grid 7 material be polysilicon or metal.
As Figure 8-Figure 10, a kind of dual-grate tunneling transistor structure with asymmetric channels thickness is chosen with two kinds often
It advises dual-grate tunneling transistor structure and carries out performance comparison, respectively (channel thickness=10 nm), (channel thickness=20 nm)
(asymmetric channels thickness), wherein the source area channel thickness of leaning on of asymmetric channels thickness structure is 10 nm, close to drain region ditch
Road is with a thickness of 20 nm.
Wherein, Fig. 8 is conventional dual-grate tunneling transistor structure and asymmetric channels thickness double grid tunnel proposed by the invention
Wear the transfer characteristic comparison of transistor arrangement.Fig. 9 be conventional dual-grate tunneling transistor structure with it is proposed by the invention asymmetric
The ON state tunnelling probability of channel thickness dual-grate tunneling transistor structure compares.Figure 10 is conventional dual-grate tunneling transistor structure and this
Invent the bipolar state tunnelling probability comparison of proposed asymmetric channels thickness dual-grate tunneling transistor structure.
Conventional dual-grate tunneling transistor structure and asymmetric channels thickness double grid proposed by the invention are compared in fig. 8
The transfer characteristic of tunneling transistor arrangement.When the thickness of channel region reduces, the global tunnelling probability of dual-grate tunneling transistor is all
It will increase, therefore the on-state current with the conventional dual-grate tunneling transistor compared with small channel thickness is than with larger channel thickness
The on-state current of conventional dual-grate tunneling transistor is higher.However due to the raising of tunnelling probability be it is global, have it is smaller
The bipolar current of the conventional dual-grate tunneling transistor of channel thickness is equally more brilliant than the conventional dual-grate tunneling with larger channel thickness
The bipolar current of body pipe is higher.From the figure not difficult to find, the ON state electricity of the dual-grate tunneling transistor with asymmetric channels thickness
It flows suitable with the on-state current of conventional dual-grate tunneling transistor compared with small channel thickness；It is double with asymmetric channels thickness
The bipolar current of grid tunneling transistor is suitable with the bipolar current of conventional dual-grate tunneling transistor with larger channel thickness.
The reason of in order to further illustrate this effect is generated.Conventional dual-grate tunneling transistor structure is compared in Fig. 9
It is distributed with the ON state tunnelling probability of asymmetric channels thickness dual-grate tunneling transistor structure proposed by the invention.It can be seen that tool
There is the ON state tunnelling probability of the dual-grate tunneling transistor of asymmetric channels thickness and with the conventional double grid tunnel compared with small channel thickness
The tunnelling probability for wearing transistor is suitable；And the tunnelling probability of the conventional dual-grate tunneling transistor with larger channel thickness is minimum,
Therefore the dual-grate tunneling transistor with asymmetric channels thickness has and has the conventional dual-grate tunneling crystalline substance compared with small channel thickness
The comparable on-state current of body pipe.
Conventional dual-grate tunneling transistor structure is compared in Figure 10 and asymmetric channels thickness proposed by the invention is double
The bipolar state tunnelling probability of grid tunneling transistor arrangement is distributed.It can be seen that the dual-grate tunneling crystal with asymmetric channels thickness
The bipolar state tunnelling probability of pipe is suitable with the tunnelling probability of conventional dual-grate tunneling transistor with larger channel thickness；And have
Compared with the tunnelling probability highest of the conventional dual-grate tunneling transistor of small channel thickness, therefore the double grid tunnel with asymmetric channels thickness
Wearing transistor has and the comparable bipolar current of conventional dual-grate tunneling transistor with larger channel thickness.
Embodiment one
As shown in figure 5, the thickness of channel region 5 is in asymmetric distribution in the horizontal direction, the thickness change mode of channel region 5 is more
Stepped change.The ladder number can be 2, can also be greater than 2.The small side of the thickness of channel region 5 is equipped with source region 9, thickness
Big side is equipped with drain region 4, and source region 9 is equipped with source electrode 8 far from the side of channel region, and drain region 4 is equipped with leakage far from the side of channel region
Pole 3；The upper and lower surfaces of channel region 5 are covered each by the first gate dielectric layer 2 and the second gate dielectric layer 6, the first gate dielectric layer 2 it is upper
Surface is equipped with first grid 1, and the lower surface of the second gate dielectric layer 6 is equipped with second grid 7, and first grid 1 and second grid 7 are constituted
Double-gate structure.
In this configuration, thickness of the channel region 5 in 2 side of source region is smaller than the thickness in 6 side of drain region, is set by this
It sets, tunnelling probability when can effectively increase ON state by the lesser channel of the thickness of source area 2, to improve on-state current；And
Tunnelling probability when bipolar state can be effectively reduced in the biggish channel of thickness close to drain region 6, therefore its bipolar current is dropped
It is low.
Embodiment two
As shown in fig. 6, the face XY is defined as parallel with crystal column surface in the present embodiment, Z-direction is defined as the normal of crystal column surface
Direction.
The thickness of channel region 5 is set as change in ladder shape in z-direction, which can be 1, can also be greater than 1.
The small side of thickness is equipped with source region 2, and the big side of thickness is equipped with drain region 6, and source region 2 is equipped with source electrode 1 far from the side of channel region,
Drain region 6 is equipped with drain electrode 7 far from the side of channel region；The side of channel region 5 is covered each by the first gate dielectric layer 3 and the second gate medium
Layer 9, the first gate dielectric layer 3 are equipped with first grid 4, the second side of the gate dielectric layer 9 far from channel region 5 far from the side of channel region 5
Face is equipped with second grid 8, and first grid 4 and second grid 8 constitute double-gate structure.
In this configuration, thickness of the channel region 5 in 2 side of source region is smaller than the thickness in 6 side of drain region, is set by this
It sets, tunnelling probability when can effectively increase ON state by the lesser channel of the thickness of source area 2, to improve on-state current；And
Tunnelling probability when bipolar state can be effectively reduced in the biggish channel of thickness close to drain region 6, therefore its bipolar current is dropped
It is low.
Embodiment three
As shown in fig. 7, the face XY is defined as parallel with crystal column surface in the present embodiment, Z-direction is defined as the normal of crystal column surface
Direction.
The thickness of channel region 5 is set as change in ladder shape on X/Y plane, which can be 1, can also be greater than
1.The small side of thickness is equipped with source region 2, and the big side of thickness is equipped with drain region 6, and source region 2 is equipped with source electrode far from the side of channel region
1, drain region 6 is equipped with drain electrode 7 far from the side of channel region；The side of channel region 5 is covered each by the first gate dielectric layer 4 and second gate is situated between
Matter layer 8, the first gate dielectric layer 4 are equipped with first grid 3 far from the side of channel region 5, and the second gate dielectric layer 8 is far from channel region 5
Side is equipped with second grid 9, and first grid 3 and second grid 9 constitute double-gate structure.Substrate 10, substrate are provided with below device
10 material can be oxide or nitride.
In this configuration, thickness of the channel region 5 in 2 side of source region is smaller than the thickness in 6 side of drain region, is set by this
It sets, tunnelling probability when can effectively increase ON state by the lesser channel of the thickness of source area 2, to improve on-state current；And
Tunnelling probability when bipolar state can be effectively reduced in the biggish channel of thickness close to drain region 6, therefore its bipolar current is dropped
It is low.
The basic principles, main features and advantages of the invention have been shown and described above.Those skilled in the art should
Understand, the present invention do not limited by above-mentioned specific embodiment, the description in above-mentioned specific embodiment and specification be intended merely into
One step illustrates the principle of the present invention, and under the premise of not departing from spirit of that invention range, the present invention also has various change and changes
Into these changes and improvements all fall within the protetion scope of the claimed invention.The scope of protection of present invention is by claim
Book and its equivalent thereof.
Claims (6)
1. a kind of dual-grate tunneling transistor structure, which is characterized in that the channel region 5 including being incremented by distribution in stepped thickness, institute
The small side of thickness for stating channel region 5 is equipped with source region 9, and the big side of thickness is equipped with source region 4, and the source region 9 is far from channel region
Side be equipped with source electrode 8, the drain region far from channel region side be equipped with drain electrode 3, the upper and lower surfaces of channel region 5 are covered each by
First gate dielectric layer 2 and the second gate dielectric layer 6, the upper surface covering first grid 1 of first gate dielectric layer 2, described second
The lower surface of gate dielectric layer 6 covers second grid 7, and first grid 1 and second grid 7 constitute double-gate structure.
2. a kind of dual-grate tunneling transistor structure according to claim 1, which is characterized in that be incremented by stepped thickness and divide
The step number of the channel region 5 of cloth is greater than 0, and the position of ladder can be located at the arbitrary region in the channel region 5.
3. a kind of dual-grate tunneling transistor structure according to claim 1, which is characterized in that the channel region 5, the source
The material in area 9 and the drain region 4 is silicon or germanium, germanium silicon, GaAs, gallium nitride.
4. a kind of dual-grate tunneling transistor structure according to claim 1, which is characterized in that the channel region 5, the source
The doping type in area 9 and the drain region 4 is p-type or N-type, wherein the source region 9 is opposite with the doping type in the drain region 4.
5. a kind of dual-grate tunneling transistor structure according to claim 1, which is characterized in that first gate dielectric layer 2
Material with second gate dielectric layer 6 is the insulating materials of oxide or nitride.
6. a kind of dual-grate tunneling transistor structure according to claim 1, which is characterized in that the source electrode 8, the drain electrode
3, the material of the first grid 1 and second grid 7 is polysilicon or metal.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20160071965A1 (en) * | 2014-09-04 | 2016-03-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Leakage current suppression methods and related structures |
| CN106415848A (en) * | 2014-06-27 | 2017-02-15 | 英特尔公司 | Multi-gate transistor with variably sized fin |
| CN108074979A (en) * | 2017-11-30 | 2018-05-25 | 中国科学院上海微系统与信息技术研究所 | Field-effect transistor, biosensor based on vertical tunnelling and preparation method thereof |
| CN108767011A (en) * | 2018-04-28 | 2018-11-06 | 南京邮电大学 | A kind of double grids MOSFET structure |
-
2019
- 2019-08-01 CN CN201910705903.2A patent/CN110416288A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106415848A (en) * | 2014-06-27 | 2017-02-15 | 英特尔公司 | Multi-gate transistor with variably sized fin |
| US20160071965A1 (en) * | 2014-09-04 | 2016-03-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Leakage current suppression methods and related structures |
| CN108074979A (en) * | 2017-11-30 | 2018-05-25 | 中国科学院上海微系统与信息技术研究所 | Field-effect transistor, biosensor based on vertical tunnelling and preparation method thereof |
| CN108767011A (en) * | 2018-04-28 | 2018-11-06 | 南京邮电大学 | A kind of double grids MOSFET structure |
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