CN104617137B - A kind of fieldtron and preparation method thereof - Google Patents
A kind of fieldtron and preparation method thereof Download PDFInfo
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- CN104617137B CN104617137B CN201510026477.1A CN201510026477A CN104617137B CN 104617137 B CN104617137 B CN 104617137B CN 201510026477 A CN201510026477 A CN 201510026477A CN 104617137 B CN104617137 B CN 104617137B
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Abstract
The embodiment of the invention discloses a kind of fieldtrons and preparation method thereof, and for solving number of drawbacks existing for existing tunneling transistor, present invention method includes：Semiconductor substrate with the first doping type；Drain region formed in semiconductor substrate surface, with the first doping type；Convex body is formed on drain region surface；The grid that drain region surface other than convex body is formed, grid are higher than convex body, and the gate dielectric layer between grid and drain region and between grid and convex body；In the semiconductive thin film that the body structure surface that gate dielectric layer and convex body form is formed, as pocket layer；In the source region that pocket layer surface is formed, source region is the semi-conducting material with second of doping type；Convex body is as the raceway groove between drain region and source region.
Description
Technical field
The present invention relates to technical field of semiconductors, and in particular to a kind of fieldtron and preparation method thereof.
Background technology
With the evolution of semiconductor fabrication process, the size of electronic device gradually reduces, and carrys out speed for chip belt, integrates
The improvement of degree, power consumption and cost etc., but with the physics limit that is closely sized to of electronic device, the power density of chip
It improves therewith, and as the bottleneck of limitation semiconductor technology evolution.
In order to continue to obtain promotion of the novel technique to chip characteristics, the power consumption of transistor must reduce, wherein
The most effective approach for reducing transistor dissipation is reduction supply voltage, but due to mos field effect transistor
The carrier thermodynamics of (Metal Oxide Semiconductor Field Effect Transistor, MOSFET) transports
Mechanism limits, and the lower limit of subthreshold swing is 60mV/dec, and device sub-threshold current can be brought by reducing the supply voltage of device
Increase, total Leakage Current of device is caused to increase.Tunneling field-effect transistor (Tunnel Field Effect
Transistor, TFET) due to the quantum-mechanical mechanisms of its unique inter-band tunneling, the subthreshold swing of device can be broken through
The limitation of 60mV/dec realizes the reduction of device supply voltage while ensureing device current driving capability.In addition, TFET
Also have the advantages that weaker short-channel effect, off-state current are low, is considered that the potentiality device of MOSFET can be replaced by industry
Framework.
For a kind of existing conventional n-type TFFT transistors as shown in Figure 1, source region 101 is P+ doped regions, drain region 102 is N+
Doped region, TFET in off position when, i.e., without apply grid voltage when, only minimum leakage current；When TFET is opened,
When being applied with certain grid voltage, the electron concentration in channel region 103 reaches degeneracy state, channel region 103 and source region 101
Tunnel knot is formed, energy band bends, and the conduction band of source region 101 is Chong Die with the valence band of channel region 103, and current-carrying intersubband tunnel occurs
It wears, channel region 103 generates electric current, and tunneling mechanism belongs to the scope of a tunnelling, i.e. carrier tunnelling direction does not exist with grid electric field
Same direction.
But TFFT transistors as shown in Figure 1a, it has as a drawback that：
1, the conduction band of source region and the valence band of raceway groove are Chong Die, and the tunneling mechanism of generation is a tunneling mechanism, i.e. carrier tunnelling
Direction and grid electric field be not in same direction, therefore the Electrostatic Control effect of grid voltage is weak, and carrier tunneling efficiency is low；
2, the formation of drain region electric jamming tunnel junctions influences device threshold voltage, while subthreshold swing being made to degenerate；
3, traditional TFET structures are planar structure, and occupancy Substrate Area is big, influences integration density.
The N-type TFET transistors of another existing line tunneling mechanism are as shown in Figure 1 b, grid 204 and 201 part of source region
There is the epitaxial layer 205 being lightly doped, under the action of grid electric field, extension between grid 204 and the source region 201 of heavy doping in overlapping
The carrier accumulation of layer 205 finally forms tunnel junctions with source region 201, in this device architecture, carrier tunnelling direction and grid electricity
Field is parallel.
Carrier tunnelling direction and grid field parallel, grid-control ability are strengthened in TFET transistors as shown in Figure 1 b,
And tunnelling current size can also be regulated and controled by the overlapping area in grid source, effectively improve TFET crystal shown in Fig. 1 a
1st kind of defect of pipe.
But the Substrate Area of device consumption also increases, to reduce the integration density of transistor, in addition, planar structure
Using source replacement technique, epitaxial layer can be damaged, device property is caused to decline.
Invention content
An embodiment of the present invention provides a kind of fieldtrons and preparation method thereof, for solving existing tunneling transistor
Existing above-mentioned number of drawbacks.
The first aspect of the present invention provides a kind of fieldtron, including：
Semiconductor substrate with the first doping type；
Drain region formed in the semiconductor substrate surface, with the first doping type；
In the convex body that the drain region surface is formed, the convex body is perpendicular to the drain region surface, is mixed with the first
The fin ray or nano wire of miscellany type；
The grid that drain region surface other than the convex body is formed, the grid are higher than the convex body；
The gate dielectric layer formed between the grid and the convex body between the grid and the drain region；
In the semiconductive thin film that the body structure surface that the gate dielectric layer and the convex body form is formed, as pocket layer；
In the source region that the pocket layer surface is formed, the source region is the semi-conducting material with second of doping type；
The convex body is as the raceway groove between the drain region and the source region.
In conjunction with the first aspect of the present invention, in the first possible realization method of first aspect present invention, the field-effect
Device further includes：
The electrode formed in the source region, the drain region and the source region respectively.
In conjunction with the first aspect of the present invention, second of first aspect present invention may in realization method, the source region and
The pocket layer forms tunnel junctions, and the tunnel junctions control the tunnelling of carrier by gate electric field, can realize electric in device
The on and off of stream.
In conjunction with the first possible realization method of the first aspect of the present invention, first aspect present invention or first party of the present invention
Second of face may realization method, in the third possible realization method of first aspect present invention：
The first described doping type is N-shaped, and second of doping type is p-type；
Or, the first described doping type is p-type, second of doping type is N-shaped.
In conjunction with the first possible realization method of the first aspect of the present invention, first aspect present invention or first party of the present invention
Second of face may realization method, in the 4th kind of possible realization method of first aspect present invention：
The semiconductor substrate be body silicon, the silicon on insulator, germanium or III-V compound semiconductor material, it is described to receive
Rice noodles and fin ray are silicon, germanium, germanium silicon or III-V compound semiconductor material, and the pocket layer is silicon, germanium, germanium silicon or III-V
Group iii v compound semiconductor material, the source region are silicon, germanium, germanium silicon or III-V compound semiconductor material, the gate dielectric layer
First part is silica, silicon nitride, high dielectric material or dielectric insulation material, and the grid is metal, alloy or doping
Polysilicon.
In conjunction with the first possible realization method of first aspect present invention, the 5th kind of first aspect present invention may be realized
In mode：
The electrode is aluminium or copper or aluminium alloy or copper alloy；
Spacer is provided between the drain region, grid and source region, the spacer is silica, silicon nitride or nitrogen oxygen
SiClx.
Second aspect of the present invention provides a kind of preparation method of fieldtron as described above, including：
Alternative source film layer is formed in the semiconductor substrate surface with the first doping type；
Hard mask layer is deposited in the alternative source thin-film surface, and it is convex by lithography and etching technique to define device
The position of body and drain region, the convex body are fin ray or nano wire with the first doping type；
Using the hard mask layer as mask, the alternative source film layer and described is etched by reactive ion etching technology
Semiconductor substrate forms the convex body；
Using the hard mask layer as mask, the ion by carrying out the first doping type to the semiconductor substrate is noted
Enter, and the activation injection ion of annealing, forms the drain region；
Gate dielectric layer first part is formed being formed by body structure surface；
Grid is formed on the gate dielectric layer first part, and etches the grid and the gate dielectric layer first
Point, expose the hard mask layer；
Gate dielectric layer second part is formed in the exposed surface of the grid, and removes the hard mask layer and described replaces
For source film layer, the gate dielectric layer of the gate dielectric layer first part and gate dielectric layer second part composition device；
Semiconductive thin film is formed being formed by body structure surface, as pocket layer；
Source region is formed in the pocket layer surface, the source region is the plate conductor substrate with second of doping type.
In conjunction with second aspect of the present invention, in the first possible realization method of second aspect of the present invention, further include：
The electrode window through ray that drain region and source region and grid are opened by lithography and etching technology deposits gold in electrode window through ray
Belong to, forms electrode on drain region and source region and grid respectively.
In conjunction with the possible realization method of the first of second aspect of the present invention or second aspect of the present invention, second party of the present invention
In second of possible realization method in face：
The first described doping type is N-shaped, and second of doping type is p-type；
Alternatively, the first described doping type is p-type, second of doping type is N-shaped.
In conjunction with the possible realization method of the first of second aspect of the present invention or second aspect of the present invention, second party of the present invention
In the third possible realization method in face：
The alternative source film layer is polysilicon or polycrystalline germanium, and the hard mask layer is the material of resistance to ion etching.
Therefore the fieldtron of the embodiment of the present invention forms source by forming pocket layer in pocket layer surface
Area, pocket layer constitute the tunnel junctions of device with source region, thus, it has the following technical effect that：
(1), the device is using opisthogenesis replacement technique, i.e., in the last making source region of technological process, in technological process
Behind make pocket layer and source region so that a plurality of types of heterogeneous tunnel junctions can be selected in the preparation, improve preparation source
The engineering flexibility ratio of the heterogeneous tunnel junctions in area；
(2), source region with the contact surface of tunnel junctions and gate dielectric layer that pocket layer forms is vertical, carrier in the device
The direction of tunnelling is necessarily consistent with the direction of grid electric field, which belongs to line tunneling mechanism, and grid voltage controls the tunnel of carrier
It wears, the direction of carrier tunnelling is consistent with the direction of grid electric field in line tunneling mechanism, therefore the voltage control capability of grid obtains
Reinforce, and tunnelling current size can also be regulated and controled by the overlapping area of grid and tunnel junctions, improve tunneling efficiency,
In addition, quantum-mechanical mechanisms of the line tunneling mechanism due to its unique inter-band tunneling, can reduce subthreshold swing.
Description of the drawings
Technical solution in order to illustrate the embodiments of the present invention more clearly, below will be to institute in embodiment and description of the prior art
Attached drawing to be used is needed to be briefly described, it should be apparent that, the accompanying drawings in the following description is only some implementations of the present invention
Example, for those of ordinary skill in the art, without creative efforts, can also obtain according to these attached drawings
Obtain other attached drawings.
Fig. 1 a are a kind of N-type tradition TFET schematic diagrames；
Fig. 1 b are that a kind of N-type threaded list wears TFET schematic diagrames；
Fig. 2 is a kind of schematic diagram of fieldtron provided in an embodiment of the present invention；
Fig. 3 is a kind of flow chart of the preparation method of fieldtron provided in an embodiment of the present invention；
Fig. 4 a to Fig. 4 k are the schematic diagrames in each processing step in present invention method.
Specific implementation mode
A kind of fieldtron of offer of the embodiment of the present invention and preparation method thereof exists to solve existing tunneling transistor
Above-mentioned number of drawbacks.
In order to enable those skilled in the art to better understand the solution of the present invention, below in conjunction in the embodiment of the present invention
Attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is only
The embodiment of a part of the invention, instead of all the embodiments.Based on the embodiments of the present invention, ordinary skill people
The every other embodiment that member is obtained without making creative work should all belong to the model that the present invention protects
It encloses.
Below by specific embodiment, it is described in detail respectively.
Referring to Fig. 2, the embodiment of the present invention provides a kind of fieldtron, including：
A kind of semiconductor substrate 301 with the first doping type；
Drain region 302 formed on 301 surface of the semiconductor substrate, with the first doping type；
Convex body 303 is formed on 302 surface of the drain region, the convex body 303 is perpendicular to the drain region surface, has the
A kind of fin ray or nano wire of doping type；
The grid 305 that drain region surface other than the convex body 303 is formed, the grid 305 are higher than the convex body 303,
And the grid between the grid 305 and the drain region 302 and between the grid 305 and the convex body 303 are situated between
Matter layer 304；
In the semiconductive thin film that the body structure surface that the gate dielectric layer 304 and the convex body 303 form is formed, as pocket
Layer 306；
In the source region 307 that 306 surface of pocket layer is formed, the source region 307 is half with second of doping type
Conductor material.
In some embodiments of the invention, the fieldtron further includes：
The electrode formed on the source region 307, the drain region 302 and the grid 305 respectively；It specifically includes：Drain region
Electrode 308, source region electrode 309 and gate electrode 310.
Optionally, the first described doping type is N-shaped, and second of doping type is p-type；Or, it is described the first
Doping type is p-type, and second of doping type is N-shaped.
Optionally, the semiconductor substrate 301 is body silicon, the silicon on insulator, germanium or Group III-V compound semiconductor material
Material, the nano wire and fin ray are silicon, germanium, germanium silicon or III-V compound semiconductor material, the pocket layer 306 be silicon,
Germanium, germanium silicon or III-V compound semiconductor material, the source region 307 are silicon, germanium, germanium silicon or Group III-V compound semiconductor
Material, the gate dielectric layer 304 are silica, silicon nitride, high dielectric material or other dielectric insulation materials, the grid
305 be metal, alloy or the polysilicon of doping.
Optionally, the electrode is aluminium or copper or aluminium alloy or copper alloy；It is provided between the drain region, grid and source region
Spacer 311, the spacer 311 are silica, silicon nitride or silicon oxynitride.
In the fieldtron of the embodiment of the present invention：
The source region 307 and the pocket layer 306 form tunnel junctions, and the tunnel junctions control carrier by gate electric field
Tunnelling, can realize the on and off of electric current in device.
The principle of technical solution of the embodiment of the present invention is as follows：
The embodiment of the present invention uses opisthogenesis replacement technique, and source region 307 forms the tunnel junctions of device with pocket layer 306, by grid
Electric field is come whether regulating and controlling to bring control carrier tunnelling, it is clear that the direction of carrier tunnelling is consistent with the direction of grid electric field, belongs to
In line tunneling mechanism, by taking enhanced N-channel field effect transistor as an example, source region 307 is adulterated for p-type, and drain region 302 is adulterated for N-shaped,
Pocket layer 306 adulterates for N-shaped, and convex body 303 (i.e. silicon fin or silicon nanowires) is used as raceway groove, the doping with semiconductor substrate 301
It is identical, it is adulterated for N-shaped, when the application forward voltage of grid 305, when drain region 302 applies reverse-biased, convex body 303 and gate dielectric layer 304
Surface can enter accumulated state, and convex body 303 and pocket layer 306 have a large amount of carrier to be gathered in surface, source region 307 and pocket layer
306 form tunnel junctions, and therefore, for electronics from 303 tunnelling of convex body to source region 307, source region 307 has electric current generation with drain region 302；Work as leakage
302 positively biased of area and when reverse-biased grid 305, without tunnelling carrier in tunnel junctions, no current generates between source region 307 and drain region 302.
In order to preferably implement the said program of the embodiment of the present invention, it is also provided below to be used to prepare and implements above-mentioned field-effect
The correlation technique of device, in the figure for convenience of explanation, the thickness of layer and region are amplified, and shown size does not represent reality
Size, reference chart be the present invention idealized embodiments schematic diagram, the present invention shown in embodiment should not be considered as only limiting
Deviation caused by specific shape in region as shown in the figure, but include obtained shape, such as manufacture, such as etching are convex
Body etc. has the characteristics that bending or mellow and full, but in embodiments of the present invention, is indicated with rectangle, but this should not be considered as
It limits the scope of the invention.
It please refers to Fig.2 and provides a kind of preparation side of fieldtron with Fig. 3 and Fig. 4 a to Fig. 4 j, the embodiment of the present invention
Method, this method may include：
401, as shown in fig. 4 a, to form alternative source on 301 surface of semiconductor substrate with the first doping type thin
Film layer 502 forms hard mask layer 501 in alternative thin-film surface, and alternative 502 material of source film layer is different from semiconductor lining
Bottom 301, and it is easy to removed, can be polysilicon, polycrystalline germanium or other similar materials, hard mask layer 501 is resistance to ion
The material of etching can be specifically silicon nitride etc., the first doping type can be n doping or p doping, and semiconductor substrate 301 can
Think body silicon, the silicon on insulator, germanium or III-V compound semiconductor material.
402, as shown in Figure 4 b, hard mask is defined using photoetching process, and using hard mask as mask, pass through etching technics
(such as reactive ion etching) performs etching alternative source film layer 502 and semiconductor substrate 301, in semiconductor substrate 301
Upper formation convex body 303, the thickness that substrate is etched can be 10 nanometers to hundreds of nanometers.
403, as illustrated in fig. 4 c, on generating structure, to carrying out autoregistration first type of semiconductor substrate 301
Ion implanting, and activation injection ion of annealing, form the drain region 302 of device.
404, as shown in figure 4d, in generated structure, deposition silica, silicon nitride, high dielectric material or other
Dielectric insulation material forms one layer of insulation film, as gate dielectric layer first part 3041, in gate dielectric layer first part 3041
Surface deposited metal, alloy or the polysilicon of doping form conductive film and planarize structure formed above as grid 305,
After planarizing, using carving technology etching grid 305 and gate dielectric layer first part 3041 is gone back to, until exposing hard mask layer
501,3041 thickness of gate dielectric layer first part is at 10 nanometers or less；Grid 305 is metal, alloy or the polysilicon of doping.
405, as shown in fig 4e, the exposed surface of grid 305 deposit silica, silicon nitride, high dielectric material or its
He forms one layer of insulation film at dielectric insulation material, as gate dielectric layer second part 3042, gate dielectric layer first part 3041
It is consistent with the generation material of gate dielectric layer second part 3042, it is connected with each other composition gate dielectric layer 304.
406, as shown in fig. 4f, alternative source film layer 502 and hard mask layer 501 are removed using lithographic technique.
407, as shown in figure 4g, silicon, germanium, germanium silicon or Group III-V compound semiconductor are precipitated on generated structure
Material forms layer of semiconductor film, and as pocket layer 306,306 thickness of pocket layer is between 1 nanometer and 10 nanometers.
408, as shown in figure 4h, in 306 Surface Creation source region 307 of pocket layer, source region 307 is with second of doping type
Semi-conducting material, source region 307 is inverted convex, and size do not limit.
409, as shown in figure 4i, further include before step 410：By lithographic technique above drain region 302 and grid 305
Rectangular area is formed on the outside of left area, 307 right side of source region forms rectangular area, rectangle region above 305 right area of grid
Domain upper surface is with source region upper surface flush, and in rectangular area, deposition electrically insulating material forms spacer 311, in order to step
Drain region electrode 308 and gate electrode 310 and the source region 307 formed in 410 is kept apart.
410, as shown in figure 4j, by the electrode window through ray of lithography and etching technology, opening drain region 302 and grid 305, in electricity
After 307 deposited metal of pole window and source region, by lift-off technology (lift-off), source region electrode 309, the drain region of device are formed
Electrode 308 and gate electrode 310.
It should be noted that structure as shown in fig. 4k, if the source region 307 with the pocket layer 306 only described convex
Between body 303 and the grid 305, and height be not higher than grid 305 when, pocket layer 306 compare and above structure, size subtract
Few, but do not influence performance, in this structure, 307 upper surface of source region is no more than the upper surface of grid 305, therefore gate dielectric layer second
Part 3042 can not generate, and step 405 need not execute, and concrete condition can be depending on actual state in technological process.
It should be noted that the first doping type is N-shaped, second of doping type is p-type；Or, it is described the first mix
Miscellany type is p-type, and second of doping type is N-shaped.
Optionally, the semiconductor substrate 301 is body silicon, the silicon on insulator, germanium or Group III-V compound semiconductor material
Material, the nano wire and fin ray are silicon, germanium, germanium silicon or III-V compound semiconductor material, the pocket layer 306 be silicon,
Germanium, germanium silicon or III-V compound semiconductor material, the source region 307 are silicon, germanium, germanium silicon or Group III-V compound semiconductor
Material, the gate dielectric layer 304 are silica, silicon nitride, high dielectric material or other dielectric insulation materials, the grid
305 be metal, alloy or the polysilicon of doping.
Optionally, the electrode is aluminium or copper or aluminium alloy or copper alloy；It is provided between the drain region, grid and source region
Spacer 311, the spacer 311 are silica, silicon nitride or silicon oxynitride.
To sum up, the fieldtron of the embodiment of the present invention forms source region, mouth by forming pocket layer in pocket layer surface
Bag layer constitutes the tunnel junctions of device with source region, thus, it has the following technical effect that：
(1), the device is using opisthogenesis replacement technique, i.e., in the last making source region of technological process, in technological process
Behind make pocket layer and source region so that a plurality of types of heterogeneous tunnel junctions can be selected in the preparation, improve preparation source
The engineering flexibility ratio of the heterogeneous tunnel junctions in area；
(2), source region with the contact surface of tunnel junctions and gate dielectric layer that pocket layer forms is vertical, carrier in the device
The direction of tunnelling is necessarily consistent with the direction of grid electric field, which belongs to line tunneling mechanism, and grid voltage controls the tunnel of carrier
It wears, the direction of carrier tunnelling is consistent with the direction of grid electric field in line tunneling mechanism, therefore the voltage control capability of grid obtains
Reinforce, and tunnelling current size can also be regulated and controled by the overlapping area of grid and tunnel junctions, improve tunneling efficiency,
In addition, quantum-mechanical mechanisms of the line tunneling mechanism due to its unique inter-band tunneling, can reduce subthreshold swing.
In the above-described embodiments, it all emphasizes particularly on different fields to the description of each embodiment, is not described in some embodiment
Part, may refer to the associated description of other embodiments.
It should be noted that for each method embodiment above-mentioned, for simple description, therefore it is all expressed as a series of
Combination of actions, but those skilled in the art should understand that, the present invention is not limited by described sequence of movement because according to
According to the present invention, certain steps may be used other sequences or be carried out at the same time.Next, those skilled in the art should also know that,
Embodiment described in this description belongs to preferred embodiment, and not necessarily the present invention must for involved action and module
Must.
The above, the above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although with reference to before
Stating embodiment, invention is explained in detail, it will be understood by those of ordinary skill in the art that：It still can be to preceding
The technical solution recorded in each embodiment is stated to modify or equivalent replacement of some of the technical features；And these
Modification or replacement, the spirit and scope for various embodiments of the present invention technical solution that it does not separate the essence of the corresponding technical solution.
Claims (10)
1. a kind of fieldtron, which is characterized in that including：
Semiconductor substrate with the first doping type；
Drain region formed in the semiconductor substrate surface, with the first doping type；
In the convex body that the drain region surface is formed, the convex body is perpendicular to the drain region surface, has the first doping class
The fin ray or nano wire of type；
The grid that drain region surface other than the convex body is formed, the grid are higher than the convex body；
The gate dielectric layer formed between the grid and the convex body between the grid and the drain region；
In the semiconductive thin film that the body structure surface that the gate dielectric layer and the convex body form is formed, as pocket layer；
In the source region that the pocket layer surface is formed, the source region is the semi-conducting material of second of doping type；
The convex body is as the raceway groove between the drain region and the source region.
2. fieldtron according to claim 1, which is characterized in that further include：
The electrode formed on the source region, the drain region and the grid respectively.
3. fieldtron according to claim 1, which is characterized in that the source region and the pocket layer form tunnelling
Knot, the tunnel junctions are controlled the tunnelling of carrier by gate electric field, can realize the on and off of electric current in device.
4. fieldtron according to any one of claim 1 to 3, it is characterised in that：
The first described doping type is N-shaped, and second of doping type is p-type；
Or, the first described doping type is p-type, second of doping type is N-shaped.
5. fieldtron according to any one of claim 1 to 3, it is characterised in that：
The semiconductor substrate is body silicon, the silicon on insulator, germanium or III-V compound semiconductor material, the nano wire
It is silicon, germanium, germanium silicon or III-V compound semiconductor material with fin ray, the pocket layer is silicon, germanium, germanium silicon or iii-v
Object semi-conducting material is closed, the source region is silicon, germanium, germanium silicon or III-V compound semiconductor material, and the gate dielectric layer is two
Silica, silicon nitride or high dielectric material, the grid are metal, alloy or the polysilicon of doping.
6. fieldtron according to claim 2, it is characterised in that：
The electrode is aluminium or copper or aluminium alloy or copper alloy；
Spacer is provided between the drain region, grid and source region, the spacer is silica, silicon nitride or nitrogen oxidation
Silicon.
7. a kind of preparation method of fieldtron as described in claim 1, which is characterized in that including：
Alternative source film layer is formed in the semiconductor substrate surface with the first doping type；
Deposit hard mask layer in the alternative source thin-film surface, and by lithography and etching technique define device convex body and
The position in drain region, the convex body are fin ray or nano wire with the first doping type；
Using the hard mask layer as mask, the alternative source film layer is etched by reactive ion etching technology and described is partly led
Body substrate forms the convex body；
Using the hard mask layer as mask, by carrying out the ion implanting of the first doping type to the semiconductor substrate, and
Annealing activates the injection ion, forms the drain region；
Gate dielectric layer first part is formed being formed by body structure surface；
Grid is formed on the gate dielectric layer first part, and etches the grid and the gate dielectric layer first part,
Expose the hard mask layer；
Gate dielectric layer second part is formed in the exposed surface of the grid, and removes the hard mask layer and the alternative source
Film layer, the gate dielectric layer of the gate dielectric layer first part and gate dielectric layer second part composition device；
Semiconductive thin film is formed being formed by body structure surface, as pocket layer；
Source region is formed in the pocket layer surface, the source region is the semi-conducting material with second of doping type.
8. the method according to the description of claim 7 is characterized in that further including：
The electrode window through ray that drain region and source region and grid are opened by lithography and etching technology is divided in electrode window through ray deposited metal
Electrode is not formed on drain region and source region and grid.
9. the method according to claim 7 or 8, it is characterised in that：
The first described doping type is N-shaped, and second of doping type is p-type；
Alternatively, the first described doping type is p-type, second of doping type is N-shaped.
10. the method according to claim 7 or 8, it is characterised in that：
The alternative source film layer is polysilicon or polycrystalline germanium, and the hard mask layer is the material of resistance to ion etching.
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| CN107924941B (en) | 2015-09-01 | 2020-09-04 | 华为技术有限公司 | Tunneling field effect transistor and preparation method thereof |
| CN108352401A (en) * | 2015-11-11 | 2018-07-31 | 华为技术有限公司 | Tunneling field-effect transistor and preparation method thereof |
| US9431305B1 (en) | 2015-12-18 | 2016-08-30 | International Business Machines Corporation | Vertical transistor fabrication and devices |
| CN105633142B (en) * | 2016-03-29 | 2018-07-27 | 电子科技大学 | A kind of tunneling field-effect transistor inhibiting off-state current |
| CN108369960A (en) * | 2016-04-22 | 2018-08-03 | 华为技术有限公司 | Tunneling field-effect transistor and its manufacturing method |
| CN109478562B (en) * | 2016-11-17 | 2022-04-22 | 华为技术有限公司 | Tunneling field effect transistor and manufacturing method thereof |
| CN108369954B (en) * | 2016-11-26 | 2021-02-23 | 华为技术有限公司 | Tunneling field effect transistor and manufacturing method thereof |
| WO2018148909A1 (en) * | 2017-02-16 | 2018-08-23 | 华为技术有限公司 | Method for fabricating tunneling field effect transistor |
| CN109716490B (en) * | 2017-08-21 | 2021-05-11 | 华为技术有限公司 | TFET and preparation method thereof |
| CN112002760B (en) * | 2020-08-28 | 2023-05-23 | 河南师范大学 | MnBi-based alloy 2 Te 4 Single layer nanoscale field effect transistor |
| CN113078208A (en) * | 2021-03-09 | 2021-07-06 | 深圳大学 | Surrounding grid field effect transistor and preparation method thereof |
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| US8026509B2 (en) * | 2008-12-30 | 2011-09-27 | Intel Corporation | Tunnel field effect transistor and method of manufacturing same |
| US8309989B2 (en) * | 2010-08-18 | 2012-11-13 | Purdue Research Foundation | Tunneling field-effect transistor with low leakage current |
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| CN101416288A (en) * | 2006-04-04 | 2009-04-22 | 美光科技公司 | Grown nanofin transistors |
| CN103779418A (en) * | 2014-02-08 | 2014-05-07 | 华为技术有限公司 | Tunnel penetration field-effect transistor of novel structure and preparation method thereof |
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