CN113078208A - Surrounding grid field effect transistor and preparation method thereof - Google Patents

Surrounding grid field effect transistor and preparation method thereof Download PDF

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CN113078208A
CN113078208A CN202110258903.XA CN202110258903A CN113078208A CN 113078208 A CN113078208 A CN 113078208A CN 202110258903 A CN202110258903 A CN 202110258903A CN 113078208 A CN113078208 A CN 113078208A
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layer
channel region
effect transistor
field effect
semiconductor substrate
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刘新科
杨嘉颖
陈勇
王磊
林峰
利健
宋利军
何文龙
姜全忠
贺威
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Shenzhen University
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    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
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    • H01L29/66409—Unipolar field-effect transistors
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    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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Abstract

The invention provides a surrounding grid field effect transistor and a preparation method thereof, wherein the surrounding grid field effect transistor comprises: a semiconductor substrate; a semiconductor nanowire located on the semiconductor substrate, the semiconductor nanowire comprising a channel region; the gate dielectric layer is positioned on the semiconductor substrate and surrounds the channel region; and the interface layer is positioned on the semiconductor substrate, is positioned between the channel region and the gate dielectric layer and is suitable for preventing oxygen in the gate dielectric layer from diffusing to the channel region. The surrounding gate field effect transistor has a stable threshold voltage.

Description

Surrounding grid field effect transistor and preparation method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a surrounding grid field effect transistor and a preparation method thereof.
Background
The Field Effect Transistor (Field Effect Transistor) has the outstanding characteristics that the control capability of a grid layer on a channel is very excellent, so that the Field Effect Transistor can generate faster driving current, the width of the channel is allowed to be further reduced, so that the integration degree is higher, and low driving voltage, low threshold voltage and high switching current ratio can be realized, High current density and high power density, suitable for low power consumption applications.
However, in the conventional gate-around field effect transistor, high-density traps are easily generated at the interface between the gate dielectric layer and the semiconductor nanowire, so that the threshold voltage is unstable.
Disclosure of Invention
Therefore, the technical problem to be solved by the present invention is to overcome the defect of unstable threshold voltage of the conventional surrounding gate field effect transistor, thereby providing a surrounding gate field effect transistor and a method for manufacturing the same.
The invention provides a gate-wrap field effect transistor, comprising: a semiconductor substrate; a semiconductor nanowire located on the semiconductor substrate, the semiconductor nanowire comprising a channel region; the gate dielectric layer is positioned on the semiconductor substrate and surrounds the channel region; and the interface layer is positioned on the semiconductor substrate, is positioned between the channel region and the gate dielectric layer and is suitable for preventing oxygen in the gate dielectric layer from diffusing to the channel region.
Optionally, the oxygen content in the interfacial layer is greater than or equal to 0 and less than 0.1%.
Optionally, the material of the interfacial layer includes aluminum nitride; the material of the gate dielectric layer comprises aluminum oxide.
Optionally, the semiconductor nanowire comprises a GaN-based semiconductor nanowire.
Optionally, the thickness of the interface layer is 2nm to 4 nm.
Optionally, the diameter of the semiconductor nanowire is no more than 6 nm.
Optionally, the surrounding gate field effect transistor is a vertical surrounding gate field effect transistor.
Optionally, the semiconductor nanowire further includes a source region and a drain region respectively located at two sides of the channel region, the drain region, the channel region and the source region are arranged along an extending direction of the semiconductor nanowire, and the drain region is located between the channel region and the semiconductor substrate; the surrounding gate field effect transistor further includes: a first isolation layer on the semiconductor substrate, the first isolation layer surrounding the drain region; the gate dielectric layer and the interface layer are located on the first isolation layer.
The invention also provides a preparation method of the surrounding grid field effect transistor, which comprises the following steps: providing a semiconductor substrate; forming a semiconductor nanowire on the semiconductor substrate, the semiconductor nanowire comprising a channel region; forming an interface layer surrounding the channel region on the semiconductor substrate; after the interface layer is formed, a gate dielectric layer surrounding the interface layer is formed on the semiconductor substrate; the interface layer is suitable for blocking oxygen in the gate dielectric layer from diffusing to the channel region.
Optionally, the surrounding gate field effect transistor is a vertical surrounding gate field effect transistor; the semiconductor nanowire further comprises a source region and a drain region which are respectively positioned on two sides of the channel region, the drain region, the channel region and the source region are arranged along the extending direction of the semiconductor nanowire, and the drain region is positioned between the channel region and the semiconductor substrate; the preparation method of the surrounding grid field effect transistor further comprises the following steps: and before the interface layer and the gate dielectric layer are formed, forming the first isolation layer on the semiconductor substrate, wherein the first isolation layer surrounds the drain region and exposes the channel region and the source region.
Optionally, the step of forming the interface layer includes: forming an initial interface film covering the first isolation layer and surfaces of the channel region and the source region of the semiconductor nanowire; and etching the initial interface film back until the surface of the first isolation layer, the top surface of the source region and the side wall surface are exposed to form the interface layer.
Optionally, the process for forming the initial interface film includes a plasma enhanced chemical vapor deposition process or an atomic layer deposition process; the process of etching back the initial interface film includes an anisotropic plasma etch process.
The technical scheme of the invention has the following advantages:
1. according to the gate-surrounding field effect transistor, the interface layer is arranged between the channel region of the semiconductor nanowire and the gate dielectric layer, so that the channel region and the gate dielectric layer can be isolated by the interface layer, oxygen atoms in the gate dielectric layer can be prevented from being diffused to the channel region in the process of forming the gate dielectric layer by the interface layer, the oxygen atoms are prevented from entering a vacancy of the channel region and generating oxide at the interface of the gate dielectric layer and the semiconductor nanowire, high-density traps are prevented from being generated, the interface quality is improved, the control capability of the gate layer on the channel region and the transmission capability of the gate-surrounding field effect transistor are improved, and the stability of the threshold voltage of the gate-surrounding field effect transistor is ensured.
2. According to the surrounding gate field effect transistor provided by the invention, the thickness of the interface layer is 2nm-4 nm. The smaller the thickness of the interface layer is, the smaller the total thickness of the interface layer and the gate dielectric layer is, and the larger the total capacitance of the interface layer and the gate dielectric layer is, so that under the same gate layer voltage, the more charges can be stored in the interface layer and the gate dielectric layer, the larger the current is, namely, the smaller the thickness of the interface layer is, the stronger the current control capability of the gate layer on the channel is; however, when the thickness of the interface layer is too small, the total thickness of the interface layer and the gate dielectric layer is too small, and an electric field with a larger intensity is easily generated by an external voltage applied to the surrounding gate field effect transistor, so that the surrounding gate field effect transistor is broken down, and the service life of the surrounding gate field effect transistor is influenced. By limiting the thickness of the interface layer to be 2nm-4nm, on one hand, the gate layer has stronger control capability on a channel, on the other hand, the surrounding gate field effect transistor is prevented from being broken down, and the service life of the surrounding gate field effect transistor is ensured.
3. According to the gate-surrounding field effect transistor, the diameter of the semiconductor nanowire is limited to be not more than 6nm, so that the distance between the central axis of the channel region and the outer surface layer of the channel region is smaller, the current density difference between the central axis and the outer surface layer is reduced, the uniformity of current distribution of the channel region in the radial direction of the channel region is improved, the current of the outer surface of the channel region is equal to the current of the central axis of the channel region, the effective area of the channel region, through which the current passes, is the actual area of the channel region, the effective on-resistance is reduced, and the power consumption is reduced; meanwhile, the smaller diameter of the semiconductor nanowire enables the surrounding gate field effect transistor to have a smaller size, so that the integration level of the surrounding gate field effect transistor is improved.
4. The preparation method of the field effect transistor surrounding the grid electrode provided by the invention forms the interface layer surrounding the channel region after the semiconductor nanowire is formed and before the grid dielectric layer is formed, so that the interface layer is positioned between the semiconductor nanowire and the grid dielectric layer, the channel region can be separated from the grid dielectric layer by the interface layer, the interface layer can prevent oxygen atoms in the gate dielectric layer from diffusing to the channel region in the process of forming the gate dielectric layer, so that the oxygen atoms are prevented from entering vacancies in the channel region and generating oxides at the interface between the gate dielectric layer and the semiconductor nanowire, thereby avoiding the generation of high-density traps and improving the interface quality, and the control capability of the grid layer on the channel region and the transmission capability of the surrounding grid field effect transistor are further improved, and the stability of the threshold voltage of the surrounding grid field effect transistor is ensured.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic diagram of a gate-wrap field effect transistor;
fig. 2 is a schematic structural diagram of a surrounding gate field effect transistor according to embodiment 1 of the present invention;
fig. 3-14 are schematic structural diagrams of a surrounding gate field effect transistor provided in example 2 during a manufacturing process of the surrounding gate field effect transistor;
description of reference numerals:
1-a semiconductor substrate; 2-a semiconductor nanowire; 21-a drain region; 22-a channel region; 23-a source region; 24-a first semiconductor film; 25-a second semiconductor film; 26-a third semiconductor film; 3-an interfacial layer; 4-a gate dielectric layer; 5-a gate layer; 6-a first isolation layer; 7-a second isolation layer; 8-a source electrode layer; 9-drain electrode layer.
Detailed Description
As shown in fig. 1, a gate-all-around field effect transistor includes: a semiconductor substrate 1; the semiconductor nanowire 2 is positioned on the semiconductor substrate 1, the semiconductor nanowire 2 comprises a channel region 22 and a source region 23 and a drain region 21 which are respectively positioned at two sides of the channel region 22, and the drain region 21, the channel region 22 and the source region 23 are arranged along the extending direction of the semiconductor nanowire 2; a first isolation layer 6 on the semiconductor substrate, the first isolation layer 6 surrounding the drain region 21; the gate dielectric layer 4' is positioned on the first isolation layer 6 and surrounds the channel region 22, and the material of the gate dielectric layer comprises metal oxide; a gate layer 5 on the first isolation layer 6, the gate layer surrounding the gate dielectric layer; a second isolation layer 7 surrounding the source region 23; a source electrode layer 8 located on a side of the semiconductor nanowire 2 facing away from the semiconductor substrate 1; and the drain electrode layer 9 is positioned on the side, away from the gate electrode layer 5, of the semiconductor substrate 1. Forming a gate dielectric layer by adopting an atomic deposition process or a plasma enhanced chemical vapor deposition process; specifically, metal halide and oxygen are introduced into the chamber, and the metal halide and the oxygen chemically react to generate metal oxide. However, vacancies exist in the semiconductor nanowire, and even if the vacancies are compensated for, the vacancies still exist. Oxygen atoms in oxygen enter vacancies of the semiconductor nanowire in the preparation process of the gate dielectric layer, so that oxide is generated at the interface of the gate dielectric and the semiconductor nanowire, a high-density trap is generated, the control capability of a gate layer on a channel and the transmission capability of a field effect transistor surrounding the gate are reduced, and the threshold voltage is unstable.
Specifically, when the semiconductor nanowire is a GaN-based semiconductor nanowire, a nitrogen vacancy exists in the semiconductor nanowire, oxygen atoms in oxygen enter the nitrogen vacancy in the preparation process of the gate dielectric layer, and the generated high-density trap is oxide GaOx。
On the basis, the invention provides a surrounding grid field effect transistor, which comprises: a semiconductor substrate; a semiconductor nanowire located on the semiconductor substrate, the semiconductor nanowire comprising a channel region; the gate dielectric layer is positioned on the semiconductor substrate and surrounds the channel region; and the interface layer is positioned on the semiconductor substrate, is positioned between the channel region and the gate dielectric layer and is suitable for preventing oxygen in the gate dielectric layer from diffusing to the channel region. The surrounding gate field effect transistor has a stable threshold voltage.
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "inside", "outside", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention.
Example 1
Referring to fig. 2, the present embodiment provides a gate-all-around field effect transistor, including: a semiconductor substrate 1; a semiconductor nanowire 2 located on the semiconductor substrate 1, the semiconductor nanowire 2 comprising a channel region 22; the gate dielectric layer 4 is positioned on the semiconductor substrate 1, and the gate dielectric layer 4 surrounds the channel region 22; and the interface layer 3 is positioned on the semiconductor substrate 1, the interface layer 3 is positioned between the channel region 22 and the gate dielectric layer 4, and the interface layer is suitable for blocking oxygen in the gate dielectric layer from diffusing to the channel region.
According to the gate-surrounding field effect transistor, the interface layer is arranged between the channel region of the semiconductor nanowire and the gate dielectric layer, so that the channel region and the gate dielectric layer can be isolated by the interface layer, oxygen atoms in the gate dielectric layer can be prevented from diffusing to the channel region in the process of forming the gate dielectric layer by the interface layer, the oxygen atoms are prevented from entering a vacancy of the channel region and generating oxide at the interface of the gate dielectric layer and the semiconductor nanowire, high-density traps are prevented from being generated, the interface quality is improved, the control capability of the gate layer on the channel region and the transmission capability of the gate-surrounding field effect transistor are improved, and the stability of the threshold voltage of the gate-surrounding field effect transistor is ensured.
In the present embodiment, the semiconductor substrate 1 includes, but is not limited to, a SiC-based semiconductor substrate or a GaN-based semiconductor substrate; preferably, the semiconductor substrate 1 is a GaN-based semiconductor substrate. Further, the semiconductor substrate 1 is an N-type semiconductor substrate. Specifically, when the semiconductor substrate 1 is a GaN-based semiconductor substrate, the dopant in the semiconductor substrate 1 includes, but is not limited to, silicon; when the semiconductor substrate 1 is a SiC-based semiconductor substrate, the dopant species in the semiconductor substrate 1 includes, but is not limited to, phosphorus; further, the doping concentration of the doping substance in the semiconductor substrate 1 is 3 × 1018atom/cm3-8×1018atom/cm3. The thickness of the semiconductor substrate 1 is 250-350 μm; preferably, the thickness of the semiconductor substrate 1 may be 250 μm, 300 μm, or 350 μm.
In the present embodiment, the material of the gate dielectric layer 4 includes, but is not limited to, Al2O3。
In the present embodiment, the semiconductor nanowire 2 comprises a GaN-based semiconductor nanowire. Further, the material of the semiconductor nanowire 2 is an N-type semiconductor material. Specifically, the semiconductor nanowire 2 is doped with a doping material, which includes but is not limited to silicon. The semiconductor nanowire 2 further comprises a source region 23 and a drain region 21 which are respectively located at two sides of the channel region 22, the drain region 21, the channel region 22 and the source region 23 are arranged along the extending direction of the semiconductor nanowire 2, and the drain region 21 is located between the channel region 22 and the semiconductor substrate 1.
The doping concentration of the channel region 22 is less than that of the drain region 21, and the doping concentration of the channel region 22 is less than that of the source region 23;in one embodiment, the doping concentration of the drain region 21 is equal to the doping concentration of the source region 23. Specifically, the doping concentration of the drain region 21 is 1 × 1018atom/cm3-4x1018atom/cm3The doping concentration of the channel region 22 is 1x1015 atom/cm3-8x1015 atom/cm3The doping concentration of the source region 23 is 1x1018atom/cm3-4x1018 atom/cm3. Preferably, the doping concentration of the drain region 21 is 2 × 1018 atom/cm3The doping concentration of the channel region 22 is 5x1015 atom/cm3The doping concentration of the source region 23 is 2x1018 atom/cm3。
Further, along the extension direction of the semiconductor nanowire 2, the size of the channel region 22 is larger than that of the drain region 21, and the size of the channel region 22 is equal to that of the source region 23; in an embodiment, the size of the drain region 21 is equal to the size of the source region 23 along the extension direction of the semiconductor nanowire 2. Specifically, along the extending direction of the semiconductor nanowire 2, the size of the drain region 21 is 0.2 μm to 0.5 μm, the size of the channel region 22 is 0.3 μm to 0.6 μm, and the size of the source region 23 is 0.2 μm to 0.5 μm. Preferably, along the extension direction of the semiconductor nanowire 2, the size of the drain region 21 is 0.3 μm, the size of the channel region 22 is 0.4 μm, and the size of the source region 23 is 0.3 μm.
In this embodiment, the oxygen content in the interfacial layer 3 is 0% or more and less than 0.1%. The micro oxygen content in the interface layer 3 can prevent oxygen atoms from entering a vacancy of a channel region and generating oxide at an interface between a gate dielectric layer and the channel region in the forming process of the interface layer 3, so that the generation of high-density traps is avoided, the interface quality is improved, the control capability of a gate layer on the channel and the transmission capability of a surrounding gate field effect transistor are improved, and the stability of the threshold voltage of the surrounding gate field effect transistor is ensured. Illustratively, the oxygen content may be 0, 0.01%, 0.02%, 0.03%, 0.04%, 0.05%, 0.06%, 0.07%, 0.08%, or 0.09%.
Preferably, the material of the interfacial layer 3 includes aluminum nitride. The aluminum nitride has high density, and oxygen atoms enter the vacancy of the semiconductor nanowire 2 through the aluminum nitride with high difficulty, so that the difficulty of generating a high-density trap on the interface between the semiconductor nanowire 2 and the gate dielectric layer 4 is avoided, and the stability of threshold voltage of the field effect transistor surrounding the gate is ensured.
In this embodiment, the thickness of the interfacial layer 3 is 2nm to 4 nm. The smaller the thickness of the interfacial layer 3 is, the smaller the total thickness of the interfacial layer 3 and the gate dielectric layer 4 is, so that the larger the total capacitance of the interfacial layer 3 and the gate dielectric layer 4 is, and the more charges can be stored in the interfacial layer 3 and the gate dielectric layer 4 under the same voltage of the gate layer 5, the larger the current is, that is, the smaller the thickness of the interfacial layer 3 is, the stronger the current control capability of the gate layer 5 on the channel is; however, when the thickness of the interfacial layer 3 is too small, the total thickness of the interfacial layer 3 and the gate dielectric layer 4 is too small, and an electric field with a larger intensity is easily generated by an applied voltage applied to the surrounding gate field effect transistor, so that the surrounding gate field effect transistor is broken down, and the service life of the surrounding gate field effect transistor is affected. By limiting the thickness of the interface layer 3 to be 2nm-4nm, on one hand, the gate layer 5 has stronger control capability on a channel, on the other hand, the surrounding gate field effect transistor is prevented from being broken down, and the service life of the surrounding gate field effect transistor is ensured. Illustratively, the thickness of the interfacial layer 3 may be 2nm, 2.5nm, 3nm, 3.5nm, or 4 nm.
It should be understood that, as shown in fig. 2, the interface layer is annular, and the thickness of the interface layer in this embodiment refers to the difference between the outer diameter and the inner diameter of the interface layer; the interface layer and the gate dielectric layer also form a ring shape, and the total thickness of the interface layer and the gate dielectric layer in this embodiment refers to the difference between the outer diameter of the gate dielectric layer and the inner diameter of the interface layer.
When the existing gate-around field effect transistor device is turned on, a skin effect phenomenon exists, that is, the current distribution through the channel region 22 is not uniform, the current density gradually increases along the radial direction of the semiconductor nanowire 2, the current is mainly concentrated on the skin part of the channel region 22, that is, the outer surface layer of the channel region 22, and the current at the central axis of the channel region 22 is small. This results in a smaller effective area for the channel region 22 to pass current and an increased effective on-resistance, resulting in increased power consumption.
In this embodiment, the diameter of the semiconductor nanowire 2 does not exceed 6 nm. By limiting the diameter of the semiconductor nanowire 2 to be not more than 6nm, the distance between the central axis of the channel region 22 and the outer surface layer of the channel region 22 is smaller, so that the current density difference between the central axis and the outer surface layer is reduced, the uniformity of current distribution of the channel region 22 along the radius direction of the channel region 22 is improved, the current on the outer surface of the channel region 22 is equal to the current on the central axis of the channel region 22, the effective area of the channel region 22 through which the current passes is the actual area of the channel region 22, the effective on-resistance is reduced, and the power consumption is reduced; meanwhile, the smaller diameter of the semiconductor nanowire 2 enables the size of the surrounding gate field effect transistor to be smaller, thereby improving the integration level of the surrounding gate field effect transistor. Illustratively, the semiconductor nanowire 2 may have a diameter of 1nm, 2nm, 3nm, 4nm, 5nm, or 6 nm.
In this embodiment, the surrounding gate field effect transistor is a vertical surrounding gate field effect transistor. Specifically, as shown in fig. 2, the surrounding gate field effect transistor further includes: a first isolation layer 6 on the semiconductor substrate 1, the first isolation layer 6 surrounding the drain region 21; the gate layer 5 is positioned on the semiconductor substrate 1, and the gate layer 5 surrounds the gate dielectric layer 4; a second isolation layer 7 on the semiconductor substrate 1, the second isolation layer 7 surrounding the source region 23; a source electrode layer 8 located on a side of the semiconductor nanowire 2 facing away from the semiconductor substrate 1, the source electrode layer 8 being electrically connected to the source region 23; and the drain electrode layer 9 is positioned on the side, away from the gate electrode layer 5, of the semiconductor substrate 1, and the drain electrode layer 9 is electrically connected with the drain region 21.
Further, the first isolation layer 6 includes, but is not limited to, aluminum oxide; the material of the gate layer 5 includes but is not limited to chromium; the material of the second isolation layer 7 includes but is not limited to silicon dioxide; the material of the source electrode layer 8 is gold, the thickness of the source electrode layer 8 is 150nm-250nm, and exemplarily, the thickness of the source electrode layer 8 may be 150nm, 175nm, 200nm, 225nm or 250 nm; or, the source electrode layer 8 includes a first titanium layer, a first aluminum layer, a first nickel layer and a first gold layer, which are sequentially stacked, the first titanium layer is in contact with the second isolation layer 7 and the source region 23, the arrangement direction of the first titanium layer, the first aluminum layer, the first nickel layer and the first gold layer is perpendicular to the surface of the semiconductor substrate 1, the thickness of the first titanium layer is 20nm to 30nm, the thickness of the first aluminum layer is 70nm to 80nm, the thickness of the first nickel layer is 20nm to 30nm, the thickness of the first gold layer is 70nm to 80nm, preferably, the thickness of the first titanium layer is 25nm, the thickness of the first aluminum layer is 75nm, the thickness of the first nickel layer is 25nm, and the thickness of the first gold layer is 75 nm; by defining the source electrode layer 8 as the above material, a good ohmic contact between the source electrode layer 8 and the source region 23 is ensured, and it is understood that the material of the source electrode layer 8 includes, but is not limited to, the above materials. The material of the drain electrode layer 9 is gold, the thickness of the drain electrode layer 9 is 150nm-250nm, and exemplarily, the thickness of the drain electrode layer 9 can be 150nm, 175nm, 200nm, 225nm or 250 nm; or, the drain electrode layer 9 includes a second titanium layer, a second aluminum layer, a second nickel layer and a second gold layer which are sequentially stacked, the second titanium layer contacts with the semiconductor substrate 1, the arrangement direction of the second titanium layer, the second aluminum layer, the second nickel layer and the second gold layer is perpendicular to the surface of the semiconductor substrate 1, the thickness of the second titanium layer is 20nm to 30nm, the thickness of the second aluminum layer is 70nm to 80nm, the thickness of the second nickel layer is 20nm to 30nm, the thickness of the second gold layer is 70nm to 80nm, preferably, the thickness of the second titanium layer is 25nm, the thickness of the second aluminum layer is 75nm, the thickness of the second nickel layer is 25nm, and the thickness of the second gold layer is 75 nm; by defining the drain electrode layer 9 as a material as described above, a good ohmic contact between the drain electrode layer 9 and the drain region 21 is ensured, and it is to be understood that the material of the drain electrode layer 9 includes, but is not limited to, the above materials.
Example 2
The embodiment provides a preparation method of a gate-surrounding field effect transistor, which comprises the following steps: providing a semiconductor substrate 1; forming a semiconductor nanowire 2 on the semiconductor substrate 1, the semiconductor nanowire 2 comprising a channel region 22; forming an interfacial layer 3 surrounding the channel region 22 on the semiconductor substrate 1; after the interface layer 3 is formed, a gate dielectric layer 4 surrounding the interface layer 3 is formed on the semiconductor substrate 1; the interfacial layer 3 is adapted to block oxygen in the gate dielectric layer 4 from diffusing into the channel region 22.
In the preparation method of the gate surrounding field effect transistor, after the semiconductor nanowire is formed and before the gate dielectric layer is formed, the interface layer surrounding the channel region is formed, so that the interface layer is positioned between the semiconductor nanowire and the gate dielectric layer and can isolate the channel region from the gate dielectric layer, the interface layer can prevent oxygen atoms in the gate dielectric layer from diffusing to the channel region in the process of forming the gate dielectric layer, so that the oxygen atoms are prevented from entering vacancies in the channel region and generating oxides at the interface between the gate dielectric layer and the semiconductor nanowire, thereby avoiding the generation of high-density traps and improving the interface quality, and the control capability of the grid layer on the channel region and the transmission capability of the surrounding grid field effect transistor are further improved, and the stability of the threshold voltage of the surrounding grid field effect transistor is ensured.
The technical solution of the present invention will be clearly and completely described with reference to fig. 3-14.
Referring to fig. 3, a semiconductor substrate 1 is provided.
Specifically, the semiconductor substrate 1 includes, but is not limited to, a SiC-based semiconductor substrate or a GaN-based semiconductor substrate; preferably, the semiconductor substrate 1 is a GaN-based semiconductor substrate. Further, the semiconductor substrate 1 is an N-type semiconductor substrate. Specifically, when the semiconductor substrate 1 is a GaN-based semiconductor substrate, the dopant in the semiconductor substrate 1 includes, but is not limited to, silicon; when the semiconductor substrate 1 is a SiC-based semiconductor substrate, a dopant substance in the semiconductor substrate 1Including but not limited to phosphorus; further, the doping concentration of the doping substance in the semiconductor substrate 1 is 3 × 1018atom/cm3-8×1018atom/cm3。
Referring to fig. 4-7, a semiconductor nanowire 2 is formed on the semiconductor substrate 1, the semiconductor nanowire 2 including a channel region 22.
Specifically, the surrounding gate field effect transistor is a vertical surrounding gate field effect transistor; the preparation method of the semiconductor nanowire 2 comprises the following steps: referring to fig. 4, a first semiconductor film 24 is formed on the surface of the semiconductor substrate 1; referring to fig. 5, a second semiconductor film 25 is formed on the surface of the first semiconductor film 24; referring to fig. 6, a third semiconductor film 26 is formed on the surface of the second semiconductor film 25; referring to fig. 7, the third semiconductor film 26, the second semiconductor film 25, and the first semiconductor film 24 are patterned to form a cylindrical semiconductor nanowire 2.
The semiconductor nanowire 2 includes: a channel region 22, and a source region 23 and a drain region 21 respectively located at both sides of the channel region 22, wherein the drain region 21, the channel region 22, and the source region 23 are arranged along an extending direction of the semiconductor nanowire 2, the drain region 21 is formed of the patterned first semiconductor film 24, the channel region 22 is formed of the patterned second semiconductor film 25, and the source region 23 is formed of the patterned third semiconductor film 26.
Further, methods of forming the first semiconductor film 24, the second semiconductor film 25, and the third semiconductor film 26 are all Metal Organic Chemical Vapor Deposition (MOCVD) processes; obtaining the semiconductor nanowire 2 by sequentially performing dry etching and wet etching on the third semiconductor film 26, the second semiconductor film 25 and the first semiconductor film 24, wherein a gas used for the dry etching includes Cl2And SiCl4The solution used for wet etching includes a tetramethylammonium hydroxide (TMAH) solution.
In the present embodiment, the semiconductor nanowire 2 comprises a GaN-based semiconductor nanowire. Further, the material of the semiconductor nanowire 2 is an N-type semiconductor material. Specifically, the semiconductorThe nanowires 2 are doped with a doping material, including but not limited to silicon. The semiconductor nanowire 2 further comprises a source region 23 and a drain region 21 which are respectively located at two sides of the channel region 22, the drain region 21, the channel region 22 and the source region 23 are arranged along the extending direction of the semiconductor nanowire 2, the doping concentration of the channel region 22 is less than that of the drain region 21, and the doping concentration of the channel region 22 is less than that of the source region 23; in one embodiment, the doping concentration of the drain region 21 is equal to the doping concentration of the source region 23. Specifically, the doping concentration of the drain region 21 is 1 × 1018 atom/cm3-4x1018 atom/cm3The doping concentration of the channel region 22 is 1x1015 atom/cm3-8x1015 atom/cm3The doping concentration of the source region 23 is 1x1018atom/cm3-4x1018 atom/cm3. Preferably, the doping concentration of the drain region 21 is 2 × 1018 atom/cm3The doping concentration of the channel region 22 is 5x1015 atom/cm3The doping concentration of the source region 23 is 2x1018 atom/cm3。
Further, along the extension direction of the semiconductor nanowire 2, the size of the channel region 22 is larger than that of the drain region 21, and the size of the channel region 22 is equal to that of the source region 23; in an embodiment, the size of the drain region 21 is equal to the size of the source region 23 along the extension direction of the semiconductor nanowire 2. Specifically, along the extending direction of the semiconductor nanowire 2, the size of the drain region 21 is 0.2 μm to 0.5 μm, the size of the channel region 22 is 0.3 μm to 0.6 μm, and the size of the source region 23 is 0.2 μm to 0.5 μm. Preferably, along the extension direction of the semiconductor nanowire 2, the size of the drain region 21 is 0.3 μm, the size of the channel region 22 is 0.4 μm, and the size of the source region 23 is 0.3 μm.
Further, the diameter of the semiconductor nanowire 2 does not exceed 6 nm. Illustratively, the semiconductor nanowire 2 may have a diameter of 1nm, 2nm, 3nm, 4nm, 5nm, or 6 nm.
Referring to fig. 8, a first isolation layer 6 is formed on the semiconductor substrate 1, the first isolation layer 6 surrounding the drain region 21 and exposing the channel region 22 and the source region 23.
Specifically, the process for forming the first isolation layer 6 includes a Plasma Enhanced Chemical Vapor Deposition (PECVD) process or an Atomic Layer Deposition (ALD) process; the first barrier layer 6 includes, but is not limited to, alumina.
Referring to fig. 9, an interfacial layer 3 surrounding the channel region 22 is formed on the semiconductor substrate 1; the interfacial layer 3 is located on the first isolation layer 6.
Specifically, the step of forming the interface layer 3 includes: forming an initial interface film covering the first isolation layer 6 and the surfaces of the channel region 22 and the source region 23 of the semiconductor nanowire; the initial interface film is etched back until the surface of the first isolation layer 6, and the top surface and sidewall surface of the source region 23 are exposed, forming the interface layer 3. The process for forming the initial interface film comprises a plasma enhanced chemical vapor deposition process or an atomic layer deposition process; the process of etching back the initial interface film includes an anisotropic plasma etch process.
Further, the material of the interfacial layer 3 includes, but is not limited to, aluminum nitride; the thickness of the interface layer 3 is 2nm-4 nm; the oxygen content is 0% or more and less than 0.1%. Illustratively, the thickness of the interfacial layer 3 may be 2nm, 2.5nm, 3nm, 3.5nm, or 4 nm; the oxygen content may be 0, 0.01%, 0.02%, 0.03%, 0.04%, 0.05%, 0.06%, 0.07%, 0.08%, or 0.09%.
Referring to fig. 10, a gate dielectric layer 4 surrounding the interfacial layer 3 is formed on the semiconductor substrate 1.
Specifically, the gate dielectric layer 4 is located on the first isolation layer 6. The process for forming the gate dielectric layer 4 comprises a Plasma Enhanced Chemical Vapor Deposition (PECVD) process or an Atomic Layer Deposition (ALD) process; the material of the gate dielectric layer 4 includes but is not limited to Al2O3。
Referring to fig. 11, a drain electrode layer 9 is formed on a side of the semiconductor substrate 1 away from the gate electrode layer 5, and the drain electrode layer 9 is electrically connected to the drain region 21.
Specifically, the step of forming the drain electrode layer 9 is: forming a metal film by thermal evaporation, magnetron sputtering or electron beam evaporation, and depositing the metal film on the N2Annealing at 600-700 ℃ under the environment to obtain the drain electrode layer 9; preferably, the annealing temperature is 650 ℃. The material of the drain electrode layer 9 is gold, the thickness of the drain electrode layer 9 is 150nm-250nm, and exemplarily, the thickness of the drain electrode layer 9 can be 150nm, 175nm, 200nm, 225nm or 250 nm; or, the drain electrode layer 9 includes a second titanium layer, a second aluminum layer, a second nickel layer and a second gold layer which are sequentially stacked, the second titanium layer contacts with the semiconductor substrate 1, the arrangement direction of the second titanium layer, the second aluminum layer, the second nickel layer and the second gold layer is perpendicular to the surface of the semiconductor substrate 1, the thickness of the second titanium layer is 20nm to 30nm, the thickness of the second aluminum layer is 70nm to 80nm, the thickness of the second nickel layer is 20nm to 30nm, the thickness of the second gold layer is 70nm to 80nm, preferably, the thickness of the second titanium layer is 25nm, the thickness of the second aluminum layer is 75nm, the thickness of the second nickel layer is 25nm, and the thickness of the second gold layer is 75 nm; it is to be understood that the material of the drain electrode layer 9 includes, but is not limited to, the above materials.
Referring to fig. 12, a gate layer 5 is formed on the semiconductor substrate 1, and the gate layer 5 surrounds the gate dielectric layer 4.
Specifically, the step of forming the gate layer 5 is: forming a metal film by thermal evaporation, magnetron sputtering or electron beam evaporation, and depositing the metal film on the N2Annealing at 600-700 ℃ under the environment to obtain the gate layer 5; preferably, the annealing temperature is 650 ℃. The material of the gate layer 5 includes but is not limited to chromium; the ring width of the gate layer 5 is 175nm-225 nm. Illustratively, the ring width of the gate layer 5 may be 175nm, 200nm, or 225 nm. It should be understood that the gate layer 5 is annular, and the annular width is the difference between the outer diameter of the gate layer and the inner diameter of the gate layer.
Referring to fig. 13, a second isolation layer 7 is formed on the semiconductor substrate 1, wherein the second isolation layer 7 surrounds the source region 23 and is located on the upper surfaces of the interfacial layer 3, the gate dielectric layer 4 and the gate electrode layer 5.
Specifically, the process for forming the second isolation layer 7 includes a Plasma Enhanced Chemical Vapor Deposition (PECVD) process or an Atomic Layer Deposition (ALD) process; the material of the second isolation layer 7 includes, but is not limited to, silicon dioxide.
Referring to fig. 14, a source electrode layer 8 is formed on the side of the semiconductor nanowire 2 facing away from the semiconductor substrate 1, and the source electrode layer 8 is electrically connected to the source region 23.
Specifically, the step of forming the source electrode layer 8 is: forming a metal film by thermal evaporation, magnetron sputtering or electron beam evaporation, and depositing the metal film on the N2Annealing at 600-700 ℃ under the environment to obtain the source electrode layer 8; preferably, the annealing temperature is 650 ℃. The material of the source electrode layer 8 is gold, the thickness of the source electrode layer 8 is 150nm-250nm, and exemplarily, the thickness of the source electrode layer 8 may be 150nm, 175nm, 200nm, 225nm or 250 nm; or, the source electrode layer 8 includes a first titanium layer, a first aluminum layer, a first nickel layer and a first gold layer, which are sequentially stacked, the first titanium layer is in contact with the second isolation layer 7 and the source region 23, the arrangement direction of the first titanium layer, the first aluminum layer, the first nickel layer and the first gold layer is perpendicular to the surface of the semiconductor substrate 1, the thickness of the first titanium layer is 20nm to 30nm, the thickness of the first aluminum layer is 70nm to 80nm, the thickness of the first nickel layer is 20nm to 30nm, the thickness of the first gold layer is 70nm to 80nm, preferably, the thickness of the first titanium layer is 25nm, the thickness of the first aluminum layer is 75nm, the thickness of the first nickel layer is 25nm, and the thickness of the first gold layer is 75 nm; it is to be understood that the material of the source electrode layer 8 includes, but is not limited to, the above materials.
It should be understood that the order of forming the first isolation layer 6, the interface layer 3, the gate dielectric layer 4, the drain electrode layer 9, the gate layer 5, the second isolation layer 7, and the source electrode layer 8 may be adjusted as required.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.

Claims (12)

1. A wrap gate field effect transistor, comprising:
a semiconductor substrate;
a semiconductor nanowire located on the semiconductor substrate, the semiconductor nanowire comprising a channel region;
the gate dielectric layer is positioned on the semiconductor substrate and surrounds the channel region;
and the interface layer is positioned on the semiconductor substrate, is positioned between the channel region and the gate dielectric layer and is suitable for preventing oxygen in the gate dielectric layer from diffusing to the channel region.
2. The wrap gate field effect transistor of claim 1, wherein the oxygen content in the interfacial layer is 0 or greater and less than 0.1%.
3. The wrap gate field effect transistor of claim 1, wherein a material of the interfacial layer comprises aluminum nitride; the material of the gate dielectric layer comprises aluminum oxide.
4. The wrap gate field effect transistor of claim 1, wherein the semiconductor nanowires comprise GaN-based semiconductor nanowires.
5. The wrap gate field effect transistor of claim 1, wherein the interfacial layer has a thickness of 2nm to 4 nm.
6. The wrap gate field effect transistor of claim 1, wherein the semiconductor nanowire has a diameter of no more than 6 nm.
7. The surround-gate fet of claim 1, wherein the surround-gate fet is a vertical surround-gate fet.
8. The wrap gate field effect transistor of claim 7, wherein the semiconductor nanowire further comprises a source region and a drain region respectively located at two sides of the channel region, the drain region, the channel region and the source region are arranged along an extending direction of the semiconductor nanowire, and the drain region is located between the channel region and the semiconductor substrate;
the surrounding gate field effect transistor further includes: a first isolation layer on the semiconductor substrate, the first isolation layer surrounding the drain region; the gate dielectric layer and the interface layer are located on the first isolation layer.
9. A method of fabricating a surrounding gate field effect transistor as claimed in any one of claims 1 to 8, comprising the steps of:
providing a semiconductor substrate;
forming a semiconductor nanowire on the semiconductor substrate, the semiconductor nanowire comprising a channel region;
forming an interface layer surrounding the channel region on the semiconductor substrate;
after the interface layer is formed, a gate dielectric layer surrounding the interface layer is formed on the semiconductor substrate;
the interface layer is suitable for blocking oxygen in the gate dielectric layer from diffusing to the channel region.
10. The method of claim 9, wherein the surrounding gate field effect transistor is a vertical surrounding gate field effect transistor; the semiconductor nanowire further comprises a source region and a drain region which are respectively positioned on two sides of the channel region, the drain region, the channel region and the source region are arranged along the extending direction of the semiconductor nanowire, and the drain region is positioned between the channel region and the semiconductor substrate;
the preparation method of the surrounding grid field effect transistor further comprises the following steps: and before the interface layer and the gate dielectric layer are formed, forming a first isolation layer on the semiconductor substrate, wherein the first isolation layer surrounds the drain region and exposes the channel region and the source region.
11. The method of claim 10, wherein the step of forming the interfacial layer comprises: forming an initial interface film covering the first isolation layer and surfaces of the channel region and the source region of the semiconductor nanowire; and etching the initial interface film back until the surface of the first isolation layer, the top surface of the source region and the side wall surface are exposed to form the interface layer.
12. The method of manufacturing a surrounding gate field effect transistor according to claim 11, wherein the process of forming the initial interface film comprises a plasma enhanced chemical vapor deposition process or an atomic layer deposition process;
the process of etching back the initial interface film includes an anisotropic plasma etch process.
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