TW201830672A - Complementary device and the method for making the same - Google Patents
Complementary device and the method for making the same Download PDFInfo
- Publication number
- TW201830672A TW201830672A TW106111938A TW106111938A TW201830672A TW 201830672 A TW201830672 A TW 201830672A TW 106111938 A TW106111938 A TW 106111938A TW 106111938 A TW106111938 A TW 106111938A TW 201830672 A TW201830672 A TW 201830672A
- Authority
- TW
- Taiwan
- Prior art keywords
- type
- layer
- gate
- nanowire
- channel
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 47
- 230000000295 complement effect Effects 0.000 title claims abstract description 37
- 239000002070 nanowire Substances 0.000 claims abstract description 104
- 239000004065 semiconductor Substances 0.000 claims abstract description 46
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 239000002184 metal Substances 0.000 claims description 66
- 229910052751 metal Inorganic materials 0.000 claims description 66
- 239000000463 material Substances 0.000 claims description 64
- 238000004519 manufacturing process Methods 0.000 claims description 26
- 230000004888 barrier function Effects 0.000 claims description 24
- 238000002955 isolation Methods 0.000 claims description 22
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims description 17
- 230000005533 two-dimensional electron gas Effects 0.000 claims description 17
- 239000007769 metal material Substances 0.000 claims description 14
- 230000000903 blocking effect Effects 0.000 claims description 10
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 7
- 229910004129 HfSiO Inorganic materials 0.000 claims description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical group [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 7
- 229910006501 ZrSiO Inorganic materials 0.000 claims description 7
- 238000000059 patterning Methods 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 238000009616 inductively coupled plasma Methods 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 239000012141 concentrate Substances 0.000 claims description 4
- 238000001459 lithography Methods 0.000 claims description 4
- 239000013078 crystal Substances 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 239000000725 suspension Substances 0.000 claims 2
- 230000005669 field effect Effects 0.000 abstract description 4
- 230000003071 parasitic effect Effects 0.000 abstract description 4
- 230000009467 reduction Effects 0.000 abstract description 3
- 238000000231 atomic layer deposition Methods 0.000 description 7
- 230000008569 process Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 238000001451 molecular beam epitaxy Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 241000209094 Oryza Species 0.000 description 2
- 235000007164 Oryza sativa Nutrition 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 235000012149 noodles Nutrition 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 235000009566 rice Nutrition 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000002902 organometallic compounds Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
本發明涉及積體電路技術領域,特別是涉及一種互補電晶體元件結構及其製作方法。 The invention relates to the technical field of integrated circuits, in particular to a complementary transistor element structure and a manufacturing method thereof.
隨著積體電路技術的進一步發展,人們希望通過採用超薄體(UTB)如量子阱結構,來避免MOS電晶體繼續按比例縮小至更小尺寸時引發更嚴重的短通道效應。高電子遷移率電晶體(HEMT)的基本結構由一個調整摻雜異質結及其源汲結構組成。存在於調製摻雜異質接面中的二維電子氣(2-DEG),由於不受電離雜質離子散射的影響,其遷移率非常高。HEMT是電壓控制元件,閘極電壓Vg可控制異質接面電位阱的深度,從而控制電位阱中2-DEG的面密度,進而控制元件的工作電流。 With the further development of integrated circuit technology, it is hoped that the use of ultra-thin body (UTB) such as quantum well structure can prevent the MOS transistor from scaling down to a smaller size to cause more severe short-channel effects. The basic structure of a high electron mobility transistor (HEMT) consists of a tuning doped heterojunction and its source-drain structure. The two-dimensional electron gas (2-DEG) existing in the modulation-doped heterojunction has a high mobility because it is not affected by the scattering of ionized impurity ions. HEMT is a voltage control element. The gate voltage V g can control the depth of the heterojunction potential well, thereby controlling the areal density of 2-DEG in the potential well, and then controlling the working current of the element.
對於GaAs體系的HEMT,通常其中的n-AlxGa1-xAs控制層(或勢障層)應該是耗盡的,厚度一般為數百nm,摻雜濃度為107~108/cm3。若n-AlxGa1-xAs層厚度較大、摻雜濃度又高,則在Vg=0時就存在有2-DEG,元件為耗盡型元件,反之則為增強型元件,即Vg=0時,蕭特基耗盡層即延伸到本質GaAs層內部;對於HEMT,主要是要控制好寬禁帶半導體層(控制層)的摻雜濃度和厚度,特別是厚度。2-DEG面電荷密度Ns將受到閘極電壓Vg 的控制。然而,這些元件結構目前基本都是傳統的平面型結構,寄生電阻較高,閘極控制難以滿足低壓邏輯的應用。 For GaAs-based HEMTs, the n-Al x Ga 1-x As control layer (or barrier layer) should be depleted, the thickness is usually several hundred nm, and the doping concentration is 10 7 to 10 8 / cm. 3 . If the thickness of the n-Al x Ga 1-x As layer is large and the doping concentration is high, then 2-DEG exists at V g = 0, the element is a depletion element, and the opposite is an enhanced element, that is, When V g = 0, the Schottky depletion layer extends into the intrinsic GaAs layer; for HEMT, it is mainly to control the doping concentration and thickness of the wide band gap semiconductor layer (control layer), especially the thickness. The 2-DEG surface charge density N s will be controlled by the gate voltage V g . However, these element structures are basically traditional planar structures at present, parasitic resistance is high, and gate control is difficult to meet the application of low-voltage logic.
因此,實有必要突破傳統設計,提供新的HEMT元件結構,以滿足低壓邏輯應用的需要。 Therefore, it is necessary to break the traditional design and provide a new HEMT component structure to meet the needs of low-voltage logic applications.
鑒於以上所述現有技術,本發明的目的在於提供一種互補電晶體元件結構及其製作方法,用於解決現有技術中的種種問題。 In view of the foregoing prior art, an object of the present invention is to provide a complementary transistor element structure and a manufacturing method thereof for solving various problems in the prior art.
為實現上述目的及其他相關目的,本發明提供一種互補電晶體元件結構,包括:位於同一半導體基板之上的P型Ge無接面電晶體和N型III-V族半導體奈米線量子阱電晶體;所述P型Ge無接面電晶體和N型III-V族半導體奈米線量子阱電晶體之間以及所述P型Ge無接面電晶體和N型III-V族半導體奈米線量子阱電晶體與所述半導體基板之間設有絕緣埋層;其中,所述P型Ge無接面電晶體包括:第一通道,所述第一通道為長條形狀的P型Ge奈米線;分別環繞所述第一通道兩端的P型源區和P型汲區,所述P型源區和P型汲區的材料為重摻雜P型Ge;位於所述P型源區和P型汲區之間環繞所述第一通道中部的第一閘區,所述第一閘區包括第一閘金屬層和將所述第一閘金屬層與所述第一通道、P型源區和P型汲區隔開的第一閘介電層;所述N型III-V族半導體奈米線量子阱電晶體包括:第二通道,所述第二通道包括長條形狀的P型Ge奈米線通道和環繞包裹 所述P型Ge奈米線通道的二維電子氣層,所述二維電子氣層的材料為N型InGaAs;分別環繞所述第二通道兩端的N型源區和N型汲區,所述N型源區和N型汲區的材料為重摻雜N型InGaAs;位於所述N型源區和N型汲區之間環繞所述第二通道中部的第二閘區;以及將所述第二閘區與所述第二通道、N型源區和N型汲區隔開的阻擋層;所述第二閘區包括第二閘金屬層和將所述第二閘金屬層與所述阻擋層隔開的第二閘介電層。 In order to achieve the above object and other related objects, the present invention provides a complementary transistor element structure including: a P-type Ge contactless transistor and an N-type III-V semiconductor nanowire quantum well circuit on the same semiconductor substrate. Crystal; between the P-type Ge interfaceless transistor and an N-type III-V semiconductor nanowire quantum well transistor and the P-type Ge interfaceless transistor and an N-type III-V semiconductor nanometer An insulating buried layer is provided between the linear quantum well transistor and the semiconductor substrate, wherein the P-type Ge contactless transistor includes a first channel, and the first channel is a long-shaped P-type Ge nano Rice wire; surrounding the P-type source region and the P-type drain region at both ends of the first channel, the material of the P-type source region and the P-type drain region is heavily doped P-type Ge; A first gate region surrounding the middle of the first channel between a P-type drain region, the first gate region including a first gate metal layer, and connecting the first gate metal layer with the first channel and a P-type source. A first gate dielectric layer separated from the P-type drain region; the N-type III-V group semiconductor nanowire quantum well transistor includes: a second channel The second channel includes a long P-type Ge nanowire channel and a two-dimensional electron gas layer surrounding the P-type Ge nanowire channel. The material of the two-dimensional electron gas layer is N-type InGaAs; N-type source regions and N-type drain regions surrounding the two ends of the second channel, respectively, and the materials of the N-type source regions and N-type drain regions are heavily doped N-type InGaAs; A second gate region surrounding the middle of the second channel between the regions; and a barrier layer separating the second gate region from the second channel, the N-type source region, and the N-type drain region; the second The gate region includes a second gate metal layer and a second gate dielectric layer separating the second gate metal layer from the barrier layer.
可選地,所述P型源區和P型汲區環繞所述第一通道的厚度為10-200nm。 Optionally, the thickness of the P-type source region and the P-type drain region surrounding the first channel is 10-200 nm.
可選地,所述N型源區和N型汲區環繞所述第二通道的厚度為10-200nm。 Optionally, the thickness of the N-type source region and the N-type drain region surrounding the second channel is 10-200 nm.
可選地,所述二維電子氣層環繞所述P型Ge奈米線通道的厚度為10-100nm。 Optionally, the thickness of the two-dimensional electron gas layer surrounding the P-type Ge nanowire channel is 10-100 nm.
可選地,所述第一閘介電層和第二閘介電層的材料為高介電常數材料。 Optionally, the materials of the first gate dielectric layer and the second gate dielectric layer are high dielectric constant materials.
可選地,所述第一閘介電層和第二閘介電層的材料選自Al2O3、TiSiOx、HfSiON、HfO2、HfSiOx、ZrSiOx以及ZrO2中的一種或多種。 Alternatively, the material of the first gate dielectric layer and the second gate dielectric layer is selected from Al 2 O 3, TiSiO x, HfSiON, HfO 2, HfSiO x, ZrSiO x , and one or more of ZrO 2.
可選地,所述第一閘介電層和第二閘介電層的厚度均為1-5nm。 Optionally, the thickness of the first gate dielectric layer and the second gate dielectric layer are both 1-5 nm.
可選地,所述第一閘金屬層和所述第二閘金屬層的材料選自 TiN、NiAu、CrAu、Au/Ge/Ni疊層、Ti/Pt疊層和Ti/Au疊層中的一種或多種。 Optionally, the material of the first gate metal layer and the second gate metal layer is selected from the group consisting of TiN, NiAu, CrAu, Au / Ge / Ni stack, Ti / Pt stack, and Ti / Au stack. One or more.
可選地,所述阻擋層的材料為N型矽摻雜的InP。 Optionally, the material of the blocking layer is N-type silicon-doped InP.
進一步可選地,所述阻擋層的矽摻雜的濃度為1.2×1018cm-3。 Further optionally, the blocking layer has a silicon-doped concentration of 1.2 × 10 18 cm -3 .
進一步可選地,所述阻擋層的厚度為50-100nm。 Further optionally, the thickness of the barrier layer is 50-100 nm.
可選地,所述P型Ge無接面電晶體還包括引出所述第一閘金屬層的第一閘電極、分別設於所述P型源區和P型汲區上的第一源電極和第一汲電極,在所述第一閘電極周圍設有側牆隔離結構。 Optionally, the P-type Ge contactless transistor further includes a first gate electrode leading to the first gate metal layer, and first source electrodes respectively provided on the P-type source region and the P-type drain region. And a first drain electrode, a side wall isolation structure is provided around the first gate electrode.
可選地,所述N型III-V族半導體奈米線量子阱電晶體還包括引出所述第二閘金屬層的第二閘電極、分別設於所述N型源區和N型汲區上的第二源電極和第二汲電極,在所述第二閘電極周圍設有側牆隔離結構。 Optionally, the N-type III-V semiconductor nanowire quantum well transistor further includes a second gate electrode that leads to the second gate metal layer, and is disposed in the N-type source region and the N-type drain region, respectively. A second source electrode and a second drain electrode on the upper side, a side wall isolation structure is provided around the second gate electrode.
可選地,所述第一閘金屬層與第一閘電極一體成型,所述第二閘金屬層與第二閘電極一體成型。 Optionally, the first gate metal layer is integrally formed with the first gate electrode, and the second gate metal layer is integrally formed with the second gate electrode.
可選地,所述P型Ge無接面電晶體和N型III-V族半導體奈米線量子阱電晶體周圍設有淺溝渠隔離結構。 Optionally, a shallow trench isolation structure is provided around the P-type Ge contactless transistor and the N-type III-V semiconductor nanowire quantum well transistor.
為實現上述目的及其他相關目的,本發明還提供一種互補電晶體元件結構的製作方法,包括如下步驟:提供一具有絕緣埋層的SiGe基板;在所述SiGe基板上圖形化有源區並形成在有源區內懸架於絕緣埋層上方的Ge奈米線;以所述Ge奈米線為基礎製作P型Ge無接面電晶體和N型III-V族半導體奈米線量子阱電晶體;其中, 所述P型Ge無接面電晶體的製作方法包括如下步驟:S101以所述Ge奈米線為第一通道;S102在所述Ge奈米線上進行Ge磊晶生長,形成環繞所述Ge奈米線的重摻雜P型Ge材料層;S103去除環繞所述Ge奈米線的重摻雜P型Ge材料層的中段部分形成第一溝渠,得到分別環繞所述Ge奈米線兩端的P型源區和P型汲區,露出懸架於所述第一溝渠內的部分Ge奈米線及所述Ge奈米線下方的部分絕緣埋層;S104形成第一閘介電層,所述第一閘介電層包裹所述第一溝渠內露出的部分Ge奈米線的表面,以及所述第一溝渠露出的P型源區表面、P型汲區表面和部分絕緣埋層的表面;S105形成第一閘金屬層,所述第一閘金屬層在所述第一溝渠內環繞被所述第一閘介電層包裹的所述Ge奈米線;所述N型III-V族半導體奈米線量子阱電晶體的製作方法包括如下步驟:S201在所述Ge奈米線表面磊晶生長N型InGaAs材料作為二維電子氣層,得到第二通道,所述第二通道包括Ge奈米線和環繞包裹所述Ge奈米線的二維電子氣層;S202磊晶生長形成環繞包裹所述第二通道的重摻雜N型InGaAs材料層;S203去除環繞所述第二通道的重摻雜N型InGaAs材料層的中段部分形成第二溝渠,得到分別環繞所述第二通道兩端的N型源區和N型汲區,露出懸架於所述第二溝渠內的部分第二通道及所述第二通道下方的部分絕緣埋層; S204形成阻擋層,所述阻擋層包裹所述第二溝渠內露出的部分第二通道的表面,以及所述第二溝渠露出的N型源區和N型汲區的表面;S205形成第二閘介電層,所述第二閘介電層覆蓋所述阻擋層表面以及所述第二溝渠露出的部分絕緣埋層的表面;S206形成第二閘金屬層,所述第二閘金屬層在所述第二溝渠內環繞被所述第二閘介電層和阻擋層包裹的所述第二通道。 In order to achieve the above object and other related objects, the present invention also provides a method for manufacturing a complementary transistor element structure, including the following steps: providing a SiGe substrate with an insulating buried layer; patterning an active region on the SiGe substrate and forming Ge nanowires suspended above the insulating buried layer in the active region; based on the Ge nanowires, P-type Ge contactless transistors and N-type III-V semiconductor nanowire quantum well transistors are fabricated Wherein, the method for manufacturing the P-type Ge contactless transistor includes the following steps: S101 uses the Ge nanowire as a first channel; S102 performs epitaxial growth of Ge on the Ge nanowire to form a surround structure. The heavily doped P-type Ge material layer of the Ge nanowire is removed; S103 removes a middle portion of the heavily doped P-type Ge material layer that surrounds the Ge nanowire to form a first trench to obtain the Ge nanowires respectively. The P-type source region and the P-type drain region at both ends expose a part of the Ge nanowire suspended in the first trench and a part of the buried insulating layer below the Ge nanowire; S104 forms a first gate dielectric layer, The first gate dielectric layer surrounds a part of Ge exposed in the first trench. The surface of the rice noodle, and the surface of the P-type source region, the surface of the P-type drain region, and the surface of the buried buried layer exposed by the first trench; S105 forms a first gate metal layer, and the first gate metal layer is in the A first trench surrounds the Ge nanowires wrapped by the first gate dielectric layer; the method for manufacturing the N-type III-V group semiconductor nanowire quantum well transistor includes the following steps: S201 in the An N-type InGaAs material is epitaxially grown on the surface of a Ge nanowire as a two-dimensional electron gas layer to obtain a second channel, and the second channel includes a Ge nanowire and a two-dimensional electron gas layer surrounding the Ge nanowire; S202 is epitaxially grown to form a heavily doped N-type InGaAs material layer that surrounds the second channel; S203 removes a middle portion of the heavily doped N-type InGaAs material layer that surrounds the second channel to form second trenches, which respectively surround The N-type source region and the N-type drain region at both ends of the second channel expose part of the second channel suspended in the second trench and part of the insulating buried layer below the second channel; S204 forms a barrier layer, so The blocking layer covers a part of the second trench that is exposed in the second trench. The surface of the track, and the surface of the N-type source region and the N-type drain region exposed by the second trench; S205 forms a second gate dielectric layer, and the second gate dielectric layer covers the surface of the barrier layer and the The surface of the part of the buried buried layer exposed by the second trench; S206 forms a second gate metal layer, and the second gate metal layer surrounds the interior of the second trench surrounded by the second gate dielectric layer and the barrier layer. Mentioned second channel.
可選地,形成所述Ge奈米線的方法包括如下步驟:a在所述具有絕緣埋層的SiGe基板上圖形化有源區並蝕刻,得到長條型SiGe層;b填充淺溝渠隔離材料,並進行表面平坦化;c圖形化所述淺溝渠隔離材料,露出有源區內的長條型SiGe層;d進行溼式蝕刻,得到懸架於絕緣埋層上方的SiGe奈米線條;e氧化所述SiGe奈米線條生成表面氧化物,使Ge濃縮;f去除所述表面氧化物;g在H2環境下高溫退火,形成圓柱狀的長條型Ge奈米線。 Optionally, the method for forming the Ge nanowire includes the following steps: a) patterning an active region on the SiGe substrate with an insulating buried layer and etching to obtain a long SiGe layer; b) filling a shallow trench isolation material And planarize the surface; c pattern the shallow trench isolation material to expose the long SiGe layer in the active region; d perform wet etching to obtain SiGe nanometer lines suspended above the buried insulating layer; e oxidation The SiGe nano-lines generate surface oxides to enrich Ge; f removes the surface oxides; and g anneals at a high temperature in an H 2 environment to form cylindrical long Ge nanowires.
可選地,形成所述Ge奈米線時,反復進行步驟d和步驟e,使Ge濃縮至所需程度。 Optionally, when the Ge nanowire is formed, step d and step e are repeatedly performed to concentrate Ge to a desired degree.
可選地,通過微影和感應耦合電漿乾式蝕刻形成所述第一溝渠和所述第二溝渠。 Optionally, the first trench and the second trench are formed by lithography and inductively coupled plasma dry etching.
可選地,形成所述第一閘介電層和第二閘介電層的材料為高介電常數材料。 Optionally, a material forming the first gate dielectric layer and the second gate dielectric layer is a high dielectric constant material.
可選地,形成所述第一閘介電層和第二閘介電層的材料選自 Al2O3、TiSiOx、HfSiON、HfO2、HfSiOx、ZrSiOx以及ZrO2中的一種或多種。 Alternatively, the material forming the first gate dielectric layer and the second gate dielectric layer is selected from Al 2 O 3, TiSiO x, HfSiON, HfO 2, a medium of 2 HfSiO x, ZrSiO x or more, and ZrO .
可選地,形成所述第一閘金屬層和所述第二閘金屬層的材料選自TiN、NiAu、CrAu、Au/Ge/Ni疊層、Ti/Pt疊層和Ti/Au疊層中的一種或多種。 Optionally, a material forming the first gate metal layer and the second gate metal layer is selected from the group consisting of TiN, NiAu, CrAu, Au / Ge / Ni stack, Ti / Pt stack, and Ti / Au stack One or more.
可選地,形成所述阻擋層的方法為磊晶生長N型矽摻雜的InP。 Optionally, the method for forming the barrier layer is epitaxial growth of N-type silicon-doped InP.
進一步可選地,形成所述阻擋層時,矽摻雜的濃度為1.2×1018cm-3。 Further optionally, when the barrier layer is formed, the concentration of silicon doping is 1.2 × 10 18 cm -3 .
可選地,所述P型Ge無接面電晶體的製作方法還包括:形成引出所述第一閘金屬層的第一閘電極,並在所述第一閘電極周圍形成側牆隔離結構;形成分別設於所述P型源區和P型汲區上的第一源電極和第一汲電極。 Optionally, the method for manufacturing the P-type Ge contactless transistor further includes: forming a first gate electrode that leads to the first gate metal layer, and forming a sidewall isolation structure around the first gate electrode; A first source electrode and a first drain electrode are formed on the P-type source region and the P-type drain region, respectively.
可選地,形成第一閘金屬層時,使閘金屬材料填充所述第一溝渠並突出於所述第一溝渠表面,突出於所述第一溝渠表面的閘金屬材料作為第一閘電極。 Optionally, when forming the first gate metal layer, a gate metal material fills the first trench and protrudes from the surface of the first trench, and the gate metal material protruding from the surface of the first trench serves as the first gate electrode.
可選地,所述N型III-V族半導體奈米線量子阱電晶體的製作方法還包括:形成引出所述第二閘金屬層的第二閘電極,並在所述第二閘電極周圍形成側牆隔離結構;形成分別設於所述N型源區和N型汲區上的第二源電極和第二汲電極。 Optionally, the method for manufacturing the N-type III-V semiconductor nanowire quantum well transistor further includes: forming a second gate electrode that leads to the second gate metal layer, and surrounding the second gate electrode. Forming a sidewall isolation structure; forming a second source electrode and a second drain electrode respectively disposed on the N-type source region and the N-type drain region.
可選地,形成第二閘金屬層時,使閘金屬材料填充所述第二溝渠並突出於所述第二溝渠表面,突出於所述第二溝渠表面的閘金屬材料作為第二閘電極。 Optionally, when forming the second gate metal layer, a gate metal material fills the second trench and protrudes from the surface of the second trench, and the gate metal material protruding from the surface of the second trench serves as the second gate electrode.
如上所述,本發明的互補電晶體元件結構及其製造方法,具有以下有益效果:本發明提供的互補型電晶體,包括閘極全包圍的P型Ge無接面電晶體(junctionless transistor,JLT)和N型III-V族半導體奈米線量子阱場效電晶體(nanowire quantum well field effect transistor,QWFET),並採用了高K閘介電材料。相對於平面型元件,本發明的互補型三維電晶體結構簡化了源汲區域的圖形設計,同時實現了寄生電阻的顯著減少,明顯改善了元件的靜電完整性,從而具有更好的元件閘極控制能力,更適用於低功耗邏輯電路產品的應用。 As described above, the complementary transistor element structure and manufacturing method of the present invention have the following beneficial effects: The complementary transistor provided by the present invention includes a P-type Ge junctionless transistor (JLT) surrounded by a gate. ) And N-type III-V semiconductor nanowire quantum well field effect transistor (QWFET), and high-K gate dielectric materials are used. Compared with the planar element, the complementary three-dimensional transistor structure of the present invention simplifies the graphic design of the source-drain region, at the same time realizes a significant reduction in parasitic resistance, significantly improves the electrostatic integrity of the element, and has a better element gate The control ability is more suitable for the application of low power logic circuit products.
100‧‧‧半導體基板 100‧‧‧ semiconductor substrate
200‧‧‧絕緣埋層 200‧‧‧ Insulated buried layer
301‧‧‧第一通道 301‧‧‧First channel
3021‧‧‧P型源區 3021‧‧‧P-type source area
3022‧‧‧P型汲區 3022‧‧‧P Type
3031‧‧‧第一閘金屬層 3031‧‧‧First Gate Metal Layer
3032‧‧‧第一閘介電層 3032‧‧‧First gate dielectric layer
3051‧‧‧第一源電極 3051‧‧‧First source electrode
3052‧‧‧第一汲電極 3052‧‧‧first drain electrode
401‧‧‧第二通道 401‧‧‧Second Channel
4011‧‧‧P型Ge奈米線通道 4011‧‧‧P Type Ge Nanowire Channel
4012‧‧‧二維電子氣層 4012‧‧‧Two-dimensional electronic gas layer
4021‧‧‧N型源區 4021‧‧‧N-type source area
4022‧‧‧N型汲區 4022‧‧‧N Type
4031‧‧‧第二閘金屬層 4031‧‧‧Second gate metal layer
404‧‧‧阻擋層 404‧‧‧ barrier
4032‧‧‧第二閘介電層 4032‧‧‧Second gate dielectric layer
3051‧‧‧第一源電極 3051‧‧‧First source electrode
3052‧‧‧第一汲電極 3052‧‧‧first drain electrode
4051‧‧‧第二源電極 4051‧‧‧Second source electrode
4052‧‧‧第二汲電極 4052‧‧‧Second Drain Electrode
500‧‧‧側牆隔離結構 500‧‧‧Side wall isolation structure
第1圖顯示為本發明實施例提供的互補電晶體元件結構的示意圖。 FIG. 1 is a schematic diagram showing a structure of a complementary transistor element according to an embodiment of the present invention.
第2圖顯示為本發明實施例提供的P型Ge無接面電晶體的通道截面示意圖。 FIG. 2 is a schematic cross-sectional view of a channel of a P-type Ge contactless transistor according to an embodiment of the present invention.
第3圖顯示為本發明實施例提供的N型III-V族半導體奈米線量子阱電晶體的通道截面示意圖。 FIG. 3 is a schematic cross-sectional view of a channel of an N-type III-V semiconductor nanowire quantum well transistor according to an embodiment of the present invention.
第4圖顯示為本發明實施例提供的Ge奈米線的製造流程示意圖。 FIG. 4 is a schematic diagram of a manufacturing process of a Ge nanowire according to an embodiment of the present invention.
第5a-5e圖顯示為本發明實施例提供的P型Ge無接面電晶體的製造流程示意圖。 5a-5e are schematic diagrams showing the manufacturing process of a P-type Ge contactless transistor provided by an embodiment of the present invention.
第6a-6f圖顯示為本發明實施例提供的N型III-V族半導體奈 米線量子阱電晶體的製造流程示意圖。 Figures 6a-6f are schematic diagrams showing the manufacturing process of an N-type III-V group semiconductor nanowire quantum well transistor according to an embodiment of the present invention.
以下通過特定的具體實例說明本發明的實施方式,本領域技術人員可由本說明書所揭露的內容輕易地瞭解本發明的其他優點與功效。本發明還可以通過另外不同的具體實施方式加以實施或應用,本說明書中的各項細節也可以基於不同觀點與應用,在沒有背離本發明的精神下進行各種修飾或改變。需說明的是,在不衝突的情況下,以下實施例及實施例中的特徵可以相互組合。 The following describes the embodiments of the present invention through specific specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through different specific implementations, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, in the case of no conflict, the following embodiments and features in the embodiments can be combined with each other.
需要說明的是,以下實施例中所提供的圖示僅以示意方式說明本發明的基本構想,遂圖式中僅顯示與本發明中有關的組件而非按照實際實施時的元件數目、形狀及尺寸繪製,其實際實施時各元件的型態、數量及比例可為一種隨意的改變,且其元件佈局型態也可能更為複雜。 It should be noted that the illustrations provided in the following embodiments are only a schematic illustration of the basic idea of the present invention, and the drawings only show the components related to the present invention and not the number, shape and For size drawing, the type, quantity, and proportion of each component can be changed at will in actual implementation, and the component layout type may be more complicated.
請參閱第1圖,本實施例提供一種互補電晶體元件結構,其包括:位於同一半導體基板100之上的P型Ge無接面電晶體300和N型III-V族半導體奈米線量子阱電晶體400;所述P型Ge無接面電晶體300和N型III-V族半導體奈米線量子阱電晶體400之間以及所述P型Ge無接面電晶體300和N型III-V族半導體奈米線量子阱電晶體400與所述半導體基板100之間設有絕緣埋層200。本實施例中,所述半導體基板100為Si基板,絕緣埋層為埋層氧化層(BOX)。 Please refer to FIG. 1. This embodiment provides a complementary transistor device structure, which includes a P-type Ge contactless transistor 300 and an N-type III-V semiconductor nanowire quantum well located on the same semiconductor substrate 100. Transistor 400; between the P-type Ge contactless transistor 300 and the N-type III-V group semiconductor nanowire quantum well transistor 400 and the P-type Ge contactless transistor 300 and the N-type III- A buried buried layer 200 is provided between the group V semiconductor nanowire quantum well transistor 400 and the semiconductor substrate 100. In this embodiment, the semiconductor substrate 100 is a Si substrate, and the insulating buried layer is a buried oxide layer (BOX).
其中,所述P型Ge無接面電晶體300包括:第一通道301,所述第一通道301為長條形狀的P型Ge奈米 線;分別環繞所述第一通道301兩端的P型源區3021和P型汲區3022,所述P型源區3021和P型汲區3022的材料為重摻雜P型Ge;位於所述P型源區3021和P型汲區3022之間環繞所述第一通道301中部的第一閘區,所述第一閘區包括第一閘金屬層3031和將所述第一閘金屬層3031與所述第一通道301、P型源區3021和P型汲區3022隔開的第一閘介電層3032。所述P型Ge無接面電晶體的通道截面如第2圖所示。 Wherein, the P-type Ge contactless transistor 300 includes: a first channel 301, and the first channel 301 is a long P-type Ge nanowire; and the P-type electrodes that surround the two ends of the first channel 301, respectively. A source region 3021 and a P-type drain region 3022. The material of the P-type source region 3021 and the P-type drain region 3022 is heavily doped P-type Ge; and is located between the P-type source region 3021 and the P-type drain region 3022. The first gate region in the middle of the first channel 301 includes the first gate metal layer 3031 and the first gate metal layer 3031 and the first channel 301, a P-type source region 3021, and P The first gate dielectric layer 3032 is separated by the type drain region 3022. The channel cross section of the P-type Ge-free contactless transistor is shown in FIG. 2.
所述N型III-V族半導體奈米線量子阱電晶體400包括:第二通道401,所述第二通道401包括長條形狀的P型Ge奈米線通道4011和環繞包裹所述P型Ge奈米線通道4011的二維電子氣層4012,所述二維電子氣層4012的材料為N型InGaAs;分別環繞所述第二通道401兩端的N型源區4021和N型汲區4022,所述N型源區4021和N型汲區4022的材料為重摻雜N型InGaAs;位於所述N型源區4021和N型汲區4022之間環繞所述第二通道401中部的第二閘區;以及將所述第二閘區與所述第二通道401、N型源區4021和N型汲區4022隔開的阻擋層404;所述第二閘區包括第二閘金屬層4031和將所述第二閘金屬層4031與所述阻擋層404隔開的第二閘介電層4032。所述N型III-V族半導體奈米線量子阱電晶體的通道截面結構如第3圖所示。 The N-type III-V group semiconductor nanowire quantum well transistor 400 includes a second channel 401. The second channel 401 includes an elongated P-type Ge nanowire channel 4011 and surrounds the P-type. A two-dimensional electron gas layer 4012 of the Ge nanowire channel 4011. The material of the two-dimensional electron gas layer 4012 is N-type InGaAs. The N-type source region 4021 and the N-type drain region 4022 that surround the two ends of the second channel 401, respectively. A material of the N-type source region 4021 and the N-type drain region 4022 is a heavily doped N-type InGaAs; a second region between the N-type source region 4021 and the N-type drain region 4022 and surrounding the middle of the second channel 401; A gate region; and a barrier layer 404 separating the second gate region from the second channel 401, an N-type source region 4021, and an N-type drain region 4022; the second gate region includes a second gate metal layer 4031 And a second gate dielectric layer 4032 separating the second gate metal layer 4031 from the barrier layer 404. The channel cross-sectional structure of the N-type III-V semiconductor nanowire quantum well transistor is shown in FIG. 3.
在本實施例中,所述P型源區3021和P型汲區3022環繞所述第一通道301的厚度可以為10-200nm。所述N型源區4021和N型汲區4022環繞所述第二通道401的厚度可以為10-200nm。 In this embodiment, the thickness of the P-type source region 3021 and the P-type drain region 3022 surrounding the first channel 301 may be 10-200 nm. The thickness of the N-type source region 4021 and the N-type drain region 4022 surrounding the second channel 401 may be 10-200 nm.
在本實施例中,所述二維電子氣層4012環繞所述P型Ge奈米線通道4011的厚度可以為10-100nm。 In this embodiment, the thickness of the two-dimensional electron gas layer 4012 surrounding the P-type Ge nanowire channel 4011 may be 10-100 nm.
在本實施例中,所述第一閘介電層3032和第二閘介電層4032 的材料均為高介電常數材料。例如,所述第一閘介電層3032和第二閘介電層4032的材料可以選自Al2O3、TiSiOx、HfSiON、HfO2、HfSiOx、ZrSiOx以及ZrO2中的一種或多種,或其他適合的高K材料。所述第一閘介電層3032和第二閘介電層4032的厚度可以均為1-5nm。 In this embodiment, the materials of the first gate dielectric layer 3032 and the second gate dielectric layer 4032 are both high dielectric constant materials. For example, the material of the first gate dielectric layer 3032 and the second gate dielectric layer 4032 may be selected from Al 2 O 3, a medium of 2 TiSiO x, HfSiON, HfO 2 , HfSiO x, ZrSiO x or more, and ZrO , Or other suitable high-K materials. The thicknesses of the first gate dielectric layer 3032 and the second gate dielectric layer 4032 may both be 1-5 nm.
在本實施例中,所述第一閘金屬層3031和所述第二閘金屬層4031的材料可以選自TiN、NiAu、CrAu、Au/Ge/Ni疊層、Ti/Pt疊層和Ti/Au疊層中的一種或多種,或其他適合的金屬。 In this embodiment, the material of the first gate metal layer 3031 and the second gate metal layer 4031 may be selected from the group consisting of TiN, NiAu, CrAu, Au / Ge / Ni stack, Ti / Pt stack, and Ti / One or more of the Au stacks, or other suitable metals.
在本實施例中,所述阻擋層404的材料可以為N型矽摻雜的InP。具體地,所述阻擋層404的矽摻雜的濃度可以為1.2×1018cm-3。所述阻擋層404的厚度可以為50-100nm。 In this embodiment, the material of the blocking layer 404 may be N-type silicon-doped InP. Specifically, the silicon doping concentration of the blocking layer 404 may be 1.2 × 10 18 cm -3 . The thickness of the blocking layer 404 may be 50-100 nm.
具體地,所述P型Ge無接面電晶體300還可以包括引出所述第一閘金屬層3031的第一閘電極、分別設於所述P型源區3021和P型汲區3022上的第一源電極3051和第一汲電極3052,在所述第一閘電極周圍設有側牆隔離結構(spacer)500。所述N型III-V族半導體奈米線量子阱電晶體400還包括引出所述第二閘金屬層4031的第二閘電極、分別設於所述N型源區4021和N型汲區4022上的第二源電極4051和第二汲電極4052,在所述第二閘電極周圍設有側牆隔離結構500。 Specifically, the P-type Ge contactless transistor 300 may further include a first gate electrode leading to the first gate metal layer 3031, and the first gate electrode provided on the P-type source region 3021 and the P-type drain region 3022, respectively. A first source electrode 3051 and a first drain electrode 3052 are provided with a spacer 500 around the first gate electrode. The N-type III-V semiconductor nanowire quantum well transistor 400 further includes a second gate electrode that leads to the second gate metal layer 4031, and is provided in the N-type source region 4021 and the N-type drain region 4022, respectively. On the second source electrode 4051 and the second drain electrode 4052 on the upper side, a side wall isolation structure 500 is provided around the second gate electrode.
其中,所述P型Ge無接面電晶體300的汲極,即第一汲電極3052連接電源+Vdd,所述P型Ge無接面電晶體300的源極與所述N型III-V族半導體奈米線量子阱電晶體400汲極連接作為輸出,即第一源電極3051與第二汲電極4052連接作為Vout,所述N型III-V族半導體奈米線量子阱電晶體400的源極,即第二源電極4051接地GND,所述P型Ge無接面電晶體300與所述N 型III-V族半導體奈米線量子阱電晶體400的閘極相連,即第一閘電極與第二閘電極相連作為輸入Vin。 Wherein, the drain of the P-type Ge contactless transistor 300, that is, the first drain electrode 3052 is connected to a power source + Vdd, and the source of the P-type Ge contactless transistor 300 is connected to the N-type III-V. Group semiconductor nanowire quantum well transistor 400 has the drain connected as an output, that is, the first source electrode 3051 and the second drain electrode 4052 are connected as Vout. The N-type III-V group semiconductor nanowire quantum well transistor 400 has The source, that is, the second source electrode 4051 is grounded to GND, and the P-type Ge contactless transistor 300 is connected to the gate of the N-type III-V semiconductor nanowire quantum well transistor 400, that is, the first gate The electrode is connected to the second gate electrode as an input Vin.
在本實施例中,所述第一閘金屬層3031與第一閘電極一體成型,所述第二閘金屬層4031與第二閘電極一體成型。 In this embodiment, the first gate metal layer 3031 is integrally formed with the first gate electrode, and the second gate metal layer 4031 is integrally formed with the second gate electrode.
在本實施例中,所述P型Ge無接面電晶體和N型III-V族半導體奈米線量子阱電晶體周圍設有淺溝渠隔離結構(STI)。 In this embodiment, a shallow trench isolation structure (STI) is provided around the P-type Ge contactless transistor and the N-type III-V semiconductor nanowire quantum well transistor.
下面結合附圖進一步詳細說明本實施例提供的互補電晶體元件結構的製作方法。 The manufacturing method of the complementary transistor element structure provided in this embodiment is further described in detail below with reference to the accompanying drawings.
請參閱第4圖、第5a-5e圖和第6a-6f圖,本實施例提供一種互補電晶體元件結構的製作方法,包括如下步驟:提供一具有絕緣埋層的SiGe基板;在所述SiGe基板上圖形化有源區並形成在有源區內懸架於絕緣埋層上方的Ge奈米線;以所述Ge奈米線為基礎製作P型Ge無接面電晶體和N型III-V族半導體奈米線量子阱電晶體。 Referring to FIGS. 4, 5a-5e and 6a-6f, this embodiment provides a method for manufacturing a complementary transistor element structure, including the following steps: providing a SiGe substrate with an insulating buried layer; and in the SiGe The active area is patterned on the substrate and a Ge nanowire suspended above the insulating buried layer is formed in the active area; a P-type Ge contactless transistor and an N-type III-V are fabricated based on the Ge nanowire. Group semiconductor nanowire quantum well transistor.
其中,形成所述Ge奈米線的方法可以根據實際情況而定,作為本發明的一個優選方案,具體形成所述Ge奈米線的方法可以如第4圖所示,包括如下步驟: The method for forming the Ge nanowire may be determined according to the actual situation. As a preferred solution of the present invention, the method for forming the Ge nanowire may be shown in FIG. 4 and includes the following steps:
a在所述具有絕緣埋層的SiGe基板上圖形化有源區並蝕刻,得到長條型SiGe層。本實施例採用SiGeOI結構進行圖形化有源區和蝕刻,SiGeOI結構即絕緣體上SiGe,包括Si基底、Si基底上的埋層氧化層BOX、埋層氧化層BOX層上的SiGe層。絕緣埋層採用埋層氧化層BOX。 a patterning an active region on the SiGe substrate with an insulating buried layer and etching to obtain a long SiGe layer. In this embodiment, a SiGeOI structure is used for patterning the active area and etching. The SiGeOI structure, that is, SiGe on insulator, includes a Si substrate, a buried oxide layer BOX on the Si substrate, and a SiGe layer on the buried oxide layer BOX layer. The buried buried layer uses a buried oxide layer BOX.
b填充淺溝渠隔離材料STI,並進行表面平坦化。 b Fill the shallow trench isolation material STI and perform surface planarization.
c圖形化所述淺溝渠隔離材料STI,露出有源區內的長條型SiGe層。 c patterning the shallow trench isolation material STI to expose the long SiGe layer in the active region.
d採用緩衝HF蝕刻液進行溼式蝕刻,長條型SiGe層下面的BOX會從側面被蝕刻掉(undercut),得到懸架於絕緣埋層BOX上方的SiGe奈米線條。 d The buffer HF etching solution is used for wet etching, and the BOX under the long SiGe layer will be undercut from the side to obtain SiGe nano-lines suspended above the insulating buried layer BOX.
e氧化所述SiGe奈米線條生成表面氧化物,使Ge濃縮。 e oxidizes the SiGe nano-lines to form surface oxides, so that Ge is concentrated.
f去除所述表面氧化物。 f Remove the surface oxide.
g在H2環境下高溫退火,形成圓柱狀的長條型Ge奈米線。 g is annealed at a high temperature in an H 2 environment to form a cylindrical elongated Ge nanowire.
可選地,形成所述Ge奈米線時,可反復進行步驟d和步驟e,使Ge濃縮至所需程度。反復進行步驟d和步驟e的次數可根據實際情況,視需要而定。 Optionally, when the Ge nanowire is formed, steps d and e can be repeatedly performed to concentrate Ge to a desired degree. The number of repetitions of steps d and e can be determined according to actual conditions and needs.
如第5a-5e圖所示,所述P型Ge無接面電晶體的製作方法可包括如下步驟: As shown in Figures 5a-5e, the method for manufacturing the P-type Ge contactless transistor may include the following steps:
S101以所述Ge奈米線為第一通道301。 S101 uses the Ge nanowire as the first channel 301.
S102在所述Ge奈米線上進行Ge磊晶生長,形成環繞所述Ge奈米線的重摻雜P型Ge材料層302’;磊晶生長重摻雜P型Ge材料層302’的方法可以為分子束磊晶(MBE)、原子層沉積(ALD)、金屬有機化合物化學氣相沉積(MOCVD),或其他適合的製程。 S102 performs epitaxial growth of Ge on the Ge nanowire to form a heavily doped P-type Ge material layer 302 'surrounding the Ge nanowire; a method of epitaxial growth of the heavily doped P-type Ge material layer 302' may It is molecular beam epitaxy (MBE), atomic layer deposition (ALD), metal organic compound chemical vapor deposition (MOCVD), or other suitable processes.
S103去除環繞所述Ge奈米線的重摻雜P型Ge材料層302’的中段部分形成第一溝渠,得到分別環繞所述Ge奈米線兩端的P型源區3021和P型汲區3022,露出懸架於所述第一溝渠內的部分Ge奈米線及所述Ge奈米 線下方的部分絕緣埋層200;形成所述第一溝渠可以通過微影和感應耦合電漿(ICP)乾式蝕刻完成。 S103 removes a middle portion of the heavily doped P-type Ge material layer 302 ′ surrounding the Ge nanowire to form a first trench, and obtains a P-type source region 3021 and a P-type drain region 3022 that surround the two ends of the Ge nanowire. To expose part of the Ge nanowire suspended in the first trench and part of the buried insulating layer 200 below the Ge nanowire; forming the first trench can be performed by lithography and inductively coupled plasma (ICP) dry-type Etching is complete.
S104形成第一閘介電層3032,所述第一閘介電層3032包裹所述第一溝渠內露出的部分Ge奈米線的表面,以及所述第一溝渠露出的P型源區3021表面、P型汲區3022表面和部分絕緣埋層200的表面;形成所述第一閘介電層3032的方法可以是MOCVD、ALD、電漿增強化學氣相沉積(PECVD)或其他適合的製程,所述第一閘介電層3032的材料採用高介電常數材料,例如Al2O3、TiSiOx、HfSiON、HfO2、HfSiOx、ZrSiOx以及ZrO2或其他適合的材料。 S104 forms a first gate dielectric layer 3032. The first gate dielectric layer 3032 covers a surface of a part of the Ge nanowire exposed in the first trench, and a surface of the P-type source region 3021 exposed in the first trench. , The surface of the P-type drain region 3022 and the surface of the part of the buried insulating layer 200; the method for forming the first gate dielectric layer 3032 may be MOCVD, ALD, plasma enhanced chemical vapor deposition (PECVD), or other suitable processes, The first gate dielectric layer 3032 is made of a high dielectric constant material, such as Al 2 O 3 , TiSiO x , HfSiON, HfO 2 , HfSiO x , ZrSiO x , ZrO 2 or other suitable materials.
S105形成第一閘金屬層3031,所述第一閘金屬層3031在所述第一溝渠內環繞被所述第一閘介電層3032包裹的所述Ge奈米線。形成所述第一閘金屬層3031的方法可以是物理氣相沉積(PVD)、MOCVD、ALD、MBE,或其他適合的製程,所述第一閘金屬層3031的材料可以是TiN、NiAu、CrAu、Au/Ge/Ni疊層、Ti/Pt疊層和Ti/Au疊層中的一種或多種,或其他適合的金屬。 S105 forms a first gate metal layer 3031, and the first gate metal layer 3031 surrounds the Ge nanowire wrapped by the first gate dielectric layer 3032 in the first trench. The method for forming the first gate metal layer 3031 may be physical vapor deposition (PVD), MOCVD, ALD, MBE, or other suitable processes. The material of the first gate metal layer 3031 may be TiN, NiAu, CrAu , Au / Ge / Ni stack, Ti / Pt stack and Ti / Au stack, or other suitable metals.
本實施例中,所述P型Ge無接面電晶體的製作方法還包括:形成引出所述第一閘金屬層3031的第一閘電極,並在所述第一閘電極周圍形成側牆隔離結構500;形成分別設於所述P型源區3021和P型汲區3022上的第一源電極3051和第一汲電極3052。其中,形成第一閘金屬層時,使閘金屬材料填充所述第一溝渠並突出於所述第一溝渠表面,突出於所述第一溝渠表面的閘金屬材料作為第一閘電極,即第一閘電極與第一閘金屬層一體成型。形成第一源電極3051和第一汲電極3052可採用如NiAu等金屬材料。 In this embodiment, the method for manufacturing the P-type Ge no-contact transistor further includes: forming a first gate electrode that leads to the first gate metal layer 3031, and forming a side wall isolation around the first gate electrode. Structure 500; forming a first source electrode 3051 and a first drain electrode 3052 disposed on the P-type source region 3021 and the P-type drain region 3022, respectively. When the first gate metal layer is formed, the gate metal material fills the first trench and protrudes from the surface of the first trench, and the gate metal material protruding from the surface of the first trench serves as the first gate electrode, that is, the first gate electrode. A gate electrode is integrally formed with the first gate metal layer. The first source electrode 3051 and the first drain electrode 3052 may be formed using a metal material such as NiAu.
如第6a-6f圖所示,所述N型III-V族半導體奈米線量子阱電晶 體的製作方法包括如下步驟: As shown in Figures 6a-6f, the method for manufacturing the N-type III-V semiconductor nanowire quantum well electric crystal includes the following steps:
S201在所述Ge奈米線表面磊晶生長N型InGaAs材料作為二維電子氣層4012,得到第二通道401,所述第二通道401包括Ge奈米線通道4011和環繞包裹所述Ge奈米線通道4011的二維電子氣層4012。 S201 epitaxially grows an N-type InGaAs material on the surface of the Ge nanowire as a two-dimensional electron gas layer 4012 to obtain a second channel 401. The second channel 401 includes a Ge nanowire channel 4011 and surrounds the Ge nanowire. The two-dimensional electron gas layer 4012 of the noodle channel 4011.
S202磊晶生長形成環繞包裹所述第二通道401的重摻雜N型InGaAs材料層402’。 S202 is epitaxially grown to form a heavily doped N-type InGaAs material layer 402 'surrounding the second channel 401.
其中,磊晶生長InGaAs材料作為二維電子氣層4012和磊晶生長重摻雜N型InGaAs材料層402’可以採用MBE、ALD、MOCVD、或其他適合的製程。 The epitaxially grown InGaAs material is used as the two-dimensional electron gas layer 4012 and the epitaxially grown heavily doped N-type InGaAs material layer 402 'may adopt MBE, ALD, MOCVD, or other suitable processes.
S203去除環繞所述第二通道401的重摻雜N型InGaAs材料層402’的中段部分形成第二溝渠,得到分別環繞所述第二通道兩端的N型源區4021和N型汲區4022,露出懸架於所述第二溝渠內的部分第二通道401及所述第二通道401下方的部分絕緣埋層200;形成所述第二溝渠可通過微影和ICP乾式蝕刻完成。 S203 removes the middle portion of the heavily doped N-type InGaAs material layer 402 'surrounding the second channel 401 to form a second trench, and obtains an N-type source region 4021 and an N-type drain region 4022 respectively surrounding the two ends of the second channel. A part of the second channel 401 suspended in the second trench and a part of the insulating buried layer 200 below the second channel 401 are exposed; forming the second trench can be completed by lithography and ICP dry etching.
S204形成阻擋層404,所述阻擋層404包裹所述第二溝渠內露出的部分第二通道401的表面,以及所述第二溝渠露出的N型源區4021和N型汲區4022的表面;形成所述阻擋層404的方法可以為磊晶生長N型矽摻雜的InP。具體地,形成所述阻擋層404時,可採用MOCVD、MBE、ALD、或其他適合的製程,矽摻雜的濃度可以為1.2×1018cm-3。 S204 forms a blocking layer 404, which covers the surface of a portion of the second channel 401 exposed in the second trench and the surfaces of the N-type source region 4021 and the N-type drain region 4022 exposed by the second trench; The method for forming the blocking layer 404 may be epitaxial growth of N-type silicon-doped InP. Specifically, when the barrier layer 404 is formed, MOCVD, MBE, ALD, or other suitable processes may be used, and the concentration of silicon doping may be 1.2 × 10 18 cm -3 .
S205形成第二閘介電層4032,所述第二閘介電層4032覆蓋所述阻擋層404表面以及所述第二溝渠露出的部分絕緣埋層200的表面;形成所述第二閘介電層4032的方法可以是MOCVD、ALD、PECVD、或其他適合 的製程,所述第二閘介電層4032的材料採用高介電常數材料,例如Al2O3、TiSiOx、HfSiON、HfO2、HfSiOx、ZrSiOx以及ZrO2或其他適合的材料。 S205 forms a second gate dielectric layer 4032, and the second gate dielectric layer 4032 covers the surface of the barrier layer 404 and the surface of a part of the buried insulating layer 200 exposed by the second trench; forming the second gate dielectric The method of layer 4032 may be MOCVD, ALD, PECVD, or other suitable processes. The material of the second gate dielectric layer 4032 is a high dielectric constant material, such as Al 2 O 3 , TiSiO x , HfSiON, HfO 2 , HfSiO x , ZrSiO x and ZrO 2 or other suitable materials.
S206形成第二閘金屬層4031,所述第二閘金屬層4031在所述第二溝渠內環繞被所述第二閘介電層4032和阻擋層404包裹的所述第二通道401;形成所述第二閘金屬層4031的材料可以是TiN、NiAu、CrAu、Au/Ge/Ni疊層、Ti/Pt疊層和Ti/Au疊層中的一種或多種,或其他適合的金屬。 S206 forms a second gate metal layer 4031, and the second gate metal layer 4031 surrounds the second channel 401 surrounded by the second gate dielectric layer 4032 and the barrier layer 404 in the second trench; The material of the second gate metal layer 4031 may be one or more of TiN, NiAu, CrAu, Au / Ge / Ni stack, Ti / Pt stack, and Ti / Au stack, or other suitable metals.
本實施例中,所述N型III-V族半導體奈米線量子阱電晶體的製作方法還包括:形成引出所述第二閘金屬層4031的第二閘電極,並在所述第二閘電極周圍形成側牆隔離結構500;形成分別設於所述N型源區4021和N型汲區4022上的第二源電極4051和第二汲電極4052。具體地,在形成第二閘金屬層4031時,可以使閘金屬材料填充所述第二溝渠並突出於所述第二溝渠表面,突出於所述第二溝渠表面的閘金屬材料作為第二閘電極,然後通過ICP蝕刻掉不需要的第二閘介電層4032和阻擋層404,留出用於形成第二源電極4051和第二汲電極4052的空間,製作側牆隔離結構500,最後採用如NiAu等金屬材料完成第二源電極4051和第二汲電極4052的沉積。 In this embodiment, the method for manufacturing the N-type III-V semiconductor nanowire quantum well transistor further includes: forming a second gate electrode that leads to the second gate metal layer 4031, and forming a second gate electrode on the second gate. A sidewall isolation structure 500 is formed around the electrodes; a second source electrode 4051 and a second drain electrode 4052 are formed on the N-type source region 4021 and the N-type drain region 4022, respectively. Specifically, when the second gate metal layer 4031 is formed, a gate metal material may fill the second trench and protrude from the surface of the second trench, and the gate metal material protruding from the surface of the second trench is used as the second gate. Electrode, and then etch away the unwanted second gate dielectric layer 4032 and barrier layer 404 by ICP, leaving space for forming the second source electrode 4051 and the second drain electrode 4052, making a sidewall isolation structure 500, and finally using Metal materials such as NiAu complete the deposition of the second source electrode 4051 and the second drain electrode 4052.
實際應用中,可根據電路設計的需要,將所述P型Ge無接面電晶體和N型III-V族半導體奈米線量子阱電晶體的電極連接引出,得到互補型電晶體。 In practical applications, the electrodes of the P-type Ge contactless transistor and the N-type III-V semiconductor nanowire quantum well transistor can be connected to each other according to the needs of circuit design to obtain a complementary transistor.
綜上所述,本發明的互補型電晶體結構,包括閘極全包圍的P型Ge無接面電晶體(JLT)和N型III-V族半導體奈米線量子阱場效電晶體(QWFET),並採用了高K閘介電材料。相對於平面型元件,本發明簡化了源汲區域的圖形設計,同時實現了寄生電阻的顯著減少。相比於平面型場效 應管,閘極全包圍的奈米線FET明顯改善了靜電完整性,從而具有更好的元件閘極控制能力,更適用於低功耗邏輯電路產品的應用。所以,本發明有效克服了現有技術中的種種缺點而具高度產業利用價值。 In summary, the complementary transistor structure of the present invention includes a P-type Ge contactless transistor (JLT) surrounded by a gate and an N-type III-V semiconductor nanowire quantum well field-effect transistor (QWFET ), And uses high-K gate dielectric materials. Compared with the planar element, the present invention simplifies the graphic design of the source-drain region, while achieving a significant reduction in parasitic resistance. Compared with the planar field effect transistor, the nanowire FET surrounded by the gate significantly improves the electrostatic integrity, so it has better component gate control ability and is more suitable for the application of low power logic circuit products. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.
上述實施例僅例示性說明本發明的原理及其功效,而非用於限制本發明。任何熟悉此技術的人士皆可在不違背本發明的精神及範疇下,對上述實施例進行修飾或改變。因此,舉凡所屬技術領域中具有通常知識者在未脫離本發明所揭示的精神與技術思想下所完成的一切等效修飾或改變,仍應由本發明的權利要求所涵蓋。 The above-mentioned embodiments merely illustrate the principle of the present invention and its effects, but are not intended to limit the present invention. Anyone familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field to which they belong without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.
Claims (28)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
??201610986588.1 | 2016-11-09 | ||
CN201610986588.1A CN108063143B (en) | 2016-11-09 | 2016-11-09 | Complementary transistor device structure and manufacturing method thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201830672A true TW201830672A (en) | 2018-08-16 |
TWI647823B TWI647823B (en) | 2019-01-11 |
Family
ID=62136940
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW106111938A TWI647823B (en) | 2016-11-09 | 2017-04-10 | Complementary transistor element structure and manufacturing method thereof |
Country Status (2)
Country | Link |
---|---|
CN (1) | CN108063143B (en) |
TW (1) | TWI647823B (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109244073B (en) * | 2018-09-03 | 2020-09-29 | 芯恩(青岛)集成电路有限公司 | Semiconductor device structure and manufacturing method thereof |
US11799035B2 (en) * | 2019-04-12 | 2023-10-24 | The Research Foundation For The State University Of New York | Gate all-around field effect transistors including quantum-based features |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100585111B1 (en) * | 2003-11-24 | 2006-06-01 | 삼성전자주식회사 | Non-planar transistor having germanium channel region and method for forming the same |
US7154118B2 (en) * | 2004-03-31 | 2006-12-26 | Intel Corporation | Bulk non-planar transistor having strained enhanced mobility and methods of fabrication |
US8188513B2 (en) * | 2007-10-04 | 2012-05-29 | Stc.Unm | Nanowire and larger GaN based HEMTS |
KR101678044B1 (en) * | 2011-12-19 | 2016-11-21 | 인텔 코포레이션 | Non-planar iii-n transistor |
US9240410B2 (en) * | 2011-12-19 | 2016-01-19 | Intel Corporation | Group III-N nanowire transistors |
KR102104062B1 (en) * | 2013-10-31 | 2020-04-23 | 삼성전자 주식회사 | Substrate structure, complementary metal oxide semiconductor device and method of manufacturing complementary metal oxide semiconductor |
CN104752200A (en) * | 2013-12-27 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Transistor and manufacturing method thereof |
US9287360B1 (en) * | 2015-01-07 | 2016-03-15 | International Business Machines Corporation | III-V nanowire FET with compositionally-graded channel and wide-bandgap core |
-
2016
- 2016-11-09 CN CN201610986588.1A patent/CN108063143B/en active Active
-
2017
- 2017-04-10 TW TW106111938A patent/TWI647823B/en active
Also Published As
Publication number | Publication date |
---|---|
CN108063143A (en) | 2018-05-22 |
TWI647823B (en) | 2019-01-11 |
CN108063143B (en) | 2020-06-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9397226B2 (en) | Vertical field effect transistors with controlled overlap between gate electrode and source/drain contacts | |
TWI695507B (en) | Crystalline multiple-nanosheet iii-v channel fets and methods of fabricating the same | |
TWI685972B (en) | Crystalline multiple-nanosheet strained channel fets | |
Moon et al. | Investigation of silicon nanowire gate-all-around junctionless transistors built on a bulk substrate | |
US9564514B2 (en) | Reducing direct source-to-drain tunneling in field effect transistors with low effective mass channels | |
US8716156B1 (en) | Methods of forming fins for a FinFET semiconductor device using a mandrel oxidation process | |
EP3127862A1 (en) | Gate-all-around nanowire device and method for manufacturing such a device | |
US10103268B2 (en) | Vertical junctionless transistor devices | |
CN108172549B (en) | Stacked fence nanowire CMOS field effect transistor structure and manufacturing method | |
TWI572033B (en) | Field effect transistor with heterostructure channel and manufacturing method thereof | |
CN109979938A (en) | Field effect transistor, system on chip and the method for manufacturing it | |
TWI630719B (en) | Expitaxially regrown heterostructure nanowire lateral tunnel field effect transistor | |
TW201622159A (en) | Tunneling field effect transistor and methods of making such a transistor | |
US8685817B1 (en) | Metal gate structures for CMOS transistor devices having reduced parasitic capacitance | |
TWI647823B (en) | Complementary transistor element structure and manufacturing method thereof | |
TWI628747B (en) | Method for manufacturing complementary metal-oxide-semiconductor device | |
US11201246B2 (en) | Field-effect transistor structure and fabrication method | |
CN107424994A (en) | Ring grid III-V quantum well transistors and germanium nodeless mesh body pipe and its manufacture method | |
WO2014108940A1 (en) | Field-effect transistor | |
US20230326925A1 (en) | Monolithic complementary field-effect transistors having carbon-doped release layers | |
CN102593177B (en) | Tunneling transistor with horizontal quasi coaxial cable structure and forming method thereof | |
CN102544069B (en) | Tunneling transistor with horizontal alignment coaxial cable structure and method for forming tunneling transistor |