TWI647823B - Complementary transistor element structure and manufacturing method thereof - Google Patents

Abstract

The invention provides a complementary transistor element structure and a method for manufacturing the same, patterning an active region on a SiGe substrate having an insulating buried layer and forming a Ge nanowire suspended above the insulating buried layer in the active region; Based on Ge nanowires, P-type Ge contactless transistors and N-type III-V group semiconductor nanowire quantum well transistors, which are completely surrounded by gates, are fabricated. Compared with the planar element, the complementary three-dimensional transistor structure of the present invention simplifies the graphic design of the source-drain region, at the same time realizes a significant reduction in parasitic resistance, significantly improves the electrostatic integrity of the element, and has a better element gate. Extremely controllable, more suitable for the application of low power logic circuit products.

Description

   Complementary transistor element structure and manufacturing method thereof   

The invention relates to the technical field of integrated circuits, in particular to a complementary transistor element structure and a manufacturing method thereof.

With the further development of integrated circuit technology, it is hoped that the use of ultra-thin body (UTB) such as quantum well structure can prevent the MOS transistor from scaling down to a smaller size to cause more severe short-channel effects. The basic structure of a high electron mobility transistor (HEMT) consists of a tuning doped heterojunction and its source-drain structure. The two-dimensional electron gas (2-DEG) existing in the modulation-doped heterojunction has a high mobility because it is not affected by the scattering of ionized impurity ions. HEMT is a voltage control element. The gate voltage V _g can control the depth of the heterojunction potential well, thereby controlling the areal density of 2-DEG in the potential well, and then controlling the working current of the element.

For GaAs-based HEMTs, the n-Al _x Ga _1-x As control layer (or barrier layer) should be depleted, the thickness is usually several hundred nm, and the doping concentration is 10 ⁷ to 10 ⁸ / cm. ³ . If the thickness of the n-Al _x Ga _1-x As layer is large and the doping concentration is high, then 2-DEG exists at V _g = 0, the element is a depletion element, and the opposite is an enhanced element, that is, When V _g = 0, the Schottky depletion layer extends into the intrinsic GaAs layer; for HEMT, it is mainly to control the doping concentration and thickness of the wide band gap semiconductor layer (control layer), especially the thickness. The 2-DEG surface charge density N _s will be controlled by the gate voltage V _g . However, these element structures are basically traditional planar structures at present, parasitic resistance is high, and gate control is difficult to meet the application of low-voltage logic.

Therefore, it is necessary to break the traditional design and provide a new HEMT component structure to meet the needs of low-voltage logic applications.

In view of the foregoing prior art, an object of the present invention is to provide a complementary transistor element structure and a manufacturing method thereof for solving various problems in the prior art.

In order to achieve the above object and other related objects, the present invention provides a complementary transistor element structure including: a P-type Ge contactless transistor and an N-type III-V semiconductor nanowire quantum well circuit on the same semiconductor substrate. Crystal; between the P-type Ge interfaceless transistor and an N-type III-V semiconductor nanowire quantum well transistor and the P-type Ge interfaceless transistor and an N-type III-V semiconductor nanometer An insulating buried layer is provided between the linear quantum well transistor and the semiconductor substrate, wherein the P-type Ge contactless transistor includes a first channel, and the first channel is a long-shaped P-type Ge nano Rice wire; surrounding the P-type source region and the P-type drain region at both ends of the first channel, the material of the P-type source region and the P-type drain region is heavily doped P-type Ge; A first gate region surrounding the middle of the first channel between a P-type drain region, the first gate region including a first gate metal layer, and connecting the first gate metal layer with the first channel and a P-type source. A first gate dielectric layer separated from the P-type drain region; the N-type III-V group semiconductor nanowire quantum well transistor includes: a second channel The second channel includes a long P-type Ge nanowire channel and a two-dimensional electron gas layer surrounding the P-type Ge nanowire channel. The material of the two-dimensional electron gas layer is N-type InGaAs; N-type source regions and N-type drain regions surrounding the two ends of the second channel, respectively, and the materials of the N-type source regions and N-type drain regions are heavily doped N-type InGaAs; A second gate region surrounding the middle of the second channel between the regions; and a barrier layer separating the second gate region from the second channel, the N-type source region, and the N-type drain region; the second The gate region includes a second gate metal layer and a second gate dielectric layer separating the second gate metal layer from the barrier layer.

Optionally, the thickness of the P-type source region and the P-type drain region surrounding the first channel is 10-200 nm.

Optionally, the thickness of the N-type source region and the N-type drain region surrounding the second channel is 10-200 nm.

Optionally, the thickness of the two-dimensional electron gas layer surrounding the P-type Ge nanowire channel is 10-100 nm.

Optionally, the materials of the first gate dielectric layer and the second gate dielectric layer are high dielectric constant materials.

Alternatively, the material of the first gate dielectric layer and the second gate dielectric layer is selected from _{Al 2 O 3, TiSiO x,} HfSiON, HfO 2, HfSiO x, ZrSiO x , and one or more of ZrO _2.

Optionally, the thickness of the first gate dielectric layer and the second gate dielectric layer are both 1-5 nm.

Optionally, the material of the first gate metal layer and the second gate metal layer is selected from the group consisting of TiN, NiAu, CrAu, Au / Ge / Ni stack, Ti / Pt stack, and Ti / Au stack. One or more.

Optionally, the material of the blocking layer is N-type silicon-doped InP.

Further optionally, the blocking layer has a silicon-doped concentration of 1.2 × 10 ¹⁸ cm ^-3 .

Further optionally, the thickness of the barrier layer is 50-100 nm.

Optionally, the P-type Ge contactless transistor further includes a first gate electrode leading to the first gate metal layer, and first source electrodes respectively provided on the P-type source region and the P-type drain region. And a first drain electrode, a side wall isolation structure is provided around the first gate electrode.

Optionally, the N-type III-V semiconductor nanowire quantum well transistor further includes a second gate electrode that leads to the second gate metal layer, and is disposed in the N-type source region and the N-type drain region, respectively. A second source electrode and a second drain electrode on the upper side, a side wall isolation structure is provided around the second gate electrode.

Optionally, the first gate metal layer is integrally formed with the first gate electrode, and the second gate metal layer is integrally formed with the second gate electrode.

Optionally, a shallow trench isolation structure is provided around the P-type Ge contactless transistor and the N-type III-V semiconductor nanowire quantum well transistor.

In order to achieve the above object and other related objects, the present invention also provides a method for manufacturing a complementary transistor element structure, including the following steps: providing a SiGe substrate with an insulating buried layer; patterning an active region on the SiGe substrate and forming Ge nanowires suspended above the insulating buried layer in the active region; based on the Ge nanowires, P-type Ge contactless transistors and N-type III-V semiconductor nanowire quantum well transistors are fabricated Wherein, the method for manufacturing the P-type Ge contactless transistor includes the following steps: S101 uses the Ge nanowire as a first channel; S102 performs epitaxial growth of Ge on the Ge nanowire to form a surround structure. The heavily doped P-type Ge material layer of the Ge nanowire is removed; S103 removes a middle portion of the heavily doped P-type Ge material layer that surrounds the Ge nanowire to form a first trench to obtain the Ge nanowires respectively. The P-type source region and the P-type drain region at both ends expose a part of the Ge nanowire suspended in the first trench and a part of the buried insulating layer below the Ge nanowire; S104 forms a first gate dielectric layer, The first gate dielectric layer surrounds a part of Ge exposed in the first trench. The surface of the rice noodle, and the surface of the P-type source region, the surface of the P-type drain region, and the surface of the buried buried layer exposed by the first trench; S105 forms a first gate metal layer, and the first gate metal layer is in the A first trench surrounds the Ge nanowires wrapped by the first gate dielectric layer; the method for manufacturing the N-type III-V group semiconductor nanowire quantum well transistor includes the following steps: S201 in the An N-type InGaAs material is epitaxially grown on the surface of a Ge nanowire as a two-dimensional electron gas layer to obtain a second channel, and the second channel includes a Ge nanowire and a two-dimensional electron gas layer surrounding the Ge nanowire; S202 is epitaxially grown to form a heavily doped N-type InGaAs material layer that surrounds the second channel; S203 removes a middle portion of the heavily doped N-type InGaAs material layer that surrounds the second channel to form second trenches, which respectively surround The N-type source region and the N-type drain region at both ends of the second channel expose part of the second channel suspended in the second trench and part of the insulating buried layer below the second channel; S204 forms a barrier layer, so The blocking layer covers a part of the second trench that is exposed in the second trench. The surface of the track, and the surface of the N-type source region and the N-type drain region exposed by the second trench; S205 forms a second gate dielectric layer, and the second gate dielectric layer covers the surface of the barrier layer and the The surface of the part of the buried buried layer exposed by the second trench; S206 forms a second gate metal layer, and the second gate metal layer surrounds the interior of the second trench surrounded by the second gate dielectric layer and the barrier layer. Mentioned second channel.

Optionally, the method for forming the Ge nanowire includes the following steps: a) patterning an active region on the SiGe substrate with an insulating buried layer and etching to obtain a long SiGe layer; b) filling a shallow trench isolation material And planarize the surface; c pattern the shallow trench isolation material to expose the long SiGe layer in the active region; d perform wet etching to obtain SiGe nanometer lines suspended above the buried insulating layer; e oxidation The SiGe nano-lines generate surface oxides to enrich Ge; f removes the surface oxides; and g anneals at a high temperature in an H ₂ environment to form cylindrical long Ge nanowires.

Optionally, when the Ge nanowire is formed, step d and step e are repeatedly performed to concentrate Ge to a desired degree.

Optionally, the first trench and the second trench are formed by lithography and inductively coupled plasma dry etching.

Optionally, a material forming the first gate dielectric layer and the second gate dielectric layer is a high dielectric constant material.

Alternatively, the material forming the first gate dielectric layer and the second gate dielectric layer is selected from _{Al 2 O 3, TiSiO x,} HfSiON, HfO 2, a medium of ₂ HfSiO _x, ZrSiO _x or more, and ZrO .

Optionally, a material forming the first gate metal layer and the second gate metal layer is selected from the group consisting of TiN, NiAu, CrAu, Au / Ge / Ni stack, Ti / Pt stack, and Ti / Au stack One or more.

Optionally, the method for forming the barrier layer is epitaxial growth of N-type silicon-doped InP.

Further optionally, when the barrier layer is formed, the concentration of silicon doping is 1.2 × 10 ¹⁸ cm ^-3 .

Optionally, the method for manufacturing the P-type Ge contactless transistor further includes: forming a first gate electrode that leads to the first gate metal layer, and forming a sidewall isolation structure around the first gate electrode; A first source electrode and a first drain electrode are formed on the P-type source region and the P-type drain region, respectively.

Optionally, when forming the first gate metal layer, a gate metal material fills the first trench and protrudes from the surface of the first trench, and the gate metal material protruding from the surface of the first trench serves as the first gate electrode.

Optionally, the method for manufacturing the N-type III-V semiconductor nanowire quantum well transistor further includes: forming a second gate electrode that leads to the second gate metal layer, and surrounding the second gate electrode. Forming a sidewall isolation structure; forming a second source electrode and a second drain electrode respectively disposed on the N-type source region and the N-type drain region.

Optionally, when forming the second gate metal layer, a gate metal material fills the second trench and protrudes from the surface of the second trench, and the gate metal material protruding from the surface of the second trench serves as the second gate electrode.

As described above, the complementary transistor element structure and manufacturing method of the present invention have the following beneficial effects: The complementary transistor provided by the present invention includes a P-type Ge junctionless transistor (JLT) surrounded by a gate. ) And N-type III-V semiconductor nanowire quantum well field effect transistor (QWFET), and high-K gate dielectric materials are used. Compared with the planar element, the complementary three-dimensional transistor structure of the present invention simplifies the graphic design of the source-drain region, at the same time realizes a significant reduction in parasitic resistance, significantly improves the electrostatic integrity of the element, and has a better element gate The control ability is more suitable for the application of low power logic circuit products.

100‧‧‧ semiconductor substrate

200‧‧‧ Insulated buried layer

301‧‧‧First channel

3021‧‧‧P-type source area

3022‧‧‧P Type

3031‧‧‧First Gate Metal Layer

3032‧‧‧First gate dielectric layer

3051‧‧‧First source electrode

3052‧‧‧first drain electrode

401‧‧‧Second Channel

4011‧‧‧P Type Ge Nanowire Channel

4012‧‧‧Two-dimensional electronic gas layer

4021‧‧‧N-type source area

4022‧‧‧N Type

4031‧‧‧Second gate metal layer

404‧‧‧ barrier

4032‧‧‧Second gate dielectric layer

3051‧‧‧First source electrode

3052‧‧‧first drain electrode

4051‧‧‧Second source electrode

4052‧‧‧Second Drain Electrode

500‧‧‧Side wall isolation structure

FIG. 1 is a schematic diagram showing a structure of a complementary transistor element according to an embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view of a channel of a P-type Ge contactless transistor according to an embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view of a channel of an N-type III-V semiconductor nanowire quantum well transistor according to an embodiment of the present invention.

FIG. 4 is a schematic diagram of a manufacturing process of a Ge nanowire according to an embodiment of the present invention.

5a-5e are schematic diagrams showing the manufacturing process of a P-type Ge contactless transistor provided by an embodiment of the present invention.

Figures 6a-6f are schematic diagrams showing the manufacturing process of an N-type III-V group semiconductor nanowire quantum well transistor according to an embodiment of the present invention.

The following describes the embodiments of the present invention through specific specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through different specific implementations, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, in the case of no conflict, the following embodiments and features in the embodiments can be combined with each other.

It should be noted that the illustrations provided in the following embodiments are only a schematic illustration of the basic idea of the present invention, and the drawings only show the components related to the present invention and not the number, shape and For size drawing, the type, quantity, and proportion of each component can be changed at will in actual implementation, and the component layout type may be more complicated.

Please refer to FIG. 1. This embodiment provides a complementary transistor device structure, which includes a P-type Ge contactless transistor 300 and an N-type III-V semiconductor nanowire quantum well located on the same semiconductor substrate 100. Transistor 400; between the P-type Ge contactless transistor 300 and the N-type III-V group semiconductor nanowire quantum well transistor 400 and the P-type Ge contactless transistor 300 and the N-type III- A buried buried layer 200 is provided between the group V semiconductor nanowire quantum well transistor 400 and the semiconductor substrate 100. In this embodiment, the semiconductor substrate 100 is a Si substrate, and the insulating buried layer is a buried oxide layer (BOX).

Wherein, the P-type Ge contactless transistor 300 includes: a first channel 301, and the first channel 301 is a long P-type Ge nanowire; and the P-type electrodes that surround the two ends of the first channel 301, respectively. A source region 3021 and a P-type drain region 3022. The material of the P-type source region 3021 and the P-type drain region 3022 is heavily doped P-type Ge; and is located between the P-type source region 3021 and the P-type drain region 3022. The first gate region in the middle of the first channel 301 includes the first gate metal layer 3031 and the first gate metal layer 3031 and the first channel 301, a P-type source region 3021, and P The first gate dielectric layer 3032 is separated by the type drain region 3022. The channel cross section of the P-type Ge-free contactless transistor is shown in FIG. 2.

The N-type III-V group semiconductor nanowire quantum well transistor 400 includes a second channel 401. The second channel 401 includes an elongated P-type Ge nanowire channel 4011 and surrounds the P-type. A two-dimensional electron gas layer 4012 of the Ge nanowire channel 4011. The material of the two-dimensional electron gas layer 4012 is N-type InGaAs. The N-type source region 4021 and the N-type drain region 4022 that surround the two ends of the second channel 401, respectively. A material of the N-type source region 4021 and the N-type drain region 4022 is a heavily doped N-type InGaAs; a second region between the N-type source region 4021 and the N-type drain region 4022 and surrounding the middle of the second channel 401; A gate region; and a barrier layer 404 separating the second gate region from the second channel 401, an N-type source region 4021, and an N-type drain region 4022; the second gate region includes a second gate metal layer 4031 And a second gate dielectric layer 4032 separating the second gate metal layer 4031 from the barrier layer 404. The channel cross-sectional structure of the N-type III-V semiconductor nanowire quantum well transistor is shown in FIG. 3.

In this embodiment, the thickness of the P-type source region 3021 and the P-type drain region 3022 surrounding the first channel 301 may be 10-200 nm. The thickness of the N-type source region 4021 and the N-type drain region 4022 surrounding the second channel 401 may be 10-200 nm.

In this embodiment, the thickness of the two-dimensional electron gas layer 4012 surrounding the P-type Ge nanowire channel 4011 may be 10-100 nm.

In this embodiment, the materials of the first gate dielectric layer 3032 and the second gate dielectric layer 4032 are both high dielectric constant materials. For example, the material of the first gate dielectric layer 3032 and the second gate dielectric layer 4032 may be selected from Al ₂ O _3, a medium of _{2 TiSiO x, HfSiON, HfO 2} , HfSiO x, ZrSiO x or more, and ZrO , Or other suitable high-K materials. The thicknesses of the first gate dielectric layer 3032 and the second gate dielectric layer 4032 may both be 1-5 nm.

In this embodiment, the material of the first gate metal layer 3031 and the second gate metal layer 4031 may be selected from the group consisting of TiN, NiAu, CrAu, Au / Ge / Ni stack, Ti / Pt stack, and Ti / One or more of the Au stacks, or other suitable metals.

In this embodiment, the material of the blocking layer 404 may be N-type silicon-doped InP. Specifically, the silicon doping concentration of the blocking layer 404 may be 1.2 × 10 ¹⁸ cm ^-3 . The thickness of the blocking layer 404 may be 50-100 nm.

Specifically, the P-type Ge contactless transistor 300 may further include a first gate electrode leading to the first gate metal layer 3031, and the first gate electrode provided on the P-type source region 3021 and the P-type drain region 3022, respectively. A first source electrode 3051 and a first drain electrode 3052 are provided with a spacer 500 around the first gate electrode. The N-type III-V semiconductor nanowire quantum well transistor 400 further includes a second gate electrode that leads to the second gate metal layer 4031, and is provided in the N-type source region 4021 and the N-type drain region 4022, respectively. On the second source electrode 4051 and the second drain electrode 4052 on the upper side, a side wall isolation structure 500 is provided around the second gate electrode.

Wherein, the drain of the P-type Ge contactless transistor 300, that is, the first drain electrode 3052 is connected to a power source + Vdd, and the source of the P-type Ge contactless transistor 300 is connected to the N-type III-V. Group semiconductor nanowire quantum well transistor 400 has the drain connected as an output, that is, the first source electrode 3051 and the second drain electrode 4052 are connected as Vout. The N-type III-V group semiconductor nanowire quantum well transistor 400 has The source, that is, the second source electrode 4051 is grounded to GND, and the P-type Ge contactless transistor 300 is connected to the gate of the N-type III-V semiconductor nanowire quantum well transistor 400, that is, the first gate The electrode is connected to the second gate electrode as an input Vin.

In this embodiment, the first gate metal layer 3031 is integrally formed with the first gate electrode, and the second gate metal layer 4031 is integrally formed with the second gate electrode.

In this embodiment, a shallow trench isolation structure (STI) is provided around the P-type Ge contactless transistor and the N-type III-V semiconductor nanowire quantum well transistor.

The manufacturing method of the complementary transistor element structure provided in this embodiment is further described in detail below with reference to the accompanying drawings.

Referring to FIGS. 4, 5a-5e and 6a-6f, this embodiment provides a method for manufacturing a complementary transistor element structure, including the following steps: providing a SiGe substrate with an insulating buried layer; and in the SiGe The active area is patterned on the substrate and a Ge nanowire suspended above the insulating buried layer is formed in the active area; a P-type Ge contactless transistor and an N-type III-V are fabricated based on the Ge nanowire. Group semiconductor nanowire quantum well transistor.

The method for forming the Ge nanowire may be determined according to the actual situation. As a preferred solution of the present invention, the method for forming the Ge nanowire may be shown in FIG. 4 and includes the following steps:

a patterning an active region on the SiGe substrate with an insulating buried layer and etching to obtain a long SiGe layer. In this embodiment, a SiGeOI structure is used for patterning the active area and etching. The SiGeOI structure, that is, SiGe on insulator, includes a Si substrate, a buried oxide layer BOX on the Si substrate, and a SiGe layer on the buried oxide layer BOX layer. The buried buried layer uses a buried oxide layer BOX.

b Fill the shallow trench isolation material STI and perform surface planarization.

c patterning the shallow trench isolation material STI to expose the long SiGe layer in the active region.

d The buffer HF etching solution is used for wet etching, and the BOX under the long SiGe layer will be undercut from the side to obtain SiGe nano-lines suspended above the insulating buried layer BOX.

e oxidizes the SiGe nano-lines to form surface oxides, so that Ge is concentrated.

f Remove the surface oxide.

g is annealed at a high temperature in an H ₂ environment to form a cylindrical elongated Ge nanowire.

Optionally, when the Ge nanowire is formed, steps d and e can be repeatedly performed to concentrate Ge to a desired degree. The number of repetitions of steps d and e can be determined according to actual conditions and needs.

As shown in Figures 5a-5e, the method for manufacturing the P-type Ge contactless transistor may include the following steps:

S101 uses the Ge nanowire as the first channel 301.

S102 performs epitaxial growth of Ge on the Ge nanowire to form a heavily doped P-type Ge material layer 302 'surrounding the Ge nanowire; a method of epitaxial growth of the heavily doped P-type Ge material layer 302' may It is molecular beam epitaxy (MBE), atomic layer deposition (ALD), metal organic compound chemical vapor deposition (MOCVD), or other suitable processes.

S103 removes a middle portion of the heavily doped P-type Ge material layer 302 ′ surrounding the Ge nanowire to form a first trench, and obtains a P-type source region 3021 and a P-type drain region 3022 that surround the two ends of the Ge nanowire. To expose part of the Ge nanowire suspended in the first trench and part of the buried insulating layer 200 below the Ge nanowire; forming the first trench can be performed by lithography and inductively coupled plasma (ICP) dry-type Etching is complete.

S104 forms a first gate dielectric layer 3032. The first gate dielectric layer 3032 covers a surface of a part of the Ge nanowire exposed in the first trench, and a surface of the P-type source region 3021 exposed in the first trench. , The surface of the P-type drain region 3022 and the surface of the part of the buried insulating layer 200; the method for forming the first gate dielectric layer 3032 may be MOCVD, ALD, plasma enhanced chemical vapor deposition (PECVD), or other suitable processes, The first gate dielectric layer 3032 is made of a high dielectric constant material, such as Al ₂ O ₃ , TiSiO _x , HfSiON, HfO ₂ , HfSiO _x , ZrSiO _x , ZrO ₂ or other suitable materials.

S105 forms a first gate metal layer 3031, and the first gate metal layer 3031 surrounds the Ge nanowire wrapped by the first gate dielectric layer 3032 in the first trench. The method for forming the first gate metal layer 3031 may be physical vapor deposition (PVD), MOCVD, ALD, MBE, or other suitable processes. The material of the first gate metal layer 3031 may be TiN, NiAu, CrAu , Au / Ge / Ni stack, Ti / Pt stack and Ti / Au stack, or other suitable metals.

In this embodiment, the method for manufacturing the P-type Ge no-contact transistor further includes: forming a first gate electrode that leads to the first gate metal layer 3031, and forming a side wall isolation around the first gate electrode. Structure 500; forming a first source electrode 3051 and a first drain electrode 3052 disposed on the P-type source region 3021 and the P-type drain region 3022, respectively. When the first gate metal layer is formed, the gate metal material fills the first trench and protrudes from the surface of the first trench, and the gate metal material protruding from the surface of the first trench serves as the first gate electrode, that is, the first gate electrode. A gate electrode is integrally formed with the first gate metal layer. The first source electrode 3051 and the first drain electrode 3052 may be formed using a metal material such as NiAu.

As shown in Figures 6a-6f, the method for manufacturing the N-type III-V semiconductor nanowire quantum well electric crystal includes the following steps:

S201 epitaxially grows an N-type InGaAs material on the surface of the Ge nanowire as a two-dimensional electron gas layer 4012 to obtain a second channel 401. The second channel 401 includes a Ge nanowire channel 4011 and surrounds the Ge nanowire. The two-dimensional electron gas layer 4012 of the noodle channel 4011.

S202 is epitaxially grown to form a heavily doped N-type InGaAs material layer 402 'surrounding the second channel 401.

The epitaxially grown InGaAs material is used as the two-dimensional electron gas layer 4012 and the epitaxially grown heavily doped N-type InGaAs material layer 402 'may adopt MBE, ALD, MOCVD, or other suitable processes.

S203 removes the middle portion of the heavily doped N-type InGaAs material layer 402 'surrounding the second channel 401 to form a second trench, and obtains an N-type source region 4021 and an N-type drain region 4022 respectively surrounding the two ends of the second channel. A part of the second channel 401 suspended in the second trench and a part of the insulating buried layer 200 below the second channel 401 are exposed; forming the second trench can be completed by lithography and ICP dry etching.

S204 forms a blocking layer 404, which covers the surface of a portion of the second channel 401 exposed in the second trench and the surfaces of the N-type source region 4021 and the N-type drain region 4022 exposed by the second trench; The method for forming the blocking layer 404 may be epitaxial growth of N-type silicon-doped InP. Specifically, when the barrier layer 404 is formed, MOCVD, MBE, ALD, or other suitable processes may be used, and the concentration of silicon doping may be 1.2 × 10 ¹⁸ cm ^-3 .

S205 forms a second gate dielectric layer 4032, and the second gate dielectric layer 4032 covers the surface of the barrier layer 404 and the surface of a part of the buried insulating layer 200 exposed by the second trench; forming the second gate dielectric The method of layer 4032 may be MOCVD, ALD, PECVD, or other suitable processes. The material of the second gate dielectric layer 4032 is a high dielectric constant material, such as Al ₂ O ₃ , TiSiO _x , HfSiON, HfO ₂ , HfSiO _x , ZrSiO _x and ZrO ₂ or other suitable materials.

S206 forms a second gate metal layer 4031, and the second gate metal layer 4031 surrounds the second channel 401 surrounded by the second gate dielectric layer 4032 and the barrier layer 404 in the second trench; The material of the second gate metal layer 4031 may be one or more of TiN, NiAu, CrAu, Au / Ge / Ni stack, Ti / Pt stack, and Ti / Au stack, or other suitable metals.

In this embodiment, the method for manufacturing the N-type III-V semiconductor nanowire quantum well transistor further includes: forming a second gate electrode that leads to the second gate metal layer 4031, and forming a second gate electrode on the second gate. A sidewall isolation structure 500 is formed around the electrodes; a second source electrode 4051 and a second drain electrode 4052 are formed on the N-type source region 4021 and the N-type drain region 4022, respectively. Specifically, when the second gate metal layer 4031 is formed, a gate metal material may fill the second trench and protrude from the surface of the second trench, and the gate metal material protruding from the surface of the second trench is used as the second gate. Electrode, and then etch away the unwanted second gate dielectric layer 4032 and barrier layer 404 by ICP, leaving space for forming the second source electrode 4051 and the second drain electrode 4052, making a sidewall isolation structure 500, and finally using Metal materials such as NiAu complete the deposition of the second source electrode 4051 and the second drain electrode 4052.

In practical applications, the electrodes of the P-type Ge contactless transistor and the N-type III-V semiconductor nanowire quantum well transistor can be connected to each other according to the needs of circuit design to obtain a complementary transistor.

In summary, the complementary transistor structure of the present invention includes a P-type Ge contactless transistor (JLT) surrounded by a gate and an N-type III-V semiconductor nanowire quantum well field-effect transistor (QWFET ), And uses high-K gate dielectric materials. Compared with the planar element, the present invention simplifies the graphic design of the source-drain region, while achieving a significant reduction in parasitic resistance. Compared with the planar field effect transistor, the nanowire FET surrounded by the gate significantly improves the electrostatic integrity, so it has better component gate control ability and is more suitable for the application of low power logic circuit products. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

The above-mentioned embodiments merely illustrate the principle of the present invention and its effects, but are not intended to limit the present invention. Anyone familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field to which they belong without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims (28)

A complementary transistor element structure includes: a P-type Ge interfaceless transistor and an N-type III-V semiconductor nanowire quantum well transistor on the same semiconductor substrate; and the P-type Ge interfaceless transistor Between the N-type III-V group semiconductor nanowire quantum well transistor and the P-type Ge contactless transistor and the N-type III-V group semiconductor nanowire quantum well transistor and the semiconductor substrate An insulating buried layer is provided; wherein the P-type Ge contactless transistor includes: a first channel, the first channel is a long P-type Ge nanowire; A P-type source region and a P-type drain region, and the materials of the P-type source region and the P-type drain region are heavily doped P-type Ge; and the first channel is located between the P-type source region and the P-type drain region and surrounds the first channel A first gate region in the middle, the first gate region including a first gate metal layer and a first gate separating the first gate metal layer from the first channel, a P-type source region, and a P-type drain region A dielectric layer; the N-type III-V semiconductor nanowire quantum well transistor includes: a second channel, the second channel including a long P-type Ge nanowire And a two-dimensional electron gas layer surrounding the P-type Ge nanowire channel, and the material of the two-dimensional electron gas layer is N-type InGaAs; and an N-type source region and an N-type drain that surround the two ends of the second channel, respectively. Material of the N-type source region and the N-type drain region is a heavily doped N-type InGaAs; a second gate region surrounding the middle of the second channel between the N-type source region and the N-type drain region; and A barrier layer separating the second gate region from the second channel, the N-type source region, and the N-type drain region; the second gate region includes a second gate metal layer and the second gate metal layer A second gate dielectric layer spaced from the barrier layer. The complementary transistor element structure according to claim 1, wherein the thickness of the P-type source region and the P-type drain region surrounding the first channel is 10-200 nm. The complementary transistor element structure according to claim 1, wherein the thickness of the N-type source region and the N-type drain region surrounding the second channel is 10-200 nm. The complementary transistor element structure according to claim 1, wherein the thickness of the two-dimensional electron gas layer surrounding the P-type Ge nanowire channel is 10-100 nm. The complementary transistor device structure according to claim 1, wherein a material of the first gate dielectric layer and the second gate dielectric layer is a high dielectric constant material. The complementary transistor element structure according to claim 1, wherein the material of the first gate dielectric layer and the second gate dielectric layer is selected from the group consisting of Al ₂ O ₃ , TiSiO _x , HfSiON, HfO ₂ , HfSiO _x , ZrSiO One or more of _x and ZrO ₂ . The complementary transistor element structure according to claim 1, wherein the thicknesses of the first gate dielectric layer and the second gate dielectric layer are both 1-5 nm. The complementary transistor element structure according to claim 1, wherein the material of the first gate metal layer and the second gate metal layer is selected from the group consisting of TiN, NiAu, CrAu, Au / Ge / Ni stack, Ti / Pt One or more of a stack and a Ti / Au stack. The complementary transistor device structure according to claim 1, wherein a material of the barrier layer is N-type silicon-doped InP. The complementary transistor element structure according to claim 9, wherein a silicon-doped concentration of the blocking layer is 1.2 × 10 ¹⁸ cm ^-3 . The complementary transistor element structure according to claim 9, wherein the thickness of the barrier layer is 50-100 nm. The complementary transistor element structure according to claim 1, wherein the P-type Ge contactless transistor further includes a first gate electrode that leads to the first gate metal layer, and is provided in the P-type source region and A first source electrode and a first drain electrode on the P-type drain region are provided with a side wall isolation structure around the first gate electrode. The complementary transistor element structure according to claim 1, wherein the N-type III-V semiconductor nanowire quantum well transistor further includes a second gate electrode that leads to the second gate metal layer, and is provided in each of the gate electrodes. The second source electrode and the second drain electrode on the N-type source region and the N-type drain region are provided with a side wall isolation structure around the second gate electrode. The complementary transistor element structure according to claim 1, wherein the first gate metal layer is integrally formed with the first gate electrode, and the second gate metal layer is integrally formed with the second gate electrode. The complementary transistor element structure according to claim 1, wherein a shallow trench isolation structure is provided around the P-type Ge contactless transistor and the N-type III-V semiconductor nanowire quantum well transistor. A method for manufacturing a complementary transistor element structure includes the following steps: providing a SiGe substrate with an insulating buried layer; patterning an active region on the SiGe substrate and forming a suspension over the insulating buried layer in the active region; Ge nanowires; based on the Ge nanowires, P-type Ge junctionless transistors and N-type III-V group semiconductor nanowire quantum well transistors are fabricated; wherein the P-type Ge junctionless The method for manufacturing a transistor includes the following steps: S101 uses the Ge nanowire as a first channel; S102 performs epitaxial growth of Ge on the Ge nanowire to form a heavily doped P-type that surrounds the Ge nanowire. Ge material layer; S103 removes the middle portion of the heavily doped P-type Ge material layer surrounding the Ge nanowire to form a first trench, and obtains a P-type source region and a P-type drain region that surround the two ends of the Ge nanowire. A part of the Ge nanowire suspended in the first trench and a part of the buried insulating layer below the Ge nanowire are exposed; S104 forms a first gate dielectric layer, and the first gate dielectric layer surrounds the The surface of a part of the Ge nanowire exposed in the first trench, and the P-type source exposed in the first trench Area, surface of P-type drain area, and part of the surface of the buried buried layer; S105 forms a first gate metal layer, and the first gate metal layer is surrounded by the first gate dielectric layer in the first trench. The Ge nanowire; the method for manufacturing the N-type III-V group semiconductor nanowire quantum well transistor includes the following steps: S201 epitaxially grows an N-type InGaAs material on the surface of the Ge nanowire as a two-dimensional electron Gas layer to obtain a second channel, the second channel including a Ge nanowire and a two-dimensional electron gas layer surrounding the Ge nanowire; S202 epitaxial growth to form a heavily doped surrounding the second channel N-type InGaAs material layer; S203 removes a middle portion of the heavily doped N-type InGaAs material layer surrounding the second channel to form a second trench, and obtains an N-type source region and an N-type drain region surrounding the two ends of the second channel, respectively. To expose a portion of the second channel suspended in the second trench and a portion of the buried insulating layer below the second channel; S204 forms a barrier layer that surrounds a portion of the second channel exposed in the second trench Surface, and the N-type source exposed by the second trench And the surface of the N-type drain region; S205 forms a second gate dielectric layer, and the second gate dielectric layer covers the surface of the barrier layer and the surface of the buried buried layer exposed by the second trench; S206 forms the second A gate metal layer surrounding the second channel surrounded by the second gate dielectric layer and the barrier layer in the second trench. The method for manufacturing a complementary transistor element structure according to claim 16, wherein the method for forming the Ge nanowire includes the following steps: a patterning an active region on the SiGe substrate with an insulating buried layer and etching, Obtain a long SiGe layer; b fill the shallow trench isolation material and planarize the surface; c pattern the shallow trench isolation material to expose the long SiGe layer in the active region; d perform wet etching to obtain a suspension SiGe nano-lines above the buried buried layer; e oxidizes the SiGe nano-lines to generate surface oxides to concentrate Ge; f removes the surface oxides; g anneals at high temperature in an H ₂ environment to form a cylindrical long Striped Ge nanowires. The method for manufacturing a complementary transistor device structure according to claim 17, wherein when the Ge nanowire is formed, steps d and e are repeated to concentrate Ge to a desired level. The method for manufacturing a complementary transistor element structure according to claim 16, wherein the first trench and the second trench are formed by lithography and inductively coupled plasma dry etching. The method for manufacturing a complementary transistor device structure according to claim 16, wherein the materials of the first gate dielectric layer and the second gate dielectric layer are high dielectric constant materials. The method for manufacturing a complementary transistor device structure according to claim 16, wherein the material of the first gate dielectric layer and the second gate dielectric layer is selected from the group consisting of Al ₂ O ₃ , TiSiO _x , HfSiON, HfO ₂ , and HfSiO. One or more of _x , ZrSiO _x and ZrO ₂ . The method for manufacturing a complementary transistor element structure according to claim 16, wherein the material of the first gate metal layer and the second gate metal layer is selected from the group consisting of TiN, NiAu, CrAu, Au / Ge / Ni stack, One or more of a Ti / Pt stack and a Ti / Au stack. The method for manufacturing a complementary transistor device structure according to claim 16, wherein the method for forming the barrier layer is epitaxial growth of N-type silicon-doped InP. The method for fabricating a complementary transistor device structure according to claim 23, wherein, in the blocking layer, a silicon doping concentration is 1.2 × 10 ¹⁸ cm ^-3 . The method for manufacturing a complementary transistor element structure according to claim 16, wherein the method for manufacturing the P-type Ge non-contact transistor further includes: forming a first gate electrode that leads to the first gate metal layer, and A side wall isolation structure is formed around the first gate electrode; a first source electrode and a first drain electrode are respectively formed on the P-type source region and the P-type drain region. The method for manufacturing a complementary transistor element structure according to claim 16, wherein when the first gate metal layer is formed, the gate metal material fills the first trench and protrudes from the surface of the first trench, and protrudes from the first trench. A gate metal material on a trench surface serves as a first gate electrode. The method for fabricating a complementary transistor device structure according to claim 16, wherein the method for fabricating the N-type III-V semiconductor nanowire quantum well transistor further includes: forming a first electrode that leads to the second gate metal layer. Two gate electrodes, and a side wall isolation structure is formed around the second gate electrode; and a second source electrode and a second drain electrode are respectively provided on the N-type source region and the N-type drain region. The method for manufacturing a complementary transistor element structure according to claim 16, wherein when a second gate metal layer is formed, the gate metal material fills the second trench and protrudes from the surface of the second trench, and protrudes from the first trench. The gate metal material on the surface of the two trenches serves as the second gate electrode.