TWI685972B - Crystalline multiple-nanosheet strained channel fets - Google Patents

Abstract

A field effect transistor includes a body layer having a strained crystalline semiconductor channel region, and a gate stack on the channel region. The gate stack includes a crystalline semiconductor gate layer that is lattice mismatched with the channel region, and a crystalline gate dielectric layer between the gate layer and the channel region. Related devices and fabrication methods are also discussed.

Description

Crystalline Strain Channel Field Effect Transistor 【Priority Announcement】

This application is a partial continuation of US Patent Application No. 14/270,690 filed on May 6, 2014. The name of the case is " Crystalline Multiple-Nanosheet III-V Channel FETs and Methods of Fabricating the Same. " The priority of US Provisional Application No. 61/898,815, which was applied on November 1, 2013. The name of the case is " Fully-Crystalline Multiple-Nanosheet III-V Channel MOSFET ", and the entire contents are incorporated into this case for reference. This application also claims the priority of US Provisional Application No. 62/010,585 filed on June 11, 2014. The name of the case is " A Fully Crystalline Multiple-Nanosheet Strained Si/SiGe Channel MOSFET ", and the entire contents are incorporated This case is for reference.

The concept of the present invention relates to semiconductor elements, and more specifically to semi-conductors Conductor field effect transistor element.

Metal-oxide-semiconductor field-effect transistors (MOSFETs) of group III-V semiconductors containing group III-V channel materials can have good CV/I characteristics and relatively low voltages High current. This can be attributed to the relatively high mobility that can be achieved in the channel, and the relatively low parasitic resistance of some semiconductor/metal combinations. The high mobility can be due at least in part to the relatively low effective mass of electrons. Because of the isotropic nature of the effective mass in many III-V semiconductors, the quantum-confinement mass can also be small, which can result in the electron wave function being wide and penetrating to surrounding channels In the gate dielectric layer. The gate dielectric layer may be a non-crystalline layer on the channel and/or may separate the channel from the amorphous gate electrode. The presence of these non-crystalline layers on the surface of a typical crystalline channel may cause carrier scattering (commonly referred to as surface roughness (SR) scattering), which may limit the confined electron (confined electron) Mobility.

Some III-V semiconductor-based MOSFETs containing III-V channel materials may include a crystalline buffer layer (such as indium phosphide (InP)) around the channel. The crystalline buffer layer may have a thickness sufficient to separate the crystalline channel from the non-crystalline layer and help reduce carrier scattering. However, these buffer layers reduce the short-channel performance of the device due to the increased separation between the gate electrode and the channel inversion layer. because Thus, the use of crystalline buffer layers limits the use of III-V group MOSFETs to relatively long gate lengths (eg, greater than about 40 nanometers).

For example, due to the improved static electricity (about fin field effect transistors) and nanochip stacking, Group IV semiconductor-type MOSFETs (such as silicon (Si) and silicon germanium (SiGe) nanochip transistors) can be A choice of 10 nanometer technology. However, improving the DC performance associated with fin field-effect transistors may require relatively wide nanochips to achieve sufficient I _eff in the required layout area and have the required number of stacked nano-crystals Rice slices. The above situation presents difficulty in processing because it may require highly selective etching to undercut one type of nanoplate (such as Si or SiGe) relative to other types of nanoplates (such as SiGe or Si) to produce There are required conduction channels for the desired type of nanosheet material. In addition, the etching process temporarily creates a free surface surrounding the nanosheet, which causes any built-in strain to relax, which limits the effectiveness of the nanosheet.

According to some embodiments of the inventive concept, a field effect transistor includes a stack of nanosheets with multiple individually gated conductive channels. The individually gated conduction channels each include a crystalline semiconductor channel layer, a crystalline gate dielectric layer on the channel layer, and a crystalline semiconductor gate layer, the crystalline semiconductor gate layer is located at On the gate dielectric layer opposite to the channel layer. The nanosheet stack is composed of the crystalline semiconductor channel layer, the junction The lattice mismatch between the crystalline dielectric layer and the crystalline semiconductor gate layer is strained.

In some embodiments, the crystalline channel layer, the crystalline gate dielectric layer, and the crystalline gate layer may be heteroepitaxial layers.

In some embodiments, the field effect transistor may be an n-type device and the crystalline channel layer includes silicon (Si).

In some embodiments, the field effect transistor may be a p-type device and the crystalline channel layer includes silicon germanium (SiGe).

In some embodiments, the crystalline dielectric layer may be calcium fluoride (CaF ₂ ), zinc sulfide (ZnS), oxide oxide (Pr ₂ O ₃ ), and/or gadolinium oxide (Gd ₂ O ₃ ).

In some embodiments, the field effect transistor may be an n-type device, and the crystalline gate layer may be doped silicon germanium (SiGe).

In some embodiments, the field effect transistor may be a p-type device, and the crystalline gate layer may be doped silicon (Si).

According to other embodiments of the inventive concept, the field effect transistor includes a body layer containing a crystalline semiconductor channel region, and a gate stack on the channel region. The gate stack includes a crystalline semiconductor gate layer that has a lattice mismatch with the channel region and includes a crystalline gate dielectric between the gate layer and the channel region Floor.

In some embodiments, the interface between the channel region and the gate stack may be free of amorphous material. For example, the gate dielectric layer may be directly The high dielectric constant crystalline insulating layer on the channel area.

In some embodiments, the gate layer may be directly on the gate dielectric layer. The channel region and the gate layer may be heteroepitaxial strained semiconductor layers.

In some embodiments, the channel region and the gate layer may be different Group IV materials, and the gate layer may be heavily doped relative to the channel region.

In some embodiments, one of the channel region and the gate layer may be compressively strained silicon germanium (SiGe), and the other of the channel region and the gate layer may be Tensile strained silicon (Si).

In some embodiments, the gate layer may include separate crystalline semiconductor gate layers on opposite surfaces of the channel region, and the gate dielectric layer may include separate gate layers and the Gate dielectric layers between the opposing surfaces of the channel area.

In some embodiments, the structure including the gate stack and the body layer may be repeatedly stacked to define a plurality of individually gated channel regions, and may remain in the channel region and the gate electrode throughout the structure Strain in the layer.

In some embodiments, the structure may have a width greater than about 30 nanometers but less than about 100 nanometers. The channel region can be separated from the gate layer by the gate dielectric layer having a thickness of less than about 3 nanometers. The channel region and/or the gate layer may have various thicknesses of less than about 10 nanometers in some embodiments.

In some embodiments, each gate layer on the opposite surface of the channel area may be a main gate layer. The secondary gate layer may be disposed on at least one side wall of the channel region between the opposing surfaces of the channel region. Said The secondary gate layer may be formed of metal material or doped polycrystalline material.

In some embodiments, the plurality of individually gated channel regions may define fins protruding from the substrate, and the secondary gate layer may extend on opposing sidewalls of the fin and on surfaces between the opposing sidewalls .

In some embodiments, an amorphous insulating layer may separate the side wall of the channel region from the secondary gate layer, and the secondary gate layer may be conductively coupled to all of the primary gate layers .

In some embodiments, the source/drain regions may be disposed on opposite ends of the channel region and electrically coupled to the channel region, and adjacent to the gate stack on the channel region. An amorphous insulating layer may separate the opposite sidewalls of the gate layer from the source/drain regions.

According to other embodiments of the inventive concept, a method of manufacturing a field effect transistor includes: providing a body layer including a crystalline semiconductor channel region, and providing a gate stack on the channel region. The gate stack includes a crystalline semiconductor gate layer that is lattice mismatched with the channel region, and includes a crystalline gate dielectric layer between the gate layer and the channel region.

In some embodiments, the gate dielectric layer may be a high dielectric constant crystalline semiconductor layer formed directly on the channel region. The channel region and the gate layer may be strained semiconductor layers.

In some embodiments, the channel region, the gate dielectric layer, and the gate layer may be formed by heteroepitaxial growth.

In some embodiments, the channel region and the gate layer may be different Group IV materials are formed, and the gate layer may be heavily doped with respect to the channel region.

In some embodiments, one of the channel region and the gate layer may be compressively strained silicon germanium (SiGe), and the other of the channel region and the gate layer may be tensile strain Silicon (Si).

In some embodiments, when providing the gate stack, respective gate dielectric layers and respective gate layers on the respective gate dielectric layers may be formed on opposite surfaces of the channel region .

In some embodiments, providing the gate stack and the body layer may include forming a structure including the repeated stack of the gate stack and the body layer to define a plurality of individually gated channel regions.

In some embodiments, the respective gate layers on the opposite surfaces of the channel area may be primary gate layers, and the secondary gate layer may be on the opposite surface of the channel area Is formed on at least one side wall of the channel area. The secondary gate layer may be formed of metal material or doped polycrystalline material.

In some embodiments, the plurality of individually gated channel regions may define fins protruding from the substrate, and the secondary gate layer may be formed on opposing sidewalls of the fin and on surfaces between the opposing sidewalls .

In some embodiments, before forming the secondary gate layer, the sidewall of the channel region may be selectively recessed to define a recess therein, and may be in the sidewall of the channel region An amorphous insulating layer is formed in the recess. The amorphous insulating layer may separate the channel region from the secondary gate layer.

In some embodiments, the relative The sidewall is recessed to define respective recessed regions therein, and an amorphous insulating layer may be formed in the respective recessed regions. Source/drain regions can be epitaxially grown from opposite ends of the channel region, and the amorphous insulating layer can separate the opposite sidewalls of the main gate layer from the source/drain regions.

After reviewing the drawings and detailed description, other elements and/or methods according to some embodiments will become apparent to those of ordinary skill in the art. All such additional embodiments other than any and all combinations of the above embodiments are intended to be included within this description and within the scope of the present invention, and are protected by the scope of the accompanying patent application.

100, 100’, 1300, 1300’, 1300” ‧‧‧ transistor

101, 101’, 1301‧‧‧ Nano tablets

102, 102’, 1302‧‧‧Stack

103’, 1303’, 2420r‧‧‧

105, 105’, 1305, 1305’‧‧‧ channel area

105d, 105d’, 1305d, 1305d’‧‧‧ Drain area

105s, 105s’, 1305s, 1305s’‧‧‧‧ source region

1308d, 1308d’, 1308d” ‧‧‧ metal drain region

1308s, 1308s’, 1308s”‧‧‧‧metal source region

105r’, 115r’, 1315r’‧‧‧ depressed area

106, 106’, 1306‧‧‧ gate stack

107‧‧‧ substrate

110, 110’, 1310, 1310’, 1310” ‧‧‧ dielectric layer

115, 115’, 1315, 1315’, 1315” ‧‧‧ gate layer

420r, 420’, 1020’, 1820r‧‧‧Insulation

420r’, 1020r’‧‧‧ remaining

615, 615’, 2015, 2015’, 2015” ‧‧‧ gate contact layer

1390‧‧‧Gap

The aspect of the present disclosure is illustrated by way of example, and is not limited by the accompanying drawings. Symbols of similar elements indicate similar parts.

FIG. 1A is a perspective view illustrating an FET having a crystalline channel layer, a dielectric layer, and a gate layer according to some embodiments of the inventive concept.

1B and 1C are cross-sectional views taken along lines B-B' and C-C' of FIG. 1A, respectively.

2 to 6 are cross-sectional views taken along line B-B' of FIG. 1A, illustrating a method of manufacturing an FET having a crystalline channel layer, a dielectric layer, and a gate layer according to some embodiments of the inventive concept.

7 to 12 are cross-sectional views taken along line C-C' of FIG. 1A, illustrating a crystalline channel layer, a dielectric layer, and a gate layer according to some embodiments of the inventive concept FET manufacturing method.

13 is a perspective view illustrating an FET having a crystalline channel layer, a dielectric layer, and a gate layer according to other embodiments of the inventive concept.

14A and 14B are cross-sectional views taken along lines A-A' and B-B' of FIG. 13, respectively, illustrating n-channel FETs according to other embodiments of the inventive concept.

15A and 15B are cross-sectional views taken along lines A-A' and B-B' of FIG. 13, respectively, illustrating p-channel FETs according to other embodiments of the inventive concept.

16 to 20 are cross-sectional views taken along line AA' of FIG. 13, respectively, illustrating an n-type FET having a crystalline channel layer, a dielectric layer, and a gate layer according to other embodiments of the inventive concept Manufacturing method.

21 to 26 are cross-sectional views taken along line BB' of FIG. 13, respectively, illustrating an n-type FET having a crystalline channel layer, a dielectric layer, and a gate layer according to some embodiments of the inventive concept Manufacturing method.

Various embodiments will now be described more fully with reference to the drawings, in which some embodiments are presented. However, the inventive concept can be embodied in different forms and should not be interpreted as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that the disclosure will be comprehensive and complete, and fully convey the concept of the present invention to those with ordinary knowledge in the art. In the drawings, the sizes and relative sizes of layers and regions are not drawn to scale, and in some cases, may be exaggerated for clarity.

Present the following description to enable those with ordinary knowledge in the technical field Enough to make and use the invention, and provide the following description in the context of the patent application and its requirements. Various modifications to the exemplary embodiments and general principles and features described herein will be readily apparent. Exemplary embodiments are described primarily in terms of specific methods and systems provided in specific implementations. However, the method and system will operate effectively in other implementations. Words such as "exemplary embodiment", "one embodiment" and "another embodiment" may refer to the same or different embodiments and to multiple embodiments. Embodiments will be described with respect to systems and/or elements with certain components. However, the system and/or elements may include more or less components than those shown, and changes in the configuration and type of the components may be made without departing from the scope of the present invention. Exemplary embodiments will also be described in the context of specific methods with certain steps. However, for other methods with different and/or additional steps and steps in different orders that do not conform to the exemplary embodiments, the method and system can still operate efficiently. Therefore, the present invention is not intended to be limited to the illustrated embodiments, but should conform to the broadest scope consistent with the principles and features described herein.

Some embodiments of the inventive concept stem from the recognition that the use of crystalline buffer materials on and/or around the channel region can suppress SR scattering at the expense of short channel performance, in III-V MOSFETs, mobility and short channel There is a trade-off between performance. Some embodiments of the inventive concept provide a III-V FET structure that reduces and/or eliminates this trade-off to improve the potential of the III-V FET.

In particular, some embodiments of the inventive concept introduce III-V group channel FETs, where the channel layer and the gate stack are formed substantially or entirely by a lattice-matched semiconductor of single crystal. For example, the gate stack may include II-VI wide bandgap high dielectric A coefficient (ie, having a high dielectric constant relative to silicon dioxide) semiconductor serves as the gate dielectric layer, and includes a medium band gap III-V group semiconductor as the gate layer. In some embodiments, the channel material is indium arsenide (InAs), the gate dielectric material is zinc telluride (ZnTe), and the gate material is aluminum antimonide (AlSb). Multiple channel layers (and multiple gate stacks) can be formed, for example, by the target current carrying capacity requirements of the device or based on the target current carrying capacity requirements of the device. Each channel layer can be gated from above and below by a heavily doped AlSb layer. The ZnTe gate dielectric layer can be disposed between each channel layer and the adjacent gate layer. The channel/dielectric/gate stack can be configured as a thin layer, hereinafter referred to as a nanosheet (each thin layer has a width greater than its respective thickness). The entire structure can provide the FET with high channel mobility (for example, this is due to the reduction or minimization of surface roughness (SR) scattering), good short channel performance (for example, this is due to the absence of the channel A conductive buffer layer where the crystalline layer is further separated, thus keeping the inversion layer close to the gate) and low parasitic resistance (for example, this is due to the high conductivity and n-contact of the doped InAs )'S low contact resistance), so it is suitable for technologies below 7nm.

FIG. 1A is a perspective view illustrating a FET having a crystalline channel layer, a dielectric layer, and a gate layer according to some embodiments of the inventive concept, and FIGS. 1B and 1C are along the line BB′ and FIG. 1A, respectively. Cross-sectional view taken by CC'. As shown in FIGS. 1A to 1C, a field-effect transistor (FET) 100 according to some embodiments of the inventive concept includes a semiconductor active layer or body layer having a transistor channel layer or transistor channel region 105 defined and located in the channel region The structure of the semiconductor gate stack 106 on 105. The gate stack 106 includes a crystalline gate dielectric layer 110 and a crystalline gate dielectric The crystalline gate layer 115 on the electrical layer 110 (also referred to herein as the main gate layer or the first gate electrode). The crystalline gate dielectric layer 110 may be a high dielectric constant wide band gap semiconductor, and the crystalline gate layer 115 may be a medium band gap semiconductor with high dopant activation. For example, the structure may include an indium arsenide (InAs) channel region 105, a zinc telluride (ZnTe) gate dielectric layer 110, and a highly doped aluminum antimonide (AlSb) gate layer 115, which is In some embodiments, all may be single crystal.

The channel region 105 is a crystalline semiconductor layer, which extends between the source region 105s and the drain region 105d on opposite sides of the crystalline semiconductor layer. The source region 105s/drain region 105d may be highly doped, resulting in low contact resistance. The source region 105s/drain region 105d may also be formed of a crystalline semiconductor material, and in some embodiments may be formed of the same material as the channel region 105. In some embodiments, the source region 105s/drain region 105d may also be partially formed of metal to achieve lower resistance.

The structure including the channel region 105, the gate dielectric layer 110, and the gate layer 115 defines individually gated channel regions also referred to herein as nanosheets 101, which are repeated to define nanometers 101 also referred to herein. Multiple stacked individually gated channel areas of the rice sheet stack 102. The nanosheet stack 102 is therefore a three-dimensional structure that can be formed on the substrate 107 (eg, as a protruding fin on the surface of the substrate 107) or within the substrate 107 (eg, in a trench defined in the substrate 107), And, for example, any number/number of individually gated channel regions 105 may be included based on the desired application. For example, the number or number of channel regions 105 in the transistor 100 can be determined by the target current carrying capacity of the transistor 100. Each of the channel areas 105 The person may be relatively thin (ie, the thickness is less than about 10 nm), thereby achieving improved static control. The substrate 107 may be, for example, a silicon substrate, a silicon-on-insulator (SOI) substrate, or other substrates.

The use of crystalline semiconductor materials for the gate dielectric layer 110, the gate layer 115, and the channel region 105 realizes a nanocrystal stack 102 that is almost completely crystallized, wherein the crystalline gate dielectric layer 110 is directly on the crystalline channel region 105 . The interface between the channel region 105 and the gate stack 106 may therefore be free of amorphous or non-crystalline layers, thereby reducing SR scattering due to lack of interface surface roughness. The transistor 100 can thereby exhibit extremely high channel mobility. The interface between the channel region 105 and the gate stack 106 may also be free of low dielectric constant crystalline buffer layers (such as indium phosphide (InP)), so that the equivalent oxide thickness can be improved (ie, reduced) (equivalent oxide thickness, EOT) to improve the short channel performance of the transistor 100, because only a relatively thin gate dielectric layer 110 (for example, a thickness of about 2 to 3 nanometers) will connect the gate layer 115 and the channel The area 105 is separated.

And, as shown in the embodiment of FIGS. 1A to 1C, each of the channel regions 105 includes a gate stack 106 above and below it (ie, on the opposite surface of the channel region 105), thereby achieving improvements control. For example, the two-dimensional electron gas (2DEG) in each indium arsenide channel region 105 can be from above (ie, on top of the channel region 105) and below (ie, in the channel (At the bottom of the area 105). In addition, each of the channel region 105, the gate dielectric layer 110, and the gate layer 115 of the nanosheet stack 102 may have respective crystal structures that substantially lattice match the underlying layers. For example, the channel area The domain 105, the gate dielectric layer 110, and/or the gate layer 115 may be lattice-matched heteroepitaxial layers.

The transistor 100 also includes a metal or polycrystalline gate contact layer (also referred to herein as a secondary gate layer or a first gate layer) on the upper surface of the nanosheet stack 102 and on opposite sidewalls (ie, on at least three sides) Second gate electrode) 615. The gate contact layer 615 electrically contacts each of the gate layers 115 in the nanochip stack 102 so that multiple gate layers 115 can be controlled by a single gate contact layer 615, thereby defining multiple gate multi-channel devices.

The physical properties of the nanosheet stack 102 according to some embodiments of the inventive concept may include (but is not limited to): a fully crystalline lattice-matched multi-channel structure including a crystalline semiconductor channel region 105 and a gate dielectric layer 110 And gate layer 115; each channel region 105 is gated at the top and bottom of the gate layer 115 electrically contacted by the common gate contact layer 615; the ZnTe gate dielectric layer 110 has a band gap of about 3 electron volts (Wide band gap semiconductor) and a k value of 7.9 (medium high dielectric constant); AlSb gate layer 115 has a band gap of about 1.5 electron volts (medium band gap semiconductor) and highly doped activation; and/or multiple The number of channel areas 105 depends on the specific application.

The electrical properties of the nanosheet stack 102 according to some embodiments of the inventive concept may include (but is not limited to): improved (ie, thinner) EOT, which is attributed to the channel region 105 and the gate layer 115 No InP or other buffer layers are present or omitted; the 2DEG in each InAs channel region 105 can be controlled from above and below by each gate layer 115; reduced SR scattering is due to the channel region No interface/absence of surface roughness/amorphism at interface between 105 and gate dielectric layer 110 Layer (in which only a small amount of amorphous insulating layer 420r is present at the sidewall of the channel region 105 to insulate from the gate contact layer 615); low parasitic resistance and/or low contact resistance due to highly doped InAs Source region 105s/drain region 105d; and high channel mobility without the use of a buffer layer (this is due to the absence of an amorphous layer at the interface between channel region 105 and gate dielectric layer 110) . Therefore, embodiments of the inventive concept may reduce and/or eliminate the mobility/EOT trade-off.

Although described with reference to the example structures in FIGS. 1A to 1C, it should be understood that the embodiments of the present inventive concept are not limited thereto. For example, in some embodiments, in a finFET structure, the nanosheet stack 102 may define a three-dimensional fin-shaped active region protruding from the substrate, where the gate contact layer 615 is located on the upper surface and sidewalls of the nanosheet stack 102 . In other embodiments, the nanochip stack 102 may be similarly formed in the trench structure in the substrate, wherein the gate contact layer 615 extends at least along the sidewall of the trench between the substrate and the nanochip stack 102. The gate contact layer 615 may also extend on the top surface of the nanochip stack in a gate-all-around (GAA) FET structure. More generally, although described herein with reference to specific structures, embodiments of the inventive concepts may include any structure or substructure that implements the substantially crystalline channel/dielectric/gate stack described herein .

2 to 12 are cross-sectional views illustrating a method of manufacturing a FET element according to some embodiments of the inventive concept, where FIGS. 2 to 6 are cross-sectional views taken along line B-B' of FIG. 1. Referring now to FIG. 2, when forming a multi-channel III-V group FET according to some embodiments of the inventive concept, a substantially or fully crystalline nanosheet stack 102' is formed. Each nanosheet 101' in the stack 102' includes a gate layer 115' and a gate dielectric The electrical layer 110' (both define the gate stack 106') and the channel region 105'. One or more of the channel region 105', the gate dielectric layer 110', and the gate layer 115' in the stack 102' may be epitaxially grown crystalline semiconductor layers (including, for example, Group II-VI and/or III- Group V materials), so that the crystalline directions of the channel region 105', the gate dielectric layer 110', and/or the gate layer 115' are ordered or matched to the underlying layers. In the embodiments of FIGS. 2-12, each of the channel regions 105' includes a gate layer 115' on its opposite side, and is connected to the gate layer 115' by each gate dielectric layer 110' Separated so that the channel area 105' is individually gated from above and below.

Some or all of the channel region 105', the gate dielectric layer 110', and the gate layer 115' are formed using a semiconductor material having a substantially lattice-matched crystal structure. In the example manufacturing method shown in FIGS. 2 to 12, the gate layer 115′ is formed using heavily doped (n+) AlSb, and the gate dielectric layer 110′ uses intrinsic ZnTe (or Other wide bandgap II-VI semiconductors), and the channel region 105' is formed using intrinsic (or lightly doped) InAs. The channel region 105' may be relatively thin (e.g., a thickness of about 2 nm to about 10 nm) to achieve good electrostatic control, thereby forming a plurality of quantum wells. Multiple nanosheets 101' can be formed (e.g., by alternating heteroepitaxial growth of channel region 105', gate dielectric layer 110', and gate layer 115') to define the number of inclusions as required The stacking of the channel regions 105', for example, to meet current and/or layout area constraints.

The use of substantially or fully crystallized nanosheet stacks 102' according to embodiments of the inventive concept can greatly reduce SR scattering, even when no buffer layer is used. In addition, the absence or omission of the buffer layer can improve short-channel performance, Thereby providing components suitable for sub-10 nm integration. FET devices according to embodiments of the inventive concept can therefore have high mobility, good short channel behavior, and excellent parasitics in addition to the low-density state in the channel and the corresponding low capacitance found in other III-V devices resistance.

Therefore, an element according to an embodiment of the present invention can be measured in CV/I (CV/I metric) is excellent or provides improved CV/I measurement. The low charge sheet density of the inversion layer in the channel region 105' may also allow the use of heavily doped polycrystalline gate contacts (rather than metal gate contacts) to surround on multiple sides of the fully crystallized stack 102' A fully crystalline stack 102', which simplifies the process (discussed below with reference to FIG. 6), because the associated low charge density in the heavily doped gate contact can result in an extremely thin depletion layer (and therefore Can not significantly reduce the static performance).

To form a contact with the three-dimensional nanosheet stack 102', the channel region 105' should be insulated without contact with any gate or metal layer. Therefore, as shown in FIG. 3, selective isotropic etching of the channel region 105' is performed. The etchant may be selected to remove portions of the channel region 105' at the sidewalls of the nanosheet stack 102' without substantially removing or damaging the gate layer 115' and/or the gate dielectric layer 110'. For example, in order to selectively etch the InAs channel region 105' of FIG. 3, acetic acid and hydrogen peroxide may be used as etchant. However, depending on the particular material, other etching chemicals can be used to selectively etch the channel region 105' without substantially etching the gate layer 115' and/or the gate dielectric layer 110'. Therefore, the sidewall of the channel region 105' is selectively recessed with respect to the sidewall of the nanosheet stack 102', thereby defining the recessed region 105r'.

Referring now to FIG. 4, deposited or shaped on the sidewalls and upper surface of the nanosheet stack An insulating layer 420' is formed. The insulating layer 420' may be an oxide or other amorphous layer, and may be formed on the stack 102' to substantially fill the recessed region 105r' at the sidewall of the channel region 105'.

As shown in FIG. 5, an etching process is performed to remove the insulating layer 420' from the upper surface and sidewalls of the nanosheet stack 102'. For example, in the case where an oxide layer is used as the insulating layer 420', a plasma etching process may be used to remove the oxide layer. However, part of the insulating layer 420' may remain in the recessed region 105r' at the sidewall of the channel region 105'. These remaining portions 420r' of the insulating layer 420' can electrically isolate the channel region 105' from one or more conductive layers formed in subsequent processes.

Referring now to FIG. 6, a gate contact layer 615' is selectively formed on the upper surface of the nanosheet stack 102' and portions of the sidewalls. Herein, the gate contact layer 615' may also be referred to as a secondary gate or a top gate. The gate contact layer 615' can thereby "wrap" the entire nanosheet stack 102', thereby providing electrical contact with each of the gate layers 115' of the stack 102', thereby achieving its overall control. However, the channel region 105' can be electrically isolated from the gate contact layer 615' by the remaining portion 420r' of the insulating layer 420' at its sidewall. Specifically, as shown in FIG. 6, the gate contact layer 615 ′ may contact the AlSb gate layer 115 ′ at the side wall of the AlSb gate layer 115 ′, but may communicate with the InAs channel through the remaining portion of the insulating layer 420 r ′ The area 105' is separated and electrically isolated.

The gate contact layer 615' may include metal or semiconductor materials. For example, in some embodiments, polycrystalline semiconductor material may be used as the gate contact layer 615'. The polycrystalline gate contact layer 615' may be heavily doped, and the relatively low charge density in the heavily doped gate contact layer 615' may result in a relatively thin depletion layer (and therefore may not be significant Reduce the electrostatic performance of the component). The absence of metal in the gate contact layer 615' can also simplify the manufacturing process. However, in other embodiments, metallic materials can be used as the gate contact layer 615' to achieve improved control and/or performance. For example, in some embodiments, the polycrystalline gate contact layer 615' may be replaced with metal at the end of or after the processing operation as described herein.

7 to 12 are cross-sectional views further illustrating a method of manufacturing a FET element according to some embodiments of the inventive concept, which is taken along line C-C' of FIG. 1A. In the embodiment where the gate contact layer 615' of FIG. 6 includes a polycrystalline semiconductor material, the operations of FIGS. 7 to 12 may be performed after the formation of the gate contact layer 615' of FIG.

As shown in the cross-section in FIG. 7, the side wall of the channel region 105' is kept electrically insulated by the remaining portion 420r' of the insulating layer in its recessed region 105r'. Therefore, in order to achieve contact between the channel region 105' and the source/drain regions, an etching process is performed to remove a portion of the nanosheet stack 102' at the source/drain regions to be formed in subsequent operations. In particular, as shown in FIG. 8, the nanosheet stack 102' is patterned (eg, using a mask) and etched to remove the nanosheet stack 102' at opposite sides of the channel region 105' Part 103'.

Referring now to Fig. 9, selective etching of the gate layer 115' is performed. The etchant is selected to selectively remove portions of the gate layer 115' without substantially removing or damaging the gate dielectric layer 110' and/or the channel region 105'. For example, for the AlSb gate layer 115' shown in FIG. 9, hydrogen fluoride, hydrogen peroxide, and lactic acid and/or AZ400K can be used as an etchant. However, depending on the particular material, other etching chemicals may be used to selectively etch the gate layer 115' without substantially etching the gate dielectric layer 110' and/or the channel region Domain 105’. Therefore, the sidewall of the gate layer 115' is selectively recessed with respect to the sidewall of the nanosheet stack 102' to define a recessed region 115r'.

As shown in FIG. 10, an insulating layer 1020' is deposited or formed on the sidewalls and upper surface of the nanosheet stack 102'. The insulating layer 1020' may be an oxide or other amorphous layer, and may be formed on the recessed region 115r' at the sidewall of the gate layer 115' and/or substantially fill the recessed region 115r at the sidewall of the gate layer 115' '.

Referring now to FIG. 11, an etching process is performed to remove the insulating layer 1020' from the upper surface and sidewalls of the nanosheet stack 102'. For example, in the case where an oxide layer is used as the insulating layer 1020', a plasma etching process may be used to remove the oxide layer. However, the remaining portion 1020r' of the insulating layer 1020' may remain in the recessed region 115r' at the sidewall of the gate layer 115'. These remaining portions 1020r' of the insulating layer can electrically isolate the gate layer 115' from the source/drain regions formed in subsequent processes.

Specifically, as shown in FIG. 12, InAs source regions 105s'/drain regions 105d' are formed at opposite sides of the InAs channel region 105' in the nanosheet stack 102' to complete the field effect transistor 100' . The source region 105s'/drain region 105d' can be formed by an epitaxial regrowth process. In particular, in the example of FIG. 12, in-situ doped n+InAs regions are on opposite sides of the channel region 105' (ie, the nano-patterns that are patterned and etched in FIG. 8 At the portion 103' of the sheet stack) epitaxial growth. Therefore, the source region 105s'/drain region 105d' may contact the channel region 105' at the sidewall of the channel region 105'. However, the remaining portion of the insulating layer 1020r' in the recessed region 115r' at the sidewall of the gate layer 115' electrically isolates the source region 105s'/drain region 105d' from the gate layer 115'. In particular, FIG. 12 illustrates the InAs source region 105s’ and The pole region 105d' can contact the InAs channel region 105', but can be separated and electrically isolated from the AlSb gate 115' by the remaining portion of the insulating layer 1020r'.

Although embodiments of the inventive concept have been described herein with reference to the channel region, gate dielectric layer, and specific materials of the gate layer, it should be understood that other materials may be used. In particular, the InAs channel region 105'/ZnTe dielectric layer 110'/AlSb gate layer 115' nanochip stack 102' described herein can be selected to pass through the channel region 105', gate dielectric layer 110 A reduced or minimal lattice mismatch is provided between'and gate layer 115'. However, in some embodiments, a small amount of mismatch (eg, on the order of 1%) may be used, thereby causing strain in the channel region 105', the gate dielectric layer 110', and/or the gate layer 115' As long as the layer is thin enough (or the strain is small enough) to reduce or prevent slack (and the subsequent introduction of defects). For example, gallium antimonide (GaSb) can be used for the gate layer 115' and indium antimonide (InSb) for the channel region 105', which can result in higher or increased mobility. Also, InAs can be used to create ohmic contacts at the source region 105s and the drain region 105d, which can result in lower or reduced parasitic resistance.

Embodiments of the inventive concept can provide several advantages. In particular, the devices described herein can provide a high mobility channel because the absence of an amorphous layer at the interface between the channel region 105 and the gate stack 106 greatly reduces and/or eliminates SR scattering. Also, the short channel performance can be compatible with the sub-10 nanometer scale due to the absence of a buffer layer that increases the effective gate oxide thickness.

In addition, the gate contact layer 615 surrounding (or "winding") the stack 102 of nanosheets 101 may be a metal or polycrystalline semiconductor. In some embodiments, given the expected low charge sheet density (charge sheet density), multiple The gate contact layer 615 has very little static electricity, and the absence of metal in the gate contact layer 615 can simplify the manufacturing process. However, in other embodiments, metal can be used as the gate contact layer 615 to provide improved control and/or performance.

Some embodiments of the inventive concept may thus provide high-performance multi-channel III-V group FinFETs, where each channel is individually gated. The crystalline buffer layer may not be used, thereby achieving high mobility and good (ie, thinner) EOT. FinFETs as described herein can also be manufactured using some existing processing operations. The features of specific example embodiments of the inventive concept are as follows:

(1) An FET comprising a substantially or completely crystalline stack of a plurality of lattice-matched layers, the plurality of lattice-matched layers forming individually gated conduction channels.

(2) The FET as described in (1), wherein a subset of the plurality of lattice-matched layers forms a crystalline conduction channel, and a subset of the plurality of lattice-matched layers forms a crystalline gate dielectric And a subset of the plurality of lattice-matched layers form a crystalline first gate electrode, each crystalline conduction channel in the substantially or completely crystalline stack is partially or completely mediated by a crystalline gate The first gate electrode of the crystal and crystal is surrounded.

(3) The FET as described in (1), wherein the lattice-matched layer contains a group III-V or group II-VI material.

(4) The FET as described in (2), wherein the conduction channel is formed of InAs, the gate dielectric is formed of ZnTe, and the first gate electrode includes AlSb.

(5) The FET as described in (4), further including a finFET formed with the substantially or completely crystallized stacking periphery wound around a plurality of lattice-matched layers Surrounding second gate electrode, the second gate electrode selectively contacts the first gate electrode, the second gate electrode and the first gate electrode form a wraparound gate structure, the wraparound gate electrode The structure surrounds the individually gated conduction channels.

(6) The FET described in (5), the second gate electrode includes a metal or a polycrystalline semiconductor.

(7) The FET described in (6), the finFET forms a source/drain electrode that only selectively contacts the conduction channel.

(8) The FET as described in (7), the source/drain electrode contains InAs.

(9) The FET as described in (8), including high-mobility conduction channels, the high mobility is due to the reduction or substantial elimination of surface roughness scattering in the areas above and below each conduction channel.

(10) A method of forming a finFET as described in (8), the method comprising forming a substantially or completely crystalline stack of a plurality of lattice-matched layers, forming a layer wound around the plurality of lattice-matched layers A second gate electrode around the crystalline stack of the second gate electrode, the second gate electrode selectively contacts the first gate electrode, and forms a source/drain electrode that selectively contacts the conductive channel.

Therefore, field effect transistors according to some embodiments of the inventive concept can achieve both high channel mobility (eg, this is due to the fact that there is substantially no amorphous or non-crystalline layer in the channel area) and improved short channel performance (For example, this is due to the absence of a crystalline buffer layer between the channel region and the gate stack, which may increase the effective gate oxide thickness). Therefore, embodiments of the inventive concept may reduce and/or eliminate the mobility/EOT trade-off.

Other embodiments of the inventive concept stem from the recognition that crystalline materials on and/or around the channel region can be used to suppress SR scattering, and combined with a strained layer in the Group IV MOSFET to provide high mobility, which may exceed some Mobility of III-V group elements. Embodiments of the inventive concept described in detail below provide a strained nanoplate structure that can be used in field effect transistor applications such as MOSFETs, as well as auxiliary components and host devices for such FETs. These embodiments can also promote strain retention in the channel layer of the nanosheet stack, and also facilitate the manufacture of nanosheets with a width of 30 nanometers or more or more than 40 nanometers, which can be compared to using some conventional etch-and-fill (etch-and-fill) method can actually achieve the width of the nanochip. For example, for III-V systems, the chip width can be limited by high dielectric constant and/or metal filling, and for Si/SiGe systems, the chip width can be selected by etching between the sacrificial material and the channel material To limit further (not high dielectric constant/metal filling or in addition to high dielectric constant/metal filling).

In particular, some embodiments of the inventive concept introduce a Group IV channel FET, where the body layer or channel layer and the gate stack are formed substantially or entirely by a single crystal lattice mismatch solid state material layer. In a specific embodiment, a multi-channel Si/SiGe MOSFET is implemented with a fully crystalline stack of alternating layers of Si, SiGe and a crystalline insulator (eg calcium fluoride, CaF ₂ ). For n-channel MOSFET (also referred to herein as nFET) devices, the channel can be silicon and the gate can be heavily doped silicon germanium. For p-channel MOSFET (also referred to herein as pFET) devices, the channel can be silicon germanium, and the gate can be heavily doped silicon. Due to the lattice mismatch between the crystal structure of each channel and the material of the gate layer, the entire stack structure is strained to increase the channel mobility of nFET and pFET. In addition, the absence of an amorphous dielectric layer or the interface of the amorphous dielectric layer greatly suppresses SR scattering, thereby improving channel mobility. The growth of epitaxial properties and the absence of deep and highly selective lateral (undercut) etching can achieve nanosheet structures with height and/or width that do not contain the limitations normally found in standard nanosheet processes Of manufacturing. Components according to embodiments of the inventive concept can thus provide significant improvements in direct current (DC) and alternating current (AC) properties over some conventional (undercut etched) nanochips and FinFETs.

13 is a perspective view illustrating a FET having a crystalline channel layer, a dielectric layer, and a gate layer according to some embodiments of the inventive concept. 14A and 14B are cross-sectional views taken along lines AA' and BB' of FIG. 13, respectively, illustrating n-type FETs according to other embodiments of the inventive concept, and FIGS. 15A and 15B are Cross-sectional views taken along lines AA' and BB' of FIG. 13, respectively, illustrating p-type FETs according to other embodiments of the inventive concept.

As shown in FIGS. 13-15B, a field effect transistor 1300/1300'/1300" according to some embodiments of the inventive concept includes a semiconductor active having a defined transistor channel layer or channel region 1305/1305'/1305" Layer or body layer and the structure of the semiconductor gate stack 1306 on the channel area 1305/1305'/1305". The gate stack 1306 includes a crystalline gate dielectric layer 1310/1310'/1310" and a crystalline gate layer 1315/ 1315'/1315" (also referred to herein as the main gate layer or the first gate electrode). The crystalline gate dielectric layer 1310/1310'/1310" can be an undoped, high dielectric constant, wide band gap semiconductor Or an insulator, and the crystalline gate layer 1315/1315'/1315" may be a highly doped, medium band gap semiconductor.

Specifically, as shown in the example nFET shown in FIGS. 14A to 14B, the structure may include a silicon channel region 1305′, calcium fluoride (CaF ₂ ), zinc sulfide (ZnS), oxide (Pr ₂ O ₃ ), and/or Or a Gd ₂ O ₃ gate dielectric layer 1310′ and a highly doped silicon germanium (n++SiGe) gate layer 1315′, which in some embodiments may all be single crystal. The channel region 1305' may be under tensile strain (t-Si), and the gate layer 1315' may be under compressive strain (c-SiGe).

And, as in the example pFET shown in FIGS. 15A-15B, the structure may include a silicon germanium channel region 1305″, calcium fluoride (CaF ₂ ), zinc sulfide (ZnS), oxide (Pr ₂ O ₃ ), and/or Gd ₂ O ₃ gate dielectric layer 1310″ and highly doped silicon (p++Si) gate layer 1315″, which in some embodiments may all be single crystal. Channel region 1305″ It may be under compressive strain (c-SiGe), while the gate layer 1315" may be under tensile strain (t-Si).

The channel region 1305 is a crystalline semiconductor layer that extends between the source region 1305s and the drain region 1305d on the opposite side. The source region 1305s/drain region 1305d may be highly doped to provide low contact resistance. The source region 1305s/drain region 1305d (source region 1305s'/drain region 1305d' in FIG. 14B; source region 1305s"/drain region 1305d" in FIG. 15B can also be formed of a crystalline semiconductor material, and In some embodiments, it may be formed of the same material as the channel region 1305 (channel region 1305′ in FIGS. 14A to 14B; channel region 1305″ in FIGS. 15A to 15B). In some embodiments, the source region 1305s/d The source region 1305d (source region 1305s'/drain region 1305d' in FIG. 14B; source region 1305s"/drain region 1305d" in FIG. 15B may also be partially formed by a metal source region The domain 1308s/metal drain region 1308d (metal source region 1308s'/metal drain region 1308d' in FIG. 14B; metal source region 1308s"/metal drain region 1308d" in FIG. 15B are formed to achieve lower resistance.

The structure including the channel region 1305, the gate dielectric layer 1310, and the gate layer 1315 defines individual gated channel regions, also referred to herein as nanosheets 1301, which are repeated to define the document Multiple stacked individually gated channel regions, also known as nanosheet stacks 1302. The nanosheet stack 1302 is therefore a three-dimensional structure that can be formed on the substrate 1307 (for example, as a protruding fin on the surface of the substrate 1307) or within the substrate 1307 (for example, in a trench defined in the substrate 1307), And, for example, any number/number of individually gated channel regions 1305 may be included based on the desired application and/or related stack height to provide the required current density. In addition, the strain in the channel region 1305 can be maintained in the entire stack 1302 regardless of or independent of the stack height, as the source of strain (ie, the lattice mismatch between the channel region 1305 and the lower/upper gate layer 1315) The entire stack 1302 continues. Each of the channel regions 1305 may be relatively thin (that is, less than about 10 nanometers thick), thereby achieving improved static control. The substrate 1307 may be, for example, a silicon substrate, a silicon-on-insulator (SOI) substrate, or other substrates.

Using a crystalline material for the gate dielectric layer 1310, the gate layer 1315, and the channel region 1305 realizes a nearly entirely crystalline nanoplate stack 1302, where the crystalline gate dielectric layer 1310 is directly on the crystalline channel region 1305. The interface between the channel region 1305 and the gate stack 1306 may therefore not contain an amorphous layer or an amorphous layer, thereby reducing SR scattering due to lack of interface surface roughness. Transistor 1300 can be used to show Very high channel mobility.

In some embodiments (for example, an embodiment characterized by a SiGe channel with a high Ge content), the interface between the channel region 1305 and the gate stack 1306 may also not contain a low dielectric constant crystal buffer layer, which can be improved by (Ie, reduce) the equivalent oxide thickness to improve the short channel performance of transistor 1300, because only a relatively thin gate dielectric layer 1310 (eg, a thickness of about 2 to 3 nanometers) The layer 1315 is separated from the channel area 1305.

In addition, the fully crystalline nanosheet stack 1302 (including the crystalline material for the gate dielectric layer 1310, the gate layer 1315, and the channel region 1305) is realized to have a stack width that exceeds what can be achieved by some conventional methods and/or Or the manufacture of highly strained channel areas. In particular, since embodiments of the inventive concept provide a complete crystalline stack by epitaxial growth, the conventional undercut/side etching and filling of strained nanosheet materials can be avoided (the strain between layers can be relaxed), thereby The realization does not depend on the stack height while maintaining strain and the realization of the stack width is not limited by the lateral etching limitation. Therefore, embodiments of the inventive concept can achieve stack widths greater than about 100 nanometers or more and/or stack heights greater than about 100 nanometers or more, which may not be achieved by some conventional methods. For example, a 6-layer stack of 5nm nanosheets (which is surrounded by 7 gate layers each 10nm thick) can provide a stack height of about 100nm, which may not be able to use some conventional etching- And-filling method is achieved.

And, as shown in the embodiment of FIGS. 13 to 15B, each of the channel regions 1305/1305'/1305" includes a gate stack 1306 above and below (ie, on the opposite surface of the channel region) To achieve improved control. For example In other words, the two-dimensional electron gas in each silicon channel region 1305' or silicon germanium channel region 1305" can be from above (ie, on top of the channel region 1305'/1305") and below (ie, in the channel region At the bottom of 1305'/1305"). In addition, each of the channel region 1305, the gate dielectric layer 1310, and the gate layer 1315 of the nanosheet stack 1302 may have a lattice mismatch with the underlying layer For example, the channel region 1305, the gate dielectric layer 1310, and/or the gate layer 1315 may be heteroepitaxial layers with lattice mismatch.

Transistor 1300/1300'/1300" also includes a metal or polycrystalline gate contact layer (also referred to herein as a secondary) on the upper surface and opposite sidewalls of the nanosheet stack 1302 (ie, on at least three sides) Gate layer or second gate electrode) 2015/2015'/2015". For example, the gate contact layer 2015' for nFET 1300' may be SiGe, and the gate contact layer 2015" for pFET 1300" may be Si. The gate contact layer 2015 electrically contacts each of the gate layers 1315 in the nanosheet stack 1302 so that multiple gate layers 1315 can be controlled by a single gate electrode/gate contact layer 2015 to define multiple gates Channel element. A wraparound spacer 1390 may be provided on the opposite side of the gate contact layer 2015/2015'/2015".

The physical properties of the nanosheet stack 1302 according to some embodiments of the inventive concept may include (but is not limited to): a fully crystalline lattice mismatched multi-channel structure, including a crystalline semiconductor channel region 1305, and a gate dielectric layer 1310 And the gate layer 1315; each channel region 1305 is gated at the top and bottom, where the gate layer 1315 is electrically contacted by a common gate contact layer 2015; CaF ₂ , ZnS with a wide band gap with a medium high dielectric constant , Pr ₂ O ₃ and/or Gd ₂ O ₃ gate dielectric layer 1310; a Si/SiGe layer epitaxially grown on the gate dielectric layer 1310; multiple channel regions 1305, the number of which depends on the specific application Depends; the insulation between the channel region 1305 and the gate layer 1315 by a dielectric layer (eg, SiO ₂ ); the dielectric layer between the gate layer 1315 and the source region 1305s/drain region 1305d ( For example, SiO ₂ ) insulation; highly doped single crystal gate layer 1315; lightly doped (or intrinsic) channel region 1305; and stoichiometry for the SiGe layer, which is selected to be in the silicon layer Caused enough strain in the process.

The electrical properties of the nanosheet stack 1302 according to some embodiments of the present inventive concept may include (but is not limited to): the 2DEG in each Si or SiGe channel region 1305' or 1305" may be each gate layer 1315' or 1315" Control from above and below; reduced SR scattering due to the absence/omitting of the surface roughness/amorphous layer (only a small amount of amorphous) at the interface between the channel region 1305 and the gate dielectric layer 1310 Insulation layer 1820r exists at the side wall of the channel region 1305 to insulate from the gate contact layer 2015); high tensile strain in the Si channel (or high compressive strain in the SiGe channel), which is attributed to the height along the entire stack Maintain reduced or minimal relaxation of strain sources; high channel mobility, no buffer layer used (because there is no amorphous layer at the interface between channel region 1305 and gate dielectric layer 1310); due to gate depletion Moderate reversal charge/low capacitance; and low parasitic resistance (Rpara) due to large contact area.

In some embodiments, the strength of the strain in the channel layer may depend on the relative thickness (rather than the absolute thickness) of the channel layer, the dielectric layer and the gate layer and the difference in lattice constant of the channel and gate stack . For what is described in this article For some materials, a thickness ratio of 1 can result in a stress of about 1.5 GPa in the channel. For a ratio of approximately 2 in some embodiments described herein, the stress is possible in the range of 2.5 Gpa to 3 Gpa; the layer can therefore be kept thin (for example, the critical thickness is less than 20 nm) to reduce or prevent sagging.

Although described with reference to the example structures in FIGS. 13 to 15B, it should be understood that the embodiments of the present inventive concept are not limited thereto. For example, in some embodiments, the nanosheet stack 1302 may define a three-dimensional fin-shaped active region protruding from the substrate in the finFET structure, where the gate contact layer 2015 is located on the upper surface and sidewalls of the nanosheet stack 1302. In other embodiments, the nanosheet stack 1302 may be similarly formed in the trench structure in the substrate, wherein the gate contact layer 2015 extends between the substrate and the nanosheet stack 1302 at least along the sidewall of the trench. The gate contact layer 2015 may also extend on the top surface of the nanosheet stack in a gate-all-around (GAA) FET structure. More generally, although described herein with reference to specific structures, embodiments of the inventive concept may include any structure or sub-structure that implements substantially crystalline strained channel/dielectric/gate stacks described herein structure.

16 to 20 are cross-sectional views illustrating a method of manufacturing an nFET element as shown in FIGS. 14A to 14B according to some embodiments of the inventive concept, where FIGS. 16 to 20 are along the line A- of FIG. 13 A'interception. However, it should be understood that the method of FIGS. 16 to 20 can be similarly applied to manufacturing the pFET device as shown in FIGS. 15A to 15B (by using the materials presented therein). That is, although reference is made to the manufacturing of nFETs, it should be understood that the illustrated manufacturing steps can be similarly applied to the manufacturing of pFETs by replacing the corresponding material layers.

Referring now to FIG. 16, when forming a multi-channel Si/SiGe MOSFET according to some embodiments of the inventive concept, a substantially or fully crystalline nanosheet stack 1302 is formed. Each nanoplate 1301 in the stack 1302 includes a crystalline gate layer 1315' and a crystalline gate dielectric layer 1310' (both define the gate stack 1306) and a crystalline channel region 1305'. All the channel regions 1305', the gate dielectric layer 1310', and the gate layer 1315' are formed using a crystalline semiconductor or an insulator. One or more of the channel region 1305', the gate dielectric layer 1310', and the gate layer 1315' in the stack 1302 may be epitaxially grown so that the channel region 1305', the gate dielectric layer 1310' and/or Or the crystal direction of each gate layer 1315' is ordered or matched with the layer below. In the embodiments of FIGS. 16 to 26, each of the channel regions 1305' includes a gate layer 1315' on its opposite side and is separated from the gate layer 1315' by respective dielectric layers 1310', In this way, the channel area 1305' is individually gated from above and below.

Some or all of the channel region 1305', the gate dielectric layer 1310', and the gate layer 1315' are formed using a semiconductor material having a crystal structure with lattice mismatch. In the embodiments of FIGS. 16 to 26, the gate layer 1315′ is formed using heavily doped (n++) SiGe, and the crystalline dielectric layer 1310′ is formed using CaF ₂ , ZnS, Pr ₂ O ₃ or Gd ₂ One of O ₃ is formed, and the channel region 1305 ′ is formed using intrinsic (or lightly doped) Si. In addition, for the pFET, the gate layer 1315′ is formed using heavily doped Si, and the crystalline dielectric layer 1310′ is formed using one of CaF ₂ , ZnS, Pr ₂ O _3, or Gd ₂ O ₃ , And the channel region 1305' is formed using intrinsic (or lightly doped) SiGe. The channel region 1305' is thin (on the order of a few nanometers in one embodiment) to achieve good electrostatic control, thereby forming multiple quantum wells. Multiple nanochips 1301 can be used to obtain the required current/layout area.

The use of a substantially or fully crystalline nanoplate stack 1302 according to an embodiment of the present inventive concept can greatly reduce or eliminate SR scattering, which is attributed to the absence of non-existence at the interface between the channel region 1305 and the gate stack 1306 Crystal layer/non-crystalline layer. In addition, the lattice mismatch between the Si layer and the SiGe layer produces strain throughout the stack. The SiGe layer is subjected to compressive strain, while the Si layer has tensile strain. When the stack is a fully crystalline stack, even in higher stacks (ie, not subject to stack height), strain can be maintained due to strain sources (lattice mismatch) maintained along the height of the entire stack . This is different from bottom-strained finFETs (on a stress-relaxed buffer (SRB) or silicon (or other) (xOI) on an insulating layer, where the strain can be directed towards the fin's The top is slack. Indeed, some standard nanosheets (etched by undercutting a nanosheet material relative to other nanosheet materials and then formed by backfilling the undercut regions with appropriate materials) may be unstrained because In the relaxation stress treatment, each channel sheet may have two free surfaces. Therefore, according to an embodiment of the inventive concept, the combination of SR suppression and strain in the channel layer can result in extremely high mobility, exceeding the mobility of unbuffered III-V Group InGaAs devices.

The use of heavily doped semiconductors instead of metal gates can result in loss of inversion density ("poly" depletion). However, for overall higher current density, extremely high channel mobility compensates for the loss in charge density. Therefore, devices according to embodiments of the inventive concept can provide improved current density and reduced capacitance, thereby optimizing CV/I measurement. The number of nanochips can be Modified for use, it has a larger number of back end of line (BEOL) loading parts of the circuit, and gate-loaded (gate-loaded), small-fan-out ( small-fanout) applied to a smaller number of slices.

The method of fabricating components as described herein may point out some challenges related to forming contacts on the 3-D nanosheet stack, for example, the source region 1305s'/drain region 1305d' should electrically contact the channel region 1305', but The gate layer 1315' is not contacted (as shown in FIG. 14B), and the wrap around or secondary gate contact layer 2015' should be in electrical contact with the gate layer 1315', but not the channel region 1305' (as shown in FIG. 14A Show). In particular, as shown in FIG. 17, in order to form a contact with the three-dimensional nanosheet stack 1302 to insulate the channel region 1305' from any gate or metal layer contact, the channel region 1305' is selected, etc. Directional etching. Depending on the particular material, the etchant is selected to remove the portion of the channel region 1305' at the sidewall of the nanosheet stack 1302 without substantially removing or damaging the gate layer 1315' and/or the gate dielectric layer 1310 '. For example, some conventional etching chemicals for Si/SiGe selective etching may be used, and extremely high selectivity may not be required to provide shallow etching. Therefore, the sidewall of the channel region 1305' is selectively recessed relative to the sidewall of the nanosheet stack 1302, thereby defining the recessed region 1305r'.

Referring now to FIG. 18, an insulating layer 1820' is deposited or formed on the sidewalls and upper surface of the nanosheet stack. The insulating layer 1820' may be an oxide or other amorphous layer, and may be formed on the stack 1302 to substantially fill the recessed region 1305r' at the sidewall of the channel region 1305'. For example, in some embodiments, the insulating layer 1820' may be a low dielectric constant dielectric layer, such as silicon dioxide (SiO ₂ ).

As shown in FIG. 19, an etching process is performed to remove the insulating layer 1820' from the upper surface and sidewalls of the nanosheet stack 1302. For example, when an oxide layer is used as the insulating layer 1820', a plasma etching process can be used to remove the oxide layer. However, a portion of the insulating layer 1820' may remain in the recessed region 1305r' at the sidewall of the channel region 1305'. These remaining portions 1820r of the insulating layer 1820' can electrically isolate the channel region 1305' from one or more conductive layers formed in subsequent processes.

Referring now to FIG. 20, a gate contact layer 2015' is selectively formed on the upper surface of the nanosheet stack 1302 and a portion of the sidewall. Herein, the gate contact layer 2015' may also be referred to as a secondary gate or a top gate. The gate contact layer 2015' can thereby "wrap" around the entire nanosheet stack 1302, thereby providing electrical contact with each of the gate layers 1315' of the stack 1302, thereby achieving its overall control. However, the channel region 1305' can be electrically isolated from the gate contact layer 2015' by the remaining portion 1820r of the insulating layer 1820 at its sidewall. In particular, as shown in FIG. 20, the gate contact layer 2015' may contact the SiGe gate layer 1315' at the sidewall of the SiGe gate layer 1315', but may be connected to the Si channel region by the remaining portion of the insulating layer 1820r 1305' is separated and electrically isolated.

The gate contact layer 2015' may include metal or semiconductor materials. In some embodiments, polycrystalline semiconductor material may be used as the gate contact layer 2015'. The polycrystalline gate contact layer 2015' may be heavily doped, and the relatively low charge density in the heavily doped gate contact layer 2015' may result in a relatively thin depletion layer (and therefore may not significantly reduce the device Electrostatic performance). For example, the gate contact layer 2015' for nFET may be SiGe, and the gate contact layer 2015" for pFET may be Si. The absence of metal in the gate contact layer 2015' may also simplify the process. However , In other embodiments, the metal Materials can be used as the gate contact layer 2015' to improve control and/or performance. For example, in some embodiments, the polycrystalline gate contact layer 2015' may be replaced with metal at the end of or after the processing operation as described herein.

21 to 26 are cross-sectional views further illustrating a method of manufacturing an nFET element according to some embodiments of the inventive concept, which is taken along the line B-B' of FIG. 13. In the embodiment in which the gate contact layer 2015' of FIG. 20 includes a polycrystalline semiconductor material, the operations of FIGS. 21 to 26 may be performed after the formation of the gate contact layer 2015' in FIG. 20.

As shown in the cross-section of FIG. 21, the side wall of the channel region 1305' is kept electrically insulated by the remaining portion of the insulating layer 1820r in its recessed region 1305r'. Therefore, in order to achieve the contact between the channel region 1305' and the source/drain regions, an etching process is performed to remove the portion where the nanosheet stack 1302 at the source/drain regions is formed in the subsequent operation. In particular, as shown in FIG. 22, the nanosheet stack 1302 is patterned (e.g., using a mask) and etched to remove the portion 1303' of the nanosheet stack at opposite sides of the channel region 1305'.

Referring now to Fig. 23, selective isotropic etching of the gate layer 1315' is performed. Depending on the particular material, the etchant is selected to selectively remove portions of the gate layer 1315' without substantially removing or damaging the gate dielectric layer 1310' and/or the channel region 1305'. Therefore, the sidewall of the gate layer 1315' is selectively recessed relative to the sidewall of the nanosheet stack 1302 to define a recessed region 1315r'.

As shown in FIG. 24, an insulating layer 2420 is deposited or formed on the sidewalls and upper surface of the nanosheet stack 1302. The insulating layer 2420 may be an oxide or other amorphous layer, and may be formed on the recessed region 1315r' at the sidewall of the gate layer 1315' and/or substantially fill the recessed region 1315r' at the sidewall of the gate layer 1315' . For example, in some embodiments, the insulating layer 2420 may be a low dielectric constant dielectric layer, such as silicon dioxide (SiO ₂ ).

Referring now to FIG. 25, an etching process is performed to remove the insulating layer 2420 from the upper surface and sidewalls of the nanosheet stack 1302. For example, in the case where an oxide layer is used as the insulating layer 2420, a plasma etching process may be used to remove the oxide layer. However, a portion 2420r of the insulating layer 2420 may remain in the recessed area 1315r' at the sidewall of the gate layer 1315'. These remaining portions 2420r of the insulating layer can electrically isolate the gate layer 1315' from the source/drain regions formed in subsequent processes.

Specifically, as shown in FIG. 26, n++ Si source regions 1305s'/drain regions 1305d' are formed at opposite sides of the Si channel region 1305' in the nanosheet stack 1302' to complete the nFET 1300'. The source region 1305s'/drain region 1305d' can be formed by an epitaxial regrowth process. For example, in the nFET 1300' of FIG. 26, the in-situ doped n+Si source region 1305s'/drain region 1305d' are on opposite sides of the Si channel region 1305' (that is, The patterned and etched portion of the nanosheet stack 1303') is epitaxially grown. Likewise, in pFET1300" shown in FIG. 15B, the in-situ doped p++SiGe source region 1305s"/drain region 1305d" can be epitaxially grown on the opposite side of the SiGe channel region 1305". Therefore, the source region 1305s'/drain region 1305d' may contact the channel region 1305' at the sidewall of the channel region 1305'. However, the remaining portion of the insulating layer 2420r in the recessed region 1315r' at the side wall of the gate layer 1315' connects the source region 1305s'/drain region 1305d' with The gate layer 1315' is electrically isolated. Specifically, FIG. 26 illustrates that the Si source region 1305s' and the drain region 1305d' can contact the Si channel region 1305', but can be separated from and electrically isolated from the SiGe gate layer 1315' by the remaining portion of the insulating layer 2420r.

The configuration of the source of strain (interface of the material) between the gate layer 1315' and the channel region 1305' across or throughout the height of the entire stack 1302 can reduce or prevent strain loss due to the source shown in Figure 22 Pole/drain pole depression. Therefore, a relatively deep source/drain recess can be made, and most or the entire vertical sidewalls of the remaining source/drain epitaxial layer can be silicidated to define the metal as shown in FIGS. 13, 14B, and 15B Source regions 1308s, 1308s', 1308s"/metal drain regions 1308d, 1308d', 1308d". This can provide a relatively large contact area, thereby reducing the overall parasitic resistance.

Although embodiments of the inventive concept have been described herein with reference to the channel layer, gate dielectric layer, and specific materials of the gate layer in the context of n-type finFETs, it should be understood that other materials may be used. In particular, as indicated above, the p-type finFET 1300" (as shown in the examples shown in FIGS. 15A to 15B) can be formed by substantially similar manufacturing techniques as illustrated in FIGS. 16 to 26, except that it is made of SiGe A channel layer or channel region 1305" is formed, a gate layer 1315" is formed from Si, and a source region 1305s"/drain region 1305d" is formed from SiGe.

In the n-type FET1300' and p-type FET1300" described herein, a lattice mismatch between the channel region 1305'/1305" and the gate layer 1315'/1315" is used to create strain (compression in the SiGe layer Strain; tensile strain in the Si layer).

Embodiments of the inventive concept can provide several advantages. For example, the device described herein can provide a high mobility channel because (by the channel region The absence of an amorphous layer at the interface between the domain 1305 and the gate stack 1306) can greatly reduce and/or eliminate SR scattering, and because of the high strain maintained in the channel region 1305. Also, the width of the nanosheet according to an embodiment of the inventive concept may not be limited by the undercut etching selectivity of the nanosheet material or the metal filling of the undercut region, unlike some The material undercuts a conventional nanosheet formed by etching a nanosheet material and then metal backfilling the undercut region. In addition, when the embodiments of the inventive concept achieve precise control of the thin channel layer, the elements described herein can be adjusted to short Lg (gate length) technology.

Embodiments of the inventive concept therefore provide a method of manufacturing fully crystallized crystalline nano-strain Group IV MOSFETs. Some operations described herein may include (but are not limited to) conventional techniques. For example, the substrate may include any semiconductor material containing (but not limited to) semiconductors such as GaAs and InAs, or such as Si, bulk silicon, monocrystalline silicon, polycrystalline silicon, SiGe, amorphous silicon, silicon on insulator , SiGe-on-insulator (SGOI), strained-silicon-on-insulator, annealed poly-Si, and/or other Si-containing materials. In other embodiments, for example, the gate dielectric layer may use conventional techniques (eg, chemical vapor deposition, atomic layer deposition, pulsed chemical vapor deposition, plasma-assisted chemical vapor deposition, sputtering, electron beam deposition) (e-beam deposition) and/or solution-based deposition), and/or may be formed using a thermal growth process (thermal growth process), the thermal growth process may include oxidation, oxynitridation, nitridation And/or plasma treatment.

In other embodiments, the gate structure can be manufactured using some conventional processes Manufacturing, for example, a conventional deposition process (such as chemical vapor deposition, plasma-assisted chemical vapor deposition, or sputtering) can be used to form a hard mask on top of the layer of semiconductor material, and/or traditional thermal oxidation can be used The process and the subsequent nitriding process will grow the hard mask on the semiconductor body. Traditional lithography and etching can be used for patterning. In particular, the lithography process may include applying a photoresist, exposing the photoresist to the irradiated pattern, and developing the pattern to the photoresist using a conventional resist developer. After the photoresist is patterned, the exposed portion (eg, the portion that is not protected by the patterned photoresist) can be removed using an etching process that is highly selective in removing the light-exposed portion. Suitable types of etching that can be applied to form the patterned layer include, but are not limited to, reactive-ion etching (RIE), plasma etching (eg ion cutting), and/or laser ablation. After this etching step, the photoresist can be removed from the structure.

In other embodiments, conventional implantation processes can be performed to form source/drain implant regions in the structure in regions adjacent to the channel region in, for example, the fin. The implant can be n-type or p-type. In one example, the exposed regions adjacent to the fins can be doped with different implanted species (such as arsenic and/or boron) to form source/drain regions with donor impurities or acceptor impurities, respectively.

The features of specific example embodiments of the inventive concept are as follows: In one embodiment, the FET includes a plurality of fully crystallized crystalline Si/SiGe and a stack of insulating layers that form individually gated conduction channels.

In one embodiment, the FET includes a fully crystalline stack of multiple crystalline Si/SiGe and includes an insulating layer that includes multiple fully crystalline and fully crystallized strained crystalline Si/SiGe The stack of marginal layers.

In one embodiment, the FET includes the plurality of subsets of strain layers forming lightly doped crystalline conductive channels, the subset of strain layers forming undoped crystalline gate dielectrics, and forming A subset of the strained layer of the heavily doped crystalline gate electrode, each crystalline conduction channel in the fully crystallized stack is surrounded by a crystalline gate dielectric and a crystalline first gate electrode.

In one embodiment, the nFET includes a conductive channel formed of Si, a crystalline gate dielectric formed of CaF ₂ , ZnS, Pr ₂ O ₃ or Gd ₂ O ₃ , and a first gate electrode formed of SiGe.

In one embodiment, the pFET includes a conductive channel formed of SiGe, a crystalline gate dielectric formed of CaF ₂ , ZnS, Pr ₂ O ₃ or Gd ₂ O ₃ , and a first gate electrode formed of Si.

In one embodiment, the FET includes a nanochip FET formed with a second gate electrode wrapped around the fully crystalline stack of the plurality of layers, the second gate electrode only selectively In contact with the first gate electrode, the second gate electrode and the first gate electrode form a wrap-around gate structure that completely surrounds the individually gated conduction channel.

In one embodiment, the FET includes a second gate electrode formed of metal or polycrystalline semiconductor.

In one embodiment, the FET includes a nanochip FET that forms a source/drain electrode that selectively contacts the conductive channel without contacting the Gate electrode.

In one embodiment, the nFET includes a source/drain electrode formed by one (but not the only) of the following: Si, C, n-type dopant, and metal.

In one embodiment, the pFET includes source/drain electrodes formed by one (but not the only) of the following: SiGe, C, p-type dopant, and metal.

In one embodiment, the nanochip FET includes high mobility conductive channels, the high mobility is due to the substantial elimination of surface rough scattering in the areas above and below each conductive channel.

In one embodiment, a method of forming a nanochip FET includes forming a fully crystalline stack of strained layers, forming a second gate electrode wound around the fully crystalline stack of the plurality of strained layers, the second gate The electrode selectively contacts the first gate electrode without contacting the conduction channel, and includes forming a source/drain electrode that selectively contacts the conduction channel without contacting the first gate electrode.

In one embodiment, the nanochip FET includes a SiGe layer, the Ge% in the SiGe layer is less than 100% to provide a suitable strain or mobility in the channel layer without excessive defects, and substantially less than 50% Non-excessive defects are achieved, and substantially less than or equal to 30% to achieve non-excessive defects, where the Ge% in the gate region of the nFET need not be the same as the Ge% in the channel conduction layer of the pFETs.

In an embodiment, the nanochip FET may include an nFET element having a gate region, wherein the range of Ge% in the gate region realizes a mobility advantage of 30% to 50% depending on the thickness of the layer, And/or including a pFET element, the pFET The device has a high Ge% in the channel conduction layer (for example, 100% (for increased mobility)), but band-to-band-tunneling current and parasitic bipolar effect effect) limits Ge% to about 70% (or higher (for VDD operation below 0.6V).

The terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit example embodiments. As used herein, unless the context clearly indicates otherwise, the singular forms "a" and "said" are intended to include the plural forms as well. It should be further understood that the terms "including" and/or "comprising" when used herein specify the presence of the recited features, wholes, steps, operations, parts and/or components, but do not exclude one or more other features, The existence or addition of wholes, steps, operations, parts, components, and/or groups thereof.

For simplicity of description, spatial relative terms such as "below", "below", "below", "above", "above", and similar terms may be used in this article To describe the relationship of one component or feature relative to another (other) component or feature as illustrated in the figures. It should be understood that in addition to the orientations depicted in the figures, the spatial relative terms are intended to also cover different orientations of elements in use or operation. For example, if the elements in the figures are turned over, the components described as "below" or "beneath" other components or features would then be oriented "above" the other components or features. Therefore, the term "below" can cover both "above" and "below" orientations. Elements can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly. In addition, it should also be understood that when a layer is When referred to as "between" two layers, it may be the only layer between the two layers or there may be one or more intervening layers.

It should be understood that although the terms "first", "second", etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component discussed below may be referred to as the second component without departing from the scope of the inventive concept. In addition, as used herein, unless the context clearly indicates otherwise, the singular forms "a" and "said" are intended to include the plural forms as well. It should also be understood that as used herein, the term "comprising" is inclusive and includes one or more recited components, operations, and/or functions, but does not exclude one or more undescribed components, operations, and/or functions. Features. The term "and/or" includes any and all combinations of one or more of the associated listed items.

It should also be understood that when a component is referred to as being “on” or “connected to” another component, the component can be directly on or connected to the other component, or it can be There are intervening components. In contrast, when a component is referred to as being "directly on" or "directly connected to" another component, there are no intervening components. However, in any case, "on" or "directly on" should not be interpreted as requiring a layer to completely cover the layer below.

Embodiments are described herein with reference to cross-sectional illustrations and/or perspective illustrations, which are schematic illustrations of idealized embodiments (and intermediate structures). Therefore, it should be expected that there will be a change in shape from the description due to, for example, manufacturing techniques and/or tolerances. Therefore, the embodiments should not be interpreted as being limited to the specific shapes of the regions described herein, but should include manufacturing by, for example, The resulting deviation in shape. For example, an implanted area illustrated as a rectangle will generally have round or curved features and/or an implant concentration gradient at the edge of the implanted area, rather than a binary from the implanted area to the non-implanted area (binary) change. Likewise, an embedded area formed by implantation may result in some implantation in the area between the embedded area and the surface through which the implantation is performed. Therefore, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the elements and are not intended to limit the scope of the inventive concept.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those generally understood by those skilled in the art to which the concepts of the present invention belong. It should be further understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the relevant technical background, and should not be interpreted in an idealized or excessively formal sense unless in this context So clearly defined.

Methods and systems for providing strained Group IV nanosheet structures (eg, Si/SiGe nanosheet structures) that can be used in field effect transistor applications (eg, MOSFET) have been described. The method and system have been described according to the illustrated exemplary embodiments, and those of ordinary skill in the art will readily understand that there may be changes to the illustrated embodiments, and any changes are within the methods and systems Within spirit and scope. Therefore, those of ordinary skill in the art can modify the concept of the present invention without departing from the spirit and scope defined by the invention described herein and the accompanying patent application.

1300‧‧‧transistor

1305‧‧‧channel area

1305d‧‧‧Drainage area

1308d‧‧‧Metal Drain Region

1305s‧‧‧Source region

1308s‧‧‧Metal source area

1307‧‧‧ substrate

1310‧‧‧dielectric layer

1315‧‧‧Gate layer

1390‧‧‧Gap

2015‧‧‧Gate contact layer

Claims (19)

A field effect transistor including: a stack of nanosheets including a plurality of individually gated conductive channels, each of the individually gated conductive channels includes a crystalline semiconductor channel layer; a crystalline dielectric layer located on the crystalline semiconductor channel layer Upper; and a crystalline semiconductor gate layer on the crystalline dielectric layer opposite to the crystalline semiconductor channel layer, wherein the nanosheet stack is composed of the crystalline semiconductor channel layer, the crystalline dielectric layer And the lattice mismatch between the two in the crystalline semiconductor gate layer is strained, wherein the crystalline dielectric layer includes calcium fluoride, zinc sulfide, and/or gallium oxide. The field-effect transistor according to item 1 of the patent application range, wherein the crystalline semiconductor channel layer, the crystalline dielectric layer, and the crystalline semiconductor gate layer include a heteroepitaxial layer. The field effect transistor according to item 1 of the patent application range, wherein the field effect transistor is an n-type element, and wherein the crystalline semiconductor channel layer includes silicon. The field effect transistor according to item 1 of the patent application range, wherein the field effect transistor is a p-type element, and wherein the crystalline semiconductor channel layer includes silicon germanium. The field effect transistor according to item 1 of the patent application range, wherein the field effect transistor is an n-type element, and wherein the crystalline semiconductor gate layer includes doped silicon germanium. The field effect transistor according to item 1 of the patent application range, wherein the field effect transistor is a p-type element, and the crystalline semiconductor gate layer includes doped silicon. A field effect transistor, including: a body layer containing a crystalline semiconductor channel region; and A gate stack located on the crystalline semiconductor channel region, the gate stack including a crystalline semiconductor gate layer, a lattice mismatch between the crystalline semiconductor gate layer and the crystalline semiconductor channel region; and a crystalline gate dielectric A layer between the crystalline semiconductor gate layer and the crystalline semiconductor channel region, wherein the crystalline gate dielectric layer includes calcium fluoride, zinc sulfide, and/or gadolinium oxide. The field effect transistor as described in item 7 of the patent application range, wherein the interface between the crystalline semiconductor channel region and the gate stack is free of amorphous material. The field effect transistor according to item 8 of the patent application range, wherein the crystalline gate dielectric layer includes a high dielectric constant crystalline insulating layer directly on the crystalline semiconductor channel region. The field effect transistor according to item 9 of the patent application range, wherein the crystalline semiconductor gate layer is directly on the crystalline gate dielectric layer, and wherein the crystalline semiconductor channel region and the crystalline semiconductor gate The layer includes a heteroepitaxial strained semiconductor layer. The field-effect transistor of claim 10, wherein the crystalline semiconductor channel region and the crystalline semiconductor gate layer include different group IV materials, and wherein the crystalline semiconductor gate layer is relatively to the crystal The semiconductor channel region is heavily doped. The field effect transistor according to item 11 of the patent application range, wherein one of the crystalline semiconductor channel region and the crystalline semiconductor gate layer includes compressive strained silicon germanium, and the crystalline semiconductor channel region and the The other of the crystalline semiconductor gate layer includes tensile strained silicon. The field effect transistor of claim 10, wherein the crystalline semiconductor gate layer includes respective crystalline semiconductor gate layers on opposite surfaces of the crystalline semiconductor channel region, and wherein the crystalline gate The polar dielectric layer includes respective crystalline gate dielectric layers between the respective crystalline semiconductor gate layers and the opposite surfaces of the crystalline semiconductor channel region. The field effect transistor according to item 13 of the patent application scope, wherein the structure including the gate stack and the body layer is repeatedly stacked to define a plurality of individually gated channel regions, and wherein the crystalline semiconductor channel The strain in the region and each of the crystalline semiconductor gate layers is maintained throughout the structure. A field effect transistor as described in item 14 of the patent application range, wherein the structure has a width greater than about 30 nanometers but less than about 100 nanometers. The field effect transistor according to item 14 of the patent application range, wherein each of the crystalline semiconductor gate layers located on opposite surfaces of the crystalline semiconductor channel region includes a main gate layer, and further includes: a secondary gate A polar layer is located on a side wall of the crystalline semiconductor channel region between opposite surfaces of the crystalline semiconductor channel region, wherein the secondary gate layer includes a metal material or a doped polycrystalline material. The field effect transistor according to item 16 of the patent application range, wherein the plurality of individually gated channel regions define a fin protruding from the substrate, and wherein the secondary gate layer is on opposite side walls of the fin And extending on the surface between the opposite side walls. The field effect transistor as described in item 16 of the patent application scope further includes: an amorphous insulating layer that separates the side wall of the crystalline semiconductor channel region from the secondary gate layer, Wherein the secondary gate layer is conductively coupled to the primary gate layer. The field effect transistor as described in item 7 of the patent application scope further includes: a source/drain region located at opposite ends and electrically conductively coupled to the gate stack adjacent to the gate stack A crystalline semiconductor channel region; and an amorphous insulating layer separating the opposite sidewalls of the crystalline semiconductor gate layer from the source/drain regions.

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