JP5513955B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a field effect semiconductor device and a method for manufacturing the same.

  In order to improve the performance of a semiconductor integrated circuit for a logic circuit and a semiconductor integrated circuit for a memory, miniaturization of semiconductor elements has been promoted. However, the miniaturization of MOSFETs as these semiconductor elements has been recognized as a physical limit, that is, a limit of high performance due to an increase in junction and gate leakage current and an increase in characteristic variation between elements.

In order to solve the difficulty in improving the performance of MOSFETs due to such miniaturization, applications of materials other than silicon to channel materials are being studied. In particular, graphene, which is a single layer of graphite, has attracted attention as a next-generation semiconductor element material (see Non-Patent Document 1). Graphene has a six-membered ring structure of carbon that forms a single atomic layer. Due to its two-dimensional crystal structure, the graphene has the band structure shown in FIG. 1, and the energy of conduction electrons has a wavenumber near the Fermi surface. It is linearly proportional, so the velocity of conduction electrons can take only a certain value of Fermi velocity. As a result, the electric charge in the graphene shows very high mobility, and in particular, a very high value of 200,000 cm ² / Vs or more is known for graphene having a suspended structure (see Non-Patent Document 2).

  On the other hand, it is completely transmitted by Klein tunneling at the potential barrier due to the absence of energy band gap and the impossibility of backscattering due to the requirement of conservation of helicity freedom due to pseudo-spin degrees of freedom. (Refer nonpatent literature 3). For this reason, it is impossible to prevent charge conduction in the potential barrier, and there arises a problem that the cut-off characteristics are insufficient when applied to the channel of the MOSFET.

  In order to solve this cutoff characteristic problem, it is necessary to form a band gap in graphene. As a method for that, a method using the quantum mechanical confinement effect by the graphene nanoribbon (GNR) structure and the localized state of the ribbon edge, adsorption of substances such as oxygen, hydrogen, hydroxyl group, etc. to graphene, introduction of defects such as antidots, or A method of generating a band gap near the Dirac point by a technique such as locally destroying the electronic structure of graphene by potential modulation of the buffer layer or the like is known.

Science 306 p666 (2004) Solid State Communications 146 p351 (2008) Nature Physics 2 p620 (2006)

  For example, when a nanoribbon is formed to generate a band gap in graphene, it is currently known that the obtained band gap is about 0.3 eV at most. By applying a gate voltage to the portion where the band gap is generated by this nanoribbon structure, potential modulation is applied, and as a result, the band gap becomes a barrier and the transistor channel is turned off (FIG. 2).

  However, in the graphene nanoribbon, the available potential barrier is low due to the small band gap. For this reason, the thermal excitation leakage current increases. This large leakage current causes an increase in power consumption in a large scale integrated circuit.

  In addition, when the channel of the transistor is in the on state, the charge injection rate from the source end is slower as the effective mass of the charge is larger, but it is known that this effective mass is larger as the band gap is larger. That is, the electrical resistance is increased in the graphene nanoribbon. Therefore, when the band gap is increased in order to obtain a good off state, it is necessary to sacrifice the charge mobility in the on state. Such a trade-off is a problem that similarly occurs when a band gap is formed by a method other than the nanoribbon.

It is an object of the present invention to provide a graphene transistor structure and a method for manufacturing the same that can simultaneously achieve both the reduction of the leakage current in the off state and a high current density in the on state.

  The semiconductor device of the present invention has a substrate, a channel region having graphene formed on the substrate and having a band gap generated thereon, and a band gap formed on both sides of the channel region and smaller than the graphene in the channel region. And a source / drain region having graphene formed, and first and second gate electrodes formed on portions of the source / drain region in contact with the channel, respectively.

  In addition, a semiconductor device of the present invention includes a substrate having a back gate electrode, a channel region having graphene formed on the substrate and having a band gap formed thereon, and formed on both sides of the channel region, compared to the graphene in the channel region. And a source / drain region having graphene in which a small band gap is generated, and a gate electrode formed on any one of the portions in contact with the channel of the source / drain region.

  In addition, a semiconductor device of the present invention includes a substrate, a channel region having graphene formed on the substrate and having a band gap formed thereon, and a band gap formed on both sides of the channel region and smaller than the graphene in the channel region. A source / drain region having a graphene formed thereon and a gate electrode formed on any one of the portions in contact with the channel of the source / drain region, and any one of the channel region and the source / drain region Has a dopant.

  The method for manufacturing a semiconductor device according to the present invention includes a step of forming graphene with a band gap formed on a substrate, a step of forming a gate electrode on the graphene, and a mask material on the gate electrode. And a step of etching graphene into a thin line using a mask material and a gate electrode as a mask.

  The semiconductor device of the present invention can improve both good cut-off characteristics and high-speed operation.

The figure explaining the relationship between the Dirac point and Fermi energy in graphene. The figure explaining the graphene nanoribbon transistor in the prior art, and its operation | movement. The schematic diagram for demonstrating 1st embodiment. The schematic diagram which shows the band structure of 1st embodiment. The schematic diagram which shows the band structure of 2nd embodiment. The schematic diagram for demonstrating 4th embodiment. The schematic diagram which shows the band structure of 4th embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, the same code | symbol shall be attached | subjected to a common structure through embodiment, and the overlapping description is abbreviate | omitted. Each figure is a schematic diagram for promoting explanation and understanding of the invention, and its shape, dimensions, ratio, and the like are different from those of an actual device. However, these are in consideration of the following explanation and known techniques. The design can be changed as appropriate.

(Outline of the present invention)
The present invention employs the following element structure as means for solving the above-described problem of cut-off characteristics and the problem of reduction of on-current density due to band gap generation.

  That is, according to the present invention, a channel portion having a band gap, for example, both sides of a graphene nanoribbon are in contact with a gapless portion, that is, a graphene portion having no band gap or a very small band gap, and at least one of the gapless portions has a polarity. And the charge density is locally controlled by the gate voltage.

  Here, the polarity in graphene is N-type when Fermi energy 1 exists on the higher energy side than the Dirac point 2 of graphene or the upper end of the band gap (5 in FIG. 1), as shown in FIG. Conversely, when the Fermi energy exists on the lower energy side of the graphene Dirac point or the lower end of the band gap (3 in FIG. 1), the polarity is considered to be P-type.

  With the above device structure, by appropriately selecting the polarity of the entire graphene and the polarity of the graphene region controlled by the gate, there is a band gap in the channel portion in the device, and the polarities of the graphene at both ends of the channel portion are mutually Different states can be obtained. In this state, it is necessary to move the P-type region and N-type region relative to each other in order for the charge to pass through the channel, but the conduction of the charge is blocked by the existence of a band gap between these different polarities. The Furthermore, since the potential barrier viewed from Fermi energy can be made larger than the band gap, leakage current due to thermal excitation is suppressed. Further, interband tunneling can be suppressed by controlling the channel length to an appropriate length. Due to these effects, good cut-off characteristics are expected.

  On the other hand, by appropriately selecting the bias applied to the gate, the potential barrier can be lowered and the transistor can be easily turned on. At this time, since the source part in contact with the source end of the channel is a gapless graphene region, charges are injected into the channel part while maintaining a high speed peculiar to graphene, so that transistor operation can be performed with high charge mobility. It becomes. At the same time, it is possible to obtain an effect of reducing the resistance by suppressing the high resistance channel portion to a minimum length, and thus increasing the drive current.

  With the above effects, it is possible to achieve both good cut-off characteristics and high drive current.

  The graphene layer is formed on the surface of the substrate by, for example, heat-treating the silicon carbide substrate. Here, the silicon carbide layer may be formed on a normal substrate such as silicon. Further, for example, a chemical vapor deposition method may be used in which the catalyst layer is removed by forming on the surface of the catalyst layer on the insulating layer. Alternatively, the graphene layer formed on the catalyst may be transferred onto the insulating film layer.

Here, the graphene layer will be described assuming that the substrate 21 is formed on a silicon single crystal substrate having a silicon oxide layer on the surface. For example, as shown in FIG. 3A, source and drain contacts 17 are formed on the graphene layer 12. The contact may be a metal or carbon as long as it is a conductive substance. The contact may be formed after forming a gate or channel structure described later. A gate insulating film 22 is formed above the graphene layer 12. As for the material of the gate insulating film 22 and the formation method thereof, for example, an NO ₂ interface layer and Al ₂ O ₃ can be grown by using an atomic layer deposition method (ALD method) (see Science 317 p638 (2007)). .

(First embodiment)
Here, the first embodiment will be described with reference to FIG. A source side gate 13 and a drain side gate 14 are formed on the graphene layer 12 formed by the above method using a conductor such as metal or polysilicon as shown in FIG. That is, the two gates cross the graphene layer 12 in parallel to divide the source region 15 and the drain region 16. The gate electrode pair may be of any kind as long as it has good conductivity. The gate structure can be formed by a technique such as electron beam lithography. The graphene layer in the region sandwiched between the gate electrodes 13 and 14 is processed to be semiconducting, that is, to have an energy band gap of 0.1 eV or more. The processing method may be performed by the method described in the section of the prior art.

  In the present embodiment, an implementation method will be described using a graphene nanoribbon structure as an example.

  First, as shown in FIG. 3B, the fine line structure is transferred as a part of the mask 18 between the two gate electrodes 13 and 14. Here, as the mask 18, for example, a resist is processed into a desired shape by a technique such as electron beam lithography to form a protective film. In addition to the mask 18, the two gate electrodes 13 and 14 are simultaneously used as a protective film in channel processing. Using the resist 18 and the gate electrodes 13 and 14 as a protective film, the removed region 19 shown in FIG. 3B can be selectively removed by a technique such as oxygen plasma etching. At this time, the shape of the mask 18 may be such that the length of the fine line portion is longer than the interval between the gates 13 and 14 and both ends of the fine line portion are within the regions of both gates. By doing so, a structure in which the source and drain ends of the channel region 20 are aligned with the ends of the two gate electrodes can be easily formed in a self-aligned manner.

  The number of graphene nanoribbons may be one, but if there are a plurality of graphene nanoribbons, an increase in on-current can be expected, so it is desirable to increase as much as possible.

  In addition, the present invention is not limited to the removal of graphene by etching, and the same effect can be obtained even if the insulator is formed by modification with a substance such as oxygen or hydrogen. The source and drain contacts 6 may be under the gate electrode as long as they are not in electrical contact with the gate electrode.

  When a method other than graphene nanoribbons is used as a method for forming a semiconducting graphene channel region, a mask having a shape without a thin line portion is prepared in the mask 18 of FIG. 3B, and both gates 13 and 14 are formed. By using it as a protective film at the same time, only the graphene region 12 between both gates can be exposed. By subjecting the graphene region to chemical modification, antidot defect introduction processing, or the like, the band gap 34 can be selectively formed only in the graphene region. Also in this case, a structure in which the channel end and the gate end are aligned in a self-aligned manner can be easily realized as in the case of forming the graphene nanoribbon. Here, the distance between the source-side gate 13 and the drain-side gate 14 is 2 nm or more, and the upper limit of the distance is preferably as narrow as possible in view of the degree of device integration and the reduction of channel electrical resistance. It is desirable to be. A cross-sectional view of the formed element is shown in FIG.

  In the graphene element structure, when a positive voltage is applied to the drain 16, as shown in FIG. 4A, a Fermi energy shift 35 is generated due to the drain voltage. In this case, when a negative voltage is applied to the source side gate 13 and a positive voltage is applied to the drain side gate 14, Dirac point movements 36 and 37 occur, respectively. As a result, the potential barrier becomes high at the source end of the channel, and therefore it is expected to suppress the thermal excitation leakage current. In addition, the source side has P-type polarity and the drain side has N-type polarity, and the gap between them is separated by a band gap region. By selecting the length of the semiconductor region appropriately, inter-band tunneling is suppressed. Therefore, off-leakage current is suppressed.

  The on state of this element is shown in FIG. That is, by applying a positive voltage to both the source side gate 13 and the drain side gate 14, both the Dirac point movements 36 and 37 are in the negative energy direction, and the band gap of the channel region 20 is lower in energy than the Fermi energy. So that the transistor is turned on. At this time, since the source end of the channel is in direct contact with the gapless graphene region, the charge injection speed from the source end is the speed of the gapless graphene, which is a very high speed. Is realized. Furthermore, the length of the high-resistance semiconducting graphene channel can be suppressed to the minimum necessary, and thus high-speed operation of the device can be obtained.

  In this element, the Dirac point movements 36 and 37 due to the electric field of the gate are in the reverse direction in the case of FIG. A high charge injection rate is achieved as well. In all the above transistor operation examples, even if the drain voltage is inverted, the same effect, that is, off-leakage current suppression and high-speed operation can be achieved by inverting the polarity of the gate voltage.

  In addition, after forming this structure, the silicon oxide film portion below the channel portion made of semiconducting graphene is removed with, for example, hydrofluoric acid, so that a transistor using suspended graphene as a channel can be obtained. A suspended graphene channel structure is not possible with a prior art graphene transistor in which the gate stack is in direct contact with the graphene channel layer. In suspended graphene, it is known that the carrier mobility is about 10 times, and in the transistor structure in the present invention, the carrier mobility of the channel part that most determines the carrier movement is significantly increased, and thus the driving current is significantly increased. Be expected.

(Second embodiment)
In the second embodiment, a structure capable of applying a back gate bias is added to the configuration of the element described in the first embodiment. The back gate is formed on the back side of the substrate, for example. This will be described with reference to FIG. By applying a back gate bias, an energy offset 38 of the Dirac point 32 with respect to the Fermi energy 31 can be given, so that the entire graphene layer can be made N-type or P-type. This energy offset 38 is assumed to be larger than half of the band gap energy 34. As a result, the polarity of the voltage required for the gate operation can be operated only in either positive or negative, whereas the positive polarity is required in the first embodiment. It becomes easy.

  First, the case where the entire graphene layer is N-type due to a positive back bias will be described. As shown in FIG. 5 (a), if no voltage is applied to both gates 13 and 14, the transistor is on and operates at a high charge injection rate. When the drain bias is positive, by applying a negative voltage to the source side gate electrode 13, as shown in FIG. 5 (b), the Dirac point shift 40 is caused by the electric field of the gate, and the first implementation described above. The off state of the transistor can be obtained by the same principle as in the case of the embodiment. When a negative drain bias is applied, an off state can be similarly obtained by applying a negative voltage to the drain side gate 14.

  Next, a case where the entire graphene layer becomes P-type due to a negative voltage back bias will be described. If no voltage is applied to both gates 13 and 14, the transistor is on and operates at a high charge injection rate. When the drain bias is positive, the transistor can be turned off by applying a positive voltage to the drain-side gate electrode 14. When a negative drain bias is applied, an off state can be similarly obtained by applying a positive voltage to the source side gate 13.

  The back bias operation may be applied to each transistor independently, or may be applied to a plurality of transistors collectively.

  Also in the element in the present embodiment, the suspended graphene channel structure described in the first embodiment is possible.

(Third embodiment)
The third embodiment is similar to the second embodiment in that the entire graphene layer is doped P-type or N-type instead of applying a back gate bias to give the energy offset 38. An effect can be obtained. Here, if electrons are doped by attaching a metal such as potassium to the entire graphene layer, the graphene layer becomes N-type. Similarly, if holes are doped by attaching a substance such as oxygen to the entire graphene layer, the graphene layer becomes P-type.

  First, in the case of electron doping, if no voltage is applied to both gates 13 and 14, the transistor is in an on state, and a current flows at a high charge injection rate. When the drain bias is positive, by applying a negative voltage to the source-side gate electrode 13, the transistor can be turned off on the same principle as in the first embodiment. When a negative drain bias is applied, an off state can be similarly obtained by applying a negative voltage to the drain side gate 14.

  Next, in the case of hole doping, the same effect can be obtained by reversing the polarity of the voltage as in the case of electron doping. That is, if no voltage is applied to both gates, the transistor is on, and current flows at a high charge injection rate. When the drain bias is positive, by applying a positive voltage to the drain-side gate electrode 14, the transistor can be turned off on the same principle as in the first embodiment. When a negative drain bias is applied, an off state can be similarly obtained by applying a positive voltage to the source side gate 13.

  The doping can be applied individually to the transistors on the circuit. Moreover, it can be made P-type by applying a negative back gate bias to N-type graphene, and it can be made N-type by applying a positive back-gate voltage to P-type graphene. be able to. Further, doping of only one of the source side region and the drain side region with respect to the channel, or doping with different polarities in both are possible. In any combination of these polarities, transistor operation is performed on the same principle as in the above example, and good cut-off characteristics and high-speed operation are expected at the same time.

  Also in the element in the present embodiment, the suspended graphene channel structure described in the first embodiment is possible.

(Fourth embodiment)
The element structure in the fourth embodiment is obtained by omitting one of the source side gate 13 and the drain side gate 14 in the element structure in the second embodiment. By adopting this structure, the area of the element can be reduced because the number of gates is less than that of the structure in the first to third embodiments, and thus the manufacturing process can be simplified, and There is an effect of increasing the degree of integration of the integrated circuit. An implementation method according to the fourth embodiment will be described with reference to FIG. 6, for example, of a structure in which the drain side gate 14 is omitted in FIG.

  In the same manner as in the first to third embodiments, a gate insulating film is formed on the graphene layer 12 and a gate 39 is formed as shown in FIG. The channel region 20 composed of semiconducting graphene serving as a channel is defined by the following method. That is, the channel portion 20 is exposed so that one end of the channel region 20 is defined by the gate 39 as a mask and the other end is defined by the mask 18. Then, processing is performed so that the channel region becomes semiconductor. Here, the processing in which the channel region becomes semiconductor is the same as the method described in the first embodiment, and one or more graphene nanoribbons may be formed, or by chemical modification. It is also possible to introduce anti-dot defects. FIGS. 6B and 6C illustrate a method of forming a single graphene nanoribbon. In the fourth embodiment, it is sufficient that the length of the channel portion 20 is 2 nm or more, and the upper limit of the length is determined by the degree of integration of elements and the request for reducing the electrical resistance of the channel. Is preferably 200 nm or less. In the obtained graphene device structure, by applying a back gate bias, an energy offset 38 of the Dirac point 32 with respect to the Fermi energy 33 can be given, so that it can be made N-type or P-type over the entire graphene layer become. This energy offset 38 is assumed to be larger than half of the band gap energy 34. A cross-sectional view of the formed element is shown in FIG.

  First, the case where the entire graphene layer is N-type due to a positive back bias will be described. At this time, since the Fermi energy is on the higher energy side than the band gap, the transistor is in an on state, and a current flows at a high charge injection rate. In this case, the drain bias is a positive voltage, and as shown in FIG. 7A, a Fermi energy shift 35 due to the drain voltage occurs. Here, by applying a negative voltage to the gate 39, as shown in FIG. 7B, a Dirac point shift 36 occurs. As a result, the potential barrier becomes high at the source end of the channel, and hence the thermal excitation leakage current is suppressed. In addition, since the channel has a P-type polarity on the source side and an N-type polarity on the drain side and is partitioned by a band gap 34, the length of the semiconducting region is appropriately selected, so that the band-to-band tunneling can be achieved. Is sufficiently suppressed, and therefore, off-leakage current is suppressed.

  Next, the case where the entire graphene layer becomes P-type due to the negative voltage back bias is the same as the case of the positive voltage back gate. That is, if no voltage is applied to the gate 39, the transistor is on, and a current flows at a high charge injection rate. In this case, the drain bias is a negative voltage, and the transistor can be turned off by applying a positive voltage to the gate electrode 39.

  The back bias operation may be applied to each transistor independently, or may be applied to a plurality of transistors collectively. Further, even if a region where the gate 39 is provided is operated as a drain instead of a source, the transistor can be operated on the same principle.

  Also in the element in the present embodiment, the suspended graphene channel structure described in the first embodiment is possible.

(Fifth embodiment)
The fifth embodiment is similar to the fourth embodiment in that the entire graphene layer is doped P-type or N-type instead of applying the back gate bias to give the energy offset 38. The effect can be obtained. These doping methods are the same as those in the third embodiment. Even in this case, if no voltage is applied to the gate 39, the transistor is in an on state, and a current flows at a high charge injection rate.

  First, a case where the entire graphene layer is doped P-type will be described. By applying a negative voltage as the drain bias and applying a positive voltage to the gate electrode 39, the transistor is turned off on the same principle as in the fourth embodiment, and a good cutoff is achieved. Characteristics are obtained.

  Next, a case where the entire graphene layer is doped N-type will be described. By applying a positive voltage as a drain bias and applying a negative voltage to the gate electrode 39, the transistor is turned off on the same principle as in the fourth embodiment, and a good cutoff is achieved. Characteristics are obtained.

  The doping can be applied individually to the transistors on the circuit. Further, even if a region where the gate 39 is provided is operated as a drain instead of a source, the transistor can be operated on the same principle. Moreover, it can be made P-type by applying a negative back gate bias to N-type graphene, and it can be made N-type by applying a positive back-gate voltage to P-type graphene. be able to. In addition, doping with only one of the source side and the drain side as viewed from the channel region, or doping with different polarities in both are possible. Even in any combination of these polarities, the transistors operate on the same principle as in the above example, and good cut-off characteristics and high-speed operation are realized at the same time.

  Also in the element in the present embodiment, the suspended graphene channel structure described in the first embodiment is possible.

  As mentioned above, although embodiment of this invention was described, this invention is not restricted to these, In the category of the summary of the invention as described in a claim, it can change variously. In addition, the present invention can be variously modified without departing from the scope of the invention in the implementation stage. Furthermore, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment.

1: Fermi energy
2: Dirac point
3: P-type state
4: Normal graphene state
5: N-type state
6: Graphene nanoribbon
7: Top gate
8: Source
9: Channel
10: Band gap
11: Thermally excited leakage current
12: Graphene layer
13: Source side gate
14: Drain side gate
15: Source
16: Drain
17: Contact
18: Mask
19: Area to be removed
20: Semiconducting graphene channel
21: Board
22: Gate insulation film
31: Fermi energy of the source
32: Dirac point of gapless graphene
33: Fermi energy of drain
34: Band gap
35: Transfer of Fermi energy by drain voltage
36: Dirac point change due to electric field of source side gate
37: Dirac point change by electric field of drain side gate
38: Energy offset
39: Gate
40: Dirac point change due to gate electric field

Claims (4)

A substrate,
A channel region having graphene formed on the substrate and having a band gap generated;
A source / drain region having graphene formed on both sides of the channel region and having a smaller band gap than the graphene of the channel region;
First and second gate electrodes respectively formed on portions of the source / drain regions in contact with the channel region ;
Semiconductor device Ru equipped with. The substrate is a semiconductor device according to claim 1 that have a back gate electrode. The semiconductor device according to any one of claims 1 to 2 that any will have a dopant of the channel region and the source / drain regions. Forming a graphene with a band gap generated on a substrate;
Forming a gate electrode on the graphene;
Forming a mask material on the gate electrode;
Etching the graphene into a thin line using the mask material and the gate electrode as a mask;
The method of manufacturing a semiconductor device Ru comprising a.

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