JP2009182173A - Graphene transistor and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the performance of a graphene transistor by optimizing characteristics of a channel layer using a graphene film at respective places with respect to a graphene transistor and an electronic apparatus. <P>SOLUTION: A carbon film 12 formed of one or more layers of graphene is made of an active region where a carrier travels, and the width in a direction perpendicular to the travel direction of the carrier on the carbon film constituting the active region varies depending on places. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a graphene transistor and an electronic device, and relates to a configuration for achieving both high mobility and high breakdown voltage characteristics.

Silicon semiconductors have achieved high performance by miniaturization, but due to the limitations of processing technology and heat generation, there has been an upper limit to their progress.
Therefore, carbon, in particular, a graphene film has been proposed as an electronic material that replaces silicon. Graphene has high carrier (electron, hole) mobility due to its band structure, and is expected as a component of future high-speed information processing systems that replace silicon.

  Although graphene has a feature that the carrier velocity is high as described above, itself is a semiconductor having a zero band gap, and if used as a transistor material as it is, there is a problem that a breakdown voltage is lowered and an off-current is increased.

Therefore, various methods for providing a band gap to the graphene film have been proposed.
For example, a method is known in which the width of the graphene film in the direction perpendicular to the current is reduced and the width is quantized in the lateral direction (see, for example, Non-Patent Document 1).

FIG. 11 is an explanatory diagram of the dependency of the energy gap in the graphene film on the ribbon width. As is clear from the figure, the band gap increases as the width of the graphene film is reduced.
In recent years, it has been proposed to form a field effect transistor using such a graphene film (see, for example, Non-Patent Document 2).

Here, an example of the graphene ribbon FET will be described with reference to FIG.
FIG. 12 is a schematic plan view of a conventional graphene ribbon FET, in which a source electrode 83 and a drain electrode 84 are provided on a graphene ribbon 81 having a width of 5 nm with a gate electrode 82 interposed therebetween.

As a method for forming graphene, a method of growing directly on a substrate using a chemical vapor deposition method or the like is known (for example, see Patent Document 1 or Patent Document 2).
B. Obradovic, et al. , Applied Physics Letters, Vo 1.88, 142102, 2006. http: // www. ednjapan. com / content / I_news / 2006/04 / 19_01. . html JP 07-002508 A Japanese Patent Laid-Open No. 08-260150

The nature of the semiconductor material required to construct the FET is not necessarily the same for each part of the FET.
For example, a large electric field is applied from the gate end to the gate and drain, and the breakdown voltage of this part determines the breakdown voltage of the entire device (if necessary, M. Sze, “Physics of Semiconductor Devices”, New York: Wiley , 1981).
Therefore, a material having a large band gap between the gate and the drain is preferable.

On the other hand, since the drain voltage does not reach between the source and the gate, the electric field is usually low, and a material having high mobility, that is, a small effective mass is preferable for accelerating carriers between these.
Further, since the withstand voltage is not required because of the low electric field, the band gap may be small.
Thus, the characteristics required for the material are different between the source side and the drain side of the channel.

However, in general, in a semiconductor, the band gap and the effective mass of the carrier are proportional to each other, and there is a trade-off that the effective mass increases as the band gap increases, leading to a decrease in mobility.
For example, from a band calculation using kp perturbation, if m is the effective mass of the carrier, E _g is the band gap, and h is the Planck constant,
m = (h / 2π) ² · E _g / (2P ² )
It is known that this relationship is derived. Here, P is a constant proportional to the expected value of momentum obtained from the wave function (see Nobuo Mikoshiba, “Semiconductor Physics”, Baifukan, 1982 if necessary).

However, in the conventional graphene transistor, the width of the graphene ribbon is constant, so when the breakdown voltage is increased by narrowing the width and increasing the band gap, the effective mass of the carrier increases and operates. The speed will decrease.
On the other hand, when the operating speed is increased by increasing the effective mass of the carrier by increasing the width and decreasing the band gap, there is a problem that the withstand voltage decreases.

  Accordingly, an object of the present invention is to improve the performance of a graphene transistor by optimizing the characteristics of a channel layer using a graphene film at each location.

  From one aspect of the present invention, a carbon film made of one or more graphenes is used as an active region in which carriers travel, and the width in a direction perpendicular to the carrier traveling direction of the carbon film constituting the active region depends on the location. A changing graphene transistor is provided.

  According to the disclosed graphene transistor, it is possible to configure a high-performance field-effect transistor or a lateral heterojunction bipolar transistor by optimizing the characteristics of the channel layer at each location, and thus an electronic device using the graphene transistor This greatly contributes to the improvement of performance.

Here, with reference to FIG.1 and FIG.2, embodiment of this invention is described.
The present invention provides a transistor in which the band gap is generated and the increase in effective mass is suppressed by modulating the width of the graphene film depending on the location.
Specifically, increasing the ribbon width at the source-gate or base region to reduce the effective mass to increase the mobility, and reducing the ribbon width between the gate-drain or emitter region to reduce the band gap. By making it large, the trade-off between effective mass and band gap can be avoided, and the characteristics of the FET or lateral heterojunction bipolar transistor can be improved more actively.

  As a method for forming graphene, a method of growing directly on the substrate by chemical vapor deposition or the like (see the above-mentioned Patent Document 1 or Patent Document 2), or a graphene sheet grown on the tip of a carbon nanotube is used as an insulating substrate. Or a method of graphitizing a SiC film grown on an insulating substrate by heat treatment.

FIG. 1 is an explanatory diagram of a configuration when the present invention is applied to a graphene FET. FIG. 1A is a conceptual plan view, FIG. 1B is a schematic cross-sectional view, and FIG. It is a band diagram.
In the figure, among the graphene films 12 formed on the insulating substrate 11, the width of the graphene film 12 constituting the source region is set to 25 nm, the width of the graphene film 12 constituting the drain region is set to 5 nm, and immediately below the gate electrode 14. The width of the graphene film 12 constituting the channel region is continuously changed from 25 nm to 5 nm.

  A gate electrode 14 is provided on the channel region via a gate insulating film 13, a source electrode 15 is provided on the source region, and a drain electrode 16 is provided on the drain region.

  At this time, as shown in FIG. 1C, the band diagram on the source side is about 0.04 eV, as is apparent from the graphene ribbon width dependency of the band diagram in FIG. 11 described above, and the band diagram on the drain side is About 0.2 eV.

Here, the performance of the graphene FET of the present invention and the conventional graphene FET will be compared with a simple model with reference to FIG.
The objects of comparison are the graphene FET of the present invention in which the source side is 25 nm wide and the drain side is 5 nm wide, the conventional graphene FET having a total width of 25 nm, and the conventional graphene FET having a total width of 5 nm.

FIG. 2 is a performance comparison diagram of each graphene FET, μ _max and E _gmax are the maximum values of mobility and band gap, R _s is the source resistance, g _m is the mutual conductance, I _ON is the maximum ON current, and BV is Breakdown voltage.
Here, we assume some parameters,
Gate capacity: 640 nF / cm ² ,
Electron concentration: 10 ¹² cm ^-2 ,
Gate-source distance: 0.1 μm
Electron speed: 5 × 10 ⁷ cm / s
It was.
Note that the performance of graphene with a total thickness of 5 nm is tripled because three 5 nm channels can be arranged in the same 25 nm width.

First, the reason why the source resistance R _s is low in the two on the left in the figure is that, as described above, since the ribbon width on the source side is wide and the band gap is small, the effective mass of the carrier is small, so the mobility is high, and the channel width This is because it is wide.
Further, as a result of the low source resistance R _s , the mutual conductance g _m is improved.

On the other hand, the maximum ON current I _ON is related to the mutual conductance g _m and the maximum operating voltage, that is, BV, and is expressed as a product of both.
Since BV is proportional to the band gap and therefore inversely proportional to the ribbon width, the two on the right side in the figure have a high breakdown voltage.

From this, it can be seen that the graphene FET of the present invention shows excellent values in all items.
As described above, by changing the channel width of the graphene FET, it is possible to optimize the material in each part of the channel, avoid the trade-off between the gap and the mobility, and further improve the characteristics of the FET.

  In addition, the band gap can be continuously changed by continuously changing the width of the graphene ribbon, an electric field can be generated in the transistor, and carriers can be accelerated by forming a drift electric field.

In addition, by combining with n-type and p-type selective doping, it is possible to form a lateral heterojunction bipolar transistor in which carriers run in a direction along the substrate surface.
As a doping means for graphene, K (potassium) atoms may be adsorbed on the graphene film in order to dope n-type, and O (oxygen) in the graphene film in order to dope into p-type. What is necessary is just to dope an atom.

  Regarding the selection of the width of the graphene film, first, it is considered that the upper limit of the width of the narrow portion on the drain side is about 10 nm. From FIG. 11, the graphene ribbon has a band gap of about 0.1 eV and a room temperature thermal energy of 25 meV (= 0.025 eV). This is because the generation of carriers due to heat cannot be ignored.

Next, on the source side, the lower limit of the width is considered to be about 5 nm.
This is because the mobility at this time is considered to be about 2000 cm ² / Vs, and this degree of mobility is required considering differentiation from silicon.

  In addition, it is possible to further reduce the parasitic resistance between the source and the gate by making the band width substantially zero by making the width on the source side sufficiently large and giving the metal or metalloid characteristics. .

Based on the above, the process for forming the graphene FET according to the first embodiment of the present invention will now be described with reference to FIGS.
First, as shown in FIG. 3A, a SiO ₂ film 22 having a thickness of, for example, 200 nm is deposited on a silicon substrate 21 by, for example, a plasma CVD method using TEOS (tetraethyl orthosilicate) as a source gas. .
The thickness of the SiO ₂ film 22 is not particularly limited as long as electrical insulation is ensured.

Next, a Si active layer 23 having a thickness of, for example, 5 nm is deposited on the SiO ₂ film 22 by plasma CVD using SiH ₄ as a source gas.

Next, as shown in FIG. 3B, fullerene 24 is deposited on the Si active layer 23.
For example, a commercially available fullerene 24 is used.
As for the type of fullerene, there are C70, C82 and the like other than C60, but there is no particular limitation.

At this time, as a method for depositing fullerene, for example, an MBE method (molecular beam epitaxial growth method) is used.
In the vacuum chamber in which fullerene is deposited, the temperature of the crucible filled with fullerene is raised by resistance heating, so that fullerene is uniformly deposited on the Si active layer 23 as a molecular beam.
The temperature of the crucible is in the range of 500 to 600 ° C. (1 × 10 ⁻⁹ Torr or less), and the fullerene deposition rate can be adjusted by the temperature.
Since the sublimation temperature of fullerene differs depending on the degree of vacuum in the vacuum chamber, the rate is adjusted by a quartz oscillator film thickness meter during sublimation of fullerene.
A typical deposition rate is 1 ML (monolayer) / min or less.
In particular, when a low deposition amount of 1 ML or less is required, a slower rate is preferable.

Next, as shown in FIG. 3 (c), after the fullerene is deposited, resistance heating or a heater is applied to the substrate at 850 ° C. or higher, for example, 1100 ° C. under high vacuum of 10 ⁻² Torr or lower, for example, 10 ⁻³ Torr Heat treatment is performed by heating.
At this time, the fullerene 24 that is in direct contact with the outermost surface of the Si active layer 23 has a strong chemical bond (chemical adsorption), so that it does not desorb even when heated and changes to a silicon carbide film 25 at a higher temperature.
At this time, since the fullerenes that are not in contact with the surface are physically adsorbed to each other, they are easily detached from the surface by heating, and only one fullerene layer directly bonded to the surface of the Si active layer 23 remains, and silicon carbide (SiC) It becomes the raw material of.
This makes it possible to always supply a certain amount of carbon atoms with respect to the surface area of silicon.

Next, as shown in FIG. 3D, the produced silicon carbide film 25 is heated to 1100 to 2000 ° C., for example, 1350 ° C. by heating with a heater under a high vacuum of 10 ⁻² Torr or less, for example, 10 ⁻³ Torr. To sublimate silicon atoms to obtain a graphene film 26 on the SiO ₂ film 22 (see Appl. Phys. Lett. Vol. 77, p. 531, 2000 if necessary).
At this time, all the fullerene used in the process becomes a raw material of desorption or silicon carbide, and silicon carbide is also converted into graphene by sublimation. Therefore, the graphene film 26 can be formed on the SiO ₂ film 22 without using a catalyst.

  Next, as shown in FIG. 4E, an n-type graphene film 27 is formed by introducing K as a dopant into the graphene film 26 by ion implantation or surface adsorption.

Next, as shown in FIG. 4F, the n-type graphene film 27 is patterned by a photolithography technique using EB exposure and oxygen plasma etching.
At this time, as shown in the top plan view of FIG. 4F, the width of the source side is, for example, 25 nm, the width of the drain side is, for example, 5 nm, and the length of the channel region between them is 40 nm. The width is continuously changed from 25 nm to 5 nm.
In addition, the width of the portion where the drain electrode is formed at the end on the drain side is, for example, 25 nm in order to reduce the band gap and reduce the contact resistance.

Next, as shown in FIG. 4G, a source electrode 28 and a drain electrode 29 made of Ti / Au on which a Ti film and an Au film are sequentially deposited are formed by photolithography and evaporation / lift-off techniques.
Note that the source electrode 28 and the drain electrode 29 protrude from the n-type graphene film 27, which is to contact the side surface of the n-type graphene film 27 and reduce the contact resistance.

Next, as shown in FIG. 5H, a SiO ₂ film 30 serving as a gate insulating film is formed on the entire surface to a thickness of, for example, 10 nm by a CVD method.
Next, as shown in FIG. 5I, a gate electrode 31 made of Ti / Au in which a Ti film and an Au film are sequentially deposited is formed by photolithography and evaporation / lift-off techniques.

Next, as shown in FIG. 5J, a SiO ₂ film having a thickness of, for example, 500 nm is deposited by the CVD method to form the interlayer insulating film 32.
Thereafter, the process moves to a wiring process, but there is no difference from a normal graphene FET, and the process conforms to a silicon process, and is omitted here.

Thus, in Example 1 of the present invention, since the band gap is reduced by setting the ribbon width of the graphene film on the source-gate side to 25 nm, the source resistance is reduced and the effective mass of the carrier is reduced. Therefore, the mobility can be increased and the mutual conductance can be increased.
On the other hand, since the band gap is widened by setting the ribbon width of the graphene film on the gate-drain side to 5 nm, the breakdown voltage can be increased and both high breakdown voltage and high mobility can be achieved.

Next, the graphene FET according to the second embodiment of the present invention will be described with reference to FIG. 6, but the basic formation process is exactly the same as the formation process of the graphene FET according to the first embodiment. Only the illustration is given.
FIG. 6 is a conceptual plan view of the graphene FET according to the second embodiment of the present invention, in which the width of the n-type graphene film 33 serving as a channel region is changed stepwise from, for example, 25 nm to 5 nm.

Also in Example 2, since the ribbon width of the graphene film is locally changed so that both high mobility and high breakdown voltage can be achieved, a high-performance graphene transistor can be realized.
Note that if the difference between the ribbon widths on the source side and the drain side becomes too large, all carriers may not flow into the drain side.

Next, the graphene FET according to the third embodiment of the present invention will be described with reference to FIG. 7, but the basic formation process is exactly the same as the formation process of the graphene FET according to the first embodiment. Only the illustration is given.
Figure 7 is a schematic plan view of a graphene FET of Example 3 of the present invention, a width of the ribbon width provided three drain regions 34 ₁ to 34 ₃ of 5nm respect 25nm of the source region and the channel region .

If the difference between the ribbon widths on the source side and the drain side becomes too large, it is expected that the current capacity on the drain side will be insufficient, and the current will be limited by the resistance on the drain side.
However, in the third embodiment of the present invention, since three channels are provided on the drain side, all carriers can flow to the drain side.

Next, the graphene FET according to the fourth embodiment of the present invention will be described with reference to FIG. 8, but the basic formation process is exactly the same as the formation process of the graphene FET according to the first embodiment. Only the illustration is given.
FIG. 8A is a conceptual plan view of a graphene FET according to Example 4 of the present invention, in which the ribbon width is 5 nm with respect to the source region and the channel region whose width continuously changes from 10 nm to 25 nm. A drain region 34 is provided.

  FIG. 8B is a band diagram of the graphene FET according to Example 4 of the present invention, and the band gap is changed from 0.1 eV to 0.04 eV by continuously changing the ribbon width from the source region to the drain region. A drift electric field E that continuously changes and accelerates electrons is formed.

  In Embodiment 4 of the present invention, a drift electric field is formed from the source region to the drain region, so that the operation speed can be further increased.

In the graphene FETs of Examples 1 to 4 described above, the channel width is about 25 nm, and the absolute current capacity is very small on the order of 10 μA.
Therefore, in an actual integrated circuit, a plurality of channels are connected in parallel to form one transistor.

Next, a graphene lateral heterojunction bipolar transistor (graphene lateral HBT) according to a fifth embodiment of the present invention will be described with reference to FIG. 9. The basic formation process is the formation of the graphene FET according to the first embodiment described above. Since it is exactly the same as the process, only the shape will be described.
FIG. 9A is a conceptual plan view of a graphene lateral HBT according to Embodiment 5 of the present invention, FIG. 9B is a schematic cross-sectional view, and FIG. 9C is a band diagram.

In the graphene lateral HBT according to the fifth embodiment of the present invention, the graphene film provided on the silicon substrate 41 via the SiO ₂ film 42 is selectively doped to n, p, and n to narrow the ribbon width of the emitter, By making the width of the base collector wider than this, a heterojunction is formed at the emitter / base interface as shown in FIG.

In this case, the ribbon width of the n-type graphene film 43 that forms the emitter is, for example, 10 nm, the width of the p-type graphene film 44 that forms the base is 25 nm, the length is 40 nm, and the n-type graphene film 45 that forms the collector Is 25 nm.
Further, a Ti / Au electrode is used as the emitter electrode 46 and the collector electrode 48, and a Ti / Au electrode is used as the base electrode 47.
As described above, K is adsorbed on the graphene film for n-type doping, and O is adsorbed on the graphene film for p-type doping.

  In contrast to the conventional HBT, a vertical HBT could not be realized. In the fifth embodiment of the present invention, a lateral HBT, that is, a lateral HBT, is realized by controlling the ribbon width of the graphene film. Can do.

Next, the graphene lateral HBT of Example 6 of the present invention will be described with reference to FIG. 10, but the basic formation process is exactly the same as the formation process of the graphene FET of Example 1 described above. Only the shape will be described.
FIG. 10A is a conceptual plan view of a graphene lateral HBT according to Example 6 of the present invention, FIG. 10B is a schematic cross-sectional view, and FIG. 10C is a band diagram.

In the graphene lateral HBT according to the sixth embodiment of the present invention, the ribbon width of the n-type graphene film 51 that forms the emitter is, for example, 10 nm, and the width of the p-type graphene film 52 that is 40 nm in length to form the base is 20 nm. The width of the n-type graphene film 53 forming the collector is set to 25 nm.
Also in this case, Ti / Au electrodes are used as the emitter electrode 54 and the collector electrode 56, and Ti / Au electrodes are also used as the base electrode 55.

In the graphene HBT of Example 6, since the channel width is continuously widened at the base portion, the band gap is narrowed from the emitter end to the collector end as shown in FIG. A drift electric field E is formed.
Therefore, the operation speed can be improved as compared with the graphene HBT of the fifth embodiment.

  In the case of the graphene HBTs of the fifth and sixth embodiments of the present invention, the absolute current capacity is very small on the order of 10 μA. Therefore, in an actual integrated circuit, a plurality of active regions are connected in parallel. One transistor is formed.

Although the embodiments and examples of the present invention have been described above, the present invention is not limited to the configurations and conditions described in the embodiments and examples, and various modifications can be made.
For example, in each of the above embodiments, a graphene film is formed by sublimating Si after forming a SiC film using fullerene on the surface of the Si active layer, but the method of forming the graphene film is arbitrary. is there.

  For example, as described above, a method of growing directly on the substrate using chemical vapor deposition or the like, or a method of transferring a graphene sheet grown on the tip of the carbon nanotube to an insulating substrate may be used.

In each of the above embodiments, a silicon substrate on which a SiO ₂ film is formed is used as a growth substrate for the graphene film. However, the insulating film is not limited to the SiO ₂ film, and a SiN film may be used. good.
In the case of using a SiN film, a plasma CVD method or a thermal CVD method using SiH ₄ and NH ₃ as source gases may be used.

Furthermore, the growth substrate is not limited to a silicon substrate having an insulating film formed on the surface, and a high heat resistant insulating substrate such as a sapphire substrate may be used.
In the above-described Example 1 and the like, each electrode is formed so as to cover the end of the graphene film in order to reduce the contact resistance. Like the base electrode or collector electrode of Example 6, the electrode may be disposed only on the graphene film.

  In each of the above-described embodiments, the n-channel FET or the npn-type HBT is described. However, it is needless to say that the p-channel FET or the pnp-type HBT may be reversed from the conductivity type.

It is a structure explanatory view at the time of applying the present invention to graphene FET. It is a performance comparison figure of each graphene FET. It is explanatory drawing of the formation process to the middle of the graphene FET of Example 1 of this invention. It is explanatory drawing of the formation process to the middle after FIG. 3 of graphene FET of Example 1 of this invention. It is explanatory drawing of the formation process after FIG. 4 of graphene FET of Example 1 of this invention. It is a notional top view of graphene FET of Example 2 of the present invention. It is a notional top view of graphene FET of Example 3 of the present invention. It is a structure explanatory drawing of graphene FET of Example 4 of this invention. It is composition explanatory drawing of the graphene lateral HBT of Example 5 of this invention. It is composition explanatory drawing of the graphene lateral HBT of Example 6 of this invention. It is explanatory drawing of the ribbon width dependence of the energy gap in a graphene film. It is a schematic plan view of a conventional graphene ribbon FET.

Explanation of symbols

11 Insulating substrate 12 Graphene film 13 Gate insulating film 14 Gate electrode 15 Source electrode 16 Drain electrode 21 Silicon substrate 22 SiO ₂ film 23 Si active layer 24 Fullerene 25 Silicon carbide film 26 Graphene film 27 n-type graphene film 28 Source electrode 29 Drain electrode 30 SiO ₂ film 31 Gate electrode 32 Interlayer insulating film 33 n-type graphene film 34, 34 _{1 to} 34 ₃ drain region 41 silicon substrate 42 SiO ₂ film 43 n-type graphene film 44 p-type graphene film 45 n-type graphene film 46 emitter electrode 47 base electrode 48 collector electrode 51 n-type graphene film 52 p-type graphene film 53 n-type graphene film 54 emitter electrode 55 base electrode 56 collector electrode 81 graphene ribbon 82 gate electrode 83 source electrode 84 drain electrode

Claims (5)

A graphene characterized in that a carbon film composed of one or more graphenes serves as an active region in which carriers travel, and the width in the direction perpendicular to the carrier travel direction of the carbon film constituting the active region varies depending on the location. Transistor. The active region constitutes a channel region, a source region, and a drain region of a field effect transistor, and the width of the carbon film on the side near the source electrode in the channel region is close to the drain electrode in the channel region The graphene transistor according to claim 1, wherein the graphene transistor is wider than the width of the carbon film on the side. The graphene transistor according to claim 2, wherein the width of the carbon film constituting the channel region is continuously changed. The active region constitutes a base region, an emitter region, and a collector region of a lateral bipolar transistor, and the width of the carbon film in the portion that becomes the emitter region is narrower than the width of the carbon film in the portion that becomes the base region The graphene transistor according to claim 1. An electronic apparatus comprising the graphene transistor according to any one of claims 1 to 4.

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