JP2006100721A - Semiconductor element and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor element which has an excellent carrier controllability in a channel region and has less leakage current, and also a method for manufacturing the semiconductor element. <P>SOLUTION: In the method for manufacturing a semiconductor element, a low-concentration doped diamond layer 4 which has a cross section including a direction perpendicular to a surface of a substrate 1 and having a trapezoidal shape of an upper bottom side shorter than a lower bottom side, is formed on the substrate 1 by an epitaxial growth method. High-concentration doped diamond layers 7a and 7b having an impurity concentration higher than that of the low-concentration diamond layer 4 are formed by the epitaxial growth method on both sides of the low-concentration doped diamond layer 4. Metallic electrodes 8a and 8b are formed on the high-concentration diamond layers 7a and 7b, silicon oxide insulating layers 9a and 9b are formed, and then a gate electrode 11 is formed on the low-concentration diamond layer 4 with aluminum oxide insulating layer 10 disposed therebetween so that a distance between the high-concentration diamond layers 7a and 7b is shorter as the distance goes away from the substrate 1. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device applicable to a field effect transistor, a sensor, a light emitting diode, and the like and a manufacturing method thereof, and more particularly to a semiconductor device using a diamond thin film and a manufacturing method thereof.

Diamond shows thermal conductivity of 20W / cm · K, the band gap 5.47 eV, electron mobility is 2000 cm ² / V · sec, and 2100 cm ² / V · sec hole mobility, excellent device characteristics . For this reason, application to high power devices, high-frequency devices, and electronic devices that operate even in harsh environments exposed to high temperatures or radiation is expected.

  Conventionally, as a field effect transistor (FET) using a diamond thin film, for example, an insulated gate FET (Metal Insulator Semiconductor Field) in which an insulator layer is inserted between a gate electrode and a channel layer which is an operation layer. Effect Transistor: MISFET) (see, for example, Patent Documents 1 and 2).

  12 is a cross-sectional view showing the structure of the MISFET described in Patent Document 1, and FIG. 13 is a cross-sectional view showing the structure of the MISFET described in Patent Document 2. As shown in FIG. 12, the MISFET 100 described in Patent Document 1 includes highly doped p-type semiconductor diamond layers 102a and 102b doped with boron at a high concentration on an insulating diamond single crystal substrate 101 to serve as a source and a drain. Is formed. In addition, between the highly doped p-type semiconductor diamond layer 102a and the highly doped p-type semiconductor diamond layer 102b on the insulating diamond single crystal substrate 101, the concentration is lower than those of the highly doped p-type semiconductor diamond layers 102a and 102b. A lightly doped p-type semiconductor diamond layer 103 which is a channel layer doped with boron is formed. Further, a source electrode 104 and a drain electrode 105 are formed on the highly doped p-type semiconductor diamond layers 102a and 102b, respectively, and an undoped diamond layer serving as an insulator layer is formed on the low-doped p-type semiconductor diamond layer 103. A gate electrode 107 is formed via 106.

This MISFET100, by a channel region is the drain current I _D flows exist, a positive voltage is applied to the gate electrode 107 with respect to the source voltage V _S when the gate voltage V _G is not applied, the drain current This is a normally-on type FET in which _ID is suppressed. In such a normally-on type FET, for greatly change the drain current I _D with little gate voltage V _G, i.e., is the ratio of the amount of change in the gate voltage V _G and the variation of the drain current I _D transconductance g _m in order to increase the ₍₌ dV G / _{dI D)} is the influence of the gate voltage V _G is as extends to deep channel layer region, it is effective to widen the depletion region of the carrier increases. Specifically, the concentration of an impurity serving as a donor or acceptor in the channel layer formed between the source and the drain may be reduced and the thickness may be reduced to a range affected by the gate potential. However, in order to secure the drain current _ID , the impurity concentration of the channel layer must be increased to increase the carrier concentration.

  For this reason, in a general MISFET, the impurity concentration in the channel layer is set to about 10 to several hundred ppm by atomic ratio. For example, in the MISFET 100 described in Patent Document 1, boron (B) and carbon (C) in the lightly doped p-type semiconductor diamond layer 103 as a channel layer are calculated based on the synthesis conditions described in the examples. The atomic ratio (B / C) is 200 ppm.

  As shown in FIG. 13, in the MISFET 110 described in Patent Document 2, a base layer 112 made of diamond is formed on a silicon substrate 111, and an n-type semiconductor diamond serving as a source and a drain is formed on the base layer 112. Layers 113a and 113b and a p-type semiconductor diamond layer 114 which is a channel layer are formed. A source electrode 115 and a drain electrode 116 are formed on the n-type semiconductor diamond layers 113a and 113b, respectively, and a gate electrode is formed on the p-type semiconductor diamond layer 114 via an insulator layer 117 made of diamond. 118 is formed. The MISFET 110 described in Patent Document 2 is intended to improve mass productivity by forming a base layer 112 on a silicon substrate 111 without using a diamond single crystal substrate and forming each layer on the base layer 112. Similar to the MISFET 100 described in Patent Document 1, it is a normally-on type FET.

On the other hand, the high mobility (2000 cm ² / V · second) as described above is a value obtained in a state in which there are almost no impurities and crystal defects in the diamond layer, as in the MISFETs described in Patent Documents 1 and 2. When a diamond layer is doped with an impurity serving as a donor or acceptor in order to secure a carrier source for the channel layer, the carrier mobility is lowered depending on the impurity concentration, so that the high frequency response is deteriorated.

  In view of this, a diamond FET that can be applied to a high-frequency transistor by reducing the impurity concentration of the channel layer as much as possible has been proposed (see Patent Document 3). FIG. 14 is a schematic diagram showing the operation principle of the diamond FET described in Patent Document 3. As shown in FIG. 14, in the FET 120 described in Patent Document 3, a high resistance diamond layer 122 having a specific resistance of 100 Ω · cm or more is provided between the semiconductor diamond layer 121 and the semiconductor diamond layer 123. . A source electrode 124 and a drain electrode 126 are formed on the semiconductor diamond layers 121 and 123, respectively, and a gate electrode 125 is formed on the high resistance diamond layer 122.

In the diamond FET 120, carriers that reach the drain electrode 126 from the source electrode 124 flow through the semiconductor diamond layer 121, the high resistance diamond layer 122, and the semiconductor diamond layer 123 in this order. By varying the voltage V _G applied to the gate electrode 125, by changing the potential of the high-resistivity diamond layer 122, the amount of carrier injected from the semiconductor diamond layer 121 where the source electrode 124 is in contact to the high-resistivity diamond layer 122 I have control. Unlike the above-described MISFET, the FET 120 does not control the drain current _ID by expanding a depletion layer in the channel layer. Therefore, it is necessary to form a continuous diamond channel layer having a low impurity concentration and a small film thickness. Absent.

  In a semiconductor element in which a source electrode and a drain electrode are provided across a channel region, and a gate electrode is provided in contact with the channel region, the structure as the FET described in Patent Document 3 is provided. Contact resistance between the electrode and drain electrode and the channel region causes power loss. Therefore, in such a semiconductor element, generally, an ohmic junction is formed by providing a semiconductor layer doped with an impurity at a high concentration in a region where a source electrode and a drain electrode are in contact with a channel region. Further, in such a semiconductor element, if leakage current is generated between the channel region and the gate electrode, it causes a decrease in performance such as a decrease in amplification factor. Therefore, in general, an insulating layer is provided between the channel region and the gate electrode, or A Schottky junction interface is formed.

Japanese Patent Laid-Open No. 1-158774 JP-A-3-263872 JP-A-6-232388

However, the conventional techniques described above have the following problems. Usually, as the performance index of the FET, the control of the carrier flowing through the channel layer due to the drain current I _D and the gate voltage V _G and the like. Since the drain current _ID is the number of charges flowing between the source electrode and the drain electrode per unit time, in order to obtain a high drain current _ID , the width of the channel region is narrowed, that is, the distance between the source and the drain is shortened. problem that it is effective to, in the semiconductor device of the FET structure as described in Patent Document 3, simply when narrowing the width of the channel region, the controllability of the carriers by the gate voltage V _G is degraded There is a point. This is because the width of the channel region becomes narrow, the electric field between the source and the drain becomes strong, because the influence of the electric field applied to the channel layer is relatively weakened by the gate voltage V _G. This phenomenon becomes more prominent as the distance from the gate electrode increases. Further, if there is a channel portion that cannot be controlled by the gate electrode, an extra current, that is, a leakage current flows even when the gate voltage should be turned off.

  The present invention has been made in view of such problems, and an object of the present invention is to provide a semiconductor device having excellent carrier controllability in a channel region and a low leakage current, and a method for manufacturing the same.

  A semiconductor element according to the first invention of the present application is formed on a substrate, a first semiconductor layer locally formed on the substrate, and both sides of the first semiconductor layer, and at least a part of the first semiconductor layer is formed on the first semiconductor layer. A second semiconductor layer that contacts the semiconductor layer and has a higher impurity concentration than the first semiconductor layer; and a control layer that controls a current flowing between the second and third semiconductor layers. The distance between the second semiconductor layer and the third semiconductor layer in the portion in contact with the first semiconductor layer is greater than the portion farthest from the control layer in the thickness direction of the first semiconductor layer. It is characterized in that the part closest to is shorter.

  In the present invention, the distance between the second and third semiconductor layers is shorter in the portion closest to the control layer than in the portion farthest from the control layer in the thickness direction of the first semiconductor layer. The electric field strength in the first semiconductor layer formed between the third semiconductor layers is lower in the portion farthest from the control layer than in the portion closest to the control layer. Thereby, carrier controllability by the control layer can be improved. In addition, since the second and third semiconductor layers are doped with impurities at a higher concentration than the first semiconductor layer, a high-density charge is applied from the second or third semiconductor layer to the first semiconductor layer. In addition to being able to be implanted, it is possible to reduce the amount of defects and impurities that hinder the movement of charges in the first semiconductor layer. As a result, a charge transfer rate in the first semiconductor layer can be improved, and a semiconductor element with excellent controllability can be obtained. Furthermore, since this semiconductor element has excellent carrier controllability by the control layer, the leakage current can be reduced by adjusting the voltage applied to the control layer.

  The semiconductor element is, for example, a gate electrode in which the control layer is electrically connected to the first semiconductor layer via an insulating layer or a Schottky partition, and the second and third semiconductor layers are respectively a source. And a field effect transistor to be a drain.

  A semiconductor device according to the second invention of the present application is formed on a substrate, a first semiconductor layer locally formed on the substrate, and both sides of the first semiconductor layer, and at least a part of the first semiconductor layer is formed on the first semiconductor layer. Second and third semiconductor layers that are in contact with the semiconductor layer and have an impurity concentration higher than that of the first semiconductor layer, and the second and second semiconductor layers are in contact with the first semiconductor layer. 3 is characterized in that the portion farthest from the substrate is shorter than the portion closest to the substrate in the thickness direction of the first semiconductor layer.

  In the present invention, the distance between the second and third semiconductor layers is shorter in the portion farthest from the substrate than in the portion closest to the substrate in the thickness direction of the first semiconductor layer. The electric field strength inside is the lowest at the part closest to the substrate and the highest at the part farthest from the substrate. Thereby, carrier controllability can be improved. In addition, since the second and third semiconductor layers are doped with impurities at a higher concentration than the first semiconductor layer, the charge transfer speed in the first semiconductor layer can be increased and the carrier controllability can be improved. it can. Further, this semiconductor element reduces the excess leakage current of the substrate because the distance between the second and third semiconductor layers is long in the portion far from the surface of the first semiconductor layer, that is, in the portion close to the substrate. Can do.

  In this semiconductor element, for example, a gate electrode is formed on the first semiconductor layer via an insulating layer or a Schottky barrier, and the second and third semiconductor layers serve as a source and a drain, respectively. It is an effect transistor. Thereby, a field effect transistor excellent in carrier controllability by the gate electrode can be obtained. Alternatively, the semiconductor element can be used as a sensor or a diode. In this semiconductor element, carriers are controlled by a change in the surface state of the first semiconductor layer caused by adsorption of gas, moisture, ions, or the like, or light irradiation. Therefore, a highly sensitive sensor can be obtained.

  The insulating layer can be formed of at least one material selected from the group consisting of metal oxides, metal nitrides, metal oxynitrides, metal fluorides, and nitrogen-doped diamond. Furthermore, at least one semiconductor layer of the first to third semiconductor layers may be formed of diamond. Thereby, high voltage resistance, heat resistance, radiation resistance, and high-speed operability can be improved.

  According to a third aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: a step of locally forming a first semiconductor layer on a substrate; and at least a part of the first semiconductor layer on both sides of the first semiconductor layer. Forming a second and third semiconductor layers in contact with each other and having an impurity concentration higher than that of the first semiconductor layer; and forming a control layer for controlling a current flowing between the second and third semiconductor layers. And the distance between the second and third semiconductor layers in the portion in contact with the first semiconductor layer is the portion farthest from the control layer in the thickness direction of the first semiconductor layer. The portion closest to the control layer is shorter than the control layer.

  In the present invention, since the second and third semiconductor layers are formed after the first semiconductor layer is formed, the second and third semiconductors in the portion in contact with the first semiconductor layer are formed. The distance between the layers can easily be made shorter in the portion closest to the control layer than in the portion farthest from the control layer. As a result, a semiconductor element having a narrow electric field intensity distribution in the first semiconductor layer and excellent carrier controllability by the control layer can be manufactured. In addition, since the second and third semiconductor layers are doped with impurities at a higher concentration than the first semiconductor layer, a high-density charge is applied from the second or third semiconductor layer to the first semiconductor layer. Since it can be implanted and the amount of defects and impurities in the first semiconductor layer can be reduced, a semiconductor element having a high charge transfer rate in the first semiconductor layer and excellent controllability can be obtained.

  According to a fourth aspect of the present invention, there is provided a method for manufacturing a semiconductor element, comprising: a step of locally forming a first semiconductor layer on a substrate; and at least a part of the first semiconductor layer on both sides of the first semiconductor layer. Forming second and third semiconductor layers that are in contact with each other and have an impurity concentration higher than that of the first semiconductor layer, and the second and third semiconductor layers are in contact with the first semiconductor layer. The distance between the third semiconductor layers is characterized in that the portion farthest from the substrate is shorter than the portion closest to the substrate in the thickness direction of the first semiconductor layer.

  In the present invention, since the second and third semiconductor layers are formed after the first semiconductor layer is formed on the substrate, the second and second portions in the portion in contact with the first semiconductor layer are formed. The distance between the three semiconductor layers can be easily made shorter in the portion farthest from the substrate than in the portion closest to the substrate. Thereby, the electric field strength on the surface of the first semiconductor layer is increased, and a semiconductor element with excellent carrier controllability can be manufactured. In addition, since the second and third semiconductor layers are doped with impurities at a higher concentration than the first semiconductor layer, a high-density charge is applied from the second or third semiconductor layer to the first semiconductor layer. Since it can be implanted and the amount of defects and impurities in the first semiconductor layer can be reduced, a semiconductor element having a high charge transfer rate in the first semiconductor layer and excellent controllability can be obtained.

  In the method for manufacturing a semiconductor element, the first semiconductor layer can be formed by epitaxial growth. Thereby, the shape of the cross section including the direction perpendicular to the substrate in the first semiconductor layer can be a trapezoidal shape having an upper base shorter than the lower base. Further, the second and third semiconductor layers may be formed by epitaxial growth. Thereby, generation | occurrence | production of the defect in the interface part of a 1st semiconductor layer and a 2nd and 3rd semiconductor layer can be suppressed. In that case, when the second and third semiconductor layers are formed by epitaxial growth, the second and third semiconductor layers may be doped with impurities at a high concentration.

  Alternatively, the second and third semiconductor layers may be doped with a high concentration by ion implantation. As a result, a gentle concentration distribution is generated at the boundary between the first semiconductor layer that is not ion-implanted and the second and third semiconductor layers that are ion-implanted. The impurity concentration decreases from the first semiconductor layer toward the second and third semiconductor layers and from the surface toward the inside. As a result, the distance between the second and third semiconductor layers in the portion in contact with the first semiconductor layer is the portion farthest from the substrate than the portion closest to the substrate in the thickness direction of the first semiconductor layer. It is possible to easily form a semiconductor element that is shorter or shorter in the portion closest to the control layer than in the portion farthest from the control layer.

  In addition, at least one of the first to third semiconductor layers can be formed of diamond. Thereby, a semiconductor element excellent in high voltage resistance, heat resistance, radiation resistance, high-speed operation, etc. can be obtained.

  In the semiconductor element, since carriers move between the second and third semiconductor layers via the first semiconductor layer, the degree of freedom in selecting a material for forming the substrate is high. However, for example, in order to limit the charge transfer path and improve stability, it is desirable to use an insulating substrate so that charges do not pass through regions other than the first semiconductor layer. The substrate material can be selected as appropriate from materials capable of forming the first semiconductor layer thereover. Depending on the material, the crystal material may be used when the first semiconductor layer to be a channel region is formed. It may induce the occurrence of defects. For example, when a non-single crystal material such as quartz glass, silicon nitride, and alumina sintered body is used, it is difficult to form a high-quality single crystal film on the first semiconductor layer. Grain boundaries that impede carrier movement occur. Therefore, a single crystal of the same material as the material forming the first semiconductor layer is used as the substrate, and the first semiconductor layer is homoepitaxially grown thereon, or the first semiconductor layer is heteroepitaxially grown. It is preferable to use a substrate capable of this. Thereby, generation | occurrence | production of the crystal defect in a 1st semiconductor layer can be suppressed, and a high quality single crystal film can be formed.

  According to the present invention, the impurity concentration of the second and third semiconductor layers is made higher than that of the first semiconductor layer, and further, between the second and third semiconductor layers in the portion in contact with the first semiconductor layer. The distance is set so that the portion closest to the control layer is shorter than the portion farthest from the control layer in the thickness direction of the first semiconductor layer, or the portion farthest from the substrate than the portion closest to the substrate. Therefore, the carrier controllability in the channel region is improved and the leakage current can be reduced.

  Hereinafter, a semiconductor device according to an embodiment of the present invention will be specifically described with reference to the accompanying drawings. First, a semiconductor element according to the first embodiment of the present invention will be described. FIG. 1 is a cross-sectional view showing the structure of the semiconductor device of this embodiment. In the semiconductor device of this embodiment, a lightly doped diamond layer 4 is locally formed on a substrate 1, and the impurity concentration is higher than that of the lightly doped diamond layer 4 on both sides of the lightly doped diamond layer 4. The high-concentration doped diamond layers 7 a and 7 b are formed in contact with the low-concentration doped diamond layer 4. On the heavily doped diamond layers 7a and 7b, metal electrodes 8a and 8b serving as a source electrode and a drain electrode are formed.

  Further, a silicon oxide insulating layer 9a is formed so as to cover a part of the metal electrode 8a, a part of the high-concentration doped diamond layer 7a, and a part of the low-concentration doped diamond layer 4, and a part of the metal electrode 8b A silicon oxide insulating layer 9b is formed so as to cover a part of the diamond layer 7b and the lightly doped diamond layer 4. Further, an aluminum oxide insulating layer 10 is formed so as to cover the lightly doped diamond layer 4, a part of the metal electrodes 8a and 8b, and the silicon oxide insulating layers 9a and 9b, and above the lightly doped diamond layer 4. A gate electrode 11 made of aluminum is formed on the aluminum oxide insulating layer 10.

  The lightly doped diamond layer 4 in this semiconductor device has a trapezoidal shape in which the shape of the cross section perpendicular to the surface of the substrate 1 is parallel to the direction in which the heavily doped diamond layers 7a and 7b face each other and the upper base is shorter than the lower base. The side surfaces of the lightly doped diamond layer 4 on the side of the heavily doped diamond layers 7 a and 7 b are not perpendicular to the surface of the substrate 1 but are inclined. For this reason, in the semiconductor element of the present embodiment, the distance between the highly doped diamond layers 7 a and 7 b formed on both sides of the lightly doped diamond layer 4 is closer to the substrate 1, that is, closer to the gate electrode 11. It has become shorter. As a result, as compared with the conventional diamond semiconductor element, the influence of the gate voltage can be exerted on the deep portion of the lightly doped diamond layer 4 which is a channel layer, so that the carrier controllability can be improved.

  Further, in the semiconductor element of this embodiment, since the high-concentration doped diamond layers 7a and 7b are formed on both sides of the low-concentration doped diamond layer 4, the high-concentration doped diamond layer 7a or the high-concentration doped diamond layer 7b is used. A high-density charge can be injected into the lightly doped diamond layer 4 having a small amount of defects and impurities that hinder the movement of the charge. As a result, a charge transfer rate in the lightly doped diamond layer 4 can be improved, and a semiconductor element with excellent carrier controllability can be obtained. Furthermore, in the semiconductor element of this embodiment, since the carrier controllability by the gate electrode 11 is excellent, the leakage current can be reduced by adjusting the gate voltage.

  In the semiconductor device of the present embodiment, the distance between the high-concentration doped diamond layers 7 a and 7 b at least in the portion in contact with the low-concentration doped diamond layer 4 is the substrate in the thickness direction of the low-concentration doped diamond layer 4. It is only necessary that the portion farthest from the substrate 1 is shorter than the portion closest to 1. For this reason, for example, the side surface of the lightly doped diamond layer 4 has a stepped shape, or the lightly doped diamond layer 4 is not in contact with the lightly doped diamond layer 4 and the heavily doped diamond layers 7a and 7b. Even if the distance between the diamond layers 7a and 7b is longer in the portion far from the substrate 1 than in the portion close to the substrate 1, the same effect as the semiconductor element of the first embodiment described above can be obtained. .

Next, the operation of the semiconductor element of this embodiment will be described. The semiconductor element of the present embodiment is an FET. For example, by setting the potential of the highly doped diamond layer 7a to 0 and applying a negative potential to the highly doped diamond layer 7b, carriers are transferred from the highly doped diamond layer 7a. It moves to the high-concentration doped diamond layer 7b via the low-concentration doped diamond layer 4, and the drain current _ID flows. Then, by adjusting the gate voltage V _G in this state, it can be changed freely drain current I _D.

  Next, a method for manufacturing the semiconductor element of this embodiment will be described. 2A to 2D, FIGS. 3A to 3D, and FIGS. 4A to 4E are cross-sectional views showing the method of manufacturing the semiconductor device of this embodiment in the order of the steps. First, as shown in FIG. 2A, a resist 2 is patterned by electron beam lithography on a substrate 1 made of, for example, an insulating high-pressure synthetic diamond single crystal containing 10 to 300 ppm of nitrogen as an impurity. As shown in FIG. 2B, aluminum oxide films 3a and 3b having a thickness of, for example, 0.2 μm are formed on the substrate 1 by vapor deposition or the like. Next, as shown in FIG. 2C, the resist 2 and the aluminum oxide film 3b formed thereon are lifted off to form a mask pattern made of the aluminum oxide film 3a.

Thereafter, a B-doped p-type semiconductor diamond thin film having a thickness of, for example, 0.1 μm is formed on the substrate 1 by microwave plasma CVD (Chemical Vapor Deposition) using the aluminum oxide film 3a as an epitaxial mask. Is epitaxially grown. At that time, as the raw material gas, for example, a mixed gas in which CH ₄ is 0.3% by volume and H ₂ is 99.7% by volume and B ₂ H ₆ is added as a doping gas is used. The atomic ratio (B / C) of B and C in the inside is, for example, less than 5 ppm. The total gas flow rate during film formation is, for example, 100 standard cm ³ / min (sccm), the gas pressure is, for example, 6.6 kPa (50 Torr), and the substrate temperature is, for example, 800 ° C. As a result, as shown in FIG. 2 (d), the cross section including the direction perpendicular to the surface of the substrate 1 is selectively formed only on the region where the aluminum oxide film 3a on the surface of the substrate 1 is not formed. Thus, a trapezoidal lightly doped diamond layer 4 having a shorter upper base is formed. In the epitaxial growth method, the speed of crystal growth varies depending on the crystal plane orientation, so that the diamond crystal grows while forming a certain facet (facet plane). Therefore, when the epitaxial growth method is used, an inclined surface can be easily formed at the end of the lightly doped diamond layer 4 by adjusting the growth conditions, the plane orientation of the substrate 1 and the like. Note that the end portion where the inclined surface is formed is determined by the plane orientation, and an end surface perpendicular to the substrate surface is formed at the end portion where the inclined surface is not formed.

  Next, as shown in FIG. 3A, the aluminum oxide film 3a is etched with phosphoric acid. When the lightly doped diamond layer 4 is formed, a diamond film may be slightly formed on the aluminum oxide 3a as a mask. The diamond film on the aluminum oxide 3a is formed by this etching process. At this time, it is removed together with the aluminum oxide film 3a.

  Next, as shown in FIG. 3B, a resist 5 is patterned on the inclined surfaces of the substrate 1 and the lightly doped diamond layer 4. At that time, alignment is performed so that the resist 5 is not formed on the upper surface of the lightly doped diamond layer 4 and the inclined surface in the vicinity thereof. Subsequently, as shown in FIG. 3C, aluminum oxide films 6a and 6b having a thickness of, for example, 0.2 μm are formed on the lightly doped diamond layer 4 and the resist 5 by vapor deposition or the like. Next, as shown in FIG. 3D, the resist 5 and the aluminum oxide film 6a formed thereon are lifted off to form a mask pattern made of the aluminum oxide film 6b.

Next, a B-doped p-type semiconductor diamond thin film having a thickness of, for example, 0.1 μm is epitaxially grown on the substrate 1 by microwave plasma CVD using the aluminum oxide film 6b as a mask. At that time, as the raw material gas, for example, a mixed gas in which CH ₄ is 0.3% by volume and H ₂ is 99.7% by volume and B ₂ H ₆ is added as a doping gas is used. The atomic ratio (B / C) of B and C in the inside is, for example, 5000 ppm. The total gas flow rate during film formation is, for example, 100 standard cm ³ / min (sccm), the gas pressure is, for example, 6.6 kPa (50 Torr), and the substrate temperature is, for example, 800 ° C. As a result, as shown in FIG. 4A, highly doped diamond layers 7a and 7b are formed on the substrate 1 where the aluminum oxide film 6b is not formed, that is, on both sides of the lightly doped diamond layer 4, respectively. Is done.

  Thereafter, as shown in FIG. 4B, the aluminum oxide film 6b is etched with phosphoric acid. When the highly doped diamond layers 7a and 7b are formed, a diamond film may be slightly formed on the aluminum oxide 6b as a mask. The diamond film on the aluminum oxide 6b is etched. In the process, it is removed together with the aluminum oxide film 3a. Then, as shown in FIG. 4 (c), metal electrodes 8a and 8b to be source and drain electrodes are formed on the heavily doped diamond layers 7a and 7b by photolithography and lift-off, respectively. The metal electrodes 8a and 8b are preferably formed of a metal material exhibiting ohmic bonding characteristics such as Pt, Au, Ti and W.

  Next, after a silicon oxide film having a thickness of, for example, 0.2 μm is formed by a CVD method, as shown in FIG. 4D, patterning is performed by electron beam lithography and etching to form one of the metal electrodes 8a and 8b. The silicon oxide insulating layers 9a and 9b are formed so as to cover the portion, the highly doped diamond layers 7a and 7b, and a part of the lightly doped diamond layer 4. Subsequently, after an aluminum oxide film having a thickness of, for example, 50 nm is formed on the lightly doped diamond layer 4, the metal electrodes 8a and 8b, and the silicon oxide insulating layers 9a and 9b by an electron beam evaporation method, FIG. As shown in FIG. 2, the aluminum oxide insulating layer 10 is formed by patterning so that the metal electrodes 8a and 8b are partially exposed. Thereafter, patterning is performed by photolithography to form a gate electrode 11 made of aluminum on the aluminum oxide insulating layer 10 above the lightly doped diamond layer 4 to obtain the semiconductor element shown in FIG.

  In the method for manufacturing a semiconductor device of this embodiment, after the trapezoidal lightly doped diamond layer 4 having a trapezoidal shape in which the cross section including the direction perpendicular to the surface of the substrate 1 is shorter than the lower base is formed by epitaxial growth. Since the high-concentration diamond layers 7a and 7b are formed, the distance between the high-concentration doped diamond layers 7a and 7b can be easily shortened as the distance from the substrate increases. Further, in this method for manufacturing a semiconductor element, since the low-concentration doped diamond layer 4 and the high-concentration doped diamond layers 7a and 7b are formed by epitaxial growth, the generation of defects at these boundary portions can be suppressed.

  In the semiconductor element manufacturing method of this embodiment, B is doped as an impurity when forming the low-concentration doped diamond layer 4 and the high-concentration diamond layers 7a and 7b, but the present invention is not limited to this. For example, aluminum, gallium, indium, nitrogen, phosphorus, arsenic, antimony, oxygen and sulfur may be doped. In the method of manufacturing a semiconductor device according to the present embodiment, when the low-concentration doped diamond layer 4 is formed, the atomic ratio (B / C) of B and C in the source gas is less than 5 ppm, and the high-concentration doped diamond is formed. When forming the layers 7a and 7b, the atomic ratio (B / C) of B and C in the source gas is set to 5000 ppm, so that the space between the lightly doped diamond layer 4 and the heavily doped diamond layers 7a and 7b is increased. A difference in density is provided. Since this density difference contributes to the operating characteristics of the device, it can be set as appropriate according to the intended operation of the target device.

  Furthermore, in the semiconductor device of this embodiment, the aluminum oxide insulating layer 10 is provided as a gate insulating layer between the lightly doped semiconductor layer 4 and the gate electrode 11, but the present invention is limited to this. Instead, the gate insulating layer can be formed of a material such as metal oxide, metal nitride, metal oxynitride, metal fluoride, and nitrogen-doped diamond. Specifically, examples of metal elements contained in metal oxides, metal nitrides, and metal oxynitrides include silicon, aluminum, magnesium, titanium, zirconium, hafnium, scandium, yttrium, lanthanum, vanadium, niobium, and tantalum. Can be mentioned. Among these metal elements, silicon, aluminum, hafnium and zirconium are particularly preferable. Note that the gate insulating layer may be formed using a metal oxide, metal nitride, or metal oxynitride containing these metal elements alone, or a metal oxide or metal nitride containing two or more metals. The metal oxynitride may be used.

  Examples of the metal element contained in the metal fluoride include calcium, barium, magnesium and strontium. Furthermore, since nitrogen-doped diamond has a deep level due to nitrogen, a high-resistance gate insulating layer can be formed by using nitrogen-doped diamond.

  Furthermore, in the semiconductor element of this embodiment, the aluminum oxide insulating layer 10 and the gate electrode 11 are formed on the lightly doped diamond layer 4, but the present invention is not limited to this, and the gate electrode 11 may be electrically connected to the lightly doped diamond layer 4 through the gate insulating layer. Alternatively, the gate electrode and the lightly doped semiconductor layer 4 may be connected via a metal layer instead of the insulating layer. As a result, a Schottky barrier is formed between the lightly doped semiconductor layer 4 and the gate electrode 11, and the first semiconductor layer is formed by the gate voltage in the same manner as in the case where the insulating layer is provided via the Schottky barrier. The electric field inside can be controlled.

  In the first embodiment described above, the FET in which the gate electrode 11 is formed via the aluminum oxide insulating layer 10 and the heavily doped diamond layers 7a and 7b serve as the source and drain has been described. For example, a semiconductor element having a structure shown in FIG. 4C before forming the gate electrode can be used as a diode. Next, a semiconductor element according to a modification of the first embodiment of the present invention will be described. In the semiconductor element of this modification, as shown in FIG. 4C, a lightly doped diamond layer 4 is locally formed on a substrate 1. Further, on both sides of the lightly doped diamond layer 4, heavily doped diamond layers 7 a and 7 b having a higher impurity concentration than the lightly doped diamond layer 4 are formed so as to be in contact with the lightly doped diamond layer 4. Yes. Metal electrodes 8a and 8b are formed on the heavily doped diamond layers 7a and 7b, respectively.

  In the semiconductor element of this modification, the distance between the high-concentration doped diamond layers 7a and 7b formed on both sides of the low-concentration doped diamond layer 4 decreases as the distance from the substrate 1 increases. The electric field strength at 4 is the lowest at the part closest to the substrate 1 and the highest at the part farthest from the substrate 1. Thereby, carrier controllability in the channel region is improved as compared with the conventional diamond semiconductor element. In the semiconductor device of this embodiment, since the highly doped diamond layers 7a and 7b are formed so as to sandwich the lightly doped diamond layer 4, the highly doped diamond layer 7a or the highly doped diamond layer 7b is formed. Therefore, a high-density charge can be injected. As a result, a charge transfer rate in the lightly doped diamond layer 4 can be improved, and a semiconductor element excellent in carrier controllability due to the surface state of the lightly doped diamond layer 4 can be obtained. Furthermore, in the semiconductor element of this embodiment, the portion between the heavily doped diamond layers 7a and 7b is long near the substrate 1, so that the leakage current of the substrate 1 can be reduced.

  Next, the operation of the semiconductor element of this modification will be described. This semiconductor element is a diode. For example, the potential of the heavily doped diamond layer 7a is set to 0 and a negative potential is applied to the highly doped diamond layer 7b, so that carriers are doped from the highly doped diamond layer 7a to the lightly doped layer. The highly doped diamond layer 7b is moved through the diamond layer 4. Thereby, a current flows between the heavily doped diamond layers 7a and 7b.

  Further, in this semiconductor element, carriers are controlled in accordance with a change in the surface state of the low-concentration doped diamond layer 4 due to adsorption of a substance and incidence of light. That is, when gas, moisture, ions, etc. are adsorbed on the surface of the lightly doped diamond layer 4 or light such as ultraviolet rays is irradiated, the electric field or the number of carriers in the lightly doped diamond layer 4 changes. The value of the current flowing between the heavily doped diamond layers 7a and 7b changes. By utilizing this characteristic, the semiconductor element of this modification can also be used as a sensor for detecting the amount of adsorbed substance and the amount of ultraviolet irradiation. Furthermore, this semiconductor element can also be used as a light emitting diode by appropriately selecting a semiconductor material.

  In the semiconductor device of the first embodiment and the modification thereof, the semiconductor layer is formed of diamond. However, the present invention is not limited to this, for example, silicon, germanium, gallium arsenide. Alternatively, a semiconductor material such as gallium nitride, indium phosphide, indium arsenide, or silicon carbide may be used. Even when a material other than diamond is used, a trapezoidal semiconductor layer whose cross section including the direction perpendicular to the substrate surface is shorter than the lower base can be formed by using the epitaxial method. .

  Next, the semiconductor element of the 2nd Embodiment of this invention is demonstrated. FIG. 5 is a cross-sectional view showing the structure of the semiconductor device of this embodiment. As shown in FIG. 5, in the semiconductor element of the present embodiment, a lightly doped diamond layer 22 is formed on a substrate 21, and the surface of the lightly doped diamond layer 22 is less than the lightly doped diamond layer 22. Highly doped diamond layers 29a and 29b having a high impurity concentration are formed separately from each other. The heavily doped diamond layers 29a and 29b have a lower impurity concentration in a portion far from the surface than a portion near the surface. That is, the high-concentration doped diamond layers 29a and 29b are respectively formed with high-concentration regions 24a and 24b on the surface side and low-concentration regions 23a and 23b on the substrate 21 side. Further, the distance between the high-concentration doped diamond layers 29a and 29b is longer between the low-concentration regions 23a and 23b than between the high-concentration regions 24a and 24b.

  On the heavily doped diamond layers 29a and 29a, metal electrodes 25a and 25b to be a source electrode and a drain electrode are formed. Furthermore, a silicon oxide insulating layer 26a is formed so as to cover a part of the metal electrode 25a, a part of the highly doped diamond layer 29a and a part of the lightly doped diamond layer 22, and a part of the metal electrode 25b, a highly doped element. A silicon oxide insulating layer 26 b is formed so as to cover a part of the diamond layer 29 b and the lightly doped diamond layer 22. Further thereon, an aluminum oxide insulating layer 27 is formed so as to cover the lightly doped diamond layer 22, a part of the metal electrodes 25a and 25b, and the silicon oxide insulating layers 26a and 26b. A gate electrode 28 made of aluminum is formed on the portion of the layer 22 between the heavily doped diamond layers 29a and 29b, that is, on the aluminum oxide insulating layer 27 above the channel region.

  In the semiconductor element of the present embodiment, the distance between the heavily doped diamond layers 29a and 29b formed on both sides of the channel region decreases as the distance from the substrate 21 increases, that is, as the distance from the gate electrode 28 increases. The electric field intensity in the channel region is lower in the portion farthest from the gate electrode 28 than in the portion closest to the gate electrode 28, and carrier controllability can be improved as compared with the conventional diamond semiconductor element. In the semiconductor device of this embodiment, since the carrier controllability by the gate electrode 28 is excellent, the leakage current can be reduced by adjusting the gate voltage.

Next, the operation of the semiconductor element of this embodiment will be described. The semiconductor element of the present embodiment is a transistor. For example, the potential of the highly doped diamond layer 29a is set to 0 and a negative potential is applied to the highly doped diamond layer 29b, whereby carriers are transferred from the highly doped diamond layer 29a. It moves to the high-concentration doped diamond layer 29b via the low-concentration doped diamond layer 22, and the drain current _ID flows. Then, by adjusting the gate voltage V _G in this state, it can be changed freely drain current I _D.

Next, a method for manufacturing the semiconductor element of this embodiment will be described. 6A to 6D and FIGS. 7A to 7C are cross-sectional views showing the method of manufacturing the semiconductor device of this embodiment in the order of the steps. First, as shown in FIG. 6A, a thickness of, for example, 0 is formed on a substrate 21 made of insulating high-pressure synthetic diamond single crystal containing 10 to 300 ppm of nitrogen as an impurity by a microwave plasma CVD method. A .5 μm B-doped p-type semiconductor diamond thin film is synthesized to form a lightly doped diamond layer 22. At that time, as the raw material gas, for example, a mixed gas in which CH ₄ is 0.3% by volume and H ₂ is 99.7% by volume and B ₂ H ₆ is added as a doping gas is used. The atomic ratio (B / C) of B and C in the inside is, for example, less than 5 ppm. The total gas flow rate during film formation is, for example, 100 standard cm ³ / min (sccm), the gas pressure is, for example, 6.6 kPa (50 Torr), and the substrate temperature is, for example, 800 ° C.

Next, as shown in FIG. 6B, a resist 30 is patterned on the lightly doped diamond layer 22 by lithography. Then, using the resist 30 as a mask, for example, B ⁺ ions are irradiated under the conditions of an acceleration voltage of 30 kV and an ion dose (number of ions per unit area) of 2 × 10 ¹⁶ / cm ² . As a result, as shown in FIG. 6C, B ⁺ ions are implanted only in the region where the resist 23 is not formed on the surface of the lightly doped diamond layer 22 and separated from each other on the surface of the lightly doped diamond layer 22. The high concentration regions 24a and 24b thus formed are formed. Subsequently, using the resist 30 as a mask, for example, B ⁺ ions are irradiated under the conditions of an acceleration voltage of 60 kV and an ion dose of 1 × 10 ¹⁶ / cm ² , and as shown in FIG. Low-concentration regions 23a and 23b having a B ⁺ ion concentration lower than that of the high-concentration regions 24a and 24b are formed in the portion closer to the substrate 21 than 24b, and the high-concentration doped diamond layers 29a and 29b are formed. At this time, since although B ⁺ ions are also implanted into the lower portion of the resist 30 is a mask, the amount of the B ⁺ ions spreads laterally to increase or decrease in correlation with the B ⁺ ion implantation dose, the high concentration region 24a The distance between the low concentration regions 23a and 23b is longer than the distance between the low concentration regions 23b and 24b.

Thereafter, the substrate 21 on which the low-concentration doped diamond layer 22 and the high-concentration doped diamond layers 29a and 29b are formed is heat-treated in a vacuum at, for example, about 1000 ° C. to be injected into the high-concentration doped diamond layers 29a and 29b. Activates B ⁺ ions. Thereby, the B ⁺ ion acts as an acceptor. Note that the carrier concentration estimated by hole measurement in this semiconductor element is 1 × 10 ¹⁹ / cm ³ or more. Immediately after the implantation of B ⁺ ions, defects are generated at the boundary between the low-concentration doped diamond layer 22 and the high-concentration doped diamond layers 29a and 29b. However, heat treatment for activating the B ⁺ ions is performed. This defect is eliminated.

  Next, after removing the carbonized layer formed on the surfaces of the highly doped diamond layers 29a and 29b by heat treatment, as shown in FIG. 7A, photolithography is performed on the highly doped diamond layers 29a and 29b. The metal electrodes 25a and 25b are formed respectively. The metal electrodes 25a and 25b can be formed of a metal material having ohmic bonding characteristics such as Pt, Au, Ti, and W, for example.

  Next, after a silicon oxide film having a thickness of, for example, 0.2 μm is formed by a CVD method, as shown in FIG. 7B, patterning is performed by electron beam lithography and etching to form one of the metal electrodes 25a and 25b. The silicon oxide insulating layers 26a and 26b are formed so as to cover the portion, the heavily doped diamond layers 29a and 29b, and a part of the lightly doped diamond layer 22. Subsequently, after an aluminum oxide film having a thickness of, for example, 50 nm is formed on the lightly doped diamond layer 22, the metal electrodes 25a and 25b, and the silicon oxide insulating layers 26a and 26b by an electron beam evaporation method, FIG. As shown in FIG. 2, the aluminum oxide insulating layer 27 is formed by patterning so that the metal electrodes 25a and 25b are partially exposed. Thereafter, patterning is performed by photolithography to form a gate electrode 28 made of aluminum on the aluminum oxide insulating layer 27 above the channel region in the lightly doped diamond layer 22 to obtain the semiconductor device shown in FIG.

In the manufacturing method of the semiconductor device of this embodiment, since the high-concentration doped diamond layers 29a and 29b are formed on the surface of the low-concentration doped diamond layer 22 by the ion implantation method, the low-concentration doping without ion implantation is performed. A gentle concentration distribution is generated between the diamond layer 22 and the ion-implanted heavily doped diamond layers 29a and 29b. Further, when the highly doped diamond layers 29a and 29b are formed, ion implantation is performed twice under different conditions. Therefore, the heavily doped diamond layers 29a and 29b have high concentration regions 24a and 24b on the surface side, and a substrate 21. Low concentration regions 23a and 23b are respectively formed on the side. FIG. 8 is a graph showing the concentration distribution of the highly doped diamond layer, with the horizontal axis representing the distance from the surface and the vertical axis representing the B ⁺ ion concentration. For this reason, as shown in FIG. 8, the impurity concentration in the heavily doped diamond layers 29a and 29 decreases as the distance from the surface increases. Similarly, since the amount of impurities implanted into the lower portion of the resist 30 also decreases as the distance from the surface increases, a semiconductor element in which the distance between the heavily doped diamond layers 29a and 29b decreases as the distance from the substrate 21 decreases. be able to.

  In the above-described second embodiment, the FET in which the gate electrode 28 is formed via the aluminum oxide insulating layer 27 and the heavily doped diamond layers 24a and 24b serve as the source and drain has been described. For example, the semiconductor element having the structure shown in FIG. 7A before forming the gate electrode can be used as the diode. Next, a modification of the second embodiment of the present invention will be described. As shown in FIG. 7A, the semiconductor element of the present modification has a high concentration doping with a higher impurity concentration than the low concentration doping diamond layer 22 on the surface of the low concentration doping diamond layer 22 formed on the substrate 21. Diamond layers 29a and 29b are formed separately from each other. In the high-concentration doped diamond layers 29a and 29b, high-concentration regions 24a and 24b are formed on the surface side, and low-concentration regions 23a and 23b are formed on the substrate 21, respectively. The distance between 29b is longer between the low concentration regions 23a and 23b than between the high concentration regions 24a and 24b. Further, metal electrodes 8a and 8b are formed on the heavily doped diamond layers 29a and 29b, respectively.

  In this semiconductor device, since the distance between the highly doped diamond layers 29a and 29b becomes shorter as the distance from the substrate 1 increases, the electric field strength at the surface of the lightly doped diamond layer 22, that is, in the channel region, is applied to the substrate 21. The closest part is the lowest and the part farthest from the substrate 21 is the highest. As a result, since the carrier is sensitively controlled in accordance with the surface state of the lightly doped diamond layer 22, the carrier controllability is improved as compared with the conventional diamond semiconductor element. Furthermore, in the semiconductor element of this modification, the leakage current can be reduced because the distance between the low concentration regions 23a and 23b is longer than the distance between the high concentration regions 24a and 24b.

  Next, the operation of the semiconductor element of this modification will be described. The semiconductor element of the present embodiment is a diode. For example, the potential of the highly doped diamond layer 29a is set to 0, and a negative potential is applied to the highly doped diamond layer 29b, so that carriers can be generated from the highly doped diamond layer 29a. It moves to the high-concentration doped diamond layer 29b via the low-concentration doped diamond layer 22, thereby causing a current to flow. This current varies depending on the surface state of the low-concentration diamond layer 22. For this reason, the semiconductor element of this modification can be used as a sensor for detecting the surface state, similarly to the modification of the first embodiment described above. Further, it can also be used for a light emitting diode or the like, similar to the semiconductor element of the modified example of the first embodiment described above.

  In the semiconductor device of the second embodiment and its modification, the semiconductor layer is formed of diamond. However, the present invention is not limited to this, for example, silicon, germanium, gallium arsenide. Alternatively, it can be formed of a semiconductor material such as gallium nitride, indium phosphide, indium arsenide, or silicon carbide.

Next, effects of the embodiment of the present invention will be described in comparison with a comparative example that is out of the scope of the present invention. First, as an example of the present invention, device characteristics of a transistor having the same structure as the semiconductor element of the first embodiment described above were simulated by a device simulator MEDICI. FIG. 9A is a diagram showing the structure of the transistor of the example used in the simulation, and FIG. 9B is a diagram showing the hole concentration distribution of the transistor shown in FIG. 9A. In the simulation, the structure of the transistor was schematically shown as shown in FIG. Specifically, highly doped diamond layers 32 and 33 are formed on both sides of a lightly doped diamond layer 31 formed on the substrate 30, and an insulating layer 34 is formed thereon, and the lightly doped diamond layer 31. A gate electrode 35 is formed on 31 via an insulating layer 34. The distance between the heavily doped diamond layers 42 and 33 in this transistor decreases as the distance from the substrate 30 increases. With respect to the transistor of the embodiment having such a structure, the hole concentration distribution was calculated when a voltage of −10 V was applied to the gate electrode 35 and a voltage of −20 V was applied to the drain electrode. As shown in FIG. 3, the hole region 36 having a hole concentration of 1 × 10 ^{15 to} 1 × 10 ¹⁸ is almost present in the low-concentration doped diamond layer 31, and the distribution of holes is narrow near the surface on the gate electrode 35 side. The carrier controllability was excellent due to the gate voltage.

As a comparative example, the device characteristics were similarly simulated for a transistor having a structure in which the distance between the heavily doped diamond layers becomes longer as the distance from the substrate increases. FIG. 10A is a diagram illustrating the structure of a comparative transistor used in the simulation, and FIG. 10B is a diagram illustrating the hole concentration distribution of the transistor illustrated in FIG. As shown in FIG. 10A, in this comparative example, heavily doped diamond layers 42 and 43 are formed on both sides of a lightly doped diamond layer 41 formed on a substrate 40, and an insulating layer is formed thereon. A layer 44 is formed, and a gate electrode 45 is formed on the lightly doped diamond layer 41 with an insulating layer 44 interposed therebetween. The distance between the heavily doped diamond layers 42 and 43 in this transistor increases as the distance from the substrate 40 increases. Note that a transistor having such a structure can be manufactured by forming a heavily doped diamond layer by epitaxial growth before forming the lightly doped diamond layer. With respect to the transistor of this comparative example, when the voltage of −10 V was applied to the gate electrode 45 and the voltage of −20 V was applied to the drain electrode, the hole concentration distribution was calculated, as shown in FIG. The hole region 46 having a hole concentration of 1 × 10 ^{15 to} 1 × 10 ¹⁸ exists up to the substrate 40, and the distribution of holes is wider than that of the transistor of the above-described embodiment, and is further disturbed. It was.

  Next, for the transistors of this example and the comparative example, the voltage applied to the gate electrodes 35 and 45 (gate voltage) with the source electrode being grounded and a constant voltage (drain voltage: −20 V) applied to the drain electrode. ) Were changed, and the Poisson equation and the equation of current continuity were calculated. FIG. 10 is a graph showing the simulation results of the transistors of the example and the comparative example, with the gate voltage on the horizontal axis and the drain current on the vertical axis. In the transistor off state, that is, when the voltage applied to the gate electrode is 0 V, the current is a leakage current. However, as shown in FIG. Was kept low.

It is sectional drawing which shows the structure of the semiconductor element of the 1st Embodiment of this invention. (A) thru | or (d) It is sectional drawing which shows the manufacturing method of the semiconductor element of the 1st Embodiment of this invention in the order of the process. (A) thru | or (d) It is sectional drawing which shows the manufacturing method of the semiconductor element of the 1st Embodiment of this invention in order of the process, and shows the process following FIG.2 (d). (A) thru | or (e) It is sectional drawing which shows the manufacturing method of the semiconductor element of the 1st Embodiment of this invention in order of the process, and shows the process following FIG.3 (d). It is sectional drawing which shows the structure of the semiconductor element of the 2nd Embodiment of this invention. (A) thru | or (d) are sectional drawings which show the manufacturing method of the semiconductor element of the 2nd Embodiment of this invention in the order of the process. (A) thru | or (c) are sectional drawings which show the manufacturing method of the semiconductor element of the 2nd Embodiment of this invention in order of the process, and show the process following FIG.6 (d). It is a graph which shows the density | concentration distribution of a high concentration dope diamond layer, taking the distance from the surface on a horizontal axis, and taking B ⁺ ion concentration on the vertical axis | shaft. (A) is a figure which shows the structure of the transistor of the Example used by simulation, (b) is a figure which shows the hole concentration distribution of the transistor shown to (a). (A) is a figure which shows the structure of the transistor of the comparative example used by simulation, (b) is a figure which shows the hole concentration distribution of the transistor shown to (a). It is a graph which shows the simulation result of the transistor of an Example and a comparative example by taking a gate voltage on a horizontal axis and taking a drain current on a vertical axis | shaft. 6 is a cross-sectional view showing the structure of a MISFET described in Patent Document 1. FIG. It is sectional drawing which shows the structure of MISFET of patent document 2. As shown in FIG. It is a schematic diagram which shows the operation principle of the diamond FET described in Patent Document 3.

Explanation of symbols

1, 2, 30, 30; substrate 2, 5, 30; resist 3a, 3b, 6a, 6b; aluminum oxide film 4, 22, 31, 41; lightly doped diamond layer 7a, 7b, 29a, 29b, 32; 33, 42, 43; highly doped diamond layers 8a, 8b, 25a, 25b; metal electrodes 9a, 9b, 26a, 26b; silicon oxide insulating layers 10, 27; aluminum oxide insulating layers 11, 28, 35, 45, 107 118, 125; gate electrodes 23a, 23b; low concentration regions 24a, 24b; high concentration regions 34; insulating layers 36, 46; hole regions 100, 110;
101; Insulating diamond substrate 102a, 102b; Highly doped p-type semiconductor diamond layer 103; Low-doped p-type semiconductor diamond layer 104, 115, 124; Source electrode 105, 116, 126; Drain electrode 106; Undoped diamond layer 111; Silicon Substrate 112; base layer 113a, 113b; n-type semiconductor diamond layer 114; p-type semiconductor diamond layer 117; diamond insulator layer 120; FET
121, 123; semiconductor diamond layer 122; high resistance diamond layer

Claims (14)

A substrate, a first semiconductor layer locally formed on the substrate, and formed on both sides of the first semiconductor layer, at least part of which is in contact with the first semiconductor layer; A second and third semiconductor layer having an impurity concentration higher than that of the semiconductor layer; and a control layer for controlling a current flowing between the second and third semiconductor layers, and in contact with the first semiconductor layer. The distance between the second semiconductor layer and the third semiconductor layer in the portion where the first semiconductor layer is located is shorter in the portion closest to the control layer than in the portion farthest from the control layer in the thickness direction of the first semiconductor layer. A featured semiconductor element. The control layer is a gate electrode electrically connected to the first semiconductor layer via an insulating layer or a Schottky barrier, and the second and third semiconductor layers serve as a source and a drain, respectively. The semiconductor device according to claim 1, wherein: A substrate, a first semiconductor layer locally formed on the substrate, and formed on both sides of the first semiconductor layer, at least part of which is in contact with the first semiconductor layer; A second semiconductor layer having a higher impurity concentration than the semiconductor layer, and a distance between the second semiconductor layer and the third semiconductor layer in a portion in contact with the first semiconductor layer is A semiconductor element characterized in that a portion farthest from the substrate is shorter than a portion closest to the substrate in the thickness direction of one semiconductor layer. A gate electrode is formed on the first semiconductor layer via an insulating layer or a Schottky barrier, and the second and third semiconductor layers are field effect transistors respectively serving as a source and a drain. The semiconductor device according to claim 3, wherein: The semiconductor device according to claim 3, wherein the semiconductor device is used as a sensor or a diode. 5. The insulating layer according to claim 2, wherein the insulating layer is made of at least one material selected from the group consisting of metal oxide, metal nitride, metal oxynitride, metal fluoride, and nitrogen-doped diamond. The semiconductor element as described. 7. The semiconductor device according to claim 1, wherein at least one of the first to third semiconductor layers is formed of diamond. A step of locally forming a first semiconductor layer on a substrate; and at least a part of the first semiconductor layer on both sides of the first semiconductor layer is in contact with the first semiconductor layer and has an impurity concentration higher than that of the first semiconductor layer. A step of forming high second and third semiconductor layers, respectively, and a step of forming a control layer for controlling a current flowing between the second and third semiconductor layers, wherein the first semiconductor layer includes: The distance between the second and third semiconductor layers in the contacting portion is shorter in the portion closest to the control layer than in the portion farthest from the control layer in the thickness direction of the first semiconductor layer. A method for manufacturing a semiconductor element, characterized by comprising: A step of locally forming a first semiconductor layer on a substrate; and at least a part of the first semiconductor layer on both sides of the first semiconductor layer is in contact with the first semiconductor layer and has an impurity concentration higher than that of the first semiconductor layer. Forming high second and third semiconductor layers, respectively, and the distance between the second and third semiconductor layers in a portion in contact with the first semiconductor layer is set to the first semiconductor layer. A method of manufacturing a semiconductor element, wherein a portion farthest from the substrate is shorter than a portion closest to the substrate in a thickness direction of the semiconductor layer. 10. The method of manufacturing a semiconductor element according to claim 8, wherein the first semiconductor layer is formed by epitaxial growth. 11. The method of manufacturing a semiconductor device according to claim 8, wherein the second and third semiconductor layers are formed by epitaxial growth. 12. The method of manufacturing a semiconductor device according to claim 11, wherein when the second and third semiconductor layers are formed by epitaxial growth, the second and third semiconductor layers are doped with impurities at a high concentration. . 12. The method of manufacturing a semiconductor device according to claim 8, wherein an impurity is doped in the second and third semiconductor layers at a high concentration by an ion implantation method. 14. The method of manufacturing a semiconductor element according to claim 8, wherein at least one semiconductor layer of the first to third semiconductor layers is formed of diamond.

Images