JP4857697B2 - Silicon carbide semiconductor device - Google Patents

Description

  The present invention relates to a silicon carbide semiconductor device using silicon carbide (SiC), and more particularly to a MOS silicon carbide semiconductor device (MOSFET) having a gate electrode having a MOS (metal-oxide semiconductor) structure.

  In recent years, a field effect transistor (FET) has been proposed in which a gate electrode is provided between a source electrode into which a current flows and a drain electrode from which the current flows out, and the current between the source and the drain (drain current) is controlled by the voltage applied to the gate electrode. Are proposed, and there are a MOS type (MOSFET) having a MOS structure at the gate and a junction type using a pn junction or a Schottky junction.

  In a MOSFET provided with a gate electrode having a MOS structure, the conductivity of a channel region through which a drain current flows is controlled by utilizing the fact that an inversion layer is formed by a small number of carriers on the semiconductor surface. When the gate voltage is changed, the current value changes, so that it can function as an electric signal amplification or current on / off switch.

As described above, as a semiconductor device having a MOS structure at the gate, there is a vertical silicon carbide semiconductor device (MOSFET) using a semiconductor made of silicon carbide (see, for example, Patent Document 1). Also disclosed is a method for manufacturing a semiconductor device in which a SiGeC layer having stable crystallinity is formed by introducing Ge into the SiC layer (see, for example, Patent Document 2).
Japanese Patent No. 3307184 Japanese Patent Laid-Open No. 11-312686

  However, silicon carbide (SiC) is expected as a high-power semiconductor, but generally has a low carrier mobility, that is, electrons do not easily flow and has a high on-resistance when used as an element, resulting in a large loss. Therefore, when the channel region is composed of SiC, it is essential to improve the mobility of carriers such as electrons in order to further improve the device characteristics.

  In addition, an example in which Ge is introduced into SiC as described above has been disclosed. Although SiGeC into which Ge is introduced has good crystallinity, it does not have a carrier supply function itself, but from outside the SiGeC crystal. Although it is expected that the mobility will be improved to some extent in terms of structure, it is not sufficient in terms of higher output and higher current.

  The present invention has been made in view of the above, and an object thereof is to provide a silicon carbide semiconductor device having high carrier mobility in a channel formation region using silicon carbide, low on-resistance, and excellent element characteristics. An object is to achieve the object.

In order to achieve the above object, a silicon carbide semiconductor device according to a first aspect of the present invention includes a gate electrode, a gate oxide film, a source electrode, and a drain electrode, and a channel region forming portion is n-type by doping impurities. or together constituted the p-type semiconductor, in which Ge is configured such that the Si _1-x Ge x C mixed crystal doped [0 <x <1] to SiC crystal.

  A silicon carbide semiconductor device according to a first aspect of the present invention is configured in a MOS type in which a gate electrode is provided in a MOS structure together with a source electrode and a drain electrode.

In the first invention, the site where the channel region is formed is Ge (germanium) having a larger ionic radius and narrower forbidden band than Si or C (preferably hexagonal) SiC crystal (silicon carbide). By using the Si _1-x Ge _x C mixed crystal having a high mobility obtained by doping the channel, the lattice constant of the channel region is increased, and the lattice of the electrons moving through the crystal is increased. Since the influence of the received scattering probability is suppressed, the mobility of carriers such as electrons in the channel region can be effectively improved. Thereby, element characteristics can be improved drastically.

  In addition to improving the mobility of the channel region, doping with impurities such as phosphorus (P) and N (nitrogen) separately from Ge doping so as to constitute an n-type or p-type semiconductor, Since electrons for carriers can be supplied in the mobility crystal, the effect of improving the mobility of the channel region is great, and device characteristics with lower on-resistance can be obtained.

A silicon carbide semiconductor device according to a second aspect of the present invention includes a SiC crystal (silicon carbide) comprising a gate electrode, a gate oxide film, a source electrode, and a drain electrode, and configured as an n-type or p-type semiconductor by doping impurities. ) and the channel region forming portion consisting of, disposed over and adjacent to the channel region forming portion, said by doping impurity channel region forming portion opposite type (e.g., p-type when the channel region forming portion is n-type) A Si _1-x Ge _x C mixed crystal in which a SiC crystal (silicon carbide) (preferably hexagonal) is doped with Ge (germanium) having a larger ionic radius than Si or C is formed. And a strain supply layer composed of 0 <x <1].

  The silicon carbide semiconductor device according to the second invention is also configured in a MOS type in which a gate electrode is provided in a MOS structure together with a source electrode and a drain electrode.

In the second invention, the electron carrier adjacent the top of the channel region forming portion for supplying the strain supply layer made of the same Si _1-x Ge _x C mixed crystal [0 <x <1] By providing the strain, the size of the crystal lattice of the strain supply layer acts and strain is applied to the channel region forming portion, so that there is an effect of widening the crystal lattice of the channel region (lattice constant increases). Therefore, the influence of the scattering probability received from the lattice when electrons move in the crystal can be suppressed, and the mobility can be improved effectively.

That is, since the Si _1-x Ge _x C mixed crystal in which the SiC crystal is doped with Ge has a larger lattice constant than the SiC crystal, the lattice constant of the adjacent channel region is also Si _1-x Ge _x C. It grows under the stress of mixed crystals. As a result, the probability of electron scattering can be suppressed and the mobility can be improved. Thereby, element characteristics can be improved drastically.

In the second invention, as compared with the first invention in which the channel region forming portion is composed of Si _1-x Ge _x C mixed crystal as described above, the influence of alloy scattering due to Ge doping becomes smaller, so that the device characteristics Can be further improved.

As the SiC crystal of Si _1-x Ge _x C mixed crystal in which Ge is doped in the SiC crystal, 4H—SiC crystal or 6H—SiC crystal is effective, and 4H—SiC crystal is particularly effective.

Further, the concentration of Ge in the Si _1-x Ge _x C mixed crystal is particularly effective when x satisfies 0 <x <0.2.

  According to the present invention, it is possible to provide a silicon carbide semiconductor device having high carrier mobility in a channel formation region using silicon carbide, low on-resistance, and excellent element characteristics.

Hereinafter, an embodiment of a silicon carbide semiconductor device of the present invention will be described in detail with reference to the drawings.
(First embodiment)
A silicon carbide semiconductor device according to a first embodiment of the present invention will be described with reference to FIGS. In the silicon carbide semiconductor device of the present embodiment, the gate electrode is configured as a MOS structure, and as a channel layer forming a channel region, Ge is formed on a hexagonal SiC crystal by vapor phase growth using Si _0.9 Ge _0.1 C (x = 0.1) a layer made of a SiGeC mixed crystal doped so as to have a composition, and a longitudinal section that cuts through the device from the source side toward the drain formed on the surface opposite to the source formation surface. This is a vertical MOS field effect transistor (MOSFET) in which electrons flow in the direction.

As shown in FIG. 1, the MOSFET of this embodiment has an SiC buffer layer having a thickness of 1 μm sequentially on an N-type 4H—SiC substrate (N ⁺ ; nitrogen-doped, carrier concentration 3 × 10 ¹⁸ cm ⁻³ ) 11. (N ⁺ ; nitrogen dope, carrier concentration 3 × 10 ¹⁸ cm ⁻³ ) 12 and SiC drift layer (N ⁻ ; nitrogen dope, carrier concentration 5 × 10 ¹⁵ cm ⁻³ ) 13 having a thickness of 10 μm are laminated. On the side of the SiC drift layer 13 that is not in contact with the SiC buffer layer 12, a concave groove 19 for forming a MOS structure is formed.

On the SiC drift layer 13, a SiGeC channel layer (P ⁻ ; Al-doped, carrier concentration 5 × 10 ¹⁶ cm ⁻³ ) 14 having a thickness of 2.0 μm is laminated. This SiGeC channel layer 14 is a layer obtained by doping Si _0.9 Ge _0.1 C (x = 0.1) mixed crystal (SiGeC mixed crystal) obtained by doping Ge into hexagonal SiC by vapor deposition using Al as an impurity. This layer itself can supply electrons for carriers. The thickness of the SiGeC channel layer can be selected in the range of 0.2 to 2.0 μm.

As described above, the SiGeC channel layer 14 serving as the channel region is formed of a low on-resistance crystal layer having a crystal lattice spread using a Si _0.9 Ge _0.1 C (x = 0.1) mixed crystal, Carrier mobility is high. Since it is configured to supply electrons in a channel layer made of a SiGeC mixed crystal with high carrier mobility, the effect of reducing element loss due to the scattering probability of electrons is great, and high element characteristics can be obtained. It has become.

  In the present embodiment, the composition of the SiGeC mixed crystal is shown in the case where the Ge / (Ge + Si) ratio (x) is 0.1. However, the Ge ratio may be arbitrarily selected within the range of 0 <x <1. Within this range, similarly to the above, element loss due to the electron scattering probability in the channel region can be kept low, and a channel region with high carrier mobility can be formed. Thereby, high device characteristics can be obtained. In particular, considering the crystal quality and mobility characteristics, the Ge ratio is preferably in the range of 0 <x ≦ 0.5, more preferably in the range of 0 <x ≦ 0.2, and 0.05 ≦ x ≦ 0. A range of 15 is more preferred.

  The SiGeC channel layer 14 is formed by doping Ge into a hexagonal SiC crystal by an ordinary method using a vapor phase growth method. In the vapor phase growth method, SiC in the crystal can be replaced with SiGeC, so that a mixed crystal having a steep interface between SiC and SiGeC can be obtained instead of a mixed crystal whose component composition changes in a broad shape. This is preferable in that the layer structure can be freely controlled. Since a steep structure can be obtained, scattering of electrons and the like accompanying fluctuations at the interface of the channel layer can be avoided, and mobility is improved.

In the case of forming by vapor phase growth, for example, hydrogen gas is used as an introduction carrier gas, and an organic metal (for example, tetraethylgermanium) is used for vapor phase SiC formed by flowing SiH ₄ and propane (C ₃ H ₈ ) gas. This can be done by introducing gas or gas raw material (GeH ₄ ) and partially depositing and growing SiGeC. In this case, the pressure, temperature, flow rate and supply amount of each component, and supply ratio can be selected as desired. It can be controlled to a mixed crystal.

  The SiGeC channel layer 14 is formed using a known method such as a liquid phase growth method, an epitaxial growth method, or an ion implantation method in which source molecules are ionized and accelerated and implanted into the crystal, in addition to the vapor phase growth method. be able to. In the present invention, the vapor phase growth method is particularly preferable in that a steep interface structure in which the component composition does not change broadly is obtained and the mobility is improved.

  As silicon carbide used for forming the SiGeC mixed crystal, various silicon carbides can be selected, but hexagonal SiC crystal is preferable, and 6H-SiC crystal is preferable in addition to the 4H-SiC crystal. . The 4H—SiC crystal is preferable in that it has a high carrier mobility and has a smaller stacking fault density than the 6H—SiC crystal grown in the same direction. Even when a 6H—SiC crystal is used, a SiGeC channel layer can be formed in the same manner as described above.

  The thickness of the SiGeC channel layer is not particularly limited, but is preferably 0.1 to 4.0 μm in terms of the breakdown voltage between the source and drain and the suppression of defects due to lattice irregularities, and preferably 0.1 to 2 μm. 0.0 μm is more preferable.

On the surface of the SiGeC channel layer 14, a 0.5 μm thick SiC contact layer (N ⁺ ; nitrogen-doped, carrier concentration of 3 × 10 ¹⁸ cm ⁻³ or more) 15 is laminated. A source electrode 16 made of Ni is formed in the region. The source electrode may be composed of a Ti layer / Al layer formed by laminating Ti and Al.

Further, as shown in FIG. 1, the region where the source electrode is not formed on the SiC contact layer 15, the surface of the SiC drift layer 13 in the groove 19, and the SiGeC channel layer 14 and the SiC above the groove of the SiC drift layer 13. A gate oxide film 18 made of SiO ₂ having a thickness of ₂₀ to 100 nm is formed so as to cover the wall surface formed by the lamination of the contact layer 15.

  Then, on the gate oxide film 18 in the groove portion 19, a Ti layer / Al layer (here, the Ti layer / Al layer includes a Ti layer having a thickness of 0.03 to 0.05 μm and an Al layer having a thickness of 1 to 4 μm). The same applies to the following.), And a MOS structure is formed. The gate electrode 17 is not in contact with the source electrode 16, the SiGeC channel layer 14, and the SiC contact layer 15 by the gate oxide film 18.

  A drain electrode 20 made of Ni is formed on the surface of the 4H-SiC substrate 11 where the SiC buffer layer 12 is not provided, and the source electrode 16 to the drain electrode 20 are controlled by voltage control of the gate electrode 17. Electrons flow in a direction (longitudinal direction) longitudinally traversing the inside of the device. At this time, current flows from the drain electrode to the source electrode.

  Next, a method for manufacturing the silicon carbide semiconductor device of the present invention will be described with reference to FIGS. 2 to 3, taking as an example the case where the vertical MOSFET of the present embodiment is manufactured.

-1) Formation of each layer on the substrate
An SiC substrate (N ⁺ ; 4H—SiC (0001) 8 ° off toward [11-20], nitrogen-doped, carrier concentration 3 × 10 ¹⁸ cm ⁻³ ) is prepared, and the SiC substrate is 1400 to 2000 ° C. (more preferably 1500-1700), CVD method [carrier gas: hydrogen (H ₂ ), source gas: monosilane (SiH ₄ ) and propane (C ₃ H ₈ ), N-type conductive source: nitrogen (N ₂ ) As shown in FIG. 2A, an SiC buffer layer (N ⁺ ; nitrogen-doped, carrier concentration 3 × 10 ¹⁸ cm ⁻³ ) 12 having a thickness of 1 μm is epitaxially grown on the SiC substrate 11. Formed.

Continuously after the formation of the SiC buffer layer 12, the CVD method [carrier gas: H ₂ , source gas: SiH ₄ and C ₃ H ₈ , N-type conductive source: A SiC drift layer (N ⁻ ; nitrogen-doped, carrier concentration 5 × 10 ¹⁵ cm ⁻³ ) 13 having a thickness of 10 μm was epitaxially grown and laminated on the SiC buffer layer 12 by a conventional method using N ₂ ].

The CVD method [carrier gas: H ₂ , source gas: SiH ₄ and C ₃ H ₈ , Ge introduction source: tetraethyl germanium [( C ₂ H _{5) 4} Ge], P-type conduction material: by a conventional method using trimethylaluminum _{(TMA)], Si 0.9 Ge 0.1 C (x} = 0.1) was adjusted to a mixed crystal is obtained A SiGeC channel layer (P ⁻ ; Al-doped, carrier concentration 5 × 10 ¹⁶ cm ⁻³ ) 14 having a thickness of 2 μm was epitaxially grown on the SiC drift layer 13 and laminated.

As for Ge, the raw material gas flow rate was adjusted by introducing a predetermined flow rate of H ₂ or Ar into a vessel (bubbler) for generating an organometallic gas (tetraethyl germanium). At this time, the container is held at a constant temperature in a thermostatic bath so as to obtain a desired partial pressure. Further, a desired composition ratio can be obtained corresponding to the supply ratio of the Si and Ge source gases.

Subsequently, the CVD method [carrier gas: H ₂ , raw material gas: SiH ₄ and C ₃ H ₈ , N-type conductive raw material: N ₂ ] was used in the same manner as above while heating to 1400-2000 ° C. A SiC contact layer (N ⁺ ; nitrogen-doped, carrier concentration of 3 × 10 ¹⁸ cm ⁻³ or more) 15 having a thickness of 0.5 μm was epitaxially grown and stacked on the SiGeC channel layer 14 by a conventional method. In this way, as shown in FIG. 2A, the SiC buffer layer 12, the SiC drift layer 13, the SiGeC channel layer 14, and the SiC contact layer 15 are stacked on the SiC substrate 11 in this order from the substrate side. A laminated body (wafer) was obtained.

-2) Formation of groove-
Next, a mask SiO ₂ film was formed on the entire surface of the SiC contact layer 15 of the laminate obtained as described above by a conventional method using a plasma CVD method. In addition to the plasma CVD method, an LPCVD method, a sputtering method, or the like can be used. Furthermore on the formed SiO ₂ film, by photolithography commonly used in the semiconductor manufacturing process, a region for forming a gate electrode (gate forming region) is opening, the SiO ₂ film in the range that is to be a gate forming region A photoresist film (not shown) patterned to be exposed was formed. Then, by dry etching using CHF ₃ gas, as shown in FIG. 2B, the SiO ₂ film 21 in a range corresponding to the gate formation region is etched until the SiC contact layer 15 is exposed. Opened to form a concave groove 19. Thereafter, the remaining photoresist film was removed using a resist stripping solution.

Note that the etching treatment may be performed using a chemical solution such as buffered hydrofluoric acid. Further, the removal of the photoresist film may be performed using an ashing apparatus using O ₂ plasma or the like.

Next, by a dry etching method using SF ₆ gas, as shown in FIG. 2C, the SiGeC channel layer 14 and the SiC contact layer are within a range corresponding to the gate formation region regulated by the SiO ₂ film 21. 15 is etched so that a part of the SiC drift layer 13 is removed and a groove (depth 0.5 μm) is formed in the same width as the groove 19, and a groove (SiC contact layer) having a depth of 3.0 μm is formed. A total of (0.5 μm) 15, SiGeC channel layer (2 μm) 14 and a depth of 0.5 μm; groove 19) was formed. Thereafter, the SiO ₂ film 21 was removed by a dry etching method using CHF ₃ gas. The removal of the SiO ₂ film may be performed using a chemical solution such as buffered hydrofluoric acid.

  In the above description, the groove depth of the SiC drift layer 13 is set to 0.5 μm. However, the depth can be appropriately selected within a range of, for example, 0.1 to 0.5 μm according to the thickness and purpose of the SiC drift layer.

-3) Formation of gate oxide film by thermal oxidation method
The laminated body in which the groove portion 19 is formed is put in a thermal oxidation furnace and heated to 1000 to 1300 ° C. in an oxygen atmosphere to oxidize the entire outer surface of the laminated body, as shown in FIG. An oxide film 22 of SiO ₂ was formed. FIG. 2- (d) shows the oxide film 22 formed on the top and bottom of the laminate.

-4) Formation of source electrode
As described above, a region (source formation region) for forming a source electrode is further opened on the oxide film 22 formed on the upper portion of the stacked body by a photolithography method generally used in a semiconductor manufacturing process, that is, source formation. A photoresist film (not shown) patterned so as to expose the gate oxide film in a range to be a region was formed. Then, by dry etching using CHF ₃ gas, as shown in FIG. 2E, the oxide film 22 in the range corresponding to the source formation region is etched until the SiC contact layer 15 is exposed. did.

  At this time, as shown in FIG. 2E, on the surface of the SiC drift layer 13 in the groove 19 and on the wall surface formed by stacking the SiGeC channel layer 14 and the SiC contact layer 15 above the groove of the SiC drift layer 13. The gate oxide film 18 is formed so as to cover these surfaces and wall surfaces.

  Subsequently, as shown in FIG. 2E, Ni was deposited on the exposed portion of the SiC contact layer 15 to form a source electrode 16 having a thickness of 0.1 μm by using a vacuum deposition apparatus. Then, unnecessary electrode material formed on the photoresist film was removed together with the remaining photoresist film by a lift-off method using a resist stripping solution.

-5) Formation of drain electrode
Next, the oxide film 22 formed on the bottom of the laminate is removed by etching using a dry etching method using SF ₆ gas, and vacuum deposition is performed on the region where the oxide film 22 is removed and the SiC substrate is exposed. Using the apparatus, a drain electrode 20 was formed as shown in FIG.

  Subsequently, heat treatment was performed at 1000 ° C. for 10 minutes in an argon atmosphere so that ohmic characteristics were obtained for the source electrode and the drain electrode.

-6) Formation of gate electrode and wiring
Next, in the same manner as in the operation 4), patterning is performed so as to expose the gate oxide film 18 and the source electrode 16 on the bottom surface of the groove portion 19 which is a gate formation region by a photolithography method generally used in the semiconductor manufacturing process. A photoresist film (not shown) is formed, and Ti and Al are vapor-deposited on the exposed gate oxide film 18 and the source electrode 16 as shown in FIG. A gate electrode 17 and a wiring 23 composed of a Ti layer / Al layer (Ti thickness 0.1 μm + Al thickness 1.0 μm) having a thickness of 1.1 μm were formed. Then, both the unnecessary electrode material formed on the photoresist film and the remaining photoresist film were removed by a lift-off method using a resist stripping solution.

-7) Formation of surface protective film
Next, an SiO ₂ film for a surface protective film was formed on the entire upper surface of the laminated body so as to cover the gate electrode 17, the gate oxide film 18, the wiring 23, and the like by a conventional method using a plasma CVD method. In addition to the plasma CVD method, an LPCVD method, a sputtering method, or the like can be used. Further, a photoresist film (not shown) patterned on the formed SiO ₂ film so as to expose a part of the wiring 23 provided on the source electrode 16 by a photolithography method generally used in a semiconductor manufacturing process. Formed. Then, etching is performed by a dry etching method using CHF ₃ gas until the wiring 23 on the source electrode 16 is exposed as shown in FIG. A surface protective film (SiO ₂ film) 24 was formed. Thereafter, the remaining photoresist film was removed using a resist stripping solution.

Note that the etching treatment may be performed using a chemical solution such as buffered hydrofluoric acid, or the photoresist film may be removed using an ashing apparatus using O ₂ plasma or the like.

  As described above, the vertical MOSFET shown in FIG. 1 was manufactured. The channel mobility of the MOSFET fabricated as described above was measured using a semiconductor parameter analyzer, and it was found that the channel mobility of the channel layer made of SiC crystal (Al-doped) without Ge doping is similar to that of a vertical MOSFET with the same configuration. An improvement effect of 20% or more was observed.

In this embodiment, the case where the channel region (SiGeC channel layer) is formed using Si _0.9 Ge _0.1 C (x = 0.1) mixed crystal as the SiGeC mixed crystal has been mainly described, but x = 0.1. Any composition that can be selected within the range of 0 <x <1 can form a SiGeC channel layer in the same manner as described above, and an impurity other than Al can be introduced to form another n-type or p-type semiconductor layer. It is possible to configure.

(Second Embodiment)
2nd Embodiment of the silicon carbide semiconductor device of this invention is described with reference to FIGS. In the present embodiment, the gate electrode is configured in a MOS structure, and a layer made of Si _0.95 Ge _0.05 C mixed crystal is provided as a channel layer forming a channel region, and a source provided on one side of a stacked body (wafer) and This is a lateral MOS field effect transistor (MOSFET) in which electrons flow in the lateral direction between the drains.

  The SiGeC channel layer and other layers (excluding the SiC substrate) can be formed and formed in the same manner as in the first embodiment using the materials and methods used in the first embodiment. The same reference numerals are assigned to the same components as those in FIG.

As shown in FIG. 4, the MOSFET according to the present embodiment is formed on a P-type 4H—SiC substrate (P ⁻ ; Al-doped, carrier concentration 3 × 10 ¹⁸ cm ⁻³ ) 31 in order, P ⁻ ; Al doped, carrier concentration 3 × 10 ¹⁸ cm ⁻³ ) 32 and a SiGeC channel layer (P ⁻ ; Al doped, carrier concentration 5 × 10 ¹⁵ cm ⁻³ ) 34 having a thickness of 2 μm are laminated. In this SiGeC channel layer 34, Si _0.95 Ge _0.05 C (x = 0.05) mixed crystal (SiGeC mixed crystal) doped with Ge by a vapor phase growth method is doped with hexagonal SiC crystal as an impurity. It is a layer, and this layer itself can supply electrons for carriers.

Thus, the channel region is configured with high mobility using Si _0.95 Ge _0.05 C (x = 0.05) mixed crystal, and electrons are supplied in the channel layer made of SiGeC mixed crystal with high carrier mobility. It can be done. As a result, the SiGeC channel layer 34 has a low on-resistance due to the expansion of the crystal lattice, the device loss accompanying the electron scattering probability is kept low, and high device characteristics can be obtained. Except for the SiGeC mixed crystal composition being Si _0.95 Ge _0.05 C (x = 0.05), the details and preferred aspects of the SiGeC composition, the formation method such as the growth method, the thickness, etc. are the same as in the first embodiment. is there.

On the surface of the SiGeC channel layer 34, an exposed portion of the SiGeC channel layer 34 is left so that a groove 19 for forming a MOS structure is formed, and an SiC contact layer (N ⁺ ; nitrogen doped, (A carrier concentration of 3 × 10 ¹⁸ cm ⁻³ or more) 15 is laminated, and a source electrode 16 made of Ni and a drain electrode 20 made of Ni are formed in a partial region on the SiC contact layer 15.

Further, as shown in FIG. 4, the region where the source electrode and the drain electrode are not formed on the SiC contact layer 15, the side portion of the SiC contact layer 15, and a part of the surface of the SiGeC channel layer 34 in the groove portion 19. A gate oxide film 18 made of SiO ₂ having a thickness of 30 to 100 nm is formed so as to be covered.

  A gate electrode 17 made of a Ti layer / Al layer is formed on the surface of the gate oxide film 18 in the groove portion 19 to form a MOS structure. The gate electrode 17 is not in contact with the source electrode 16 and the SiC contact layer 15 by the gate oxide film 18.

  Next, a method for manufacturing the silicon carbide semiconductor device of the present invention will be described with reference to FIGS. 5 to 6, taking as an example the case where the lateral MOSFET of the present embodiment is manufactured.

-1) Formation of each layer on the substrate
An SiC substrate (P ⁻ ; 4H—SiC (0001) 8 ° off toward [11-20], Al-doped, carrier concentration 3 × 10 ¹⁸ cm ⁻³ ) is prepared, and the SiC substrate is heated to 1400 to 2000 ° C. As shown in FIG. 5- (a) by a conventional method using a CVD method [carrier gas: H ₂ , source gas: SiH ₄ and C ₃ H ₈ , P-type conductive material: trimethylaluminum (TMA)]. A SiC layer (P ⁻ ; Al-doped, carrier concentration 3 × 10 ¹⁸ cm ⁻³ ) 32 having a thickness of 5 μm was formed on the SiC substrate 31.

The CVD method [carrier gas: H ₂ , source gas: SiH ₄ and C ₃ H ₈ , Ge introduction source: tetraethyl germanium [(C ₂ H ₅ ) ₄ Ge], P-type conductive material: trimethylaluminum (TMA)], and component flow rate and bubbling flow rate so that Si _0.95 Ge _0.05 C (x = 0.1) mixed crystal can be obtained. The SiGeC channel layer (P ⁻ ; Al-doped, carrier concentration 5 × 10 ¹⁵ cm ⁻³ ) 34 having a thickness of 2 μm was laminated on the SiC layer 32.

Subsequently, the CVD method [carrier gas: H ₂ , raw material gas: SiH ₄ and C ₃ H ₈ , N-type conductive raw material: N ₂ ] was used in the same manner as above while heating to 1400-2000 ° C. A SiC contact layer (N ⁺ ; nitrogen-doped, carrier concentration of 3 × 10 ¹⁸ cm ⁻³ or more) 15 having a thickness of 0.5 μm was laminated on the SiGeC channel layer 34 by a conventional method. In this way, as shown in FIG. 5A, a stacked body (wafer) in which the SiC layer 32, the SiGeC channel layer 34, and the SiC contact layer 15 are stacked in this order on the SiC substrate 31 from the substrate side. Got.

-2) Formation of groove-
Next, a mask SiO ₂ film was formed on the surface of the SiC contact layer 15 of the laminate obtained as described above by a conventional method using a plasma CVD method. In addition to the plasma CVD method, an LPCVD method, a sputtering method, or the like can be used. Furthermore on the formed SiO ₂ film, by photolithography commonly used in the semiconductor manufacturing process, a region for forming a gate electrode (gate forming region) is opening, the SiO ₂ film in the range that is to be a gate forming region A photoresist film (not shown) patterned to be exposed was formed. Then, by dry etching using CHF ₃ gas, the SiO ₂ film 21 in the range corresponding to the gate formation region is etched until the SiC contact layer 15 is exposed, as shown in FIG. Opened to form a concave groove 19. Thereafter, the remaining photoresist film was removed using a resist stripping solution.

Note that the etching treatment may be performed using a chemical solution such as buffered hydrofluoric acid. Further, the removal of the photoresist film may be performed using an ashing apparatus using O ₂ plasma or the like.

Next, by dry etching using SF ₆ gas, the SiC contact layer 15 and the groove 19 are formed in a range corresponding to the gate formation region regulated by the SiO ₂ film 21 as shown in FIG. Etching was performed so that a groove having a concave shape with the same width was formed. Thereafter, the SiO ₂ film 21 was removed by a dry etching method using CHF ₃ gas. The removal of the SiO ₂ film may be performed using a chemical solution such as buffered hydrofluoric acid.

-3) Formation of gate oxide film by thermal oxidation method
The laminated body in which the groove portions 19 are formed is put in a thermal oxidation furnace, and heated to 1000 to 1300 ° C. in an oxygen atmosphere to oxidize the upper surface of the laminated body. As shown in FIG. _Two oxide films 22 were formed.

-4) Formation of source and drain electrodes
As described above, regions (source formation region and drain formation region) for forming a source electrode and a drain electrode are further formed on the oxide film 22 formed on the upper portion of the stacked body by a photolithography method generally used in a semiconductor manufacturing process. ) And a region for forming a gate electrode (gate formation region) was formed to form a photoresist film (not shown) that was patterned. Then, by dry etching using CHF ₃ gas, as shown in FIG. 5E, the oxide film 22 in a range corresponding to the source formation region and the drain formation region is etched until the SiC contact layer 15 is exposed. In addition, the oxide film 22 in the range corresponding to the gate formation region was etched until the SiGeC channel layer 34 was exposed. At this time, the gate oxide film 18 is formed so as to cover a part of the surface of the SiC contact layer 15 and the exposed side surface.

  Subsequently, using a vacuum deposition apparatus, as shown in FIG. 5E, Ni is deposited on the exposed portion of the SiC contact layer 15 to form a source electrode 16 and a drain electrode 20 having a thickness of 0.1 μm. did. Then, unnecessary electrode material formed on the photoresist film was removed together with the remaining photoresist film by a lift-off method using a resist stripping solution. Then, in an argon atmosphere, heat treatment was performed at 1000 ° C. for 10 minutes so that ohmic characteristics were obtained for the source electrode and the drain electrode.

-5) Formation of gate electrode and wiring
Next, in the same manner as in the first embodiment, in the same manner as in the operation 4), the gate oxide film 18 in the vicinity of the groove 19, the source electrode 16 and the drain electrode 20 are formed by a photolithography method generally used in the semiconductor manufacturing process. A photoresist film (not shown) patterned so as to be exposed is formed, and the source electrode is formed on the gate oxide film 18 in the vicinity of the groove 19 as shown in FIG. Ti and Al were vapor-deposited on 16 and the drain electrode 20, and the gate electrode 17 and the wiring 23 which consisted of a 1.1 micrometer-thick Ti layer / Al layer (Ti thickness 0.1 micrometer + Al thickness 1.0 micrometer) were formed. Then, both the unnecessary electrode material formed on the photoresist film and the remaining photoresist film were removed by a lift-off method using a resist stripping solution.

-6) Formation of surface protective film
Next, an SiO ₂ film for a surface protective film was formed on the entire upper surface of the laminated body so as to cover the gate electrode 17, the gate oxide film 18, the wiring 23, and the like by a conventional method using a plasma CVD method. In addition to the plasma CVD method, an LPCVD method, a sputtering method, or the like can be used. Further, a photoresist film patterned on the formed SiO ₂ film so as to expose a part of the wiring 23 provided on the source electrode 16 and the drain electrode 20 by a photolithography method generally used in a semiconductor manufacturing process. (Not shown) was formed. Then, by dry etching using CHF ₃ gas, etching is performed until the wiring 23 on the source electrode 16 and the drain electrode 20 is exposed as shown in FIG. A surface protective film (SiO ₂ film) 24 was formed so as to cover. Thereafter, the remaining photoresist film was removed using a resist stripping solution.

Note that the etching treatment may be performed using a chemical solution such as buffered hydrofluoric acid, or the photoresist film may be removed using an ashing apparatus using O ₂ plasma or the like.

  As described above, the lateral MOSFET shown in FIG. 4 was produced. When the channel mobility of the MOSFET manufactured as described above was measured using a semiconductor parameter analyzer, the mobility was higher than that of a lateral MOSFET having the same configuration with a channel layer made of SiC crystal (Al-doped) without Ge doping. However, an improvement effect of 20% or more was recognized.

(Third embodiment)
A third embodiment of the silicon carbide semiconductor device of the present invention will be described with reference to FIG. In the present embodiment, the gate electrode is configured in a MOS structure, and the SiGeC channel layer made of Si _0.9 Ge _0.1 C mixed crystal in the vertical MOSFET of the first embodiment is replaced with an SiC channel layer and an Si _0.9 Ge _0.1 C mixed crystal. It is constituted by a laminated structure with a strain supply layer made of

The other layers other than the SiC channel layer and the strain supply layer made of Si _0.9 Ge _0.1 C mixed crystal and the SiC substrate are formed in the same manner as in the first embodiment using the materials and methods used in the first embodiment. Film formation is possible, and the same components as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

As shown in FIG. 7, the MOSFET according to the present embodiment has a thickness of 0.1 mm between the SiC drift layer 13 and the SiC contact layer 15 on the surface where the groove 19 of the SiC drift layer 13 is not formed (groove non-formation surface). A SiC channel layer (P ⁻ ; Al-doped, carrier concentration 5 × 10 ¹⁶ cm ⁻³ ) 40 having a thickness of 5 μm is stacked, and a SiGeC strain supply layer (N ⁺ ; having a thickness of 0.2 μm is further formed on the surface of the SiC channel layer 40. Nitrogen dope, carrier concentration 3 × 10 ¹⁸ cm ⁻³ ) 41 is laminated.

The SiC channel layer 40 is a layer forming a channel region functioning as a p-type semiconductor, and can be formed in substantially the same manner as the other SiC layer forming method in the first embodiment. In this embodiment, specifically, in the first embodiment, the CVD method [carrier gas: H ₂ , source gas: SiH ₄ and A SiC channel layer 40 having a thickness of 0.5 μm is epitaxially grown and laminated on the SiC drift layer 13 by a conventional method using C ₃ H ₈ , P-type conductive material: trimethylaluminum (TMA)]. is there.

  Various silicon carbides can be selected for forming the SiC channel layer. Among these, hexagonal SiC crystals are preferable, and 4H—SiC crystals and 6H—SiC crystals are preferable. The 4H—SiC crystal is preferable in that it has a high carrier mobility and has a smaller stacking fault density than the 6H—SiC crystal grown in the same direction.

  Although it does not restrict | limit especially as thickness of a SiC channel layer, 0.1-2.0 micrometers is preferable from a relationship with a SiGeC strain supply layer, and 0.1-0.5 micrometer is more preferable.

The SiGeC strain supply layer 41 is a layer obtained by doping Si _0.9 Ge _0.1 C (x = 0.1) mixed crystal (SiGeC mixed crystal) in which hexagonal SiC is doped with Ge by a vapor phase growth method using nitrogen as an impurity. This layer itself can supply electrons for carriers. The details of the composition of the SiGeC mixed crystal, preferred modes, formation methods such as a growth method, and the like are the same as those in the first embodiment.

  The thickness of the SiGeC strain supply layer is not particularly limited, but is preferably from 0.01 to 2.0 μm, more preferably from 0.2 to 1.0 μm in terms of giving large strain without crystal defects. preferable.

The SiGeC strain supply layer 41 is further continuously heated after the SiC channel layer 40 is stacked, while being heated to 1400 to 2000 ° C., while the CVD method [carrier gas: H ₂ , source gas: SiH ₄ and C ₃ H ₈ , Ge introduction Si _0.9 Ge _0.1 C (x = 0.1) mixed crystal can be obtained by a conventional method using a raw material: tetraethylgermanium [(C ₂ H ₅ ) ₄ Ge], an N-type conductive raw material: N ₂ ]. The SiGeC strain supply layer 41 having a thickness of 0.5 μm is laminated on the SiC channel layer 40.

As for Ge, the raw material gas flow rate was adjusted by introducing a predetermined flow rate of H ₂ or Ar into a vessel (bubbler) for generating an organometallic gas (tetraethyl germanium). At this time, the container is held at a constant temperature in a thermostatic bath so as to obtain a desired partial pressure. Further, a desired composition ratio can be obtained corresponding to the supply ratio of the Si and Ge source gases.

  In the present embodiment, after the formation of the SiGeC strain supply layer 41, the vertical MOSFET of the present embodiment configured as shown in FIG. 7 is manufactured by performing the same operation as in the first embodiment. .

As described above, the SiGeC strain supply layer 41 using the Si _0.9 Ge _0.1 C (x = 0.1) mixed crystal is formed adjacently because the crystal lattice is widened and the lattice constant is large as compared with SiC itself. The SiC channel layer 40 receives the stress of the SiGeC strain supply layer 41 and has a large lattice constant and a high mobility. Therefore, electrons can be supplied in the SiC channel layer 40 and the SiGeC strain supply layer 41 having high carrier mobility. As a result, the on-resistance is low, and the device loss accompanying the electron scattering probability is kept low, and high device characteristics can be obtained.

  Also in this embodiment, the Ge ratio can be arbitrarily selected within the range of 0 <x <1, and within this range, the element loss accompanying the electron scattering probability in the channel region can be kept low, and the carrier A channel region with high mobility can be formed. Thereby, high device characteristics can be obtained. In particular, considering the crystal quality and mobility characteristics, the Ge ratio is preferably in the range of 0 <x ≦ 0.5, more preferably in the range of 0 <x ≦ 0.2, and 0.05 ≦ x ≦ 0. A range of 15 is more preferred.

  In the above embodiment, an example in which an N-type or P-type 4H—SiC substrate is used as the SiC substrate has been described. However, the SiC substrate may be appropriately selected according to the form of the silicon carbide semiconductor device to be manufactured.

  A concave groove 19 for forming a MOS structure is formed on the side of the SiC drift layer 13 that is not in contact with the SiC buffer layer 12, as in the first embodiment, and a gate oxide film is formed thereabove. A gate electrode 17 is formed via 18.

  When the carrier mobility of the MOSFET fabricated as described above was measured in the same manner as in the first embodiment, it was found that the vertical MOSFET had a single-phase configuration with a channel layer made of SiC crystal (Al-doped) without Ge doping. , 20% or more mobility improvement effect was observed.

In the present embodiment, as in the first embodiment, the vertical MOSFET in which electrons flow in the vertical direction from the source side to the drain formed on the surface opposite to the source formation surface has been mainly described. As another form, a lateral MOSFET similar to that of the second embodiment (see FIG. 4), for example, as shown in FIG. 8, a SiGeC channel layer 34 of FIG. P ⁻ ; Al-doped, carrier concentration 5 × 10 ¹⁵ cm ⁻³ ) 50 and a SiGeC strain supply layer (N ⁺ ; nitrogen-doped, carrier concentration 3 × 10 ¹⁸ cm ⁻³ ) 51 having a thickness of 0.2 μm are laminated. It is also possible to adopt a configuration in place of the structure. This can be produced by forming a layered structure in the same manner as described above. Similarly, a mobility improvement effect of 20% or more can be obtained with respect to a lateral MOSFET having a single-phase configuration with a channel layer made of SiC crystal (Al-doped) not subjected to Ge doping.

  In each of the above-described embodiments, an example in which nitrogen (N) or aluminum (Al) is doped as an impurity has been mainly described. However, in addition to N and Al, phosphorus (P), boron (B), and the like, Si and C Other atoms having different atomic radii can be appropriately selected so as to form an n-type or p-type semiconductor.

  Further, although an example using an N-type or P-type 4H—SiC substrate as the SiC substrate has been shown, other than the above example, a SiC substrate is appropriately selected according to the form of the silicon carbide semiconductor device to be manufactured, such as a semi-insulating SiC substrate. It is possible to select a substrate.

1 is a schematic configuration diagram showing a vertical MOSFET according to a first embodiment of the present invention. It is process drawing for demonstrating the place which is producing vertical type | mold MOSFET which concerns on 1st Embodiment of this invention. It is process drawing for demonstrating the place which is producing vertical type | mold MOSFET which concerns on 1st Embodiment of this invention. It is a schematic block diagram which shows the horizontal MOSFET which concerns on 2nd Embodiment of this invention. It is process drawing for demonstrating the place which is producing the lateral type MOSFET which concerns on 2nd Embodiment of this invention. It is process drawing for demonstrating the place which is producing the lateral type MOSFET which concerns on 2nd Embodiment of this invention. It is a schematic block diagram which shows the vertical MOSFET which concerns on 3rd Embodiment of this invention. It is a schematic block diagram which shows the other example of horizontal type | mold MOSFET which concerns on embodiment of this invention.

Explanation of symbols

14, 34 ... SiGeC channel layer 16 ... source electrode 18 ... gate oxide film 19 ... gate electrode 20 ... drain electrodes 40, 50 ... SiC channel layers 41, 51 ... SiGeC strain supply layer

Claims (4)

In a silicon carbide semiconductor device including a gate electrode and a gate oxide film, a source electrode, and a drain electrode,
Channel region forming portion, together configured to n-type or p-type semiconductor by doping of impurities, in that it consists of Si _1-x Ge _x C mixed crystal Ge doped in SiC crystal [0 <x <1] A silicon carbide semiconductor device. In a silicon carbide semiconductor device including a gate electrode and a gate oxide film, a source electrode, and a drain electrode,
A channel region formed part made of SiC crystal that is configured to n-type or p-type semiconductor by doping an impurity,
Wherein provided adjacent to the top of the channel region forming portion, by doping an impurity along with configured semiconductor of the channel region forming portion opposite type, Si _1-x Ge _x C mixed which Ge is doped SiC crystals A strain supply layer composed of crystals [0 <x <1];
A silicon carbide semiconductor device comprising: The silicon carbide semiconductor device according to claim 1, wherein the SiC crystal that forms the Si _1-x Ge _x C mixed crystal is a 4H—SiC crystal.   The silicon carbide semiconductor device according to claim 1, wherein x satisfies 0 <x <0.2.

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