JP2009158788A - Vertical mosfet and manufacturing method of the vertical mosfet - Google Patents

Vertical mosfet and manufacturing method of the vertical mosfet Download PDF

Info

Publication number
JP2009158788A
JP2009158788A JP2007336781A JP2007336781A JP2009158788A JP 2009158788 A JP2009158788 A JP 2009158788A JP 2007336781 A JP2007336781 A JP 2007336781A JP 2007336781 A JP2007336781 A JP 2007336781A JP 2009158788 A JP2009158788 A JP 2009158788A
Authority
JP
Japan
Prior art keywords
layer
conductivity type
impurity concentration
drift layer
buffer layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2007336781A
Other languages
Japanese (ja)
Other versions
JP5236281B2 (en
Inventor
Masahiro Niisato
昌弘 新里
Original Assignee
Oki Semiconductor Co Ltd
Okiセミコンダクタ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Semiconductor Co Ltd, Okiセミコンダクタ株式会社 filed Critical Oki Semiconductor Co Ltd
Priority to JP2007336781A priority Critical patent/JP5236281B2/en
Publication of JP2009158788A publication Critical patent/JP2009158788A/en
Application granted granted Critical
Publication of JP5236281B2 publication Critical patent/JP5236281B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Abstract

<P>PROBLEM TO BE SOLVED: To provide a vertical MOSFET which can have a larger current and a higher breakdown voltage, by circumventing concentrations of electric field concentration and current, even when the cells of the MOSFET having a vertical structure are integrated highly, and to provide a manufacturing method of the vertical MOSFET. <P>SOLUTION: The vertical MOSFET which has a semiconductor substrate layer and a drift layer, provided above the semiconductor substrate layer and having a lower impurity concentration than the semiconductor substrate layer is provided with a buffer layer which continuously varies in impurity concentration, with the depth position within an impurity range being lower than the impurity concentration of the semiconductor layer and higher than the impurity concentration of the drift layer between the semiconductor substrate layer and drift layer. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a vertical MOSFET using silicon carbide (SiC) as a semiconductor material and a manufacturing method thereof.

  A semiconductor made of silicon carbide SiC (Silicon carbide), which is a compound of carbon and silicon, has a wider band gap than a conventional Si semiconductor. For this reason, the electric field strength leading to dielectric breakdown is 3 MV / cm, which is about 10 times larger than that of a conventional Si semiconductor. In addition, the electron has a high saturation drift velocity, is excellent in thermal conductivity, heat resistance, and chemical resistance, and has higher radiation resistance than Si semiconductors. These features make it possible to produce power devices that are much smaller, have lower loss, and have higher efficiency than conventional Si semiconductors, and that are high-frequency devices and semiconductor devices with excellent radiation resistance. For this reason, SiC devices have high needs in the space and nuclear power fields in addition to electric power, transportation, and home appliances. Recently, the advantages of low power consumption, high heat-resistant temperature of 400 ° C, higher than Si semiconductors, and no need for heat dissipation devices such as fans to cool down, have been actively studied for semiconductors for hybrid vehicles. Yes.

  Research institutes are advancing research to apply SiC having such excellent characteristics to MOSFETs that perform power switch control. FIG. 1 shows a typical cross-sectional structure of a conventional n-channel vertical MOSFET (DMOS Double-Diffused-MOSFET) having a double diffusion structure. The basic structure of the DMOS shown in FIG. 1 is also applied to a SiC semiconductor. In the DMOS, an n-type drift layer 2 having a lower concentration than the n-type substrate layer 1 is formed on a high-concentration n-type substrate layer 1 that functions as a drain. A p-type body region 3 is formed on the surface of the n-type drift layer 2, and a high-concentration n-type source region 4 is formed inside the p-type body region 3 along the substrate surface. A portion from the end of the n-type source region 4 to the end of the p-type body region 3 is a channel region where an inversion layer is formed. A gate electrode 6 is formed on the substrate surface above the channel region via a gate oxide film 5. A drain electrode 7 is formed on the back surface of the n-type substrate layer 1, and a source electrode 8 is formed on the source region 4.

By the way, one of the most important characteristics among the electrical characteristics of the MOSFET is the on-resistance. On the principle of operation of the MOSFET, carriers move from the source to the drain by drift. For this reason, the on-resistance of the MOSFET is represented by the sum of the resistances on the path along which carriers move, as shown in FIG. That is, the on-resistance of the MOSFET can be represented by the sum of the source resistance R s , the channel resistance R ch , the epitaxial layer resistance R epi , and the substrate resistance R sub . As a technique for reducing the on-resistance of the MOSFET, application of a microfabrication process is effective. By reducing the cell size by the microfabrication process and achieving high integration, the total channel width per unit volume is widened, and the channel resistance R ch can be reduced. In addition, since the area ratio of the current path increases as the total channel width increases, the epi layer resistance R epi also decreases. For this reason, high integration of cells is extremely effective in reducing on-resistance. FIG. 2 shows the effect of reducing the on-resistance due to the high integration of cells. FIG. 2 (a) shows the carrier flow before miniaturization and FIG. 2 (b) shows the carrier flow after miniaturization. In particular, in a semiconductor device using SiC, reduction of on-resistance is one of the important technical problems, and application of a microfabrication process is indispensable.
JP 2000-150866 A JP-A-10-107319 JP 2000-148533 A JP 2000-243957

  However, when the area ratio of the current path is increased by applying the microfabrication process, an excessive current density portion is likely to be formed in the vicinity of the drain region 1 as shown in FIG. This is a serious problem in SiC semiconductors rather than ordinary Si semiconductors. Here, FIG. 3 shows a concentration distribution of impurities in a cross section along the line AA shown in FIG. In SiC semiconductors, nitrogen N is generally used as an n-type dopant. When nitrogen is introduced as a dopant into SiC, the concentration gradient near the interface between the low concentration drift layer 2 and the high concentration n-type substrate layer 1 becomes steep as shown in FIG. As a result, MOSFETs using SiC substrates are more likely to cause electric field concentration or current concentration in the portion of excess current density near the drain that occurs when cells are highly integrated, compared to MOSFETs using conventional Si substrates. This hinders current and high breakdown voltage.

  The present invention has been made in view of the above points, and even in the case where a cell is highly integrated in a vertical structure power MOSFET, particularly in a vertical structure power MOSFET using a SiC substrate, electric field concentration and current concentration are achieved. It is an object of the present invention to provide a MOSFET and a method for manufacturing the same that can increase the current and the breakdown voltage by avoiding the above.

  A vertical MOSFET according to the present invention includes a substrate layer having a first conductivity type, and a drift that is stacked on the substrate layer and has the first conductivity type and has an impurity concentration lower than that of the substrate layer. A body region having a second conductivity type different from the first conductivity type provided along a surface of the drift, and a surface of the body region inside the body region and along the surface of the body region. A vertical MOSFET including a source region having the first conductivity type, and is provided between the substrate layer and the drift layer so that the impurity concentration of the drift layer is changed from the impurity concentration of the substrate layer. The buffer layer having the first conductivity type that changes so that the impurity concentration increases in accordance with the depth position from the drift layer toward the substrate layer.

  According to another aspect of the present invention, there is provided a vertical MOSFET manufacturing method, comprising: preparing a substrate made of a semiconductor having the first conductivity type; and supplying a source gas and the first on the substrate. A buffer layer forming step of introducing a dopant gas of one conductivity type and epitaxially growing the buffer layer by a gas phase reaction; and introducing a source gas and a dopant gas of the first conductivity type onto the buffer layer to form a gas phase A drift layer forming step of epitaxially growing the drift layer by reaction; an ion implantation of the second conductivity type impurity into the surface of the drift layer to form the body region; and the first region in the body region. And ion-implanting a conductivity type impurity to form the source region. In forming step is characterized by decreasing the introduction amount of the dopant gas sequentially.

  According to another aspect of the present invention, there is provided a vertical MOSFET manufacturing method, comprising: preparing a substrate made of a semiconductor having the first conductivity type; and supplying a source gas and the first on the substrate. A drift layer forming step of introducing a dopant gas of one conductivity type and epitaxially growing the drift layer by a gas phase reaction; and a buffer layer forming step of forming the buffer layer in the drift layer by ion implantation into the drift layer Ion implantation of the second conductivity type impurity into the drift layer surface to form the body region; and ion implantation of the first conductivity type impurity into the body region to form the source region And in the buffer layer forming step, the implantation energy and the dose amount are ordered. Varied is characterized by a plurality of times of ion implantation.

  According to the MOSFET of the present invention, electric field concentration and current concentration in the vicinity of the drain region can be alleviated even when an excessive current density portion occurs during operation due to cell miniaturization. It becomes possible to achieve current and high breakdown voltage.

BEST MODE FOR CARRYING OUT THE INVENTION

(First embodiment)
Embodiments of the present invention will be described below with reference to the drawings. In the following embodiments, a case where the present invention is applied to a MOSFET using a SiC substrate will be described as an example. However, the present invention can also be applied to a MOSFET using a normal Si substrate. FIG. 4 is a sectional structural view of a unit cell of a vertical MOSFET using the SiC substrate according to the first embodiment of the present invention. The MOSFET 100 is formed from an n-type single crystal having an impurity concentration of 5 × 10 15 cm −3 , for example, on an n-type SiC substrate layer 10 made of an n-type 4H—SiC single crystal having an impurity concentration of 1 × 10 20 cm −3 functioning as a drain. An n-type drift layer 12 is formed via the buffer layer 11. The buffer layer 11 is made of an n-type SiC single crystal whose impurity concentration is lower than that of the SiC substrate layer 10 and higher than that of the drift layer 12, and an impurity concentration gradient in a section from the drift layer 12 to the SiC substrate layer 10. It is a layer that plays the role of mitigating. Specifically, the buffer layer 11 includes three layers 11a, 11b, and 11c doped with different concentrations of dopant in SiC according to the depth position from the substrate surface, and the buffer layer 11 is adjacent to the SiC substrate layer 10. The lower layer 11a has the highest impurity concentration, the uppermost layer 11c adjacent to the drift layer 12 has the lowest impurity concentration, and the intermediate layer 11b formed between these layers has an intermediate impurity concentration between the uppermost layer 11c and the lowermost layer 11a. Formed with. That is, the buffer layer 11 has a concentration distribution in which the impurity concentration changes stepwise according to the depth position. A p-type body region 13 made of, for example, a p-type SiC single crystal having a concentration of 5 × 10 15 cm −3 is formed on the surface of the drift layer 12. An n-type source region 14 made of, for example, an n-type SiC single crystal having a concentration of 5 × 10 20 cm −3 is formed inside the p-type body region 13. A portion from the end of the n-type source region 14 to the end of the p-type body region 13 is a channel region where an inversion layer is formed. A gate oxide film 15 made of SiO 2 is formed on the surface of the SiC substrate so as to cover the channel region, and a gate electrode 16 made of polysilicon is formed on the gate oxide film 15. A drain electrode 17 electrically connected thereto is formed on the back surface of the n-type SiC substrate layer 10, and a source electrode 18 electrically connected thereto is formed on the n-type source region 14. The gate electrode 16 is covered with an interlayer insulating film 19, and the gate electrode 16 and the source electrode 18 are insulated.

  The operation principle of the MOSFET 100 having such a structure is basically the same as that of the conventional structure. That is, when a gate voltage higher than the threshold is applied to the gate electrode 16, electrons are induced on the surface of the p-type body region 13 to form an inversion layer. As a result, a current path is formed between the n-type source region 14 and the drift layer 12. When the drain electrode 17 is positively biased with respect to the source electrode 18 in this state, electrons function as a drain from the n-type source region 14. A current flows by flowing toward the SiC substrate layer 10.

  FIG. 5 shows the impurity concentration distribution in the cross section along the line BB shown in FIG. 4 of the MOSFET 100 having the above structure, the horizontal axis is the distance in the depth direction from the surface of the MOSFET 100, and the vertical axis is the vertical axis. The impurity concentration is shown. As described above, the MOSFET 100 of the present invention is provided with the buffer layer 11 composed of a plurality of layers stacked so that the impurity concentration changes stepwise between the high concentration SiC substrate layer 10 and the drift layer 12. Therefore, it can be understood that the concentration gradient in the section from the drift layer 12 to the SiC substrate layer 10 is gentler than that of the conventional structure. FIG. 6 shows the electric field strength distribution along the line BB in FIG. 4 when the MOSFET 100 is in operation. In FIG. 6, the electric field strength distribution along the AA line cross section in FIG. 1 in the conventional structure is shown by a broken line as a comparison. As shown in FIG. 6, in the MOSFET 100 of the present invention, the buffer layer 11 is provided between the drift layer 12 and the SiC substrate layer 10, and the electric field strength decreases in the buffer layer 11, so that the current density is increased during operation. The electric field strength in the vicinity of the excessive SiC substrate layer 10 (drain) is reduced as compared with the conventional structure. That is, even if a current density excess portion occurs near the drain due to the miniaturization of the cell due to the gradual impurity concentration gradient in the section from the drift layer 12 to the SiC substrate layer 10 due to the action of the buffer layer 11, Electric field concentration is less likely to occur, and it becomes possible to increase the current and withstand voltage in a MOSFET using a SiC substrate.

Next, a method for manufacturing MOSFET 100 having the above structure will be described with reference to FIG. 7A to 7G are cross-sectional views showing the manufacturing process of the MOSFET 100 for each step. First, for example, an n-type 4H—SiC substrate 10 having a thickness of about 300 μm doped with nitrogen N having an impurity concentration of 1 × 10 20 cm −3 is prepared. The SiC substrate 10 is manufactured by, for example, a sublimation method (FIG. 7A).

Next, the buffer layer 11 and the drift layer 12 are sequentially epitaxially grown on the SiC substrate 10. The epitaxial growth can be performed using, for example, a CVD (chemical vapor deposition chemical vapor deposition) method. The source gas uses SiH 4 for the Si source, C 3 H 8 for the C source, and N 2 as the n-type dopant gas. A source gas and a dopant gas are introduced into the reaction tube by the carrier gas H 2 , and the buffer layer 11 and the drift layer 12 are sequentially formed on the SiC substrate 10 heated on the susceptor. The growth temperature is, for example, 1500 ° C., and the pressure in the reaction tube is, for example, 40 Torr. The buffer layer 11 is composed of the three layers 11a, 11b, and 11c having different impurity concentrations as described above. By sequentially changing the flow rate of N 2 that is an n-type dopant gas in the CVD film forming process, Impurity concentration can be controlled arbitrarily and with high accuracy. That is, the N 2 flow rate is increased when forming the lowermost layer 11a having the highest impurity concentration in the buffer layer 11, and the N 2 flow rate is decreased when forming the uppermost layer 11c having the lowest impurity concentration. When the intermediate layer 11b is formed, the intermediate flow rate is set. Thus, by changing the flow rate of the dopant gas stepwise in the CVD film forming step, it is possible to form the buffer layer 11 composed of a plurality of layers in which the impurity concentration changes stepwise (FIG. 7 ( b)). The drift layer 12 is subsequently formed in the CVD film forming process after the buffer layer 11 is formed. The impurity concentration of the drift layer 12 is also controlled by adjusting the flow rate of the dopant gas similarly to the buffer layer 11, and the drift layer 12 is grown on the buffer layer 11 (FIG. 7C).

Next, a photomask 20 is formed on the surface of the drift layer 12 epitaxially grown, and p-type body ions 13 are implanted to form a p-type body region 13. The photomask 20 is formed by patterning a SiO 2 film having a thickness of about 1 μm deposited by CVD using photolithography. For example, aluminum Al can be used as the ion species, and the ion implantation is performed, for example, with an implantation energy of 200 KeV and a dose of 5 × 10 14 cm −2 (FIG. 7D). As the p-type impurity, boron B may be used instead of aluminum Al.

Next, a photomask 21 is formed on the substrate surface, and n-type impurity ions are implanted into the p-type body region 13 formed in the previous step to form an n-type source region 14. For example, nitrogen N can be used as the ion species, and the ion implantation is performed, for example, with an implantation energy of 100 KeV and a dose of 1 × 10 15 cm −2 (FIG. 7E). As the n-type impurity, phosphorus P may be implanted instead of nitrogen N. In addition, when ion implantation is performed in a SiC single crystal, it is difficult to recover crystal defects formed during ion implantation by thermal annealing as compared with Si. Therefore, the substrate is heated during ion implantation effective for crystal defect recovery. It is preferable to perform hot ion implantation. Thereafter, activation annealing is performed for 30 minutes in an argon atmosphere at 1500 ° C., for example.

Next, the substrate after ion implantation is thermally oxidized in WetO 2 at 1100 ° C. for about 5 hours to form a gate oxide film 15 made of SiO 2 on the substrate surface. The formation of the gate oxide film is not limited to the wet oxidation method described above, but is a pyrolysis method in which dry oxygen method using dry oxygen O 2 or a gas of dry O 2 and dry hydrogen H 2 is burned at the inlet between the cores to generate water vapor. It may be carried out using a genetic method. Next, polysilicon is deposited on the gate oxide film 15 by CVD, and pattern processing is performed by photolithography to form the gate electrode 16 (FIG. 7F).

  Next, an interlayer insulating film 19 is deposited so as to cover the entire substrate surface by CVD, and a contact opening is formed in a portion corresponding to the n-type source region 14. Subsequently, Al is deposited on the surface of the substrate by sputtering and patterned to form a source electrode 18. Next, for example, titanium Ti, nickel Ni, and gold Au are sequentially deposited by sputtering on the back surface of the SiC substrate layer 10 to form the drain electrode 17 (FIG. 7G).

The MOSFET 100 is completed through the above steps. In the above-described embodiment, the buffer layer 11 is formed by changing the flow rate of the dopant gas (N 2 ) stepwise in the CVD film forming process, but nitrogen N 2 used as the SiC dopant gas is atmospheric air. Therefore, the MOSFET structure of the present invention can be obtained by stepwise changing the degree of vacuum in the CVD chamber in the CVD film forming process. That is, the amount of dopant gas introduced is controlled by the degree of vacuum in the chamber. Specifically, when forming the lowest layer 11a having the highest impurity concentration in the buffer layer 11, the N 2 content in the processing atmosphere is increased by lowering the degree of vacuum so that the lowest impurity concentration is the lowest. When forming the upper layer 11c, the N 2 content in the processing atmosphere is reduced by increasing the degree of vacuum. When the intermediate layer 11b is formed, the intermediate vacuum degree is set. Furthermore, the buffer layer 11 can also be formed by a method other than the CVD method. Hereinafter, another method for forming the buffer layer 11 will be described.

First, for example, an n-type 4H—SiC substrate 10 having a thickness of about 300 μm doped with nitrogen N having a concentration of 5 × 10 18 cm −3 is prepared. Next, the drift layer 12 is epitaxially grown on the SiC substrate 10. Epitaxial growth is performed by a CVD method, using SiH 4 as a Si source, C 3 H 8 as a C source, and N 2 as an n-type dopant gas. A source gas and an n-type dopant gas are introduced into the reaction tube by the carrier gas H 2 to form the drift layer 12 having an impurity concentration of 5 × 10 15 cm −3 on the SiC substrate 10 heated on the susceptor. The growth temperature is, for example, 1500 ° C., and the pressure in the reaction tube is, for example, 40 Torr.

After the drift layer 12 is formed, a buffer layer 11 composed of a plurality of layers having different impurity concentrations is formed near the interface between the drift layer 12 and the SiC substrate 10 by nitrogen N multiple ion implantation. That is, a desired concentration distribution is obtained by performing ion implantation while changing the implantation energy and the dose for each layer constituting the buffer layer 11. Specifically, when forming the lowermost layer 11a adjacent to the SiC substrate layer 10 among the layers constituting the buffer layer 11, for example, ion implantation is performed with an implantation energy of 1200 KeV and a dose of 5 × 10 14 cm −2. . When forming the intermediate layer 11b, ion implantation is performed with an implantation energy of 1000 KeV and a dose of 5 × 10 13 cm −2 . When the uppermost layer 11c adjacent to the drift layer 12 is formed, ion implantation is performed with an implantation energy of 800 KeV and a dose amount of 5 × 10 12 cm −2 . In addition to the nitrogen N, phosphorus P may be used as the ion species to be implanted. FIG. 8 shows an impurity concentration distribution in a cross section taken along line BB of FIG. 4 of the MOSFET 100 including the buffer layer 11 formed by multiple ion implantation. In this production method, the implantation energy is sequentially changed for each layer constituting the buffer layer 11 to control the depth position at which the concentration peak appears, and the impurity concentration in each layer is controlled by changing the dose amount for each layer. An impurity concentration distribution as shown in FIG. 8 can be obtained. As a result, buffer layer 11 is formed near the interface between SiC substrate layer 10 and drift layer 12 and plays a role of relaxing the impurity concentration gradient of these layers. Since the subsequent manufacturing steps are the same as those described above, description thereof will be omitted.

(Second embodiment)
FIG. 9 is a sectional structural view of a unit cell of a vertical MOSFET 200 using an SiC substrate according to a second embodiment of the present invention. The basic structure of the MOSFET 200 according to the second embodiment is the same as that of the first embodiment, but the structure of the buffer layer is slightly different. That is, the buffer layer 11 provided in the MOSFET 100 of the first embodiment is composed of a plurality of layers stacked so that the impurity concentration changes stepwise. On the other hand, the structure of the buffer layer 11 ′ provided in the MOSFET 200 according to the present embodiment is configured by a single layer whose impurity concentration continuously changes according to the depth position. FIG. 10 shows the impurity concentration distribution in the cross section along the line CC of the MOSFET 200 shown in FIG. The buffer layer 11 ′ has a concentration distribution such that the impurity concentration monotonously increases as the depth position from the substrate surface increases. Further, the impurity concentration in the vicinity of the interface with drift layer 12 matches the impurity concentration in drift layer 12, and the impurity concentration in the vicinity of interface with SiC substrate layer 10 matches the impurity concentration in SiC substrate layer 10. As described above, the same effect as that of the first embodiment can be obtained also by continuously changing the impurity concentration of the buffer layer 11 ′. That is, by providing the buffer layer 11 ′ between the drift layer 12 and the SiC substrate layer 10, the electric field strength in the vicinity of the SiC substrate layer 10 (drain) where the current density becomes excessive during operation is compared with the conventional structure. Can be obtained. As a result, even when a current density excess portion occurs near the drain due to the miniaturization of the cell, electric field concentration is less likely to occur, and it is possible to increase the current and withstand voltage in the MOSFET using the SiC substrate. Become.

In order to form the buffer layer 11 'in which the impurity concentration changes continuously according to the depth as described above, it can be formed by epitaxial growth using the CVD method as in the first embodiment. That is, the concentration distribution of the buffer layer 11 ′ as shown in FIG. 10 can be obtained by continuously changing the flow rate of the dopant gas N 2 introduced together with the source gas in the CVD film forming process. Specifically, in the CVD film forming process, as the buffer layer 11 ′ is sequentially formed from the lower layer portion toward the upper layer portion, the flow rate of the dopant gas N 2 is gradually decreased so as to continuously change. Thus, the structure of the buffer layer 11 ′ according to the present embodiment can be obtained. The drift layer 12 is formed by making the flow rate of the dopant gas constant by the CVD method after the formation of the buffer layer 11 ′. In the MOSFET having the buffer layer 11 ′ formed in this way, the same function and effect as those of the first embodiment can be obtained. As another method for forming the buffer layer 11 ′, the buffer layer 11 ′ can be formed by continuously changing the degree of vacuum in the CVD chamber. Specifically, in the CVD film forming process, as the buffer layer 11 ′ is sequentially formed from the lower layer portion toward the upper layer portion, the chamber is gradually adjusted so that the nitrogen content in the CVD chamber continuously changes. The structure of the buffer layer 11 ′ of this embodiment can be obtained by increasing the degree of vacuum inside.

As is clear from the above description, according to the MOSFET of the present invention, since the buffer layer that plays a role of relaxing the impurity concentration gradient of each layer is provided between the SiC substrate layer and the drift layer, the fine structure of the cell Even if an excessive current density portion is generated during operation, the electric field concentration and current concentration in the vicinity of the drain are alleviated, and it is possible to increase the device current and increase the breakdown voltage. The MOSFET structure according to the present invention has a certain effect even when applied to a MOSFET using a normal Si substrate, but the impurity concentration in the vicinity of the interface between the SiC substrate layer and the drift layer changes sharply. When the present invention is applied to a MOSFET using a SiC substrate having the above, a remarkable effect is obtained. In the case of applying the present invention to MOSFET using conventional Si substrate, for example a phosphine buffer layer as a dopant gas used when forming by CVD (PH 3) or the like can be used.

  In the above description, the case where the present invention is applied to an N-channel MOSFET has been described as an example, but it is needless to say that the present invention can also be applied to a P-channel MOSFET by changing the dopant.

It is a cross-sectional structure diagram of an n-channel vertical MOSFET having a conventional double diffusion structure. It is a figure which shows the on-resistance reduction effect by refinement | miniaturization of a cell. It is a figure which shows the impurity concentration distribution of the cross section along the AA in FIG. It is a sectional structure figure of MOSFET using a SiC substrate which is an example of the present invention. It is a figure which shows the impurity concentration distribution of the cross section along the BB line in FIG. It is a figure which shows electric field strength distribution at the time of operation | movement of MOSFET which is an Example of this invention, and MOSFET of a conventional structure. (A)-(g) is a figure which shows the manufacturing process of MOSFET which is an Example of this invention. It is a figure which shows the impurity concentration distribution of the cross section along the BB line of MOSFET including the buffer layer formed by the multiple ion implantation which is an Example of this invention. It is sectional structure drawing of MOSFET using the SiC substrate which is the other Example of this invention. It is a figure which shows the impurity concentration distribution of the cross section along CC line in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 SiC substrate layer 11 Buffer layer 12 Drift layer 13 P-type body region 14 N-type source region 15 Gate oxide film 16 Gate electrode 17 Drain electrode 18 Source electrode

Claims (8)

  1. A substrate layer having a first conductivity type, a drift layer stacked on the substrate layer and having the first conductivity type and having an impurity concentration lower than an impurity concentration of the substrate layer, and a surface of the drift A body region having a second conductivity type different from the first conductivity type provided along the first conductivity type, and the first conductivity type formed along the surface of the body region inside the body region. A vertical MOSFET including a source region having:
    The impurity concentration is provided between the substrate layer and the drift layer and ranges from the impurity concentration of the substrate layer to the impurity concentration of the drift layer, and the impurity concentration varies depending on the depth position from the drift layer toward the substrate layer. A vertical MOSFET comprising a buffer layer having the first conductivity type which is changing so as to increase.
  2.   2. The vertical MOSFET according to claim 1, wherein the buffer layer changes such that the impurity concentration thereof increases stepwise according to a depth position from the drift layer toward the substrate layer.
  3.   The vertical MOSFET according to claim 2, wherein the buffer layer includes a plurality of layers having different impurity concentrations.
  4.   The buffer layer is characterized in that its impurity concentration changes from the upper layer portion toward the lower layer portion so as to monotonically increase in the concentration range of the drift layer impurity concentration to the substrate layer impurity concentration. Item 2. The vertical MOSFET according to Item 1.
  5.   The vertical MOSFET according to claim 1, wherein the substrate layer, the drift layer, and the buffer layer are made of SiC single crystal.
  6. It is a manufacturing method of the vertical MOSFET according to claim 1,
    Providing a substrate made of a semiconductor having the first conductivity type;
    A buffer layer forming step of introducing a source gas and a dopant gas of the first conductivity type onto the substrate and epitaxially growing the buffer layer by a gas phase reaction;
    A drift layer forming step of introducing a source gas and a dopant gas of the first conductivity type onto the buffer layer and epitaxially growing the drift layer by a gas phase reaction;
    Ion implantation of the second conductivity type impurity into the drift layer surface to form the body region;
    And ion-implanting the first conductivity type impurity into the body region to form the source region, wherein in the buffer layer forming step, the introduction amount of the dopant gas is sequentially reduced. A method for manufacturing a vertical MOSFET.
  7.   The drift layer forming step is performed by introducing the dopant gas composed of the source gas and nitrogen into a chamber in which the substrate is installed, and the amount of the dopant gas introduced is controlled by the degree of vacuum in the chamber. The method for manufacturing a vertical MOSFET according to claim 6, wherein:
  8. It is a manufacturing method of the vertical MOSFET according to claim 1,
    Providing a substrate made of a semiconductor having the first conductivity type;
    A drift layer forming step of introducing a source gas and a dopant gas of the first conductivity type onto the substrate and epitaxially growing the drift layer by a gas phase reaction;
    A buffer layer forming step of forming the buffer layer in the drift layer by ion implantation into the drift layer;
    Ion implantation of the second conductivity type impurity into the drift layer surface to form the body region;
    And ion-implanting the first conductivity type impurity into the body region to form the source region. In the buffer layer forming step, the implantation energy and the dose amount are sequentially changed to perform multiple times of ion implantation. A method for manufacturing a vertical MOSFET, wherein implantation is performed.
JP2007336781A 2007-12-27 2007-12-27 Manufacturing method of vertical MOSFET Active JP5236281B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007336781A JP5236281B2 (en) 2007-12-27 2007-12-27 Manufacturing method of vertical MOSFET

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007336781A JP5236281B2 (en) 2007-12-27 2007-12-27 Manufacturing method of vertical MOSFET

Publications (2)

Publication Number Publication Date
JP2009158788A true JP2009158788A (en) 2009-07-16
JP5236281B2 JP5236281B2 (en) 2013-07-17

Family

ID=40962468

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007336781A Active JP5236281B2 (en) 2007-12-27 2007-12-27 Manufacturing method of vertical MOSFET

Country Status (1)

Country Link
JP (1) JP5236281B2 (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009295728A (en) * 2008-06-04 2009-12-17 Hitachi Cable Ltd Silicon carbide semiconductor substrate and method of manufacturing the same
WO2011083552A1 (en) * 2010-01-08 2011-07-14 三菱電機株式会社 Epitaxial wafer and semiconductor element
WO2012165008A1 (en) 2011-06-01 2012-12-06 住友電気工業株式会社 Silicon carbide semiconductor device and method for manufacturing same
JP2013018659A (en) * 2011-07-07 2013-01-31 Mitsubishi Electric Corp Epitaxial wafer and semiconductor element
WO2014125586A1 (en) * 2013-02-13 2014-08-21 富士電機株式会社 Semiconductor device
WO2016120999A1 (en) * 2015-01-27 2016-08-04 三菱電機株式会社 Semiconductor device
JP2017139362A (en) * 2016-02-04 2017-08-10 株式会社東芝 Semiconductor device
WO2019125845A1 (en) * 2017-12-21 2019-06-27 Cree, Inc. Vertical sic semiconductor device with improved ruggedness

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57153469A (en) * 1981-03-18 1982-09-22 Toshiba Corp Insulated gate type field effect transistor
JPH0734471B2 (en) * 1987-09-24 1995-04-12 三菱電機株式会社 Field effect semiconductor device
JP2000150866A (en) * 1998-09-01 2000-05-30 Fuji Electric Co Ltd Silicon carbide n channel mos semiconductor device and its manufacture
JP2000243957A (en) * 1999-02-24 2000-09-08 Nec Corp Semiconductor device and manufacture thereof
JP2000286415A (en) * 1999-03-29 2000-10-13 Sanyo Electric Co Ltd Mosfet element and manufacture thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57153469A (en) * 1981-03-18 1982-09-22 Toshiba Corp Insulated gate type field effect transistor
JPH0734471B2 (en) * 1987-09-24 1995-04-12 三菱電機株式会社 Field effect semiconductor device
JP2000150866A (en) * 1998-09-01 2000-05-30 Fuji Electric Co Ltd Silicon carbide n channel mos semiconductor device and its manufacture
JP2000243957A (en) * 1999-02-24 2000-09-08 Nec Corp Semiconductor device and manufacture thereof
JP2000286415A (en) * 1999-03-29 2000-10-13 Sanyo Electric Co Ltd Mosfet element and manufacture thereof

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009295728A (en) * 2008-06-04 2009-12-17 Hitachi Cable Ltd Silicon carbide semiconductor substrate and method of manufacturing the same
JP5430677B2 (en) * 2010-01-08 2014-03-05 三菱電機株式会社 Epitaxial wafer and semiconductor device
WO2011083552A1 (en) * 2010-01-08 2011-07-14 三菱電機株式会社 Epitaxial wafer and semiconductor element
CN102714143A (en) * 2010-01-08 2012-10-03 三菱电机株式会社 Epitaxial wafer and semiconductor element
KR101375494B1 (en) * 2010-01-08 2014-03-17 미쓰비시덴키 가부시키가이샤 Epitaxial wafer and semiconductor element
US9059193B2 (en) 2010-01-08 2015-06-16 Mitsubishi Electric Corporation Epitaxial wafer and semiconductor element
US8564017B2 (en) 2011-06-01 2013-10-22 Sumitomo Electric Industries, Ltd. Silicon carbide semiconductor device and method for manufacturing same
WO2012165008A1 (en) 2011-06-01 2012-12-06 住友電気工業株式会社 Silicon carbide semiconductor device and method for manufacturing same
JP2013018659A (en) * 2011-07-07 2013-01-31 Mitsubishi Electric Corp Epitaxial wafer and semiconductor element
WO2014125586A1 (en) * 2013-02-13 2014-08-21 富士電機株式会社 Semiconductor device
US9595608B2 (en) 2013-02-13 2017-03-14 Fuji Electric Co., Ltd. Semiconductor device
WO2016120999A1 (en) * 2015-01-27 2016-08-04 三菱電機株式会社 Semiconductor device
JPWO2016120999A1 (en) * 2015-01-27 2017-04-27 三菱電機株式会社 Semiconductor device
US10290711B2 (en) 2015-01-27 2019-05-14 Mitsubishi Electric Corporation Semiconductor device
US10665677B2 (en) 2015-01-27 2020-05-26 Mitsubishi Electric Corporation Semiconductor device
JP2017139362A (en) * 2016-02-04 2017-08-10 株式会社東芝 Semiconductor device
WO2019125845A1 (en) * 2017-12-21 2019-06-27 Cree, Inc. Vertical sic semiconductor device with improved ruggedness
US10615274B2 (en) 2017-12-21 2020-04-07 Cree, Inc. Vertical semiconductor device with improved ruggedness

Also Published As

Publication number Publication date
JP5236281B2 (en) 2013-07-17

Similar Documents

Publication Publication Date Title
JP5741674B2 (en) Semiconductor device and manufacturing method thereof
US9559188B2 (en) Trench gate type semiconductor device and method of producing the same
US8790983B2 (en) Semiconductor device and method for manufacturing the same
US9105709B2 (en) Semiconductor device and method for manufacturing the same
US10134834B2 (en) Field effect transistor devices with buried well protection regions
US9552997B2 (en) Silicon carbide switching devices including P-type channels
TWI580052B (en) Semiconductor device having vertical charge-compensated structure and sub-surface connecting layer and method
EP2248178B1 (en) Silicon carbide semiconductor device
JP4418794B2 (en) Method for manufacturing silicon carbide semiconductor element
JP4662772B2 (en) Method for forming a MOS field effect transistor
TWI288480B (en) Vertical junction field effect transistor and manufacturing method of vertical junction field effect transistor
JP4525958B2 (en) Manufacturing method of semiconductor device
US9117836B2 (en) Silicon carbide semiconductor device and manufacturing method thereof
JP4666200B2 (en) Method for manufacturing SiC semiconductor device
JP4938157B2 (en) Semiconductor device and manufacturing method thereof
CN101578705B (en) Silicon carbide semiconductor device and method for manufacturing the same
US7982224B2 (en) Semiconductor device with silicon carbide epitaxial layer including dopant profiles for reducing current overconcentration
JP4903439B2 (en) Field effect transistor
JP5544918B2 (en) Silicon carbide insulated gate type semiconductor device and manufacturing method thereof
US7846828B2 (en) Semiconductor device and method for fabricating the same
JP3784393B2 (en) Semiconductor device and manufacturing method thereof
JP5884617B2 (en) Silicon carbide semiconductor device and manufacturing method thereof
JP2004247545A (en) Semiconductor device and its fabrication process
US8658503B2 (en) Semiconductor device and method of fabricating the same
US9012984B2 (en) Field effect transistor devices with regrown p-layers

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20101101

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20121225

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20121227

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130218

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20130312

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20130327

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

Ref document number: 5236281

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20160405

Year of fee payment: 3