WO2013121954A1 - Graphene field-effect transistor and graphene semiconductor member - Google Patents
Graphene field-effect transistor and graphene semiconductor member Download PDFInfo
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- WO2013121954A1 WO2013121954A1 PCT/JP2013/052766 JP2013052766W WO2013121954A1 WO 2013121954 A1 WO2013121954 A1 WO 2013121954A1 JP 2013052766 W JP2013052766 W JP 2013052766W WO 2013121954 A1 WO2013121954 A1 WO 2013121954A1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
-
- C—CHEMISTRY; METALLURGY
- C01—INORGANIC CHEMISTRY
- C01B—NON-METALLIC ELEMENTS; COMPOUNDS THEREOF; METALLOIDS OR COMPOUNDS THEREOF NOT COVERED BY SUBCLASS C01C
- C01B32/00—Carbon; Compounds thereof
- C01B32/05—Preparation or purification of carbon not covered by groups C01B32/15, C01B32/20, C01B32/25, C01B32/30
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
Definitions
- the present invention relates to a graphene field effect transistor and a graphene semiconductor member.
- Graphite is a kind of carbon allotrope, and is a laminated film in which a six-membered ring unit composed of sp 2 carbon hybrid orbitals is two-dimensionally expanded.
- Graphene is defined as a single layer film of graphite as shown in FIG.
- the graphene energy (E) -momentum (p) (or wave number k) relationship (dispersion curve) is linear, and is completely symmetric with respect to both the E and p axes.
- FIG. 10B in the case of a general semiconductor, both the conduction band and the valence band have a parabolic shape, and the valence band has a gentler slope.
- m * effective mass of electrons in the conduction band and holes in the valence band
- a current IDS flowing between a drain and a source is expressed by the following equation.
- W is the width of the gate electrode (depth)
- e is the elementary charge
- n represents carrier density
- C is the capacitance between the gate insulating film
- V DS is the drain - source voltage
- L G is the gate electrode Length.
- n increases the electrostatic capacitance C between the gate insulating film, or to increase the carrier mobility mu, geometrically shorter L G (miniaturization) or Then, the carrier velocity v may be increased by increasing the electric field strength.
- the signal processing speed (frequency) is represented by the following equation, where f T (cutoff frequency) is defined as a frequency at which the current amplification factor falls to 1 without being able to follow the current response.
- f T cutoff frequency
- V GS and C GS are a gate-source voltage and a capacitance, respectively. From this equation, it can be seen that if the capacitance C between the gate insulating films and the carrier mobility ⁇ are large, a high operating frequency can be obtained.
- the field effect transistor using a conventional Si has reached the miniaturization limit, can not be reduced L G more, alternate channel materials have been desired large mu, graphene is one of the promising materials is there.
- the so-called GFET graphene field effect transistor
- GFET graphene field effect transistor
- the ohmic junction resistance (contact resistance) between the source / drain electrode and the graphene channel is reduced, the resistance between the gate and the drain (source) (access resistance) is reduced, It is necessary to solve various problems such as establishment of p / n-channel doping technology to solve the problem and gate stack / channel interface control.
- the current cannot be made zero, the current ON / OFF ratio necessary for digital circuit application cannot be obtained, digital switching operation is difficult, and high speed Problems such as the lack of the saturation region necessary for conversion must also be solved.
- III-V compound semiconductor devices represented by GaAs use a high electron mobility transistor (HEMT) structure in which a carrier-doped layer and a carrier-running layer (channel) are separated.
- HEMT high electron mobility transistor
- This is a semiconductor in which a semiconductor layer having a wider band gap and lower electron affinity is stacked on a channel material, and impurities are doped in layers ( ⁇ -dope) at a position slightly away from the channel in the layer. Is formed, and carriers from there are dropped at the interface with the channel and stored (modulation doping). This is because the channel is not directly modified, so that the introduced carrier is not impurity-scattered in the channel, and the carrier mobility in the channel does not decrease.
- DLC diamond-like carbon
- This DLC is doped with a DLC film formed by mixing a different element gas with a carbon-based gas, mainly for mechanical engineering purposes such as low friction, and incorporating the different element into the entire film (for example, Non-Patent Document 4 or 5), by changing the film forming conditions to control the dielectric constant of the DLC, the DLC is mainly made to have a low dielectric constant (low- ⁇ ) and used for an interlayer insulating film (for example, Non-Patent Document 6 or 7), in order to reduce the interface state, a metal element is doped into DLC, and DLC is used as a conductive channel thin film material for a thin film transistor (TFT) (for example, Non-Patent Documents 8 to 8). 11).
- TFT thin film transistor
- PA-PECVD photoelectron-controlled plasma CVD
- Patent Documents 5 to 7 or non-patent documents Patent Documents 5 to 7 or non-patent documents.
- Reference 12 The PA-PECVD method is a DC plasma film forming method using photoelectrons generated by ultraviolet light irradiation on a sample substrate as a trigger, unlike a method using normal floating electrons as a plasma trigger. Since the plasma generation is limited to the light irradiation site, the film formation site can be precisely controlled, and the generation of soot that becomes a major enemy to the clean room process can be prevented.
- a PA-PECVD apparatus used in the PA-PECVD method is shown in FIG.
- the relative dielectric constant of the DLC is about 1 to 5 depending on the concentration ratio of the CH 4 gas in the growth atmosphere (Ar + CH 4 ).
- the possibility of being able to control and modulate in a wide range up to the vicinity is shown (for example, see Non-Patent Document 13).
- An object of the present invention is to provide a graphene field effect transistor and a graphene semiconductor member capable of realizing a digital switching operation.
- the graphene field effect transistor according to the present invention is electrically connected to a channel layer made of graphene, an insulator layer provided on the channel layer and made of a material having low reactivity with graphene, and the channel layer. And a source electrode and a drain electrode which are arranged apart from each other at a position sandwiching the insulator layer, and a gate electrode provided on the insulator layer, and the insulator layer has a carrier in the channel layer. It has the thin film-like modulation
- the thin film-like modulation doped portion in the insulator layer provided on the channel layer made of graphene can supply carriers to the channel layer.
- the density can be increased.
- the channel layer is not directly modified, carriers are not scattered by impurities in the channel layer, and carrier mobility does not decrease.
- the insulator layer is made of a material having low reactivity with graphene, the channel layer is not damaged even if the insulator layer is provided directly on the channel layer made of graphene.
- the graphene field-effect transistor according to the present invention can increase the carrier density and the carrier mobility without directly damaging the graphene channel layer as in the HEMT structure, and can improve the operation speed. it can.
- the channel layer is made of graphene, so that the operation speed is higher than that of a conventional FET using Si or the like, and the operation in the terahertz region that cannot be realized by the conventional FET is achieved. Can be possible. For this reason, it is expected that the amount of information communication in the information society that will develop in the future can be covered.
- the modulation doped portion is formed by doping an impurity element (hetero element) in the insulator layer.
- an insulator layer and a material having low reactivity with graphene are carriers in the channel layer with respect to the channel layer, even if the material is in direct contact with the channel layer made of graphene. It is a material that does not damage to the extent that hinders movement.
- 1) chemical reactivity with graphene, 2) stress due to lattice mismatch or surface non-planarity with graphene, generation of defects and defect levels, and 3) scattering effect at the interface with graphene 4) is a material that is mechanically, chemically, and electrically stable against environmental changes such as temperature and humidity. Specific examples include diamond-like carbon (DLC) and hBN (hexagonal Boron Nitride).
- the thin film-like modulation dope portion only needs to be thinly distributed at least at a certain local position in the thickness direction of the insulator layer, and the distribution is uniform and planar.
- the distribution may be uneven and formed in an island shape, or may be formed in a stripe shape.
- the modulation doped portion is provided between the channel layer with a distance capable of supplying carriers to the channel layer by a tunnel effect.
- the modulation doped portion is provided with a distance of 3 to 6 nm between the channel layer and the channel layer.
- carriers can be efficiently supplied from the modulation doped portion to the channel layer without directly modifying the channel layer. For this reason, the carrier density and carrier mobility can be particularly effectively increased, and the operation speed can be improved.
- the insulator layer is preferably made of diamond-like carbon.
- Diamond-like carbon is an amorphous carbon material composed of sp 2 carbon, sp 3 carbon, and hydrogen, and has a high chemical affinity for graphene because it is the same carbonaceous material as graphene. Specifically, 1) chemical reactivity with graphene, 2) generation of stresses and defects due to lattice mismatch and surface non-uniformity with graphene, and 3) graphene / insulator interface Scattering effects are extremely low, and 4) they are mechanically, chemically and electrically stable against environmental changes such as temperature and humidity.
- the insulator layer can be provided directly on the channel layer without damaging the channel layer made of graphene. For this reason, a decrease in carrier density and carrier mobility can be prevented, and a high operating speed can be realized. Moreover, since DLC forms an amorphous and flat film, an insulator layer having a uniform film quality can be obtained.
- the DLC is made of an insulating material, and is preferably made of, for example, ta-C, ta-C: H, or aC: H.
- the insulator layer has a high dielectric constant portion extending from immediately below the gate electrode to the channel layer, and the high dielectric constant portion, the source electrode, and the drain electrode,
- the low dielectric constant portion may have a lower dielectric constant than the high dielectric constant portion, and the modulation doped portion may be included in the low dielectric constant portion.
- the high dielectric constant portion can provide a high electrostatic induction effect directly below the gate electrode, and channel interface control can be performed with high accuracy.
- the low dielectric constant portion can reduce the parasitic capacitance between the respective electrodes, and can increase the speed. Since the modulation doped portion is provided between the high dielectric constant portion and the source and drain electrodes, carriers can be effectively supplied to the channel layer in the access region, and the access resistance can be reduced.
- the insulator layer may have the modulation doped portion in the high dielectric constant portion.
- the modulation doped portion in the high dielectric constant portion.
- Pnp junctions or npn junctions can be made. Thereby, current rectification in the channel layer can be provided, and digital switching operation can be realized.
- the modulation dope portions of the low dielectric constant portion and the high dielectric constant portion may be the same distance from the channel layer or may be different.
- the graphene semiconductor member according to the present invention includes a channel layer made of graphene and an insulator layer formed on the channel layer and made of a material having low reactivity with graphene. It has a thin film-like modulation doped portion capable of supplying carriers to the channel layer.
- the graphene semiconductor member according to the present invention can be used as a member for a touch panel, for example, by using a highly transparent material for the insulator layer.
- the graphene semiconductor member according to the present invention can constitute the graphene field effect transistor according to the present invention by connecting the source electrode, the drain electrode, and the gate electrode.
- the graphene semiconductor member according to the present invention since the thin film-like modulation doped portion in the insulator layer provided on the channel layer made of graphene can supply carriers to the channel layer, the carrier density of the channel layer Can be increased. At this time, since the channel layer is not directly modified, impurities are not scattered even if carriers are moved in the channel layer, and the carrier mobility is not lowered. In addition, since the insulator layer is made of a material having low reactivity with graphene, the channel layer is not damaged even if the insulator layer is provided directly on the channel layer made of graphene. As described above, the graphene semiconductor member according to the present invention can increase the carrier density and the carrier mobility without directly damaging the graphene channel layer as in the HEMT structure, and can improve the operation speed. .
- the modulation dope portion is provided between the channel layer with a distance capable of supplying carriers to the channel layer by a tunnel effect. It is preferable that a distance of 3 to 6 nm is provided between them. In this case, carriers can be efficiently supplied from the modulation doped portion to the channel layer without directly modifying the channel layer. For this reason, the carrier density and carrier mobility can be particularly effectively increased, and the operation speed can be improved.
- the insulator layer is made of, for example, diamond-like carbon or hBN having low reactivity with graphene, and particularly preferably made of diamond-like carbon.
- diamond-like carbon has a high chemical affinity for graphene
- an insulator layer is provided directly on the channel layer without damaging the channel layer made of graphene. Can do. For this reason, a decrease in carrier density and carrier mobility can be prevented, and a high operating speed can be realized.
- DLC forms an amorphous and flat film, an insulator layer having a uniform film quality can be obtained.
- the DLC is transparent to visible light and infrared light, and can increase carrier density and carrier mobility without lowering transparency, so that it can be used as a low-resistance touch panel.
- the DLC is made of an insulating material, and is preferably made of, for example, ta-C, ta-C: H, or aC: H.
- a field effect transistor and a graphene semiconductor member can be provided.
- the CO of the DLC film withstand voltage when the CO 2 gas is introduced in addition to CH 4 + Ar. It is a graph which shows 2 flow rate ratio dependence.
- 4 is a graph showing (a) SIMS element depth profile and (b) I DS -V GS characteristics of an example ( ⁇ -doped element) of a graphene field effect transistor corresponding to FIG. 5 is a graph showing (a) SIMS element depth profile and (b) I DS -V GS characteristics of an example (interface adsorption element) of a graphene field effect transistor corresponding to FIGS.
- FIG. 11 is a schematic side view showing a PA-PECVD apparatus (cited from Non-Patent Document 12).
- FIG. 1 to 8 show a graphene field effect transistor and a graphene semiconductor member according to an embodiment of the present invention.
- a graphene field effect transistor 10 includes a channel layer 11 made of graphene provided on a substrate, and a source electrode 12 and a drain electrode 13 provided on the channel layer 11 and insulated from each other. It has a body layer 14 and a gate electrode 15 provided on the insulator layer 14.
- the source electrode 12 and the drain electrode 13 are disposed apart from each other at both ends of the channel layer 11.
- the source electrode 12 and the drain electrode 13 are electrically connected to the channel layer 11.
- the insulator layer 14 is made of diamond-like carbon (DLC) having low reactivity with graphene, and is provided between the source electrode 12 and the drain electrode 13 and around the source electrode 12 and the drain electrode 13. .
- the insulator layer 14 is doped in the DLC with an impurity such as oxygen or nitrogen that is provided in parallel to the surface of the channel layer 11 and has a thin film-like shape and capable of supplying carriers to graphene. It has a modulation dope section 14a.
- the modulation doped portion 14a is provided between the channel layer 11 and a distance that can supply carriers to the channel layer 11 by a tunnel effect. In a specific example shown in FIG.
- the modulation dope portion 14 a is provided with a distance of about 5 nm between the channel layer 11. Note that the thin film-like modulation doped portion 14a only needs to be thinly distributed at a certain local position in the thickness direction of the insulator layer 14, and the distribution is uniform and formed in a planar shape. Alternatively, the distribution may be uneven and formed in an island shape, or may be formed in a stripe shape.
- the modulation dope portion 14 a can supply carriers to the channel layer 11, so that the carrier density of the channel layer 11 can be increased. At this time, since the channel layer 11 is not directly modified, carriers are not scattered in the channel layer 11 and the carrier mobility does not decrease. Further, since the insulator layer 14 is made of DLC having high chemical affinity for graphene, the channel layer 11 is damaged even if the insulator layer 14 is provided directly on the channel layer 11 made of graphene. Absent. As described above, the graphene field-effect transistor 10 can increase the carrier density and carrier mobility without directly damaging the graphene channel layer 11 unlike the HEMT structure, and can improve the operation speed.
- the graphene field-effect transistor 10 has a channel layer 11 made of graphene, so that a higher operating speed than that of a conventional FET using Si or the like can be obtained, and operation in a terahertz region that cannot be realized by a conventional FET is possible. can do. For this reason, it is expected that the amount of information communication in the information society that will develop in the future can be covered.
- the graphene field-effect transistor 10 is, for example, a next-generation ultra-high-speed central processing unit (CPU) that significantly improves the calculation speed of a computer, an ultra-compact ultra-high-speed communication device such as a smartphone that significantly increases communication capacity, and an available radio wave region. It can be used for terahertz wave transmitters.
- CPU central processing unit
- the graphene semiconductor member according to the embodiment of the present invention has a configuration in which the gate electrode 15, the source electrode 12, and the drain electrode 13 of the graphene field effect transistor 10 are removed.
- the graphene semiconductor member according to the embodiment of the present invention not only constitutes the graphene field-effect transistor 10, but also has high DLC transparency, and thus can be used as a member for a touch panel.
- the graphene field-effect transistor 10 was manufactured by directly forming a DLC thin film as a top gate insulating film (insulator layer 14) on the graphene of the channel layer 11, and the characteristics and the like were evaluated. .
- the graphene field effect transistor 10 was manufactured by the following method. As the channel layer 11, a 6H-SiC (0001) substrate (Si surface) was ultrahigh-vacuum annealed at 1700 ° C. for 15 minutes, thereby producing an epitaxial several-layer graphene (epitaxial five-layer graphene, EFLG) on the substrate. .
- Gold (Au) -made gate electrode 15, source electrode 12, and drain electrode 13 were produced using Pt as the ohmic contact metal.
- the insulator layer 14 made of DLC is formed on the channel layer 11 made of graphene by the photoelectron-controlled plasma CVD (PA-PECVD) method using CH 4 / Ar gas.
- PA-PECVD photoelectron-controlled plasma CVD
- the film was formed directly on the top.
- the manufactured graphene field effect transistor 10 has a channel width (W C ) of 11 ⁇ m, a channel length (L C ) of 6 ⁇ m, and a gate length (L G ) of 5 ⁇ m.
- the film thickness of the insulator layer 14 was estimated to be 48 nm from the depth profile of secondary ion mass spectrometry (SIMS). From the capacitance (CV) measurement, it was determined that the relative dielectric constant was 5.1 and the equivalent oxide thickness (EOT) was 37 nm.
- the Dirac voltage (V Dirac ) which is a charge neutral point, is theoretically given by (1/2) V DS , but slightly shifts positive in FIG. This shows that the channel layer 11 has weak p property.
- FIG. 3 shows a Raman spectrum of the 2D band region of the graphene channel layer 11.
- FIG. 3 when compared with the spectrum immediately after graphene growth (As-grown), it can be seen that the 2D band peak after deposition of the DLC insulator layer 14 (After DLC forming) is shifted to a high wavenumber. . This suggests that the DLC insulator layer 14 is p-doped from the graphene channel layer 11.
- the cause of the ambipolar characteristics in the graphene on the 6H-SiC substrate exhibiting strong n-type characteristics is thought to be “unintentional p-doping” from the DLC insulator layer 14 to the graphene channel layer 11.
- FIG. 4 shows a SIMS element depth profile of the DLC insulator layer 14.
- the depth (Depth) in the vicinity of the graphene channel layer 11 is 40 to 56 nm and a rapid increase in the number of oxygen atoms is observed, the unintentional p-doping is performed in the insulator layer 14. It is thought that it originates from the oxygen atom. This oxygen atom is considered to be derived from water (H 2 O) molecules remaining in the chamber of the PA-PECVD apparatus used for film formation.
- the amount of carbon / hydrogen constituting the DLC insulator layer 14 is uniformly obtained in the depth direction of the layer. Can be expected.
- FIG. 5 shows a band prediction diagram of the graphene field-effect transistor 10 predicted from the above results. As shown in FIG. 5, it is expected that holes in the DLC insulator layer 14 (gate insulating film) are supplied to the graphene channel layer 11 to tunnel through the depletion layer barrier.
- the region where the concentration of Si atoms suddenly increases and settles to a certain high value is the SiC substrate. Since the position where the Si atom reaches a high value and the position where the concentration of C atoms starts to rise slightly coincide with the position of the dotted line in FIG. 4, the position of the dotted line is the graphene channel on the SiC substrate. It can be identified as the interface between the layer 11 and the DLC insulator layer 14. Note that the thickness of the graphene channel layer 11 is sub-nm and cannot be determined in FIG.
- the concentration of oxygen atoms is the highest value at the interface between the DLC insulator layer 14 and the graphene channel layer 11 / SiC substrate, the oxygen atoms are localized at the interface position in direct contact with the graphene, It can be seen that they are distributed in both directions of the SiC substrate and the DLC insulator layer 14 while drawing a tail. Note that the seepage to the SiC substrate side is due to a knock on effect or a mixing effect due to etching ions.
- the carrier supply capacity to the graphene channel layer 11 from the oxygen impurity existing in the vicinity of the interface is the highest, and at the same time, the oxygen impurity present in the interface is Since it acts strongly as a scattering factor, it is presumed to inhibit the transport properties of carriers traveling in the graphene channel layer 11.
- the insulator layer 14 can be formed with high accuracy, such as the formation of the modulation doped portion 14a, and the graphene shown in FIGS.
- the field effect transistor 10 can be manufactured with high quality and high accuracy. An example is shown below.
- a mixed gas source of CH 4 and Ar is generally introduced into the PA-PECVD apparatus chamber.
- a Xe excimer lamp By irradiating ultraviolet rays with a Xe excimer lamp, atoms in the deposition substrate are excited and photoelectrons are emitted from the substrate surface.
- CH 4 is ionized by the photoelectrons, and the ionized carbon ions are deposited in an amorphous state on the substrate surface.
- the film forming speed is controlled to be constant by the degree of vacuum, temperature, gas mixing ratio and flow rate.
- an oxygen impurity that acts as an acceptor can be obtained by opening a valve of a CO 2 gas source prepared in advance and introducing CO 2 gas into the chamber. Can be implanted as a dopant. The doping concentration can be controlled by the flow rate of CO 2 gas.
- the DLC insulator layer 14 having the modulation doped portion 14a can be formed by closing the valve of the CO 2 gas source and continuously forming the DLC. it can.
- an oxygen impurity gas source H 2 O may be used in addition to CO 2 .
- the modulation dope portion 14a doped with nitrogen impurities acting as a donor.
- the modulation doped portion 14a having a thickness of several nanometers can be formed at a position in the DLC insulator layer 14 that is about 10 nm away from the interface with the graphene channel layer 11.
- the impurity atoms in the modulation doped portion 14a are not in direct contact with the graphene, they do not contribute to the carriers in the graphene channel layer 11 as impurity scattering factors. For this reason, it cannot be a factor that hinders the carrier transport characteristics in the graphene channel layer 11.
- the impurity atoms have a hole carrier supply capability with respect to graphene, a depletion layer at the interface between the DLC insulator layer 14 and the graphene channel layer 11 accompanying the curvature of the band of the DLC insulator layer 14
- holes in the DLC insulator layer 14 can be quantum mechanically tunneled to the graphene channel layer 11, and a desired effect can be obtained. That is, the carrier density and the carrier mobility can be increased without directly damaging the graphene channel layer 11, and the operation speed can be improved.
- the above-described oxygen impurity atoms have almost no ability to supply hole carriers into the valence band at room temperature simply by being present in the DLC.
- the unit of the horizontal axis in FIG. 6 is SCCM (Standard Cubic Centimeter per Minute), and indicates the flow rate (cm 3 ) per minute under an environment of 0 ° C. and 1 atm.
- SCCM Standard Cubic Centimeter per Minute
- the introduction of oxygen impurities improves the insulating properties of DLC, which indicates that oxygen impurities do not have a carrier supply capability for DLC. This is because the activation energy required for ionization of oxygen impurities to capture electrons (thus supplying holes to the valence band) is higher than thermal energy (about 26 meV at room temperature). it is conceivable that.
- the DLC insulator layer 14 formed on the graphene has an ability to supply holes by oxygen impurities. As shown in FIG. 5, this is achieved by bending of the conduction band and valence band of DLC caused by the difference in electron affinity between graphene and deposited DLC. That is, when applying a negative bias to the gate electrode, the Fermi level E F of the gate electrode is raised by applying bias amount, with it, DLC bands gate electrode end is lifted, as shown in FIG. 5 is a graphene interface Band bending occurs.
- the energy level of the oxygen impurity and the value of the DLC are accompanied by the curvature of the band.
- the energy difference from the upper end of the electron band (VBM) is effectively reduced by the inclination of the band.
- this energy difference falls below the activation (ionization) energy of the oxygen impurity atoms, electrons in the valence band are captured and holes are generated in the valence band (“1” in FIG. 5).
- the thinning of the depletion layer barrier at the DLC-graphene interface accompanying the curvature of the DLC band enables a quantum mechanical tunnel from DLC to graphene, thereby supplying holes to the graphene channel layer 11. ("2" in FIG. 5).
- the distance between the interface of the graphene channel layer 11 and the modulation doped portion 14a needs to be set narrow so that carriers can tunnel to the graphene in a room temperature operating environment. Since the spread of the electron wave function is generally about 10 nm at room temperature, the interval needs to be set to about 10 nm or less in order to have a sufficiently high quantum mechanical tunnel probability. In addition, in the supply of hole carriers accompanying the curvature of the band of the DLC insulator layer 14 in the vicinity of the interface of the graphene channel layer 11, the upper end (VBM) of the valence band is high, and the region away from the interface of the graphene channel layer 11 is used.
- the carrier supply region since the carrier supply region has an expansion, it is desirable that the carrier supply region be formed in a region closer to the interface of the graphene channel layer 11 by the expansion.
- the position that can be closest to the interface of the graphene channel layer 11 needs to be set at a position where the depth distribution of oxygen impurity atoms can be sufficiently attenuated at the interface of the graphene channel layer 11. This closest position also depends on the controllability of the impurity concentration distribution of the manufacturing apparatus used for film formation. Assuming the above points and the current film forming apparatus, it is desirable to form the modulation doped portion 14a at a position of about 3 to 6 nm from the interface of the graphene channel layer 11.
- a graphene field effect transistor 10 (hereinafter referred to as “ ⁇ -doped element”) having a structure corresponding to FIG. 1A and a DLC insulator layer 14 similar to that shown in FIGS.
- a graphene field effect transistor 10 (hereinafter referred to as an “interface adsorbing element”) having a structure in which many oxygen impurity atoms are localized at the interface between the graphene channel layer 11 and the graphene channel layer 11 is formed on the same substrate, and the characteristics of both are compared. Verified.
- FIG. 7 shows the SIMS element depth profile and I DS -V GS characteristics of the ⁇ -doped element.
- FIG. 8 shows the SIMS element depth profile and I DS -V GS characteristics of the interface adsorption element.
- the thickness of the DLC insulator layer 14 can be identified as about 44 nm (position of the dotted line in FIG. 7A). Further, the concentration peak of oxygen impurity atoms is located in the DLC insulator layer 14 by about 6 nm from the interface of the graphene channel layer 11, and it can be confirmed that the modulation doped portion 14a can be formed. The concentration distribution of oxygen impurity atoms spreads in the thickness direction and cannot be completely reduced even at the interface of the graphene channel layer 11, but a situation close to the structure shown in FIG.
- the thickness of the DLC insulator layer 14 is about 31 nm (the position of the dotted line in FIG. 8A), and the ⁇ shown in FIG. It is thinner than the doping element, and the peak of the oxygen impurity atom concentration is located at the interface between the DLC insulator layer 14 and the graphene channel layer 11 as in FIG. This peak is considered to be due to adsorbed water (H 2 O) as shown in FIG. 4 as indicated by the circles (broken lines) in FIG.
- the gate capacitance C due to the gate insulating film is a simple parallel plate approximation
- the oxygen impurity concentration peak is smaller than the gate capacitance C of the interface adsorption element located at the interface of the graphene channel layer 11.
- the mutual conductance g m is proportional to the gate capacitance C and the carrier mobility ⁇ as described above. Further, the carrier mobility ⁇ is proportional to the average lifetime ⁇ of carriers. From these, the following two things are inferred.
- the carrier mobility ⁇ of the ⁇ -doped element is higher than that of the interface adsorption element.
- the effective gate capacitance C of the ⁇ -doped element is higher than the gate capacitance value assuming a simple parallel plate approximation due to the carrier injection effect from the modulation doped portion 14a. Since the oxygen impurity concentration at the interface of the graphene channel layer 11 is low in the ⁇ -doped element, it is easily inferred that carrier scattering is reduced and that it has a longer average lifetime and thus a higher carrier mobility ⁇ . At the same time, it is presumed that the carrier concentration in the graphene channel layer 11 can be increased with the application of the gate bias due to the carrier supply capability of oxygen impurities.
- the insulator layer 14 has a high dielectric constant portion (high- ⁇ film) 14 b extending from immediately below the gate electrode 15 to the channel layer 11.
- a low dielectric constant portion (low- ⁇ film) 14c having a dielectric constant lower than that of the high dielectric constant portion 14b is provided between the high dielectric constant portion 14b and the source electrode 12 and the drain electrode 13.
- the modulation dope part 14a may be included in 14c.
- the high dielectric constant portion 14b and the low dielectric constant can be obtained by applying the technique described in Non-Patent Document 13 and using the selective etching technique by light exposure or electron beam exposure used in a normal FET manufacturing process.
- a DLC insulator layer 14 having a rate portion 14c can be formed.
- a DLC film having a high dielectric constant is first formed on the entire surface of the substrate, and the DLC film in a region other than directly under the gate electrode is removed by exposure and etching in which an intrinsic channel region directly under the gate electrode is masked with a resist film.
- a DLC film having a low dielectric constant is formed on the entire surface, and the resist film in the intrinsic channel region immediately below the gate electrode is removed by lift-off, thereby forming a DLC composed of the high dielectric constant portion 14b and the low dielectric constant portion 14c.
- An insulator layer 14 can be formed.
- the high dielectric constant portion 14b can provide a high electrostatic induction effect directly below the gate electrode 15, and the channel interface can be controlled with high accuracy. Further, the low dielectric constant portion 14c can reduce the parasitic capacitance between the electrodes, and can increase the speed. Since the modulation doped portion 14a is provided between the high dielectric constant portion 14b and the source electrode 12 and the drain electrode 13, carriers can be effectively supplied to the channel layer 11 in the access region, and the access resistance is reduced. can do.
- the insulator layer 14 may have the modulation doped portion 14a in the high dielectric constant portion 14b.
- the method of forming the modulation dope portion 14a in the above-described PA-PECVD method can be realized by introducing each of the high dielectric constant portion 14b and the low dielectric constant portion 14c during film formation.
- a high carrier density and a high mobility can be obtained by distinguishing the polarities of the modulation doped portion 14a of the low dielectric constant portion 14c and the high dielectric constant portion 14b from p-type and n-type, or n-type and p-type, respectively. While maintaining, a pnp junction or an npn junction can be made. Thereby, the current rectification in the channel layer 11 can be provided, and a digital switching operation can be realized.
- the modulation dope portions 14a of the low dielectric constant portion 14c and the high dielectric constant portion 14b may be the same distance or different from the channel layer 11.
- the graphene field effect transistor 10 manufactured with high quality and high accuracy as shown in FIGS. 1A to 1C has oxygen impurities present at the interface between the insulator layer 14 and the graphene channel layer 11.
- the operation speed is extremely high. It is thought that it shows high performance.
Abstract
[Problem] To provide a graphene field-effect transistor and a graphene semiconductor member that can increase carrier density and mobility without directly damaging a graphene channel to improve operation speed, can reduce an access resistance, and can achieve a digital switching operation.
[Solution] An insulator layer (14) is formed of diamond-like carbon having a low reactivity with graphene and provided on a channel layer (11) formed of graphene. The insulator layer (14) has a thin-film-like modulation-doped portion (14a) capable of supplying carriers to the channel layer (11) by a tunnel effect. A source electrode (12) and a drain electrode (13) are electrically connected to the channel layer (11) and disposed apart from each other on mutually opposite sides of the insulator layer (14). A gate electrode (15) is provided on the insulator layer (14).
Description
本発明は、グラフェン電界効果トランジスタおよびグラフェン半導体部材に関する。
The present invention relates to a graphene field effect transistor and a graphene semiconductor member.
グラファイトは炭素同素体の一種であり、ｓｐ２炭素混成軌道から成る六員環ユニットが２次元展開したものの積層膜である。グラフェン（Ｇｒａｐｈｅｎｅ）は、図９に示すように、そのグラファイトの単層膜として定義される。図１０（ａ）に示すように、グラフェンのエネルギー（Ｅ）－運動量（ｐ）（もしくは波数ｋ）の関係（分散曲線）は直線形状となり、Ｅ、ｐ両軸に対して完全対称となる。一方、図１０（ｂ）に示すように、一般の半導体の場合、伝導帯および価電子帯共に放物線形状となり、かつ価電子帯の方が、傾きが緩やかである。古典的運動エネルギーの式から、キャリアの有効質量ｍ＊（伝導帯における電子および価電子帯における正孔の実効的な質量）を求めると、次式のようになる。
Graphite is a kind of carbon allotrope, and is a laminated film in which a six-membered ring unit composed of sp 2 carbon hybrid orbitals is two-dimensionally expanded. Graphene is defined as a single layer film of graphite as shown in FIG. As shown in FIG. 10A, the graphene energy (E) -momentum (p) (or wave number k) relationship (dispersion curve) is linear, and is completely symmetric with respect to both the E and p axes. On the other hand, as shown in FIG. 10B, in the case of a general semiconductor, both the conduction band and the valence band have a parabolic shape, and the valence band has a gentler slope. When the effective mass m * (effective mass of electrons in the conduction band and holes in the valence band) is obtained from the classical kinetic energy equation, the following equation is obtained.
すなわち、一般の半導体の場合には、Ｅ－ｐ（ｋ）分散曲線の傾きがきついほど、キャリアは軽くなって動きやすくなる。価電子帯の傾きは伝導帯のものより緩いので、正孔は電子よりも重く、動きにくい。
That is, in the case of a general semiconductor, the tighter the slope of the Ep (k) dispersion curve, the lighter the carrier and the easier it is to move. Since the slope of the valence band is gentler than that of the conduction band, holes are heavier than electrons and difficult to move.
ところがグラフェンの場合、分散曲線が直接形状のために、このような古典的な考え方は意味を成さない。グラフェンの場合は、バンド構造の線形分散の帰結として、電子・正孔ともにニュートリノ様の質量ゼロの相対論粒子として振る舞う（ｍａｓｓｌｅｓｓ Ｄｉｒａｃ Ｆｅｒｍｉｏｎ）。これにより、グラフェンのキャリア移動度μは、電子・正孔共に、２００，０００ｃｍ２／Ｖｓという途方もなく大きい値となる。なお、一般の半導体で頻繁に使用されるＳｉでは、μ＝１４５０ｃｍ２／Ｖｓ（電子）、ＧａＡｓでは、μ＝９２００ｃｍ２／Ｖｓ（電子）である。
However, in the case of graphene, such a classical idea does not make sense because the dispersion curve is directly in shape. In the case of graphene, as a result of linear dispersion of the band structure, both electrons and holes behave as neutrino-like massless relativistic particles (massless dirac fermion). As a result, the carrier mobility μ of graphene is a tremendously large value of 200,000 cm 2 / Vs for both electrons and holes. Note that it is the Si is frequently used in general semiconductor, μ = 1450cm 2 / Vs (electrons), the GaAs, μ = 9200cm 2 / Vs ( electrons).
一般に電子デバイスを作製する場合、用いる材料のキャリア移動度μが最も重要な要素となる。キャリアの速度ｖは、ｖ＝μＥ（ここで、Ｅはキャリアにかかる電界強度）と表されるため、μが大きいほどキャリア動作は速くなり、高い応答速度（周波数）が得られる。
In general, when manufacturing an electronic device, the carrier mobility μ of the material used is the most important factor. Since the carrier velocity v is expressed as v = μE (where E is the electric field strength applied to the carrier), the larger the μ, the faster the carrier operation and the higher the response speed (frequency).
電子デバイスの基本ユニットの一つである電界効果トランジスタ（ＦＥＴ）では、ドレイン－ソース間に流れる電流ＩＤＳは、次式のように表される。
ここで、Ｗはゲート電極の幅（奥行）、ｅは電荷素量、ｎはキャリア密度、Ｃはゲート絶縁膜間の静電容量、ＶＤＳはドレイン－ソース間電圧、ＬＧはゲート電極の長さである。ＶＧＳとＶＤＳが一定の条件下で、ＩＤＳを大きくしようとした場合、キャリア密度ｎを高くするか、キャリア速度ｖを高くすればよい。より具体的には、ゲート絶縁膜間の静電容量Ｃを増大してキャリア密度ｎを高くするか、キャリア移動度μを大きくしたり、幾何学的にＬＧを短く（微細化）したりして電界強度を大きくすることにより、キャリア速度ｖを高くすればよい。
In a field effect transistor (FET) which is one of basic units of an electronic device, a current IDS flowing between a drain and a source is expressed by the following equation.
Here, W is the width of the gate electrode (depth), e is the elementary charge, n represents carrier density, C is the capacitance between the gate insulating film, V DS is the drain - source voltage, L G is the gate electrode Length. When attempting to increase I DS under the condition where V GS and V DS are constant, the carrier density n may be increased or the carrier speed v may be increased. More specifically, either a high carrier density n increases the electrostatic capacitance C between the gate insulating film, or to increase the carrier mobility mu, geometrically shorter L G (miniaturization) or Then, the carrier velocity v may be increased by increasing the electric field strength.
信号処理速度（周波数）は、電流応答が追随できずに電流増幅率が１に落ち込む周波数をｆＴ（遮断周波数）と定義すると、次式のように表される。
ここで、ｇｍは相互コンダクタンス（＝∂ＩＤＳ／∂ＶＧＳ）、ＶＧＳおよびＣＧＳはそれぞれ、ゲート－ソース間の電圧および静電容量である。この式から、ゲート絶縁膜間の静電容量Ｃ、およびキャリア移動度μが大きければ、高い動作周波数が得られることがわかる。
The signal processing speed (frequency) is represented by the following equation, where f T (cutoff frequency) is defined as a frequency at which the current amplification factor falls to 1 without being able to follow the current response.
Here, g m is a mutual conductance (= ∂I DS / ∂V GS ), and V GS and C GS are a gate-source voltage and a capacitance, respectively. From this equation, it can be seen that if the capacitance C between the gate insulating films and the carrier mobility μ are large, a high operating frequency can be obtained.
従来のＳｉを用いた電界効果トランジスタは、微細化限界に到達しており、ＬＧをこれ以上小さくできないため、μの大きい代替チャネル材料が望まれており、グラフェンはその有望材料の一つである。グラフェンをＦＥＴに応用した、いわゆるＧＦＥＴ（グラフェン電界効果トランジスタ）では、テラヘルツ（１０１２Ｈｚ）級の動作速度が期待されており、今後益々増加していく情報通信量をまかなうことができるものと考えられる。
The field effect transistor using a conventional Si, has reached the miniaturization limit, can not be reduced L G more, alternate channel materials have been desired large mu, graphene is one of the promising materials is there. The so-called GFET (graphene field effect transistor), which applies graphene to FET, is expected to operate at terahertz (10 12 Hz) class, and will be able to cover the increasing amount of information communication in the future. It is done.
しかし、そのためには、図１１に示すように、ソース／ドレイン電極とグラフェンチャネルとのオーミック接合抵抗（コンタクト抵抗）の低減、ゲート－ドレイン（ソース）間の抵抗（アクセス抵抗）の低減、これらを解決するためのｐ／ｎ－チャネルドーピング技術の確立、そしてゲートスタック／チャネル界面制御などの様々な課題を解決する必要がある。また、グラフェンにはバンドギャップが存在しないため、電流をゼロにすることができず、デジタル回路応用に必要な十分な電流ＯＮ／ＯＦＦ比が取れず、デジタルスイッチング動作が困難であることや、高速化に必要な飽和領域が欠如しているといった問題も解決しなければならない。
However, for that purpose, as shown in FIG. 11, the ohmic junction resistance (contact resistance) between the source / drain electrode and the graphene channel is reduced, the resistance between the gate and the drain (source) (access resistance) is reduced, It is necessary to solve various problems such as establishment of p / n-channel doping technology to solve the problem and gate stack / channel interface control. In addition, since graphene has no band gap, the current cannot be made zero, the current ON / OFF ratio necessary for digital circuit application cannot be obtained, digital switching operation is difficult, and high speed Problems such as the lack of the saturation region necessary for conversion must also be solved.
グラフェンは固有キャリア密度が１０１０ｃｍ－２オーダーと小さく、特性向上のためにゲート長ＬＧを短くした場合、必然的にゲート／ドレイン（ソース）電極間距離が長くなり、アクセス抵抗領域が長くなる。低いキャリア密度のために、この抵抗は非常に大きくなってしまい、これを補償するためにゲート電極にかかる電界強度（ＶＤＳ／ＬＧ）が実際には小さくなるため、このまま短ゲート化していっても、特性向上は望めない。そのため、外部からチャネルにキャリアをドープして、キャリア密度を上げる必要がある。
Graphene intrinsic carrier density as small as 10 10 cm -2 order, when shortening the gate length L G in order to improve the characteristics, inevitably gate / drain (source) electrode distance is long, the access resistance region is long Become. This resistance becomes very large due to the low carrier density, and the electric field strength (V DS / L G ) applied to the gate electrode to actually compensate for this becomes small, so that the gate can be shortened as it is. However, improvement in characteristics cannot be expected. Therefore, it is necessary to dope carriers into the channel from the outside to increase the carrier density.
従来、グラフェンチャネルを「直接」化学修飾することによって不純物を導入し、キャリア密度向上を図った研究がある（例えば、非特許文献１参照）。しかし、この場合、グラフェンチャネルそのものをある意味傷つけることになってしまう。一般的に、チャネルに直接不純物を導入してキャリア密度を増大させる手法は、チャネル中でキャリアと不純物との散乱を引き起こしてしまい、結果として逆にキャリア移動度の低下を招く。
Conventionally, there is a study in which impurities are introduced by chemical modification of a graphene channel “directly” to improve carrier density (see, for example, Non-Patent Document 1). However, in this case, the graphene channel itself is damaged in a sense. In general, a method of increasing the carrier density by directly introducing impurities into the channel causes scattering of carriers and impurities in the channel, resulting in a decrease in carrier mobility.
これに対し、ＧａＡｓを代表とするＩＩＩ－Ｖ族化合物半導体デバイスにおいては、キャリアをドープする層とキャリアを走行する層（チャネル）とを分離させた高電子移動度トランジスタ（ＨＥＭＴ）構造が用いられている（例えば、特許文献１乃至４、もしくは、非特許文献２または３参照）。これは、チャネル材料上に、これよりもバンドギャップが広く、かつ電子親和力が小さい半導体層を積層し、その層内でチャネルから少し離れた位置に不純物を層状にドープ（δ－ドープ）した半導体を製膜して、そこからのキャリアをチャネルとの界面に落として溜め込む構造を有している（変調ドーピング）。これは、チャネルを直接修飾しているわけではないため、導入されたキャリアがチャネル中で不純物散乱されることはなく、チャネル中のキャリア移動度は低下しない。
On the other hand, III-V compound semiconductor devices represented by GaAs use a high electron mobility transistor (HEMT) structure in which a carrier-doped layer and a carrier-running layer (channel) are separated. (For example, see Patent Documents 1 to 4 or Non-Patent Document 2 or 3). This is a semiconductor in which a semiconductor layer having a wider band gap and lower electron affinity is stacked on a channel material, and impurities are doped in layers (δ-dope) at a position slightly away from the channel in the layer. Is formed, and carriers from there are dropped at the interface with the channel and stored (modulation doping). This is because the channel is not directly modified, so that the introduced carrier is not impurity-scattered in the channel, and the carrier mobility in the channel does not decrease.
また、チャネル材料としてグラフェンを使用する場合、炭素質であるグラフェンは、本質的に酸化ダメージを受けやすく、Ｓｉ系デバイスに用いられている酸化アルミニウム（Ａｌ２Ｏ３）や酸化ハフニウム（ＨｆＯ２）などの酸化物系高誘電率（ｈｉｇｈ－κ）材料を、直接的にトップゲート絶縁膜として適用することができない。そのため、グラフェン自身を損なわず、その上に「直接」製膜できるゲート絶縁膜物質およびその手法が必要とされている。
When graphene is used as a channel material, carbonaceous graphene is inherently susceptible to oxidative damage, and aluminum oxide (Al 2 O 3 ) and hafnium oxide (HfO 2 ) used in Si-based devices. Such oxide-based high dielectric constant (high-κ) materials cannot be directly applied as the top gate insulating film. Therefore, there is a need for a gate dielectric material and method that can be “directly” deposited on the graphene itself without damaging the graphene itself.
なお、グラフェンとの高い化学的親和性が期待できるものとして、グラフェンと同じ炭素質であるダイヤモンドライクカーボン（ＤＬＣ）がある。このＤＬＣにドーピングしたものとして、主に低摩擦化などの機械工学的目的のために、炭素系ガスに異元素ガスを混ぜてＤＬＣを製膜し、異元素を膜全体に取り込んだもの（例えば、非特許文献４または５参照）、製膜条件を変えてＤＬＣの誘電率を制御することにより、ＤＬＣを主に低誘電率（ｌｏｗ－κ）化し、層間絶縁膜用途に用いたもの（例えば、非特許文献６または７参照）、界面準位低減のため、ＤＬＣに金属元素をドープし、ＤＬＣを導電性チャネル薄膜材料として、薄膜トランジスタ（ＴＦＴ）に用いたもの（例えば、非特許文献８乃至１１参照）などがある。
Note that diamond-like carbon (DLC), which has the same carbon quality as graphene, can be expected to have high chemical affinity with graphene. This DLC is doped with a DLC film formed by mixing a different element gas with a carbon-based gas, mainly for mechanical engineering purposes such as low friction, and incorporating the different element into the entire film (for example, Non-Patent Document 4 or 5), by changing the film forming conditions to control the dielectric constant of the DLC, the DLC is mainly made to have a low dielectric constant (low-κ) and used for an interlayer insulating film (for example, Non-Patent Document 6 or 7), in order to reduce the interface state, a metal element is doped into DLC, and DLC is used as a conductive channel thin film material for a thin film transistor (TFT) (for example, Non-Patent Documents 8 to 8). 11).
また、基板の表面に薄膜を形成する方法として、光電子制御プラズマＣＶＤ（ＰＡ－ＰＥＣＶＤ；Ｐｈｏｔｏｅｍｉｓｓｉｏｎ－Ａｓｓｉｓｔｅｄ Ｐｌａｓｍａ－Ｅｎｈａｎｃｅｄ Ｃｈｅｍｉｃａｌ Ｖａｐｏｒ Ｄｅｐｏｓｉｔｉｏｎ）法が開発されている（例えば、特許文献５乃至７、または非特許文献１２参照）。ＰＡ－ＰＥＣＶＤ法は、通常の浮遊電子をプラズマのトリガーとする手法とは異なり、サンプル基板への紫外光照射により発生する光電子をトリガーとするＤＣプラズマ製膜法である。プラズマ発生は光照射部位に限定されるために製膜部位を精密制御でき、かつクリーンルームプロセスに大敵となる煤の発生を防ぐことができる。さらに低電圧でプラズマ発生できることから、ｍＷオーダーの従来よりも著しく低い電力で製膜でき、基板へのプラズマダメージをも防ぐことができる。ＰＡ－ＰＥＣＶＤ法で使用されるＰＡ－ＰＥＣＶＤ装置を、図１２に示す。
In addition, as a method for forming a thin film on the surface of a substrate, a photoelectron-controlled plasma CVD (PA-PECVD) method has been developed (for example, Patent Documents 5 to 7 or non-patent documents). Reference 12). The PA-PECVD method is a DC plasma film forming method using photoelectrons generated by ultraviolet light irradiation on a sample substrate as a trigger, unlike a method using normal floating electrons as a plasma trigger. Since the plasma generation is limited to the light irradiation site, the film formation site can be precisely controlled, and the generation of soot that becomes a major enemy to the clean room process can be prevented. Furthermore, since plasma can be generated at a low voltage, it is possible to form a film with significantly lower power than conventional ones in the order of mW, and plasma damage to the substrate can also be prevented. A PA-PECVD apparatus used in the PA-PECVD method is shown in FIG.
なお、本発明者らにより、ＰＡ－ＰＥＣＶＤ法を用いてＤＬＣを製膜する場合、成長雰囲気（Ａｒ＋ＣＨ４）中のＣＨ４ガスの濃度比によって、ＤＬＣの比誘電率を、約１程度から５付近まで広い範囲で制御・変調できる可能性が示されている（例えば、非特許文献１３参照）。
When the present inventors form a DLC film using the PA-PECVD method, the relative dielectric constant of the DLC is about 1 to 5 depending on the concentration ratio of the CH 4 gas in the growth atmosphere (Ar + CH 4 ). The possibility of being able to control and modulate in a wide range up to the vicinity is shown (for example, see Non-Patent Document 13).
When the present inventors form a DLC film using the PA-PECVD method, the relative dielectric constant of the DLC is about 1 to 5 depending on the concentration ratio of the CH 4 gas in the growth atmosphere (Ar + CH 4 ). The possibility of being able to control and modulate in a wide range up to the vicinity is shown (for example, see Non-Patent Document 13).
上記のように、グラフェンをＦＥＴに応用する場合には、図１１に示すような様々な課題が存在している。また、非特許文献１に記載のような、グラフェンチャネルを直接化学修飾することによって不純物を導入し、キャリア密度を増大させる方法では、グラフェンチャネルを傷つけてしまい、逆にキャリア移動度の低下を招くという課題もあった。
As described above, when graphene is applied to an FET, various problems as shown in FIG. 11 exist. Further, in the method of introducing impurities by directly chemically modifying the graphene channel as described in Non-Patent Document 1 to increase the carrier density, the graphene channel is damaged, and conversely, the carrier mobility is lowered. There was also a problem.
本発明は、このような課題に着目してなされたもので、グラフェンチャネルを直接傷つけることなくキャリア密度およびキャリア移動度を高め、動作速度の向上を図ることができ、さらにアクセス抵抗を低減可能で、デジタルスイッチング動作を実現することができるグラフェン電界効果トランジスタおよびグラフェン半導体部材を提供することを目的としている。
The present invention has been made paying attention to such a problem, and can increase carrier density and carrier mobility without directly damaging the graphene channel, improve the operation speed, and further reduce the access resistance. An object of the present invention is to provide a graphene field effect transistor and a graphene semiconductor member capable of realizing a digital switching operation.
本発明に係るグラフェン電界効果トランジスタは、グラフェンから成るチャネル層と、前記チャネル層の上に設けられ、グラフェンとの反応性が低い材料から成る絶縁体層と、前記チャネル層に電気的に接続され、前記絶縁体層を挟む位置に互いに離れて配置されたソース電極およびドレイン電極と、前記絶縁体層の上に設けられたゲート電極とを有し、前記絶縁体層は、前記チャネル層にキャリアを供給可能な薄膜状の変調ドープ部を有することを特徴とする。
The graphene field effect transistor according to the present invention is electrically connected to a channel layer made of graphene, an insulator layer provided on the channel layer and made of a material having low reactivity with graphene, and the channel layer. And a source electrode and a drain electrode which are arranged apart from each other at a position sandwiching the insulator layer, and a gate electrode provided on the insulator layer, and the insulator layer has a carrier in the channel layer. It has the thin film-like modulation | alteration dope part which can supply this.
本発明に係るグラフェン電界効果トランジスタでは、グラフェンから成るチャネル層の上に設けられた絶縁体層中の薄膜状の変調ドープ部が、チャネル層にキャリアを供給することができるため、チャネル層のキャリア密度を増大させることができる。このとき、チャネル層を直接修飾していないため、キャリアがチャネル層中で不純物散乱されることはなく、キャリア移動度は低下しない。また、絶縁体層がグラフェンとの反応性が低い材料から成るため、絶縁体層をグラフェンから成るチャネル層の上に直接設けても、チャネル層にダメージを与えない。このように、本発明に係るグラフェン電界効果トランジスタは、ＨＥＭＴ構造のように、グラフェンから成るチャネル層を直接傷つけることなくキャリア密度およびキャリア移動度を高めることができ、動作速度の向上を図ることができる。
In the graphene field effect transistor according to the present invention, the thin film-like modulation doped portion in the insulator layer provided on the channel layer made of graphene can supply carriers to the channel layer. The density can be increased. At this time, since the channel layer is not directly modified, carriers are not scattered by impurities in the channel layer, and carrier mobility does not decrease. In addition, since the insulator layer is made of a material having low reactivity with graphene, the channel layer is not damaged even if the insulator layer is provided directly on the channel layer made of graphene. As described above, the graphene field-effect transistor according to the present invention can increase the carrier density and the carrier mobility without directly damaging the graphene channel layer as in the HEMT structure, and can improve the operation speed. it can.
本発明に係るグラフェン電界効果トランジスタは、チャネル層がグラフェンから成るため、従来のＳｉ等を用いたＦＥＴよりも速い動作速度が得られ、さらに従来のＦＥＴでは実現できなかったテラヘルツ領域での動作を可能にすることができる。このため、今後発展していく情報化社会の情報通信量をまかなうことができるものと期待される。なお、変調ドープ部は、絶縁体層中に不純物元素（ヘテロ元素）をドープして形成される。
In the graphene field effect transistor according to the present invention, the channel layer is made of graphene, so that the operation speed is higher than that of a conventional FET using Si or the like, and the operation in the terahertz region that cannot be realized by the conventional FET is achieved. Can be possible. For this reason, it is expected that the amount of information communication in the information society that will develop in the future can be covered. The modulation doped portion is formed by doping an impurity element (hetero element) in the insulator layer.
本発明に係るグラフェン電界効果トランジスタで、絶縁体層を成す、グラフェンとの反応性が低い材料とは、グラフェンから成るチャネル層に直接接触させても、チャネル層に対して、チャネル層中のキャリアの移動を妨げるほどのダメージを与えない材料である。例えば、１）グラフェンとの化学的反応性、２）グラフェンとの格子不整合や表面不平坦性による応力や、それにともなう欠陥および欠陥準位の発生、ならびに、３）グラフェンとの界面における散乱効果、がいずれも極めて低く、４）温度・湿度等の環境変化に対しても機械的・化学的・電気的に安定である材料であり、具体的な例としては、ダイヤモンドライクカーボン（ＤＬＣ）やｈＢＮ（ｈｅｘａｇｏｎａｌ Ｂｏｒｏｎ Ｎｉｔｒｉｄｅ）である。また、薄膜状の変調ドープ部は、絶縁体層の厚み方向に対して、少なくとも、ある局所的な位置に薄く局在分布していればよく、その分布が均一で面状に形成されていても、分布が不均一で島状に形成されていても、あるいは縞状に形成されていてもよい。
In the graphene field effect transistor according to the present invention, an insulator layer and a material having low reactivity with graphene are carriers in the channel layer with respect to the channel layer, even if the material is in direct contact with the channel layer made of graphene. It is a material that does not damage to the extent that hinders movement. For example, 1) chemical reactivity with graphene, 2) stress due to lattice mismatch or surface non-planarity with graphene, generation of defects and defect levels, and 3) scattering effect at the interface with graphene 4) is a material that is mechanically, chemically, and electrically stable against environmental changes such as temperature and humidity. Specific examples include diamond-like carbon (DLC) and hBN (hexagonal Boron Nitride). In addition, the thin film-like modulation dope portion only needs to be thinly distributed at least at a certain local position in the thickness direction of the insulator layer, and the distribution is uniform and planar. Alternatively, the distribution may be uneven and formed in an island shape, or may be formed in a stripe shape.
本発明に係るグラフェン電界効果トランジスタで、前記変調ドープ部は、前記チャネル層との間に、トンネル効果により前記チャネル層にキャリアを供給可能な距離をあけて設けられていることが好ましい。特に、前記変調ドープ部は、前記チャネル層との間に、３乃至６ｎｍの距離をあけて設けられていることが好ましい。この場合、チャネル層を直接修飾することなく、効率的に変調ドープ部からチャネル層にキャリアを供給することができる。このため、特に効果的にキャリア密度およびキャリア移動度を高めることができ、動作速度を向上させることができる。
In the graphene field effect transistor according to the present invention, it is preferable that the modulation doped portion is provided between the channel layer with a distance capable of supplying carriers to the channel layer by a tunnel effect. In particular, it is preferable that the modulation doped portion is provided with a distance of 3 to 6 nm between the channel layer and the channel layer. In this case, carriers can be efficiently supplied from the modulation doped portion to the channel layer without directly modifying the channel layer. For this reason, the carrier density and carrier mobility can be particularly effectively increased, and the operation speed can be improved.
本発明に係るグラフェン電界効果トランジスタで、前記絶縁体層は、ダイヤモンドライクカーボンから成ることが好ましい。ダイヤモンドライクカーボン（ＤＬＣ）はｓｐ２炭素・ｓｐ３炭素・水素から成るアモルファス炭素材料であり、グラフェンと同じ炭素質であることから、グラフェンに対して高い化学的親和性を有している。具体的には、１）グラフェンとの化学的反応性、２）グラフェンとの格子不整合や表面不平坦性による応力やそれにともなう欠陥および欠陥準位の発生、ならびに、３）グラフェン・絶縁膜界面における散乱効果、がいずれも極めて低く、かつ、４）温度・湿度等の環境変化に対しても機械的・化学的・電気的に安定である。このため、グラフェンから成るチャネル層にダメージを与えることなく、絶縁体層をチャネル層の上に直接設けることができる。このため、キャリア密度およびキャリア移動度の低下を防ぐことができ、高い動作速度を実現することができる。また、ＤＬＣはアモルファス性で平坦な膜を成すことから、均質な膜質を有する絶縁体層を得ることができる。なお、ＤＬＣは、絶縁性を有するものから成り、例えば、ｔａ－Ｃ、ｔａ－Ｃ：Ｈ、ａ－Ｃ：Ｈから成ることが好ましい。
In the graphene field effect transistor according to the present invention, the insulator layer is preferably made of diamond-like carbon. Diamond-like carbon (DLC) is an amorphous carbon material composed of sp 2 carbon, sp 3 carbon, and hydrogen, and has a high chemical affinity for graphene because it is the same carbonaceous material as graphene. Specifically, 1) chemical reactivity with graphene, 2) generation of stresses and defects due to lattice mismatch and surface non-uniformity with graphene, and 3) graphene / insulator interface Scattering effects are extremely low, and 4) they are mechanically, chemically and electrically stable against environmental changes such as temperature and humidity. Therefore, the insulator layer can be provided directly on the channel layer without damaging the channel layer made of graphene. For this reason, a decrease in carrier density and carrier mobility can be prevented, and a high operating speed can be realized. Moreover, since DLC forms an amorphous and flat film, an insulator layer having a uniform film quality can be obtained. The DLC is made of an insulating material, and is preferably made of, for example, ta-C, ta-C: H, or aC: H.
本発明に係るグラフェン電界効果トランジスタで、前記絶縁体層は、前記ゲート電極の直下から前記チャネル層まで伸びた高誘電率部を有し、前記高誘電率部と前記ソース電極および前記ドレイン電極との間に、前記高誘電率部よりも誘電率が低い低誘電率部を有し、前記低誘電率部に前記変調ドープ部を有していてもよい。この場合、高誘電率部により、ゲート電極の直下に高い静電誘導効果をもたらすことができ、チャネル界面制御を高精度で行うことができる。また、低誘電率部により、各電極間の寄生容量を低減させることができ、高速化を図ることができる。変調ドープ部が高誘電率部とソース電極およびドレイン電極との間に設けられているため、アクセス領域のチャネル層に効果的にキャリアを供給することができ、アクセス抵抗を低減することができる。
In the graphene field effect transistor according to the present invention, the insulator layer has a high dielectric constant portion extending from immediately below the gate electrode to the channel layer, and the high dielectric constant portion, the source electrode, and the drain electrode, The low dielectric constant portion may have a lower dielectric constant than the high dielectric constant portion, and the modulation doped portion may be included in the low dielectric constant portion. In this case, the high dielectric constant portion can provide a high electrostatic induction effect directly below the gate electrode, and channel interface control can be performed with high accuracy. Further, the low dielectric constant portion can reduce the parasitic capacitance between the respective electrodes, and can increase the speed. Since the modulation doped portion is provided between the high dielectric constant portion and the source and drain electrodes, carriers can be effectively supplied to the channel layer in the access region, and the access resistance can be reduced.
本発明に係るグラフェン電界効果トランジスタで、前記絶縁体層は、前記高誘電率部にも前記変調ドープ部を有していてもよい。この場合、低誘電率部および高誘電率部の変調ドープ部の極性を、それぞれｐ型およびｎ型、またはｎ型およびｐ型と区別することにより、高いキャリア密度および高い移動度を維持しながら、ｐ－ｎ－ｐ接合またはｎ－ｐ－ｎ接合を作ることができる。これにより、チャネル層における電流の整流性をもたらすことができ、デジタルスイッチング動作を実現することができる。なお、低誘電率部および高誘電率部の各変調ドープ部は、チャネル層からの距離が同じであっても、異なっていてもよい。
In the graphene field effect transistor according to the present invention, the insulator layer may have the modulation doped portion in the high dielectric constant portion. In this case, while maintaining the high carrier density and the high mobility by distinguishing the polarities of the modulation doped portions of the low dielectric constant portion and the high dielectric constant portion from p-type and n-type, or n-type and p-type, respectively. Pnp junctions or npn junctions can be made. Thereby, current rectification in the channel layer can be provided, and digital switching operation can be realized. The modulation dope portions of the low dielectric constant portion and the high dielectric constant portion may be the same distance from the channel layer or may be different.
本発明に係るグラフェン半導体部材は、グラフェンから成るチャネル層と、前記チャネル層の上に設けられ、グラフェンとの反応性が低い材料から成る絶縁体層とを有し、前記絶縁体層は、前記チャネル層にキャリアを供給可能な薄膜状の変調ドープ部を有することを特徴とする。
The graphene semiconductor member according to the present invention includes a channel layer made of graphene and an insulator layer formed on the channel layer and made of a material having low reactivity with graphene. It has a thin film-like modulation doped portion capable of supplying carriers to the channel layer.
本発明に係るグラフェン半導体部材は、例えば、絶縁体層に透明度の高い材料を用いることにより、タッチパネル用の部材として利用することができる。また、本発明に係るグラフェン半導体部材は、ソース電極、ドレイン電極、ゲート電極を繋げることにより、本発明に係るグラフェン電界効果トランジスタを構成することができる。
The graphene semiconductor member according to the present invention can be used as a member for a touch panel, for example, by using a highly transparent material for the insulator layer. The graphene semiconductor member according to the present invention can constitute the graphene field effect transistor according to the present invention by connecting the source electrode, the drain electrode, and the gate electrode.
本発明に係るグラフェン半導体部材は、グラフェンから成るチャネル層の上に設けられた絶縁体層中の薄膜状の変調ドープ部が、チャネル層にキャリアを供給することができるため、チャネル層のキャリア密度を増大させることができる。このとき、チャネル層を直接修飾していないため、チャネル層中でキャリアを移動させても不純物散乱されることはなく、キャリア移動度は低下しない。また、絶縁体層がグラフェンとの反応性が低い材料から成るため、絶縁体層をグラフェンから成るチャネル層の上に直接設けても、チャネル層にダメージを与えない。このように、本発明に係るグラフェン半導体部材は、ＨＥＭＴ構造のように、グラフェンから成るチャネル層を直接傷つけることなくキャリア密度およびキャリア移動度を高めることができ、動作速度の向上を図ることができる。
In the graphene semiconductor member according to the present invention, since the thin film-like modulation doped portion in the insulator layer provided on the channel layer made of graphene can supply carriers to the channel layer, the carrier density of the channel layer Can be increased. At this time, since the channel layer is not directly modified, impurities are not scattered even if carriers are moved in the channel layer, and the carrier mobility is not lowered. In addition, since the insulator layer is made of a material having low reactivity with graphene, the channel layer is not damaged even if the insulator layer is provided directly on the channel layer made of graphene. As described above, the graphene semiconductor member according to the present invention can increase the carrier density and the carrier mobility without directly damaging the graphene channel layer as in the HEMT structure, and can improve the operation speed. .
本発明に係るグラフェン半導体部材で、変調ドープ部は、チャネル層との間に、トンネル効果によりチャネル層にキャリアを供給可能な距離をあけて設けられていることが好ましく、特に、チャネル層との間に、３乃至６ｎｍの距離をあけて設けられていることが好ましい。この場合、チャネル層を直接修飾することなく、効率的に変調ドープ部からチャネル層にキャリアを供給することができる。このため、特に効果的にキャリア密度およびキャリア移動度を高めることができ、動作速度を向上させることができる。
In the graphene semiconductor member according to the present invention, it is preferable that the modulation dope portion is provided between the channel layer with a distance capable of supplying carriers to the channel layer by a tunnel effect. It is preferable that a distance of 3 to 6 nm is provided between them. In this case, carriers can be efficiently supplied from the modulation doped portion to the channel layer without directly modifying the channel layer. For this reason, the carrier density and carrier mobility can be particularly effectively increased, and the operation speed can be improved.
本発明に係るグラフェン半導体部材で、絶縁体層は、例えば、グラフェンとの反応性が低いダイヤモンドライクカーボンやｈＢＮなどから成り、特に、ダイヤモンドライクカーボンから成ることが好ましい。この場合、ダイヤモンドライクカーボン（ＤＬＣ）がグラフェンに対して高い化学的親和性を有しているため、グラフェンから成るチャネル層にダメージを与えることなく、絶縁体層をチャネル層の上に直接設けることができる。このため、キャリア密度およびキャリア移動度の低下を防ぐことができ、高い動作速度を実現することができる。また、ＤＬＣはアモルファス性で平坦な膜を成すことから、均質な膜質を有する絶縁体層を得ることができる。ＤＬＣは可視光や赤外光に対して透明であり、透明度を下げることなく、キャリア密度およびキャリア移動度を高めることができるため、低抵抗のタッチパネルとして利用することができる。なお、ＤＬＣは、絶縁性を有するものから成り、例えば、ｔａ－Ｃ、ｔａ－Ｃ：Ｈ、ａ－Ｃ：Ｈから成ることが好ましい。
In the graphene semiconductor member according to the present invention, the insulator layer is made of, for example, diamond-like carbon or hBN having low reactivity with graphene, and particularly preferably made of diamond-like carbon. In this case, since diamond-like carbon (DLC) has a high chemical affinity for graphene, an insulator layer is provided directly on the channel layer without damaging the channel layer made of graphene. Can do. For this reason, a decrease in carrier density and carrier mobility can be prevented, and a high operating speed can be realized. Moreover, since DLC forms an amorphous and flat film, an insulator layer having a uniform film quality can be obtained. DLC is transparent to visible light and infrared light, and can increase carrier density and carrier mobility without lowering transparency, so that it can be used as a low-resistance touch panel. The DLC is made of an insulating material, and is preferably made of, for example, ta-C, ta-C: H, or aC: H.
本発明によれば、グラフェンチャネルを直接傷つけることなくキャリア密度およびキャリア移動度を高め、動作速度の向上を図ることができ、さらにアクセス抵抗を低減可能で、デジタルスイッチング動作を実現することができるグラフェン電界効果トランジスタおよびグラフェン半導体部材を提供することができる。
According to the present invention, it is possible to increase carrier density and carrier mobility without directly damaging the graphene channel, improve operation speed, further reduce access resistance, and realize digital switching operation. A field effect transistor and a graphene semiconductor member can be provided.
以下、図面に基づき、本発明の実施の形態について説明する。
図１乃至図８は、本発明の実施の形態のグラフェン電界効果トランジスタおよびグラフェン半導体部材を示している。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
1 to 8 show a graphene field effect transistor and a graphene semiconductor member according to an embodiment of the present invention.
図１乃至図８は、本発明の実施の形態のグラフェン電界効果トランジスタおよびグラフェン半導体部材を示している。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
1 to 8 show a graphene field effect transistor and a graphene semiconductor member according to an embodiment of the present invention.
図１（ａ）に示すように、グラフェン電界効果トランジスタ１０は、基板の上に設けられたグラフェンから成るチャネル層１１と、チャネル層１１の上に設けられたソース電極１２とドレイン電極１３と絶縁体層１４と、絶縁体層１４の上に設けられたゲート電極１５とを有している。
As shown in FIG. 1A, a graphene field effect transistor 10 includes a channel layer 11 made of graphene provided on a substrate, and a source electrode 12 and a drain electrode 13 provided on the channel layer 11 and insulated from each other. It has a body layer 14 and a gate electrode 15 provided on the insulator layer 14.
ソース電極１２およびドレイン電極１３は、それぞれチャネル層１１の両端部に、互いに離れて配置されている。ソース電極１２およびドレイン電極１３は、チャネル層１１に電気的に接続されている。
The source electrode 12 and the drain electrode 13 are disposed apart from each other at both ends of the channel layer 11. The source electrode 12 and the drain electrode 13 are electrically connected to the channel layer 11.
絶縁体層１４は、グラフェンとの反応性が低いダイヤモンドライクカーボン（ＤＬＣ）から成り、ソース電極１２とドレイン電極１３との間、およびソース電極１２およびドレイン電極１３の周囲を囲むよう設けられている。絶縁体層１４は、その層中に、チャネル層１１の表面に対して平行に設けられた、薄膜状で、かつグラフェンへのキャリア供給能力を有する酸素や窒素等の不純物をＤＬＣ中にドープした変調ドープ部１４ａを有している。変調ドープ部１４ａは、チャネル層１１との間に、トンネル効果によりチャネル層１１にキャリアを供給可能な距離をあけて設けられている。図１（ａ）に示す具体的な一例では、変調ドープ部１４ａは、チャネル層１１との間に、約５ｎｍの距離をあけて設けられている。なお、薄膜状の変調ドープ部１４ａは、絶縁体層１４の厚み方向に対して、ある局所的な位置に薄く局在分布していればよく、その分布が均一で面状に形成されていても、分布が不均一で島状に形成されていても、あるいは縞状に形成されていてもよい。
The insulator layer 14 is made of diamond-like carbon (DLC) having low reactivity with graphene, and is provided between the source electrode 12 and the drain electrode 13 and around the source electrode 12 and the drain electrode 13. . The insulator layer 14 is doped in the DLC with an impurity such as oxygen or nitrogen that is provided in parallel to the surface of the channel layer 11 and has a thin film-like shape and capable of supplying carriers to graphene. It has a modulation dope section 14a. The modulation doped portion 14a is provided between the channel layer 11 and a distance that can supply carriers to the channel layer 11 by a tunnel effect. In a specific example shown in FIG. 1A, the modulation dope portion 14 a is provided with a distance of about 5 nm between the channel layer 11. Note that the thin film-like modulation doped portion 14a only needs to be thinly distributed at a certain local position in the thickness direction of the insulator layer 14, and the distribution is uniform and formed in a planar shape. Alternatively, the distribution may be uneven and formed in an island shape, or may be formed in a stripe shape.
次に、作用について説明する。
グラフェン電界効果トランジスタ１０では、変調ドープ部１４ａが、チャネル層１１にキャリアを供給することができるため、チャネル層１１のキャリア密度を増大させることができる。このとき、チャネル層１１を直接修飾していないため、キャリアがチャネル層１１の中で不純物散乱されることはなく、キャリア移動度は低下しない。また、絶縁体層１４が、グラフェンに対して高い化学的親和性を有するＤＬＣから成るため、絶縁体層１４をグラフェンから成るチャネル層１１の上に直接設けても、チャネル層１１にダメージを与えない。このように、グラフェン電界効果トランジスタ１０は、ＨＥＭＴ構造のように、グラフェンから成るチャネル層１１を直接傷つけることなくキャリア密度およびキャリア移動度を高めることができ、動作速度の向上を図ることができる。 Next, the operation will be described.
In the graphenefield effect transistor 10, the modulation dope portion 14 a can supply carriers to the channel layer 11, so that the carrier density of the channel layer 11 can be increased. At this time, since the channel layer 11 is not directly modified, carriers are not scattered in the channel layer 11 and the carrier mobility does not decrease. Further, since the insulator layer 14 is made of DLC having high chemical affinity for graphene, the channel layer 11 is damaged even if the insulator layer 14 is provided directly on the channel layer 11 made of graphene. Absent. As described above, the graphene field-effect transistor 10 can increase the carrier density and carrier mobility without directly damaging the graphene channel layer 11 unlike the HEMT structure, and can improve the operation speed.
グラフェン電界効果トランジスタ１０では、変調ドープ部１４ａが、チャネル層１１にキャリアを供給することができるため、チャネル層１１のキャリア密度を増大させることができる。このとき、チャネル層１１を直接修飾していないため、キャリアがチャネル層１１の中で不純物散乱されることはなく、キャリア移動度は低下しない。また、絶縁体層１４が、グラフェンに対して高い化学的親和性を有するＤＬＣから成るため、絶縁体層１４をグラフェンから成るチャネル層１１の上に直接設けても、チャネル層１１にダメージを与えない。このように、グラフェン電界効果トランジスタ１０は、ＨＥＭＴ構造のように、グラフェンから成るチャネル層１１を直接傷つけることなくキャリア密度およびキャリア移動度を高めることができ、動作速度の向上を図ることができる。 Next, the operation will be described.
In the graphene
グラフェン電界効果トランジスタ１０は、チャネル層１１がグラフェンから成るため、従来のＳｉ等を用いたＦＥＴよりも速い動作速度が得られ、さらに従来のＦＥＴでは実現できなかったテラヘルツ領域での動作を可能にすることができる。このため、今後発展していく情報化社会の情報通信量をまかなうことができるものと期待される。グラフェン電界効果トランジスタ１０は、例えば、コンピュータの計算速度を著しく向上させる次世代超高速中央演算処理装置（ＣＰＵ）や、通信容量を著しく増大させるスマートフォン等の超小型超高速通信デバイス、利用可能電波領域を格段に広げるテラヘルツ波発信器などへの利用が考えられる。
The graphene field-effect transistor 10 has a channel layer 11 made of graphene, so that a higher operating speed than that of a conventional FET using Si or the like can be obtained, and operation in a terahertz region that cannot be realized by a conventional FET is possible. can do. For this reason, it is expected that the amount of information communication in the information society that will develop in the future can be covered. The graphene field-effect transistor 10 is, for example, a next-generation ultra-high-speed central processing unit (CPU) that significantly improves the calculation speed of a computer, an ultra-compact ultra-high-speed communication device such as a smartphone that significantly increases communication capacity, and an available radio wave region. It can be used for terahertz wave transmitters.
なお、本発明の実施の形態のグラフェン半導体部材は、グラフェン電界効果トランジスタ１０のゲート電極１５、ソース電極１２およびドレイン電極１３を取り除いた構成から成っている。本発明の実施の形態のグラフェン半導体部材は、グラフェン電界効果トランジスタ１０を構成するだけでなく、ＤＬＣの透明度が高いため、タッチパネル用の部材として利用することもできる。
The graphene semiconductor member according to the embodiment of the present invention has a configuration in which the gate electrode 15, the source electrode 12, and the drain electrode 13 of the graphene field effect transistor 10 are removed. The graphene semiconductor member according to the embodiment of the present invention not only constitutes the graphene field-effect transistor 10, but also has high DLC transparency, and thus can be used as a member for a touch panel.
チャネル層１１のグラフェン上に、トップゲート絶縁膜（絶縁体層１４）としてＤＬＣ薄膜を直接製膜することにより、グラフェン電界効果トランジスタ１０を製造することができたため、その特性等の評価を行った。グラフェン電界効果トランジスタ１０は、以下の方法により製造された。チャネル層１１として、６Ｈ－ＳｉＣ（０００１）基板（Ｓｉ面）を１７００℃で１５分間、超高真空アニールすることにより、基板上にエピタキシャル数層グラフェン（ｅｐｉｔａｘｉａｌ ｆｅｗ－ｌａｙｅｒ ｇｒａｐｈｅｎｅ， ＥＦＬＧ）を作製した。オーミックコンタクト金属としてＰｔを用い、金（Ａｕ）製のゲート電極１５、ソース電極１２、ドレイン電極１３を作製した。
The graphene field-effect transistor 10 was manufactured by directly forming a DLC thin film as a top gate insulating film (insulator layer 14) on the graphene of the channel layer 11, and the characteristics and the like were evaluated. . The graphene field effect transistor 10 was manufactured by the following method. As the channel layer 11, a 6H-SiC (0001) substrate (Si surface) was ultrahigh-vacuum annealed at 1700 ° C. for 15 minutes, thereby producing an epitaxial several-layer graphene (epitaxial five-layer graphene, EFLG) on the substrate. . Gold (Au) -made gate electrode 15, source electrode 12, and drain electrode 13 were produced using Pt as the ohmic contact metal.
また、図１２に示すＰＡ－ＰＥＣＶＤ装置を用いて、ＤＬＣから成る絶縁体層１４を、ＣＨ４／Ａｒガスを用いた光電子制御プラズマＣＶＤ（ＰＡ－ＰＥＣＶＤ）法により、グラフェンから成るチャネル層１１の上に直接製膜した。ＰＡ－ＰＥＣＶＤ法を用いることにより、低電圧でプラズマ発生できることから、従来よりも著しく低い電力で製膜でき、グラフェンへのプラズマダメージを防ぐことができる。
Further, using the PA-PECVD apparatus shown in FIG. 12, the insulator layer 14 made of DLC is formed on the channel layer 11 made of graphene by the photoelectron-controlled plasma CVD (PA-PECVD) method using CH 4 / Ar gas. The film was formed directly on the top. By using the PA-PECVD method, plasma can be generated at a low voltage, so that the film can be formed with significantly lower power than before and plasma damage to graphene can be prevented.
製造されたグラフェン電界効果トランジスタ１０は、チャネル幅（ＷＣ）が１１μｍ、チャネル長（ＬＣ）が６μｍ、ゲート長（ＬＧ）が５μｍである。また、絶縁体層１４の膜厚が、二次イオン質量分析（ＳＩＭＳ）の深さプロファイルより、４８ｎｍと見積もられた。容量（Ｃ－Ｖ）測定より、比誘電率が５．１、等価酸化膜厚（ＥＯＴ）が３７ｎｍと求められた。
The manufactured graphene field effect transistor 10 has a channel width (W C ) of 11 μm, a channel length (L C ) of 6 μm, and a gate length (L G ) of 5 μm. Moreover, the film thickness of the insulator layer 14 was estimated to be 48 nm from the depth profile of secondary ion mass spectrometry (SIMS). From the capacitance (CV) measurement, it was determined that the relative dielectric constant was 5.1 and the equivalent oxide thickness (EOT) was 37 nm.
図２（ａ）および（ｂ）に、製造されたグラフェン電界効果トランジスタ１０のＩＤＳ（ドレイン－ソース電流）－ＶＤＳ（ドレイン－ソース電圧）およびＩＤＳ－ＶＧＳ（ゲート－ソース電圧）特性を示す。図２（ｂ）に示すように、ＩＤＳはＶＧＳ＝＋０．５Ｖで極小値を示し、グラフェン特有のａｍｂｉｐｏｌａｒ特性を示している。電荷中性点であるディラック電圧（ＶＤｉｒａｃ）は、理論的には（１／２）ＶＤＳで与えられるが、図２（ｂ）では若干正にシフトしている。このことから、チャネル層１１は、弱いｐ性を有していることがわかる。
FIGS. 2A and 2B show the I DS (drain-source current) -V DS (drain-source voltage) and I DS -V GS (gate-source voltage) characteristics of the manufactured graphene field effect transistor 10. Indicates. As shown in FIG. 2B, I DS has a minimum value at V GS = + 0.5 V, and shows ambipolar characteristics peculiar to graphene. The Dirac voltage (V Dirac ), which is a charge neutral point, is theoretically given by (1/2) V DS , but slightly shifts positive in FIG. This shows that the channel layer 11 has weak p property.
図３に、グラフェンチャネル層１１の２Ｄバンド領域のラマンスペクトルを示す。図３に示すように、グラフェン成長直後（Ａｓ－ｇｒｏｗｎ）のスペクトルと比較すると、ＤＬＣ絶縁体層１４の製膜後（Ａｆｔｅｒ ＤＬＣ ｆｏｒｍｉｎｇ）の２Ｄバンドピークは、高波数シフトしていることがわかる。これは、ＤＬＣ絶縁体層１４からグラフェンチャネル層１１へ、ｐドープされていることを示唆している。強いｎ型特性を示す６Ｈ－ＳｉＣ基板上のグラフェンにおいてａｍｂｉｐｏｌａｒ特性を示した原因は、このＤＬＣ絶縁体層１４からグラフェンチャネル層１１への“ｕｎｉｎｔｅｎｔｉｏｎａｌ ｐ－ｄｏｐｉｎｇ”であると考えられる。
FIG. 3 shows a Raman spectrum of the 2D band region of the graphene channel layer 11. As shown in FIG. 3, when compared with the spectrum immediately after graphene growth (As-grown), it can be seen that the 2D band peak after deposition of the DLC insulator layer 14 (After DLC forming) is shifted to a high wavenumber. . This suggests that the DLC insulator layer 14 is p-doped from the graphene channel layer 11. The cause of the ambipolar characteristics in the graphene on the 6H-SiC substrate exhibiting strong n-type characteristics is thought to be “unintentional p-doping” from the DLC insulator layer 14 to the graphene channel layer 11.
図４に、ＤＬＣ絶縁体層１４のＳＩＭＳ元素深さプロファイルを示す。図４に示すように、グラフェンチャネル層１１の近傍の深さ（Ｄｅｐｔｈ）が４０～５６ｎｍで酸素原子数の急激な増加が認められたことから、ｕｎｉｎｔｅｎｔｉｏｎａｌ ｐ－ｄｏｐｉｎｇは、絶縁体層１４の中の酸素原子に由来するものと考えられる。この酸素原子は、製膜に用いたＰＡ－ＰＥＣＶＤ装置のチャンバー内に残留していた水（Ｈ２Ｏ）分子に由来すると考えられる。なお、図４に示すように、ＤＬＣ絶縁体層１４を構成する炭素・水素量が、層の深さ方向に対して一様に得られたことから、数ｎｍレベルの一層の絶縁体層１４の薄膜化が期待できる。微細化する際、短チャネル効果を抑止するためには、ゲート長ＬＧと絶縁体層１４の膜厚ｄとのアスペクト比（＝ＬＧ／ｄ）を高く保持しなければならないが、ＤＬＣ絶縁体層１４の均質性は、高い比率を保持した状態での微細化を可能にすると考えられる。
FIG. 4 shows a SIMS element depth profile of the DLC insulator layer 14. As shown in FIG. 4, since the depth (Depth) in the vicinity of the graphene channel layer 11 is 40 to 56 nm and a rapid increase in the number of oxygen atoms is observed, the unintentional p-doping is performed in the insulator layer 14. It is thought that it originates from the oxygen atom. This oxygen atom is considered to be derived from water (H 2 O) molecules remaining in the chamber of the PA-PECVD apparatus used for film formation. As shown in FIG. 4, the amount of carbon / hydrogen constituting the DLC insulator layer 14 is uniformly obtained in the depth direction of the layer. Can be expected. When miniaturized in order to suppress the short channel effect, the aspect ratio of the gate length L G and the thickness d of the insulator layer 14 (= L G / d) must be increased to hold a, DLC insulation It is considered that the homogeneity of the body layer 14 enables miniaturization while maintaining a high ratio.
図５に、以上の結果から予想される、グラフェン電界効果トランジスタ１０のバンド予想図を示す。図５に示すように、ＤＬＣ絶縁体層１４（ゲート絶縁膜）の正孔が、空乏層障壁をトンネルするためにグラフェンチャネル層１１に供給されているものと予想される。
FIG. 5 shows a band prediction diagram of the graphene field-effect transistor 10 predicted from the above results. As shown in FIG. 5, it is expected that holes in the DLC insulator layer 14 (gate insulating film) are supplied to the graphene channel layer 11 to tunnel through the depletion layer barrier.
同時に、ＤＬＣ絶縁体層１４とグラフェンチャネル層１１との界面に存在する酸素不純物からも、多大な正孔がグラフェンチャネル層１１に供給されているものと考えられる。図４に示すように、Ｓｉ原子の濃度が急激に上昇して一定の高値に落ち着いた領域は、ＳｉＣ基板である。Ｓｉ原子が高値に達した位置とＣ原子の濃度が若干上昇を開始する位置とが、図４中の点線の位置で一致していることから、この点線の位置が、ＳｉＣ基板上のグラフェンチャネル層１１とＤＬＣ絶縁体層１４との界面であると同定できる。なお、グラフェンチャネル層１１の厚さはサブｎｍであり、図４中では判別できない。
At the same time, it is considered that a large number of holes are supplied to the graphene channel layer 11 also from oxygen impurities present at the interface between the DLC insulator layer 14 and the graphene channel layer 11. As shown in FIG. 4, the region where the concentration of Si atoms suddenly increases and settles to a certain high value is the SiC substrate. Since the position where the Si atom reaches a high value and the position where the concentration of C atoms starts to rise slightly coincide with the position of the dotted line in FIG. 4, the position of the dotted line is the graphene channel on the SiC substrate. It can be identified as the interface between the layer 11 and the DLC insulator layer 14. Note that the thickness of the graphene channel layer 11 is sub-nm and cannot be determined in FIG.
図４に示すように、ＤＬＣ絶縁体層１４とグラフェンチャネル層１１・ＳｉＣ基板との界面で酸素原子の濃度が最高値であることから、酸素原子はグラフェンと直接接する界面位置に局在し、ＳｉＣ基板とＤＬＣ絶縁体層１４の両方向にしみだしてテールを引きながら分布していることがわかる。なお、ＳｉＣ基板側へのしみ出しは、エッチングイオンによるｋｎｏｃｋ ｏｎ効果もしくはｍｉｘｉｎｇ効果によるものである。このため、界面付近に存在する酸素不純物からのグラフェンチャネル層１１に対するキャリア供給能力が最も高いことが予想されると同時に、グラフェンチャネル層１１中のキャリアに対しては、界面に存在する酸素不純物が散乱因子として強く作用するため、グラフェンチャネル層１１内を走行するキャリアの輸送特性を阻害することが推察される。
As shown in FIG. 4, since the concentration of oxygen atoms is the highest value at the interface between the DLC insulator layer 14 and the graphene channel layer 11 / SiC substrate, the oxygen atoms are localized at the interface position in direct contact with the graphene, It can be seen that they are distributed in both directions of the SiC substrate and the DLC insulator layer 14 while drawing a tail. Note that the seepage to the SiC substrate side is due to a knock on effect or a mixing effect due to etching ions. For this reason, it is expected that the carrier supply capacity to the graphene channel layer 11 from the oxygen impurity existing in the vicinity of the interface is the highest, and at the same time, the oxygen impurity present in the interface is Since it acts strongly as a scattering factor, it is presumed to inhibit the transport properties of carriers traveling in the graphene channel layer 11.
図１２に示すＰＡ－ＰＥＣＶＤ装置を利用することにより、変調ドープ部１４ａの形成など、絶縁体層１４の製膜を高精度で行うことができ、図１（ａ）乃至（ｃ）に示すグラフェン電界効果トランジスタ１０を高品質・高精度で製造することができる。その一例を、以下に示す。
By using the PA-PECVD apparatus shown in FIG. 12, the insulator layer 14 can be formed with high accuracy, such as the formation of the modulation doped portion 14a, and the graphene shown in FIGS. The field effect transistor 10 can be manufactured with high quality and high accuracy. An example is shown below.
ＰＡ－ＰＥＣＶＤ装置でＤＬＣを製膜する際には、一般にＣＨ４とＡｒの混合ガス源をＰＡ－ＰＥＣＶＤ装置チャンバー内に導入する。Ｘｅエキシマランプにより紫外線を照射することによって、被製膜基板内の原子が励起され、光電子が基板表面から放出される。この光電子によってＣＨ４が電離し、電離した炭素イオンが基板表面でアモルファス状に堆積される。製膜速度は、真空度、温度、ガスの混合比および流量によって一定に制御される。そこで、製膜開始から例えば数ｎｍのＤＬＣ膜が製膜されたところで、予め用意していたＣＯ２ガス源のバルブを開き、ＣＯ２ガスをチャンバー内に導入すれば、アクセプタとして作用する酸素不純物をドーパントとして注入できる。ドーピング濃度は、ＣＯ２ガスの流量で制御できる。所望の厚さのドープ層が形成されたところで、ＣＯ２ガス源のバルブを閉じて、継続してＤＬＣを製膜すれば、変調ドープ部１４ａを有するＤＬＣ絶縁体層１4を製膜することができる。酸素不純物ガス源としては、ＣＯ２のほか、Ｈ２Ｏでもよい。また、ＮＨ３ガスあるいはＮ２ガスを用いれば、ドナーとして作用する窒素不純物をドープした変調ドープ部１４ａの製膜が実現できる。例えば、グラフェンチャネル層１１との界面から１０ｎｍ弱程度離れた、ＤＬＣ絶縁体層１４内の位置に、数ｎｍの厚みの変調ドープ部１４ａを形成することができる。
When forming a DLC film with a PA-PECVD apparatus, a mixed gas source of CH 4 and Ar is generally introduced into the PA-PECVD apparatus chamber. By irradiating ultraviolet rays with a Xe excimer lamp, atoms in the deposition substrate are excited and photoelectrons are emitted from the substrate surface. CH 4 is ionized by the photoelectrons, and the ionized carbon ions are deposited in an amorphous state on the substrate surface. The film forming speed is controlled to be constant by the degree of vacuum, temperature, gas mixing ratio and flow rate. Therefore, when a DLC film having a thickness of, for example, several nm is formed from the start of film formation, an oxygen impurity that acts as an acceptor can be obtained by opening a valve of a CO 2 gas source prepared in advance and introducing CO 2 gas into the chamber. Can be implanted as a dopant. The doping concentration can be controlled by the flow rate of CO 2 gas. When the doped layer of the desired thickness is formed, the DLC insulator layer 14 having the modulation doped portion 14a can be formed by closing the valve of the CO 2 gas source and continuously forming the DLC. it can. As an oxygen impurity gas source, H 2 O may be used in addition to CO 2 . Further, if NH 3 gas or N 2 gas is used, it is possible to realize the film formation of the modulation dope portion 14a doped with nitrogen impurities acting as a donor. For example, the modulation doped portion 14a having a thickness of several nanometers can be formed at a position in the DLC insulator layer 14 that is about 10 nm away from the interface with the graphene channel layer 11.
この場合、変調ドープ部１４ａ内の不純物原子は、グラフェンと直接接していないため、グラフェンチャネル層１１内のキャリアに対して不純物散乱因子として寄与することはない。このため、グラフェンチャネル層１１内のキャリア輸送特性を阻害する要因とは成りえない。また、その不純物原子がグラフェンに対して正孔キャリア供給能力を有していれば、ＤＬＣ絶縁体層１４のバンドの湾曲にともなう、ＤＬＣ絶縁体層１４とグラフェンチャネル層１１との界面の空乏層障壁の薄層化によって、ＤＬＣ絶縁体層１４内の正孔はグラフェンチャネル層１１への量子力学的トンネルが可能となり、所望の効果を得ることができる。すなわち、グラフェンチャネル層１１を直接傷つけることなくキャリア密度およびキャリア移動度を高めることができ、動作速度の向上を図ることができる。
In this case, since the impurity atoms in the modulation doped portion 14a are not in direct contact with the graphene, they do not contribute to the carriers in the graphene channel layer 11 as impurity scattering factors. For this reason, it cannot be a factor that hinders the carrier transport characteristics in the graphene channel layer 11. In addition, if the impurity atoms have a hole carrier supply capability with respect to graphene, a depletion layer at the interface between the DLC insulator layer 14 and the graphene channel layer 11 accompanying the curvature of the band of the DLC insulator layer 14 By thinning the barrier, holes in the DLC insulator layer 14 can be quantum mechanically tunneled to the graphene channel layer 11, and a desired effect can be obtained. That is, the carrier density and the carrier mobility can be increased without directly damaging the graphene channel layer 11, and the operation speed can be improved.
ところで、上述の酸素不純物原子は、ＤＬＣ中に存在するだけでは室温下で正孔キャリアを価電子帯内に供給する能力をほとんど有しない。これは、図６に示す、ＰＡ－ＰＥＣＶＤ装置によるＤＬＣ製膜の際に、本来のＣＨ４＋Ａｒに加えてＣＯ２ガスを導入したときの、ＤＬＣ膜絶縁耐圧のＣＯ２流量比依存性に見て取れる。なお、図６の横軸の単位は、ＳＣＣＭ（Ｓｔａｎｄａｒｄ Ｃｕｂｉｃ Ｃｅｎｔｉｍｅｔｅｒ ｐｅｒ Ｍｉｎｕｔｅ）であり、０℃、１ａｔｍ環境下での１分あたりの流量（ｃｍ３）を示している。図６に示すように、ＣＯ２流量比の増加とともに、ＤＬＣの絶縁耐圧は上昇傾向を示している。このように、酸素不純物の導入によってＤＬＣの絶縁性が向上することから、酸素不純物はＤＬＣに対してキャリア供給能力を有さないことがわかる。これは、酸素不純物がイオン化して電子を捕獲（従って、価電子帯には正孔を供給）するのに必要な活性化エネルギーが、熱エネルギー（室温下で約２６ｍｅＶ）に比して高いためと考えられる。
By the way, the above-described oxygen impurity atoms have almost no ability to supply hole carriers into the valence band at room temperature simply by being present in the DLC. This can be seen from the dependency of the DLC film dielectric breakdown voltage on the CO 2 flow rate when CO 2 gas is introduced in addition to the original CH 4 + Ar during the DLC film formation by the PA-PECVD apparatus shown in FIG. . The unit of the horizontal axis in FIG. 6 is SCCM (Standard Cubic Centimeter per Minute), and indicates the flow rate (cm 3 ) per minute under an environment of 0 ° C. and 1 atm. As shown in FIG. 6, with the increase in the CO 2 flow ratio, the withstand voltage of DLC shows an increasing trend. As described above, the introduction of oxygen impurities improves the insulating properties of DLC, which indicates that oxygen impurities do not have a carrier supply capability for DLC. This is because the activation energy required for ionization of oxygen impurities to capture electrons (thus supplying holes to the valence band) is higher than thermal energy (about 26 meV at room temperature). it is conceivable that.
しかしながら、実験結果から、グラフェン上に製膜したＤＬＣ絶縁体層１４においては、酸素不純物が正孔を供給する能力を有していることが推察される。これは、図５に示すように、グラフェンと製膜したＤＬＣとの電子親和力の相違によって生じる、ＤＬＣの伝導帯および価電子帯のバンドの湾曲によって果たされる。すなわち、ゲート電極に負バイアスを印加すると、ゲート電極のフェルミ準位ＥＦが印加バイアス分だけ上昇し、それに伴って、ＤＬＣのバンドはゲート電極端が持ち上げられ、グラフェン界面では図５に示すようなバンドの湾曲が生じる。このとき、バンドの湾曲が強いグラフェン界面近傍のＤＬＣ内に酸素不純物が厚さ方向に（わずかでも）広がりを有して存在すると、バンドの湾曲に伴い、酸素不純物のエネルギー準位とＤＬＣの価電子帯上端（ＶＢＭ）とのエネルギー差がバンドの傾斜分だけ実効的に縮まる。このエネルギー差が酸素不純物原子の活性化（イオン化）エネルギーを下回ることにより、価電子帯中の電子を捕獲して価電子帯中に正孔を生じさせる（図５中の「１」）。さらに、ＤＬＣのバンドの湾曲にともなうＤＬＣ－グラフェン界面の空乏層障壁の薄層化によって、ＤＬＣからグラフェンへの量子力学的トンネルが可能となり、それによってグラフェンチャネル層１１に正孔が供給されている（図５中の「２」）、と考えられる。
However, from the experimental results, it is presumed that the DLC insulator layer 14 formed on the graphene has an ability to supply holes by oxygen impurities. As shown in FIG. 5, this is achieved by bending of the conduction band and valence band of DLC caused by the difference in electron affinity between graphene and deposited DLC. That is, when applying a negative bias to the gate electrode, the Fermi level E F of the gate electrode is raised by applying bias amount, with it, DLC bands gate electrode end is lifted, as shown in FIG. 5 is a graphene interface Band bending occurs. At this time, if the oxygen impurity exists in the DLC near the graphene interface where the band is strongly curved and exists in the thickness direction (even if slightly), the energy level of the oxygen impurity and the value of the DLC are accompanied by the curvature of the band. The energy difference from the upper end of the electron band (VBM) is effectively reduced by the inclination of the band. When this energy difference falls below the activation (ionization) energy of the oxygen impurity atoms, electrons in the valence band are captured and holes are generated in the valence band (“1” in FIG. 5). Further, the thinning of the depletion layer barrier at the DLC-graphene interface accompanying the curvature of the DLC band enables a quantum mechanical tunnel from DLC to graphene, thereby supplying holes to the graphene channel layer 11. ("2" in FIG. 5).
グラフェンチャネル層１１の界面と変調ドープ部１４ａとの間隔は、室温動作環境下でキャリアがグラフェンにトンネルできるよう狭く設定する必要がある。室温下では一般に電子の波動関数の広がりは１０ｎｍ程度であることから、十分に高い量子力学的トンネル確率を有するためには、その間隔を１０ｎｍ程度もしくはそれ以下に設定する必要がある。加えて、グラフェンチャネル層１１の界面付近でのＤＬＣ絶縁体層１４のバンドの湾曲にともなう正孔キャリアの供給では、価電子帯の上端（ＶＢＭ）が高くグラフェンチャネル層１１の界面から遠ざかる領域に、キャリア供給域が拡がりを有することから、その拡がり分だけグラフェンチャネル層１１の界面により近接した領域に形成することが望ましい。一方、グラフェンチャネル層１１の界面に最近接可能な位置としては、酸素不純物原子の深さ方向分布がグラフェンチャネル層１１の界面で十分に減衰し得る位置に設定する必要がある。この最近接可能な位置は、製膜に用いる製造装置の不純物濃度分布の制御性にも依存する。以上の点と現状の製膜装置とを仮定すれば、変調ドープ部１４ａはグラフェンチャネル層１１の界面から３乃至６ｎｍ程度の位置に形成することが望ましい。
The distance between the interface of the graphene channel layer 11 and the modulation doped portion 14a needs to be set narrow so that carriers can tunnel to the graphene in a room temperature operating environment. Since the spread of the electron wave function is generally about 10 nm at room temperature, the interval needs to be set to about 10 nm or less in order to have a sufficiently high quantum mechanical tunnel probability. In addition, in the supply of hole carriers accompanying the curvature of the band of the DLC insulator layer 14 in the vicinity of the interface of the graphene channel layer 11, the upper end (VBM) of the valence band is high, and the region away from the interface of the graphene channel layer 11 is used. In addition, since the carrier supply region has an expansion, it is desirable that the carrier supply region be formed in a region closer to the interface of the graphene channel layer 11 by the expansion. On the other hand, the position that can be closest to the interface of the graphene channel layer 11 needs to be set at a position where the depth distribution of oxygen impurity atoms can be sufficiently attenuated at the interface of the graphene channel layer 11. This closest position also depends on the controllability of the impurity concentration distribution of the manufacturing apparatus used for film formation. Assuming the above points and the current film forming apparatus, it is desirable to form the modulation doped portion 14a at a position of about 3 to 6 nm from the interface of the graphene channel layer 11.
実際に、図１（ａ）に相当する構造のグラフェン電界効果トランジスタ１０（以下、「δ－ドープ素子」と呼ぶ）、ならびに、図２乃至４に示したものと同様の、ＤＬＣ絶縁体層１４とグラフェンチャネル層１１との界面に、酸素不純物原子の多くが局在する構造のグラフェン電界効果トランジスタ１０（以下、「界面吸着素子」と呼ぶ）を同一基板上に形成し、両者の特性を比較検証した。図７に、δ－ドープ素子のＳＩＭＳ元素深さプロファイルおよびＩＤＳ－ＶＧＳ特性を示す。また、図８に、界面吸着素子のＳＩＭＳ元素深さプロファイルおよびＩＤＳ－ＶＧＳ特性を示す。
Actually, a graphene field effect transistor 10 (hereinafter referred to as “δ-doped element”) having a structure corresponding to FIG. 1A and a DLC insulator layer 14 similar to that shown in FIGS. A graphene field effect transistor 10 (hereinafter referred to as an “interface adsorbing element”) having a structure in which many oxygen impurity atoms are localized at the interface between the graphene channel layer 11 and the graphene channel layer 11 is formed on the same substrate, and the characteristics of both are compared. Verified. FIG. 7 shows the SIMS element depth profile and I DS -V GS characteristics of the δ-doped element. FIG. 8 shows the SIMS element depth profile and I DS -V GS characteristics of the interface adsorption element.
δ－ドープ素子では、図７（ａ）に示すように、ＤＬＣ絶縁体層１４の厚さは、約４４ｎｍ（図７（ａ）中の点線の位置）と同定できる。また、酸素不純物原子の濃度ピークは、グラフェンチャネル層１１の界面から６ｎｍほどＤＬＣ絶縁体層１４に入ったところに位置しており、変調ドープ部１４ａが形成できていることが確認できる。酸素不純物原子の濃度分布は厚み方向に広がり、グラフェンチャネル層１１の界面においても完全には低減できていないが、図１（ａ）に示す構造に近い状況が再現できている。
In the δ-doped element, as shown in FIG. 7A, the thickness of the DLC insulator layer 14 can be identified as about 44 nm (position of the dotted line in FIG. 7A). Further, the concentration peak of oxygen impurity atoms is located in the DLC insulator layer 14 by about 6 nm from the interface of the graphene channel layer 11, and it can be confirmed that the modulation doped portion 14a can be formed. The concentration distribution of oxygen impurity atoms spreads in the thickness direction and cannot be completely reduced even at the interface of the graphene channel layer 11, but a situation close to the structure shown in FIG.
一方、界面吸着素子では、図８（ａ）に示すように、ＤＬＣ絶縁体層１４の厚さは、約３１ｎｍ（図８（ａ）中の点線の位置）であり、図７に示すδ－ドープ素子よりは薄く、図４と同様にＤＬＣ絶縁体層１４とグラフェンチャネル層１１との界面に、酸素不純物原子濃度のピークが位置している。なお、このピークは、図８（ａ）の丸印（破線）で示すように、図４と同様、吸着水（Ｈ２Ｏ）によるものと考えられる。
On the other hand, in the interface adsorption element, as shown in FIG. 8A, the thickness of the DLC insulator layer 14 is about 31 nm (the position of the dotted line in FIG. 8A), and the δ− shown in FIG. It is thinner than the doping element, and the peak of the oxygen impurity atom concentration is located at the interface between the DLC insulator layer 14 and the graphene channel layer 11 as in FIG. This peak is considered to be due to adsorbed water (H 2 O) as shown in FIG. 4 as indicated by the circles (broken lines) in FIG.
図７（ｂ）および図８（ｂ）に示すように、両者のＩＤＳ－ＶＧＳ特性を比較すると、両者ともグラフェンチャネルＦＥＴ特有のアンバイポーラ特性が現れているが、界面吸着素子では、Ｄｉｒａｃ電位（ＩＤＳが最小となるＶＧＳ電位）が正方向に大きくシフトしており、酸素不純物由来の正孔ドーピングによりグラフェンチャネル層１１がｐ型となっていることがわかる。両者において、特にＶＧＳがＤｉｒａｃ電位より低い領域、すなわち正孔モードによるＩＤＳ－ＶＧＳ特性に注目すると、その微係数∂ＩＤＳ／∂ＶＧＳで定義される相互コンダクタンスｇｍは、図７に示す変調ドープ部１４ａを有するδ－ドープ素子の方が高いことがわかる。
As shown in FIGS. 7B and 8B, when the I DS -V GS characteristics of both are compared, both exhibit the ambipolar characteristics peculiar to graphene channel FETs. It can be seen that the potential (V GS potential at which I DS is minimized) is greatly shifted in the positive direction, and the graphene channel layer 11 is p-type due to hole doping derived from oxygen impurities. In both cases, particularly when attention is paid to the region where V GS is lower than the Dirac potential, that is, the I DS -V GS characteristic due to the hole mode, the mutual conductance g m defined by the derivative ∂I DS / ∂V GS is shown in FIG. It can be seen that the δ-doped element having the modulation doped portion 14a shown in FIG.
ここで、ゲート絶縁膜によるゲート容量Ｃを単純な平行平板近似と仮定すれば、ＤＬＣ絶縁体層１４の厚さの差異により、ＤＬＣ絶縁体層１４が４４ｎｍと厚いδ－ドープ素子のゲート容量Ｃは、酸素不純物濃度ピークがグラフェンチャネル層１１の界面に位置する界面吸着素子のゲート容量Ｃよりも小さいものと考えられる。相互コンダクタンスｇｍは、上述のように、ゲート容量Ｃおよびキャリア移動度μに比例する。また、キャリア移動度μは、キャリアの平均寿命τに比例する。これらのことから、以下の２つのことが推察される。
Here, assuming that the gate capacitance C due to the gate insulating film is a simple parallel plate approximation, the gate capacitance C of the δ-doped element having a thick DLC insulator layer 44 nm of 44 nm due to the difference in thickness of the DLC insulator layer 14. It is considered that the oxygen impurity concentration peak is smaller than the gate capacitance C of the interface adsorption element located at the interface of the graphene channel layer 11. The mutual conductance g m is proportional to the gate capacitance C and the carrier mobility μ as described above. Further, the carrier mobility μ is proportional to the average lifetime τ of carriers. From these, the following two things are inferred.
１）δ－ドープ素子のキャリア移動度μは、界面吸着素子よりも高い。
２）δ－ドープ素子の実効的なゲート容量Ｃは、変調ドープ部１４ａからのキャリア注入効果によって、単純な平行平板近似を仮定したときのゲート容量値よりも高い。
δ－ドープ素子は、グラフェンチャネル層１１の界面の酸素不純物濃度が低いことから、キャリアの散乱が低減され、より長い平均寿命、従ってより高いキャリア移動度μを有することは容易に推察される。同時に、酸素不純物のキャリア供給能力によって、ゲートバイアス印加とともにグラフェンチャネル層１１内のキャリア濃度はより高く増加できることが推察される。 1) The carrier mobility μ of the δ-doped element is higher than that of the interface adsorption element.
2) The effective gate capacitance C of the δ-doped element is higher than the gate capacitance value assuming a simple parallel plate approximation due to the carrier injection effect from the modulation dopedportion 14a.
Since the oxygen impurity concentration at the interface of thegraphene channel layer 11 is low in the δ-doped element, it is easily inferred that carrier scattering is reduced and that it has a longer average lifetime and thus a higher carrier mobility μ. At the same time, it is presumed that the carrier concentration in the graphene channel layer 11 can be increased with the application of the gate bias due to the carrier supply capability of oxygen impurities.
２）δ－ドープ素子の実効的なゲート容量Ｃは、変調ドープ部１４ａからのキャリア注入効果によって、単純な平行平板近似を仮定したときのゲート容量値よりも高い。
δ－ドープ素子は、グラフェンチャネル層１１の界面の酸素不純物濃度が低いことから、キャリアの散乱が低減され、より長い平均寿命、従ってより高いキャリア移動度μを有することは容易に推察される。同時に、酸素不純物のキャリア供給能力によって、ゲートバイアス印加とともにグラフェンチャネル層１１内のキャリア濃度はより高く増加できることが推察される。 1) The carrier mobility μ of the δ-doped element is higher than that of the interface adsorption element.
2) The effective gate capacitance C of the δ-doped element is higher than the gate capacitance value assuming a simple parallel plate approximation due to the carrier injection effect from the modulation doped
Since the oxygen impurity concentration at the interface of the
なお、図１（ｂ）に示すように、グラフェン電界効果トランジスタ１０で、絶縁体層１４は、ゲート電極１５の直下からチャネル層１１まで伸びた高誘電率部（ｈｉｇｈ－κ膜）１４ｂを有し、高誘電率部１４ｂとソース電極１２およびドレイン電極１３との間に、高誘電率部１４ｂよりも誘電率が低い低誘電率部（ｌｏｗ－κ膜）１４ｃを有し、低誘電率部１４ｃに変調ドープ部１４ａを有していてもよい。
As shown in FIG. 1B, in the graphene field effect transistor 10, the insulator layer 14 has a high dielectric constant portion (high-κ film) 14 b extending from immediately below the gate electrode 15 to the channel layer 11. In addition, a low dielectric constant portion (low-κ film) 14c having a dielectric constant lower than that of the high dielectric constant portion 14b is provided between the high dielectric constant portion 14b and the source electrode 12 and the drain electrode 13. The modulation dope part 14a may be included in 14c.
この場合、非特許文献１３に記載の技術を適用し、かつ、通常のＦＥＴ製造加工プロセスで用いられる光露光もしくは電子線露光による選択エッチングの技術を用いることにより、高誘電率部１４ｂと低誘電率部１４ｃとを有するＤＬＣ絶縁体層１４を形成することができる。例えば、初めに高誘電率のＤＬＣ膜を基盤全面に製膜し、ゲート電極直下の真性チャネル領域をレジスト膜でマスクした露光・エッチングによって、ゲート電極直下以外の領域のＤＬＣ膜を除去する。続いて、低誘電率のＤＬＣ膜を全面に製膜し、ゲート電極直下の真性チャネル領域にあるレジスト膜をリフトオフして除去することにより、高誘電率部１４ｂと低誘電率部１４ｃからなるＤＬＣ絶縁体層１４を形成することができる。
In this case, the high dielectric constant portion 14b and the low dielectric constant can be obtained by applying the technique described in Non-Patent Document 13 and using the selective etching technique by light exposure or electron beam exposure used in a normal FET manufacturing process. A DLC insulator layer 14 having a rate portion 14c can be formed. For example, a DLC film having a high dielectric constant is first formed on the entire surface of the substrate, and the DLC film in a region other than directly under the gate electrode is removed by exposure and etching in which an intrinsic channel region directly under the gate electrode is masked with a resist film. Subsequently, a DLC film having a low dielectric constant is formed on the entire surface, and the resist film in the intrinsic channel region immediately below the gate electrode is removed by lift-off, thereby forming a DLC composed of the high dielectric constant portion 14b and the low dielectric constant portion 14c. An insulator layer 14 can be formed.
この場合、高誘電率部１４ｂにより、ゲート電極１５の直下に高い静電誘導効果をもたらすことができ、チャネル界面制御を高精度で行うことができる。また、低誘電率部１４ｃにより、各電極間の寄生容量を低減させることができ、高速化を図ることができる。変調ドープ部１４ａが高誘電率部１４ｂとソース電極１２およびドレイン電極１３との間に設けられているため、アクセス領域のチャネル層１１に効果的にキャリアを供給することができ、アクセス抵抗を低減することができる。
In this case, the high dielectric constant portion 14b can provide a high electrostatic induction effect directly below the gate electrode 15, and the channel interface can be controlled with high accuracy. Further, the low dielectric constant portion 14c can reduce the parasitic capacitance between the electrodes, and can increase the speed. Since the modulation doped portion 14a is provided between the high dielectric constant portion 14b and the source electrode 12 and the drain electrode 13, carriers can be effectively supplied to the channel layer 11 in the access region, and the access resistance is reduced. can do.
さらに、図１（ｃ）に示すように、グラフェン電界効果トランジスタ１０で、絶縁体層１４は、高誘電率部１４ｂにも変調ドープ部１４ａを有していてもよい。この場合、上述のＰＡ－ＰＥＣＶＤ法に変調ドープ部１４ａを形成する手法を、高誘電率部１４ｂおよび低誘電率部１４ｃの製膜時にそれぞれ導入することによって実現することができる。
Further, as shown in FIG. 1C, in the graphene field effect transistor 10, the insulator layer 14 may have the modulation doped portion 14a in the high dielectric constant portion 14b. In this case, the method of forming the modulation dope portion 14a in the above-described PA-PECVD method can be realized by introducing each of the high dielectric constant portion 14b and the low dielectric constant portion 14c during film formation.
この場合、低誘電率部１４ｃおよび高誘電率部１４ｂの変調ドープ部１４ａの極性を、それぞれｐ型およびｎ型、またはｎ型およびｐ型と区別することにより、高いキャリア密度および高い移動度を維持しながら、ｐ－ｎ－ｐ接合またはｎ－ｐ－ｎ接合を作ることができる。これにより、チャネル層１１における電流の整流性をもたらすことができ、デジタルスイッチング動作を実現することができる。なお、低誘電率部１４ｃおよび高誘電率部１４ｂの各変調ドープ部１４ａは、チャネル層１１からの距離が同じであっても、異なっていてもよい。
In this case, a high carrier density and a high mobility can be obtained by distinguishing the polarities of the modulation doped portion 14a of the low dielectric constant portion 14c and the high dielectric constant portion 14b from p-type and n-type, or n-type and p-type, respectively. While maintaining, a pnp junction or an npn junction can be made. Thereby, the current rectification in the channel layer 11 can be provided, and a digital switching operation can be realized. The modulation dope portions 14a of the low dielectric constant portion 14c and the high dielectric constant portion 14b may be the same distance or different from the channel layer 11.
このように、図１（ａ）乃至（ｃ）に示すような高品質・高精度で製造されたグラフェン電界効果トランジスタ１０は、絶縁体層１４とグラフェンチャネル層１１との界面に存在する酸素不純物原子、または、絶縁体層１４の中に不純物として取り込まれた酸素原子によってグラフェンがｐドープされた図２乃至４に示す実施例１のものと比べて、動作速度が飛躍的に速い等の非常に高い性能を示すものと考えられる。
As described above, the graphene field effect transistor 10 manufactured with high quality and high accuracy as shown in FIGS. 1A to 1C has oxygen impurities present at the interface between the insulator layer 14 and the graphene channel layer 11. Compared to those of Example 1 shown in FIGS. 2 to 4 in which graphene is p-doped with atoms or oxygen atoms incorporated as impurities in the insulator layer 14, the operation speed is extremely high. It is thought that it shows high performance.
１０ グラフェン電界効果トランジスタ
１１ チャネル層
１２ ソース電極
１３ ドレイン電極
１４ 絶縁体層
１４ａ 変調ドープ部
１４ｂ 高誘電率部
１４ｃ 低誘電率部
１５ ゲート電極
DESCRIPTION OFSYMBOLS 10 Graphene field effect transistor 11 Channel layer 12 Source electrode 13 Drain electrode 14 Insulator layer 14a Modulation dope part 14b High dielectric constant part 14c Low dielectric constant part 15 Gate electrode
１１ チャネル層
１２ ソース電極
１３ ドレイン電極
１４ 絶縁体層
１４ａ 変調ドープ部
１４ｂ 高誘電率部
１４ｃ 低誘電率部
１５ ゲート電極
DESCRIPTION OF
Claims (7)
- グラフェンから成るチャネル層と、
前記チャネル層の上に設けられ、グラフェンとの反応性が低い材料から成る絶縁体層と、
前記チャネル層に電気的に接続され、前記絶縁体層を挟む位置に互いに離れて配置されたソース電極およびドレイン電極と、
前記絶縁体層の上に設けられたゲート電極とを有し、
前記絶縁体層は、前記チャネル層にキャリアを供給可能な薄膜状の変調ドープ部を有することを
特徴とするグラフェン電界効果トランジスタ。 A channel layer made of graphene,
An insulator layer formed on the channel layer and made of a material having low reactivity with graphene;
A source electrode and a drain electrode that are electrically connected to the channel layer and are spaced apart from each other at a position sandwiching the insulator layer;
A gate electrode provided on the insulator layer;
The graphene field effect transistor according to claim 1, wherein the insulator layer has a thin film modulation doped portion capable of supplying carriers to the channel layer. - 前記変調ドープ部は、前記チャネル層との間に、トンネル効果により前記チャネル層にキャリアを供給可能な距離をあけて設けられていることを特徴とする請求項１記載のグラフェン電界効果トランジスタ。 2. The graphene field effect transistor according to claim 1, wherein the modulation doped portion is provided with a distance capable of supplying carriers to the channel layer by a tunnel effect between the modulation layer and the channel layer.
- 前記変調ドープ部は、前記チャネル層との間に、３乃至６ｎｍの距離をあけて設けられていることを特徴とする請求項１または２記載のグラフェン電界効果トランジスタ。 The graphene field effect transistor according to claim 1 or 2, wherein the modulation doped portion is provided with a distance of 3 to 6 nm between the channel layer and the channel layer.
- 前記絶縁体層は、ダイヤモンドライクカーボンから成ることを特徴とする請求項１乃至３のいずれか１項に記載のグラフェン電界効果トランジスタ。 The graphene field effect transistor according to any one of claims 1 to 3, wherein the insulator layer is made of diamond-like carbon.
- 前記絶縁体層は、前記ゲート電極の直下から前記チャネル層まで伸びた高誘電率部を有し、前記高誘電率部と前記ソース電極および前記ドレイン電極との間に、前記高誘電率部よりも誘電率が低い低誘電率部を有し、前記低誘電率部に前記変調ドープ部を有することを特徴とする請求項１乃至４のいずれか１項に記載のグラフェン電界効果トランジスタ。 The insulator layer has a high dielectric constant portion extending from immediately below the gate electrode to the channel layer, and is between the high dielectric constant portion and the source and drain electrodes than the high dielectric constant portion. 5. The graphene field effect transistor according to claim 1, further comprising: a low dielectric constant portion having a low dielectric constant, wherein the low dielectric constant portion includes the modulation doped portion.
- 前記絶縁体層は、前記高誘電率部にも前記変調ドープ部を有することを特徴とする請求項５記載のグラフェン電界効果トランジスタ。 6. The graphene field effect transistor according to claim 5, wherein the insulator layer has the modulation doped portion also in the high dielectric constant portion.
- グラフェンから成るチャネル層と、
前記チャネル層の上に設けられ、グラフェンとの反応性が低い材料から成る絶縁体層とを有し、
前記絶縁体層は、前記チャネル層にキャリアを供給可能な薄膜状の変調ドープ部を有することを
特徴とするグラフェン半導体部材。
A channel layer made of graphene,
An insulator layer provided on the channel layer and made of a material having low reactivity with graphene;
The graphene semiconductor member, wherein the insulator layer has a thin film-shaped modulation doped portion capable of supplying carriers to the channel layer.
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