WO2012099209A1 - Silicon carbide single crystal substrate and method for producing semiconductor element - Google Patents

Silicon carbide single crystal substrate and method for producing semiconductor element Download PDF

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Publication number
WO2012099209A1
WO2012099209A1 PCT/JP2012/051095 JP2012051095W WO2012099209A1 WO 2012099209 A1 WO2012099209 A1 WO 2012099209A1 JP 2012051095 W JP2012051095 W JP 2012051095W WO 2012099209 A1 WO2012099209 A1 WO 2012099209A1
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silicon carbide
layer
single crystal
carbide single
crystal substrate
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PCT/JP2012/051095
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French (fr)
Japanese (ja)
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賢司 沖野
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株式会社ブリヂストン
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • C—CHEMISTRY; METALLURGY
    • C01—INORGANIC CHEMISTRY
    • C01B—NON-METALLIC ELEMENTS; COMPOUNDS THEREOF; METALLOIDS OR COMPOUNDS THEREOF NOT COVERED BY SUBCLASS C01C
    • C01B32/00—Carbon; Compounds thereof
    • C01B32/15—Nano-sized carbon materials
    • C01B32/182—Graphene
    • C01B32/184—Preparation
    • C01B32/188—Preparation by epitaxial growth
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/36—Carbides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1606—Graphene
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET

Definitions

  • the present invention relates to a silicon carbide single crystal substrate and a method for manufacturing a semiconductor element.
  • a semiconductor element in which a gallium nitride hetero film (GaN film) is epitaxially grown on a support substrate made of a silicon carbide single crystal has been applied in the high frequency field (see, for example, Patent Document 1).
  • the high-frequency field include HEMT (High Electron Mobility Transistor: High Electron Mobility TranSiStor), MOSFET (Metel-Oxide-Semiconductor Field-Effect TranSiStor), and the like.
  • the present invention has been made in view of such a situation, and an object thereof is to provide a silicon carbide single crystal substrate that can be used as a semiconductor element that realizes high-speed operation, and a method for manufacturing the semiconductor element. .
  • a feature of the present invention is a silicon carbide single crystal substrate (a silicon carbide single crystal substrate 1 and a support substrate 11) including a layer formed by a epitaxial growth, and a graphene layer (graphene layer) formed by stacking a plurality of graphene layers 13) and a silicon carbide layer (second silicon carbide layer 14) formed on the surface of the graphene layer and formed by epitaxial growth, and between the silicon carbide layer and the silicon carbide single crystal substrate.
  • the gist is that the graphene layer is located.
  • the silicon carbide single crystal substrate according to the feature of the present invention has a graphene layer formed by stacking a plurality of graphenes.
  • the electrical conductivity of graphene is higher than the electrical conductivity of the ion-implanted layer obtained by adjusting the impurities of silicon carbide by the combination of conventional ion implantation and activation annealing process, so the response speed can be increased. it can. Therefore, high-speed operation of the semiconductor element can be realized, which can contribute to improvement of the performance of the semiconductor element.
  • first silicon carbide layer 12 formed on the surface of the silicon carbide single crystal substrate and formed by epitaxial growth, and the substrate side silicon carbide layer includes the graphene layer and the silicon carbide single layer. It may be located between the crystal substrate.
  • a feature of the semiconductor element of the present invention is that a silicon carbide single crystal substrate (support substrate 111) made of a silicon carbide single crystal having semi-insulating properties and a channel layer (channel layer 113) formed by stacking a plurality of graphenes. ), A doped layer (doped layer 114) formed by epitaxial growth on the surface of the channel layer, and a surface of the doped layer located on the opposite side of the surface of the doped layer on which the channel layer is formed A source electrode (source electrode 121), a gate electrode (gate electrode 122), and a drain electrode (drain electrode 123) formed on the side, and the channel between the doped layer and the silicon carbide single crystal substrate.
  • the gist is that the layer is located.
  • the graphene layer not containing silicon forms a high electron transfer layer, the mobility of electrons can be increased. Thereby, the switching speed of a semiconductor element can be improved.
  • the doped layer may be made of silicon carbide single crystal or silicon carbide polycrystal.
  • a buffer layer formed on the surface of the silicon carbide single crystal substrate and formed by epitaxial growth may be provided, and the buffer layer may be located between the channel layer and the silicon carbide single crystal substrate.
  • the source electrode and the drain electrode are formed on the surface of the doped layer, a protective layer covering the surface of the doped layer is formed between the source electrode and the drain electrode, and the gate electrode It may be formed on the surface of the protective layer.
  • a feature of the method for manufacturing a semiconductor device is a reactor for forming a crystal layer on a silicon carbide single crystal substrate made of silicon carbide single crystal by chemical vapor deposition, chemical vapor deposition, or chemical vapor deposition.
  • a method of manufacturing a semiconductor element using a reaction apparatus comprising: a step of forming a first silicon carbide layer by epitaxial growth on a surface of the silicon carbide single crystal substrate in the same reaction furnace; and A step of forming a graphene layer formed by stacking a plurality of graphenes on the surface of one silicon carbide layer, and a step of forming a second silicon carbide layer by epitaxial growth on the surface of the graphene layer,
  • the gist is that the silicon layer is located between the graphene layer and the silicon carbide single crystal substrate.
  • the graphene layer is formed on the silicon carbide single crystal substrate. Since the electrical conductivity of graphene is higher than that of the conventional channel layer, the response speed can be increased. Therefore, high-speed operation of the semiconductor element can be realized, which can contribute to improvement of the performance of the semiconductor element.
  • a silicon carbide single crystal substrate made of a silicon carbide single crystal having semi-insulating properties by chemical vapor deposition, chemical vapor deposition, or chemical vapor deposition
  • a method for manufacturing a semiconductor device comprising: a channel layer formed by stacking a plurality of graphenes; and a doped layer formed on the surface of the channel layer and formed by epitaxial growth.
  • FIG. 1 is a cross-sectional view illustrating the structure of a silicon carbide single crystal substrate shown as an embodiment of the present invention.
  • FIG. 2 is a diagram for explaining a method of manufacturing a semiconductor element shown as an embodiment of the present invention.
  • FIG. 3 is a cross-sectional view illustrating the structure of a semiconductor device shown as another embodiment of the present invention.
  • FIG. 4 is a cross-sectional view illustrating the structure of a semiconductor device shown as another embodiment of the present invention.
  • FIG. 5 is a cross-sectional view illustrating the structure of a semiconductor device shown as another embodiment of the present invention.
  • FIG. 6 is a diagram for explaining a method for manufacturing a semiconductor device shown as another embodiment of the present invention.
  • Silicon carbide single crystal substrate An embodiment of a silicon carbide single crystal substrate according to the present invention will be described with reference to FIGS. 1 and 2.
  • FIG. 1 is a cross-sectional view illustrating a silicon carbide single crystal substrate 1 according to an embodiment of the present invention.
  • Silicon carbide single crystal substrate 1 has a support substrate 11, a first silicon carbide layer 12, a graphene layer 13, and a second silicon carbide layer 14.
  • the silicon carbide single crystal substrate 1 has the first silicon carbide layer 12, the graphene layer 13, and the second silicon carbide layer 14 in this order on the surface of the silicon carbide single crystal support substrate 11.
  • Silicon carbide single crystal substrate 1 includes a layer formed by epitaxial growth.
  • the support substrate 11 is formed of a single crystal of semi-insulating or conductive silicon carbide.
  • the first silicon carbide layer 12 is formed on the surface of the support substrate 11.
  • the first silicon carbide layer 12 is located between the support substrate 11 and the graphene layer 13.
  • the first silicon carbide layer 12 is in contact with the support substrate 11 and the graphene layer 13.
  • the first silicon carbide layer 12 is formed by epitaxial growth.
  • the first silicon carbide layer 12 can be, for example, a doped layer.
  • the thickness of the first silicon carbide layer 12 can be 0.2 ⁇ m to 20 ⁇ m, and particularly 0.5 ⁇ m.
  • the graphene layer 13 is formed on the surface opposite to the surface on which the silicon carbide single crystal support substrate 11 of the first silicon carbide layer 12 is disposed.
  • the graphene layer 13 is located between the support substrate 11 and the second silicon carbide layer 14.
  • the graphene layer 13 is in contact with the first silicon carbide layer 12 and the second silicon carbide layer 14.
  • the graphene layer 13 is formed by stacking a plurality of graphenes.
  • the graphene layer 13 is formed of a plurality of graphite single layer films.
  • Graphene is composed of a single layer of carbon atoms. That is, the graphene layer 13 is composed of a two-dimensional graphite sheet in which graphite spreads in a sheet shape.
  • the thickness of the graphene layer 13 is a thickness at which a quantum effect is observed.
  • the thickness of the graphene layer can be 1 nm to 10 nm.
  • the thickness of the graphene layer 13 can be 5 nm or less.
  • the second silicon carbide layer 14 is formed by epitaxial growth on the surface of the graphene layer 13 opposite to the surface on which the first silicon carbide layer 12 is disposed.
  • the second silicon carbide layer 14 is formed of silicon carbide single crystal or polycrystal.
  • the second silicon carbide layer 14 is formed on the surface of the graphene layer 13 by epitaxial growth.
  • the thickness of the second silicon carbide layer 14 can be 10 nm to 20 nm.
  • the silicon carbide single crystal substrate 1 described above can be applied to a part of a semiconductor element.
  • the silicon carbide single crystal substrate 1 can be applied to a high electron mobility transistor (HEMT).
  • the support substrate 11 can constitute a semi-insulating silicon carbide single crystal substrate
  • the first silicon carbide layer 12 can constitute a buffer layer.
  • the graphene layer 13 can constitute a channel layer that is an electron transit layer.
  • the second silicon carbide layer 14 can constitute a doped layer that is an electron supply layer.
  • HEMT high electron mobility transistor
  • the graphene layer 13 is formed. Since the electrical conductivity of graphene is higher than the electrical conductivity of the conventional ion implantation layer, the electrical response speed can be increased. Therefore, it can contribute to the performance improvement of the semiconductor element.
  • a semiconductor element 1 according to this embodiment includes a support substrate 11, a buffer layer 12, a channel layer 13, and a doped layer.
  • Semiconductor element 1 has the same configuration as silicon carbide single crystal substrate 1 described above. That is, the buffer layer 12 is the first silicon carbide layer 12 described above.
  • the channel layer 13 is the graphene layer 13 described above.
  • the doped layer 14 is the second silicon carbide layer 14.
  • FIG. 2 is a diagram for explaining a semiconductor device manufacturing method according to an embodiment of the present invention.
  • the semiconductor element 1 is manufactured by a reaction apparatus (CVD apparatus) including a reaction furnace for forming a crystal layer on a silicon carbide single crystal substrate by chemical vapor deposition, chemical vapor deposition, or chemical vapor deposition.
  • CVD apparatus reaction apparatus including a reaction furnace for forming a crystal layer on a silicon carbide single crystal substrate by chemical vapor deposition, chemical vapor deposition, or chemical vapor deposition.
  • the first silicon carbide layer 12, the graphene layer 13, and the second silicon carbide layer 14 can be formed on the support substrate 11 in the same reaction furnace. That is, step S11, step S12, and step S13 can be performed in the same reactor.
  • step S11 a reaction gas and a carrier gas are introduced onto a silicon carbide single crystal support substrate 11 set in a CVD apparatus.
  • the reaction gas contains silane (SiH 4 ) as a silicon source and methane (C 3 H 8 ) as a carbon source.
  • the carrier gas contains hydrogen.
  • the support substrate 11 has a semi-insulating property.
  • step S11 a first silicon carbide layer 12 is formed on the surface of the silicon carbide single crystal support substrate 11 by epitaxial growth.
  • step S12 after the reaction gas is introduced, the supply of the reaction gas and the carrier gas is stopped, and the temperature of the reaction system is 1400 ° C. to 1800 ° C., and the degree of vacuum is 1 ⁇ 10 ⁇ 4 mbar to 1 ⁇ 10. Maintain at -8 mbar for 2 minutes to 1.5 hours.
  • step S ⁇ b> 12 the graphene layer 13 is formed on the surface of the m first silicon carbide layer 12 by the sublimation of silicon in the first silicon carbide layer 12.
  • step S12 the graphene layer 13 is grown.
  • step S13 the hydrogen gas and the reactive gas are again introduced so that the pressure becomes 5 mbar to 500 mbar and maintained for 1 to 2 minutes.
  • the second silicon carbide layer 14 is formed on the surface of the graphene layer 13 by epitaxial growth. Specifically, in step S13, the second silicon carbide layer 14 is formed by epitaxial growth on the surface of the graphene layer 13 opposite to the surface of the graphene layer 13 on which the silicon carbide single crystal support substrate 11 is disposed.
  • the semiconductor element 1 according to this embodiment is manufactured.
  • the graphene layer 13 is formed. Since the electrical conductivity of graphene is higher than the electrical conductivity of the conventional ion implantation layer, the electrical response speed can be increased. Therefore, it can contribute to the performance improvement of the semiconductor element.
  • graphene can be formed on the silicon carbide single crystal by a sublimation method that sublimates a silicon source, and therefore, the step of forming the first silicon carbide layer 12 and the graphene layer 13 are formed.
  • the step and the step of forming the second silicon carbide layer 14 can be performed in the same reactor. Therefore, it is possible to contribute to the improvement of the performance of the semiconductor element, and the manufacturing process can be made more efficient. Furthermore, since it can manufacture in the same reactor, mixing of an impurity can be suppressed.
  • a semiconductor device in which a doped layer and a channel layer are formed on a substrate made of a semi-insulating silicon carbide single crystal is a high frequency switch, a power amplifier, a low noise amplifier, or the like. Used in the high frequency field.
  • This semiconductor element is formed by epitaxially growing a gallium nitride film (GaN film) or an aluminum gallium nitride film (AlGaN film) on a support substrate made of a silicon carbide single crystal, and is applied to a semiconductor laser device (for example, (See JP-A-11-103134).
  • FIG. 3 is a cross-sectional view illustrating a semiconductor element 2 according to a second embodiment of the present invention.
  • the semiconductor element 2 includes a channel layer 113 that is an electron transit layer through which a main current flows and an n-type doped layer 114 that is an electron supply layer formed on a semi-insulating support substrate 111. Yes.
  • a source electrode 121, a gate electrode 122, and a drain electrode 123 are formed on the surface of the doped layer 114 opposite to the surface on which the support substrate 111 is disposed.
  • the semiconductor element 2 constitutes a high electron mobility transistor (HEMT).
  • HEMT high electron mobility transistor
  • the support substrate 111 is made of a semi-insulating silicon carbide single crystal.
  • the channel layer 113 is located between the support substrate 111 and the doped layer 114. In the present embodiment, the channel layer 113 is in contact with the support substrate 111 and the doped layer 114.
  • the channel layer 113 is formed by stacking a plurality of graphenes.
  • the channel layer 113 is formed of a plurality of graphite single layer films. That is, the channel layer 113 is composed of a two-dimensional graphite sheet in which graphite is spread in a sheet shape.
  • the thickness of the channel layer 113 can be 5 nm or less.
  • the doped layer 114 is formed of silicon carbide single crystal or polycrystal.
  • the doped layer 114 is formed on the surface of the channel layer 113 by epitaxial growth.
  • the doped layer 114 has a thickness of about 10 nm to 20 nm.
  • the source electrode 121, the gate electrode 122, and the drain electrode 123 are formed on the surface side of the doped layer 114 located on the opposite side to the surface of the doped layer 114 on which the channel layer 113 is formed.
  • the source electrode 121, the gate electrode 122, and the drain electrode 123 are formed on the surface of the doped layer 114.
  • the gate electrode 122 is in contact with the surface of the doped layer 114 to form a Schottky junction. At this time, a depletion layer having a Schottky junction is formed in the doped layer 114.
  • the source electrode 121 and the drain electrode 123 are formed so as to obtain ohmic contact with the doped layer.
  • the source electrode 121 and the drain electrode 123 are made of, for example, an AuGe alloy.
  • FIG. 4 is a cross-sectional view of a semiconductor element 3 shown as a third embodiment.
  • a buffer layer 112 made of silicon carbide is disposed between the support substrate 111 and the channel layer 113 (graphene layer). That is, the buffer layer 112 is located between the support substrate 111 and the channel layer 113. The buffer layer 112 is in contact with the support substrate 111 and the channel layer 113.
  • the buffer layer 112 is formed by epitaxially growing silicon carbide on the surface of the support substrate 111.
  • the buffer layer 112 is an undoped layer. In the embodiment, the thickness of the buffer layer 112 is about 0.1 to 1.0 ⁇ m.
  • FIG. 5 is a cross-sectional view of a semiconductor element 4 shown as a fourth embodiment.
  • a protective layer 115 covering the surface of the doped layer 114 is formed between the source electrode 121 and the drain electrode 123 on the surface of the doped layer 114.
  • the gate electrode 122 is formed on the surface of the protective layer 115.
  • the source electrode 121 and the drain electrode 123 are formed on the surface of the doped layer 114.
  • the buffer layer 112 formed of silicon carbide is disposed between the support substrate 111 and the channel layer 113 (graphene layer), but the buffer layer 112 may not be provided.
  • FIG. 6 is a diagram illustrating a manufacturing method of the semiconductor device according to the embodiment of the present invention. Below, the manufacturing method which manufactures the semiconductor element 3 which forms the buffer layer 112 is demonstrated.
  • the semiconductor element 3 is a reaction including a reaction furnace for forming a channel layer and a doped layer on a semi-insulating silicon carbide single crystal substrate by chemical vapor deposition, chemical vapor deposition, or chemical vapor deposition. Manufactured by an apparatus (CVD apparatus).
  • the semiconductor element 3 is manufactured by a series of steps shown in FIG. That is, in step S21, the reaction gas and the carrier gas are introduced onto the silicon carbide single crystal support substrate 111 set in the CVD apparatus.
  • the reaction gas includes silane (SiH 4 ) as a silicon source and methane (C 3 H 8 ) as a carbon source.
  • the carrier gas contains hydrogen.
  • the buffer layer 112 is formed by epitaxial growth on the surface of the silicon carbide single crystal support substrate 111.
  • step S22 after the reaction gas is introduced, the supply of the reaction gas and the carrier gas is stopped, and the temperature of the reaction system is 1400 ° C. to 1800 ° C., and the degree of vacuum is 1 ⁇ 10 ⁇ 4 to 1 ⁇ 10 ⁇ . Maintain at less than 8 mbar for 2 minutes to 1.5 hours.
  • the channel layer 113 (graphene layer) is grown.
  • step S23 the hydrogen gas and the reactive gas are again introduced so that the pressure becomes 1 mbar to 500 mbar and maintained for 1 to 2 minutes.
  • step S23 a silicon carbide layer is formed by epitaxial growth on the surface of the channel layer 113 (graphene layer) opposite to the silicon carbide single crystal support substrate 111.
  • the silicon carbide layer constitutes the doped layer 114.
  • step S23 After the doped layer 114 is formed in step S23, the source electrode 121, the gate electrode 122, and the drain electrode 123 are formed on the surface of the doped layer 114 by sputtering in step S24.
  • the channel layer 113 is formed of a graphene layer not containing silicon, and the graphene layer forms a high electron transfer layer. Electron mobility can be increased and the switching speed of the semiconductor element can be improved.
  • the buffer layer 112 formed of silicon carbide is disposed between the support substrate 111 and the channel layer 113 (graphene layer).
  • a protective layer 115 covering the surface of the doped layer 114 is formed between the source electrode 121 and the drain electrode 123 on the surface of the doped layer 114, and the gate electrode 122 is formed on the surface of the protective layer 115.
  • the silicon carbide single crystal substrate 1 described above has the first silicon carbide layer 12, but is not limited thereto.
  • the support substrate 11 and the graphene layer 13 may be in direct contact.
  • Example 1 Silicon Carbide Single Crystal Substrate A silicon carbide single crystal substrate according to the present invention was produced and performance was evaluated.
  • step S11 a mixed gas containing silane (SiH 4 ) gas and methane (C 3 H 8 ) gas as a reaction gas was used on a silicon carbide single crystal support substrate. Moreover, hydrogen gas was used as carrier gas.
  • the 1st silicon carbide layer was created by process S11. When the thickness of the first silicon carbide layer was grown to 6 ⁇ m, the supply of the reaction gas was stopped.
  • step S12 The reaction system conditions in step S12 were set as follows. Temperature: 1650 ° C Degree of vacuum: 1 ⁇ 10 ⁇ 5 mbar Reaction time: 1.0 hour
  • step S13 hydrogen gas and reaction gas were again introduced so that the pressure of the reaction system was 100 mbar.
  • step S21 a mixed gas containing silane (SiH 4 ) gas and methane (C 3 H 8 ) gas was used. Moreover, hydrogen gas was used as carrier gas.
  • step S22 The reaction system conditions in step S22 were set as follows. Temperature: 1650 ° C Degree of vacuum: 1 ⁇ 10 ⁇ 5 mbar Reaction time: 1.0 hour
  • step S23 hydrogen gas and reaction gas were again introduced so that the pressure of the reaction system was 100 mbar.
  • the semiconductor element according to the present invention has excellent mobility. Therefore, according to the semiconductor element of the present invention, the switching speed can be improved.
  • the present invention it is possible to provide a silicon carbide single crystal substrate that can be used as a semiconductor element that realizes high-speed operation, and a method for manufacturing a semiconductor element. Further, according to the present invention, it is possible to provide a semiconductor element capable of improving the switching speed and a method for manufacturing the semiconductor element.

Abstract

Provided is a silicon carbide single crystal substrate (1) which has: a graphene layer (13) which comprises layers formed by epitaxial growth and is formed by laminating several graphene layers; a second silicon carbide layer (14) which is formed on the surface of the graphene layer (13) and is formed by epitaxial growth, wherein the graphene layer (13) is disposed between the second silicon carbide layer (14) and a support substrate (11).

Description

炭化ケイ素単結晶基板及び半導体素子の製造方法Silicon carbide single crystal substrate and method for manufacturing semiconductor device
　本発明は、炭化ケイ素単結晶基板、及び半導体素子の製造方法に関する。 The present invention relates to a silicon carbide single crystal substrate and a method for manufacturing a semiconductor element.
　従来、炭化ケイ素単結晶からなる支持基板の上に、窒化ガリウムヘテロ膜（ＧａＮ膜）をエピタキシャル成長させた半導体素子は、高周波分野において適用されてきた（例えば、特許文献１参照）。高周波分野には、例えば、ＨＥＭＴ（高電子移動トランジスタ：High Electron Mobility TranＳiＳtor）、ＭＯＳＦＥＴ（Metel-Oxide-Ｓemiconductor Field-Effect TranＳiＳtor）などが挙げられる。 Conventionally, a semiconductor element in which a gallium nitride hetero film (GaN film) is epitaxially grown on a support substrate made of a silicon carbide single crystal has been applied in the high frequency field (see, for example, Patent Document 1). Examples of the high-frequency field include HEMT (High Electron Mobility Transistor: High Electron Mobility TranSiStor), MOSFET (Metel-Oxide-Semiconductor Field-Effect TranSiStor), and the like.
特開２０１０－２６５１２６号公報JP 2010-265126 A
　しかしながら、近年の、通信機器の通信速度向上や、半導体レーザ装置の高性能化などの要求に伴って、スイッチング、整流、発振、増幅などに適用される半導体素子の更なる改良、特に高速動作性能の向上が望まれていた。 However, due to recent demands for higher communication speed of communication equipment and higher performance of semiconductor laser devices, further improvement of semiconductor elements applied to switching, rectification, oscillation, amplification, etc., especially high-speed operation performance Improvement was desired.
　そこで、本発明は、このような状況に鑑みてなされたものであり、高速動作を実現する半導体素子として用いることが可能な炭化ケイ素単結晶基板、及び半導体素子の製造方法の提供を目的とする。 Accordingly, the present invention has been made in view of such a situation, and an object thereof is to provide a silicon carbide single crystal substrate that can be used as a semiconductor element that realizes high-speed operation, and a method for manufacturing the semiconductor element. .
　上述した課題を解決するため、本発明は、次の特徴を有している。本発明の特徴は、ピタキシャル成長によって形成された層を備える炭化ケイ素単結晶基板（炭化ケイ素単結晶基板１、支持基板１１）であって、グラフェンが複数積層されて形成されたグラフェン層（グラフェン層１３）と、前記グラフェン層の表面に形成され、エピタキシャル成長によって形成された炭化ケイ素層（第２炭化ケイ素層１４）と、を有し、前記炭化ケイ素層と前記炭化ケイ素単結晶基板との間にグラフェン層が位置することを要旨とする。 In order to solve the above-described problems, the present invention has the following features. A feature of the present invention is a silicon carbide single crystal substrate (a silicon carbide single crystal substrate 1 and a support substrate 11) including a layer formed by a epitaxial growth, and a graphene layer (graphene layer) formed by stacking a plurality of graphene layers 13) and a silicon carbide layer (second silicon carbide layer 14) formed on the surface of the graphene layer and formed by epitaxial growth, and between the silicon carbide layer and the silicon carbide single crystal substrate. The gist is that the graphene layer is located.
　本発明の特徴に係る炭化ケイ素単結晶基板は、グラフェンが複数積層されて形成されたグラフェン層を有する。グラフェンの電気伝導度は、従来のイオン注入と活性化アニール工程との組み合わせによって炭化ケイ素の不純物を調整することによって得られるイオン注入層の電気伝導度に比べて高いため、応答速度を速めることができる。従って、半導体素子の高速動作を実現でき、半導体素子の性能向上に寄与することができる。 The silicon carbide single crystal substrate according to the feature of the present invention has a graphene layer formed by stacking a plurality of graphenes. The electrical conductivity of graphene is higher than the electrical conductivity of the ion-implanted layer obtained by adjusting the impurities of silicon carbide by the combination of conventional ion implantation and activation annealing process, so the response speed can be increased. it can. Therefore, high-speed operation of the semiconductor element can be realized, which can contribute to improvement of the performance of the semiconductor element.
　前記炭化ケイ素単結晶基板の表面に形成され、エピタキシャル成長によって形成された基板側炭化ケイ素層（第１炭化ケイ素層１２）を有し、前記基板側炭化ケイ素層は、前記グラフェン層と前記炭化ケイ素単結晶基板との間に位置してもよい。 It has a substrate side silicon carbide layer (first silicon carbide layer 12) formed on the surface of the silicon carbide single crystal substrate and formed by epitaxial growth, and the substrate side silicon carbide layer includes the graphene layer and the silicon carbide single layer. It may be located between the crystal substrate.
　また、本発明の半導体素子に係る特徴は、半絶縁性を有する炭化ケイ素単結晶からなる炭化ケイ素単結晶基板（支持基板１１１）と、グラフェンが複数積層されて形成されたチャネル層（チャネル層１１３）と、前記チャネル層の表面に形成され、エピタキシャル成長よって形成されたドープ層（ドープ層１１４）と、前記チャネル層が形成された前記ドープ層の表面とは反対側に位置する前記ドープ層の表面側に形成されたソース電極（ソース電極１２１）、ゲート電極（ゲート電極１２２）及びドレイン電極（ドレイン電極１２３）と、を有し、前記ドープ層と前記炭化ケイ素単結晶基板との間に前記チャネル層が位置することを要旨とする。 In addition, a feature of the semiconductor element of the present invention is that a silicon carbide single crystal substrate (support substrate 111) made of a silicon carbide single crystal having semi-insulating properties and a channel layer (channel layer 113) formed by stacking a plurality of graphenes. ), A doped layer (doped layer 114) formed by epitaxial growth on the surface of the channel layer, and a surface of the doped layer located on the opposite side of the surface of the doped layer on which the channel layer is formed A source electrode (source electrode 121), a gate electrode (gate electrode 122), and a drain electrode (drain electrode 123) formed on the side, and the channel between the doped layer and the silicon carbide single crystal substrate. The gist is that the layer is located.
　本発明の特徴によれば、ケイ素が含まれないグラフェン層が高電子移動層を形成するため、電子の移動度を高めることができる。これにより、半導体素子のスイッチング速度を向上させることができる。 According to the feature of the present invention, since the graphene layer not containing silicon forms a high electron transfer layer, the mobility of electrons can be increased. Thereby, the switching speed of a semiconductor element can be improved.
　前記ドープ層は、炭化ケイ素単結晶又は炭化ケイ素多結晶からなってもよい。 The doped layer may be made of silicon carbide single crystal or silicon carbide polycrystal.
　前記炭化ケイ素単結晶基板の表面に形成され、エピタキシャル成長によって形成されたバッファ層を有し、前記バッファ層は、前記チャネル層と前記炭化ケイ素単結晶基板との間に位置してもよい。 A buffer layer formed on the surface of the silicon carbide single crystal substrate and formed by epitaxial growth may be provided, and the buffer layer may be located between the channel layer and the silicon carbide single crystal substrate.
　前記ソース電極及び前記ドレイン電極は、前記ドープ層の表面に形成され、前記ソース電極と前記ドレイン電極と間には、前記ドープ層の表面を被覆する保護層が形成され、前記ゲート電極は、前記保護層の表面に形成されてもよい。 The source electrode and the drain electrode are formed on the surface of the doped layer, a protective layer covering the surface of the doped layer is formed between the source electrode and the drain electrode, and the gate electrode It may be formed on the surface of the protective layer.
　また、発明の半導体素子の製造方法に係る特徴は、化学気相成長法、化学気相蒸着、又は化学蒸着によって炭化ケイ素単結晶からなる炭化ケイ素単結晶基板の上に結晶層を形成する反応炉を備えた反応装置によって半導体素子を製造する半導体素子の製造方法であって、同一の反応炉において、前記炭化ケイ素単結晶基板の表面にエピタキシャル成長によって第１炭化ケイ素層を形成する工程と、前記第１炭化ケイ素層の表面にグラフェンが複数積層されて形成されたグラフェン層を形成する工程と、前記グラフェン層の表面にエピタキシャル成長によって第２炭化ケイ素層を形成する工程とを有し、前記第１炭化ケイ素層は、前記グラフェン層と前記炭化ケイ素単結晶基板との間に位置することを要旨とする。 A feature of the method for manufacturing a semiconductor device according to the invention is a reactor for forming a crystal layer on a silicon carbide single crystal substrate made of silicon carbide single crystal by chemical vapor deposition, chemical vapor deposition, or chemical vapor deposition. A method of manufacturing a semiconductor element using a reaction apparatus comprising: a step of forming a first silicon carbide layer by epitaxial growth on a surface of the silicon carbide single crystal substrate in the same reaction furnace; and A step of forming a graphene layer formed by stacking a plurality of graphenes on the surface of one silicon carbide layer, and a step of forming a second silicon carbide layer by epitaxial growth on the surface of the graphene layer, The gist is that the silicon layer is located between the graphene layer and the silicon carbide single crystal substrate.
　本発明の特徴に係る半導体素子の製造方法によれば、炭化ケイ素単結晶基板には、グラフェン層が形成される。グラフェンの電気伝導度は、従来のチャネル層の電気伝導度に比べて高いため、応答速度を速めることができる。したがって、半導体素子の高速動作を実現でき、半導体素子の性能向上に寄与することができる。 According to the method for manufacturing a semiconductor element according to the feature of the present invention, the graphene layer is formed on the silicon carbide single crystal substrate. Since the electrical conductivity of graphene is higher than that of the conventional channel layer, the response speed can be increased. Therefore, high-speed operation of the semiconductor element can be realized, which can contribute to improvement of the performance of the semiconductor element.
　また、グラフェンは、ケイ素源を昇華させる昇華法によって炭化ケイ素単結晶の上に成膜できるため、上記第１炭化ケイ素層を形成する工程と、グラフェン層を形成する工程と、第２炭化ケイ素層を形成する工程とを、同一の反応炉において実行することができる。従って、製造工程をも効率化できる。 In addition, since graphene can be formed on a silicon carbide single crystal by a sublimation method in which a silicon source is sublimated, a step of forming the first silicon carbide layer, a step of forming a graphene layer, and a second silicon carbide layer Can be carried out in the same reactor. Therefore, the manufacturing process can be made more efficient.
　また、発明の半導体素子の製造方法に係る別の特徴は、化学気相成長法、化学気相蒸着、又は化学蒸着により、半絶縁性を有する炭化ケイ素単結晶からなる炭化ケイ素単結晶基板と、グラフェンが複数積層されて形成されたチャネル層と、前記チャネル層の表面に形成され、エピタキシャル成長よって形成されたドープ層と、を有する半導体素子の製造方法であって、前記炭化ケイ素単結晶基板上に、ケイ素源及び炭素源を含有する反応ガス及び水素キャリアガスを導入する工程と、前記反応ガスが導入された後の反応系を温度：１４００℃～１８００℃、真空度：１×１０－４～１×１０－８ｍｂａｒ以下で２分～１．５時間維持する工程と、前記工程の後に、圧力が１ｍｂａｒ以上～５００ｍｂａｒ以上になるように水素ガスと反応ガスとを再度導入する工程とを有することを要旨とする。 Another feature of the method for manufacturing a semiconductor device of the invention is that a silicon carbide single crystal substrate made of a silicon carbide single crystal having semi-insulating properties by chemical vapor deposition, chemical vapor deposition, or chemical vapor deposition, and A method for manufacturing a semiconductor device, comprising: a channel layer formed by stacking a plurality of graphenes; and a doped layer formed on the surface of the channel layer and formed by epitaxial growth. A step of introducing a reaction gas containing a silicon source and a carbon source and a hydrogen carrier gas, and a reaction system after introduction of the reaction gas at a temperature of 1400 ° C. to 1800 ° C. and a degree of vacuum of 1 × 10 −4 to a step of maintaining 2 minutes to 1.5 hours at 1 × 10 -8 mbar or less, after the step, the reaction gas with hydrogen gas so as to make the pressure to ~ than 500mbar higher 1mbar And summarized in that a step of introducing the bets again.
図１は、本発明の実施形態として示す炭化ケイ素単結晶基板の構造を説明する断面図である。FIG. 1 is a cross-sectional view illustrating the structure of a silicon carbide single crystal substrate shown as an embodiment of the present invention. 図２は、本発明の実施形態として示す半導体素子の製造方法を説明する図である。FIG. 2 is a diagram for explaining a method of manufacturing a semiconductor element shown as an embodiment of the present invention. 図３は、本発明の別の実施形態として示す半導体素子の構造を説明する断面図である。FIG. 3 is a cross-sectional view illustrating the structure of a semiconductor device shown as another embodiment of the present invention. 図４は、本発明の別の実施形態として示す半導体素子の構造を説明する断面図である。FIG. 4 is a cross-sectional view illustrating the structure of a semiconductor device shown as another embodiment of the present invention. 図５は、本発明の別の実施形態として示す半導体素子の構造を説明する断面図である。FIG. 5 is a cross-sectional view illustrating the structure of a semiconductor device shown as another embodiment of the present invention. 図６は、本発明の別の実施形態として示す半導体素子の製造方法を説明する図である。FIG. 6 is a diagram for explaining a method for manufacturing a semiconductor device shown as another embodiment of the present invention.
　本発明に係る炭化ケイ素単結晶基板、半導体素子、及び、半導体素子の製造方法の実施形態について、図面を参照しながら説明する。 Embodiments of a silicon carbide single crystal substrate, a semiconductor element, and a method for manufacturing a semiconductor element according to the present invention will be described with reference to the drawings.
　なお、以下の図面の記載において、同一または類似の部分には、同一または類似の符号を付している。ただし、図面は模式的なものであり、各寸法の比率などは現実のものとは異なることに留意すべきである。したがって、具体的な寸法などは以下の説明を参酌して判断すべきものである。また、図面相互間においても互いの寸法の関係や比率が異なる部分が含まれていることは勿論である。 In the description of the drawings below, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic and ratios of dimensions and the like are different from actual ones. Accordingly, specific dimensions and the like should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.
　［炭化ケイ素単結晶基板］
　本発明に係る炭化ケイ素単結晶基板の実施形態について、図１及び図２を参照しながら説明する。 [Silicon carbide single crystal substrate]
An embodiment of a silicon carbide single crystal substrate according to the present invention will be described with reference to FIGS. 1 and 2.
　図１は、本発明の実施形態に係る炭化ケイ素単結晶基板１を説明する断面図である。炭化ケイ素単結晶基板１は、支持基板１１と、第１炭化ケイ素層１２と、グラフェン層１３と、第２炭化ケイ素層１４とを有する。実施形態では、炭化ケイ素単結晶基板１は、炭化ケイ素単結晶の支持基板１１の表面に、第１炭化ケイ素層１２と、グラフェン層１３と、第２炭化ケイ素層１４とをこの順番に有する。炭化ケイ素単結晶基板１は、エピタキシャル成長によって形成された層を備える。 FIG. 1 is a cross-sectional view illustrating a silicon carbide single crystal substrate 1 according to an embodiment of the present invention. Silicon carbide single crystal substrate 1 has a support substrate 11, a first silicon carbide layer 12, a graphene layer 13, and a second silicon carbide layer 14. In the embodiment, the silicon carbide single crystal substrate 1 has the first silicon carbide layer 12, the graphene layer 13, and the second silicon carbide layer 14 in this order on the surface of the silicon carbide single crystal support substrate 11. Silicon carbide single crystal substrate 1 includes a layer formed by epitaxial growth.
　支持基板１１は、半絶縁性または導電性の炭化ケイ素の単結晶から形成されている。 The support substrate 11 is formed of a single crystal of semi-insulating or conductive silicon carbide.
　第１炭化ケイ素層１２は、支持基板１１の表面に形成される。第１炭化ケイ素層１２は、支持基板１１とグラフェン層１３との間に位置する。第１炭化ケイ素層１２は、支持基板１１とグラフェン層１３とに接する。第１炭化ケイ素層１２は、エピタキシャル成長によって形成される。第１炭化ケイ素層１２は、例えば、ドープ層とすることができる。実施形態では、第１炭化ケイ素層１２の厚みは、０．２μｍ～２０μｍとすることができ、特に、０．５μｍとすることができる。 The first silicon carbide layer 12 is formed on the surface of the support substrate 11. The first silicon carbide layer 12 is located between the support substrate 11 and the graphene layer 13. The first silicon carbide layer 12 is in contact with the support substrate 11 and the graphene layer 13. The first silicon carbide layer 12 is formed by epitaxial growth. The first silicon carbide layer 12 can be, for example, a doped layer. In the embodiment, the thickness of the first silicon carbide layer 12 can be 0.2 μm to 20 μm, and particularly 0.5 μm.
　グラフェン層１３は、第１炭化ケイ素層１２の炭化ケイ素単結晶の支持基板１１が配置された表面とは反対側の表面に形成される。グラフェン層１３は、支持基板１１と第２炭化ケイ素層１４との間に位置する。本実施形態において、グラフェン層１３は、第１炭化ケイ素層１２と第２炭化ケイ素層１４とに接する。グラフェン層１３は、グラフェンが複数積層されて形成されている。グラフェン層１３は、複数のグラファイト単層膜から形成されている。グラフェンは、一層の炭素原子層で構成されている。すなわち、グラフェン層１３は、グラファイトがシート状に広がった２次元グラファイトシートから構成されている。グラフェン層１３の厚みは、量子効果が見られる膜厚である。例えば、グラフェン層の厚みは、１ｎｍ～１０ｎｍとすることができる。グラフェン層１３の厚みは、５ｎｍ以下とすることができる。 The graphene layer 13 is formed on the surface opposite to the surface on which the silicon carbide single crystal support substrate 11 of the first silicon carbide layer 12 is disposed. The graphene layer 13 is located between the support substrate 11 and the second silicon carbide layer 14. In the present embodiment, the graphene layer 13 is in contact with the first silicon carbide layer 12 and the second silicon carbide layer 14. The graphene layer 13 is formed by stacking a plurality of graphenes. The graphene layer 13 is formed of a plurality of graphite single layer films. Graphene is composed of a single layer of carbon atoms. That is, the graphene layer 13 is composed of a two-dimensional graphite sheet in which graphite spreads in a sheet shape. The thickness of the graphene layer 13 is a thickness at which a quantum effect is observed. For example, the thickness of the graphene layer can be 1 nm to 10 nm. The thickness of the graphene layer 13 can be 5 nm or less.
　第２炭化ケイ素層１４は、グラフェン層１３の第１炭化ケイ素層１２が配置された表面とは反対側の表面にエピタキシャル成長によって形成される。第２炭化ケイ素層１４は、炭化ケイ素の単結晶又は多結晶で形成されている。第２炭化ケイ素層１４は、グラフェン層１３の表面にエピタキシャル成長により形成されている。第２炭化ケイ素層１４の厚みは、１０ｎｍ～２０ｎｍとすることができる。 The second silicon carbide layer 14 is formed by epitaxial growth on the surface of the graphene layer 13 opposite to the surface on which the first silicon carbide layer 12 is disposed. The second silicon carbide layer 14 is formed of silicon carbide single crystal or polycrystal. The second silicon carbide layer 14 is formed on the surface of the graphene layer 13 by epitaxial growth. The thickness of the second silicon carbide layer 14 can be 10 nm to 20 nm.
　上述の炭化ケイ素単結晶基板１は、半導体素子の一部に適用できる。例えば、炭化ケイ素単結晶基板１を高電子移動度トランジスタ（ＨＥＭＴ）に適用できる。この場合、支持基板１１は、半絶縁性の炭化ケイ素単結晶基板を構成し、第１炭化ケイ素層１２は、バッファ層を構成することができる。また、グラフェン層１３は、電子走行層であるチャネル層を構成することができる。第２炭化ケイ素層１４は、電子供給層であるドープ層を構成することができる。第２炭化ケイ素層１４の表面にソース電極、ゲート電極、ドレイン電極を形成することによって、炭化ケイ素単結晶基板１は、高電子移動度トランジスタ（ＨＥＭＴ）を構成することができる。 The silicon carbide single crystal substrate 1 described above can be applied to a part of a semiconductor element. For example, the silicon carbide single crystal substrate 1 can be applied to a high electron mobility transistor (HEMT). In this case, the support substrate 11 can constitute a semi-insulating silicon carbide single crystal substrate, and the first silicon carbide layer 12 can constitute a buffer layer. The graphene layer 13 can constitute a channel layer that is an electron transit layer. The second silicon carbide layer 14 can constitute a doped layer that is an electron supply layer. By forming a source electrode, a gate electrode, and a drain electrode on the surface of the second silicon carbide layer 14, the silicon carbide single crystal substrate 1 can constitute a high electron mobility transistor (HEMT).
　実施形態に係る炭化ケイ素単結晶基板１によれば、グラフェン層１３が形成されている。グラフェンの電気伝導度は、従来のイオン注入層の電気伝導度に比べて高いため、電気的な応答速度を速めることができる。従って、半導体素子の性能向上に寄与することができる。 According to the silicon carbide single crystal substrate 1 according to the embodiment, the graphene layer 13 is formed. Since the electrical conductivity of graphene is higher than the electrical conductivity of the conventional ion implantation layer, the electrical response speed can be increased. Therefore, it can contribute to the performance improvement of the semiconductor element.
　［半導体素子］
　本発明に係る半導体素子の実施形態について、図１から図６を参照しながら説明する。 [Semiconductor element]
Embodiments of a semiconductor device according to the present invention will be described with reference to FIGS.
　（１）第１実施形態
　（１．１）半導体素子の概略構成
　本実施形態に係る半導体素子１は、支持基板１１、バッファ層１２、チャネル層１３及びドープ層１４を有する。半導体素子１は、上述した炭化ケイ素単結晶基板１と同様の構成である。すなわち、バッファ層１２は、上述した第１炭化ケイ素層１２である。チャネル層１３は、上述したグラフェン層１３である。ドープ層１４は、第２炭化ケイ素層１４である。 (1) First Embodiment (1.1) Schematic Configuration of Semiconductor Element A semiconductor element 1 according to this embodiment includes a support substrate 11, a buffer layer 12, a channel layer 13, and a doped layer. Semiconductor element 1 has the same configuration as silicon carbide single crystal substrate 1 described above. That is, the buffer layer 12 is the first silicon carbide layer 12 described above. The channel layer 13 is the graphene layer 13 described above. The doped layer 14 is the second silicon carbide layer 14.
　（１．２）半導体素子の製造方法
　図２は、本発明の実施形態に係る半導体素子の製造方法を説明する図である。半導体素子１は、化学気相成長法、化学気相蒸着、又は化学蒸着により、炭化ケイ素の単結晶基板の上に、結晶層を形成する反応炉を備えた反応装置（ＣＶＤ装置）によって製造される。 (1.2) Semiconductor Device Manufacturing Method FIG. 2 is a diagram for explaining a semiconductor device manufacturing method according to an embodiment of the present invention. The semiconductor element 1 is manufactured by a reaction apparatus (CVD apparatus) including a reaction furnace for forming a crystal layer on a silicon carbide single crystal substrate by chemical vapor deposition, chemical vapor deposition, or chemical vapor deposition. The
　本実施形態において、第１炭化ケイ素層１２、グラフェン層１３、第２炭化ケイ素層１４は、同一の反応炉において、支持基板１１の上に形成することができる。すなわち、同一の反応炉において、工程Ｓ１１、工程Ｓ１２、及び、工程Ｓ１３ができる。 In the present embodiment, the first silicon carbide layer 12, the graphene layer 13, and the second silicon carbide layer 14 can be formed on the support substrate 11 in the same reaction furnace. That is, step S11, step S12, and step S13 can be performed in the same reactor.
　工程Ｓ１１において、ＣＶＤ装置にセットされた炭化ケイ素単結晶の支持基板１１上に、反応ガスとキャリアガスとが導入される。本実施形態では、反応ガスは、ケイ素源としてシラン（ＳｉＨ４）を含むとともに炭素源としてメタン（Ｃ３Ｈ８）を含む。また、キャリアガスは、水素を含む。本実施形態において、支持基板１１は、半絶縁性を有する。 In step S11, a reaction gas and a carrier gas are introduced onto a silicon carbide single crystal support substrate 11 set in a CVD apparatus. In this embodiment, the reaction gas contains silane (SiH 4 ) as a silicon source and methane (C 3 H 8 ) as a carbon source. The carrier gas contains hydrogen. In the present embodiment, the support substrate 11 has a semi-insulating property.
　工程Ｓ１１において、炭化ケイ素単結晶の支持基板１１の表面にエピタキシャル成長によって第１炭化ケイ素層１２が形成される。 In step S11, a first silicon carbide layer 12 is formed on the surface of the silicon carbide single crystal support substrate 11 by epitaxial growth.
　続いて、工程Ｓ１２において、反応ガスが導入された後、反応ガス及びキャリアガスの供給を停止し、反応系を温度：１４００℃～１８００℃、真空度：１×１０－４ｍｂａｒ～１×１０－８ｍｂａｒで２分～１．５時間維持する。この工程Ｓ１２において、第１炭化ケイ素層１２のケイ素が昇華することによりｍ第１炭化ケイ素層１２の表面にグラフェン層１３が形成される。工程Ｓ１２において、グラフェン層１３が成長する。 Subsequently, in step S12, after the reaction gas is introduced, the supply of the reaction gas and the carrier gas is stopped, and the temperature of the reaction system is 1400 ° C. to 1800 ° C., and the degree of vacuum is 1 × 10 −4 mbar to 1 × 10. Maintain at -8 mbar for 2 minutes to 1.5 hours. In this step S <b> 12, the graphene layer 13 is formed on the surface of the m first silicon carbide layer 12 by the sublimation of silicon in the first silicon carbide layer 12. In step S12, the graphene layer 13 is grown.
　工程Ｓ１２の後、工程Ｓ１３において、圧力が５ｍｂａｒ以上～５００ｍｂａｒ以内になるように水素ガスと反応ガスとを再度導入し、１～２分維持する。工程Ｓ１３において、グラフェン層１３の表面にエピタキシャル成長によって第２炭化ケイ素層１４が形成される。具体的には、工程Ｓ１３において、炭化ケイ素単結晶の支持基板１１が配置されたグラフェン層１３の表面とは反対側のグラフェン層１３の表面にエピタキシャル成長によって第２炭化ケイ素層１４が形成される。 After step S12, in step S13, the hydrogen gas and the reactive gas are again introduced so that the pressure becomes 5 mbar to 500 mbar and maintained for 1 to 2 minutes. In step S13, the second silicon carbide layer 14 is formed on the surface of the graphene layer 13 by epitaxial growth. Specifically, in step S13, the second silicon carbide layer 14 is formed by epitaxial growth on the surface of the graphene layer 13 opposite to the surface of the graphene layer 13 on which the silicon carbide single crystal support substrate 11 is disposed.
　以上の工程により、本実施形態に係る半導体素子１が製造される。 Through the above steps, the semiconductor element 1 according to this embodiment is manufactured.
　（１．３）作用・効果
　実施形態に係る半導体素子１（炭化ケイ素単結晶基板１）によれば、グラフェン層１３が形成されている。グラフェンの電気伝導度は、従来のイオン注入層の電気伝導度に比べて高いため、電気的な応答速度を速めることができる。従って、半導体素子の性能向上に寄与することができる。 (1.3) Action / Effect According to the semiconductor element 1 (silicon carbide single crystal substrate 1) according to the embodiment, the graphene layer 13 is formed. Since the electrical conductivity of graphene is higher than the electrical conductivity of the conventional ion implantation layer, the electrical response speed can be increased. Therefore, it can contribute to the performance improvement of the semiconductor element.
　また、実施形態の製造方法では、グラフェンは、ケイ素源を昇華させる昇華法によって炭化ケイ素単結晶の上に成膜できるため、第１炭化ケイ素層１２を形成する工程と、グラフェン層１３を形成する工程と、第２炭化ケイ素層１４を形成する工程とを同一の反応炉において実行することができる。従って、半導体素子の性能向上に寄与することができるとともに、製造工程をも効率化できる。さらに、同一の反応炉において製造することができるため、不純物の混入を抑制できる。 In the manufacturing method of the embodiment, graphene can be formed on the silicon carbide single crystal by a sublimation method that sublimates a silicon source, and therefore, the step of forming the first silicon carbide layer 12 and the graphene layer 13 are formed. The step and the step of forming the second silicon carbide layer 14 can be performed in the same reactor. Therefore, it is possible to contribute to the improvement of the performance of the semiconductor element, and the manufacturing process can be made more efficient. Furthermore, since it can manufacture in the same reactor, mixing of an impurity can be suppressed.
　（２）第２から第４実施形態
　従来、半絶縁性の炭化ケイ素単結晶から作製された基板上にドープ層及びチャネル層が形成された半導体素子は、高周波スイッチ、パワーアンプ、ローノイズアンプなどの高周波分野において使用される。この半導体素子は、炭化ケイ素単結晶からなる支持基板の上に窒化ガリウム膜（ＧａＮ膜）や窒化アルミニウムガリウム膜（ＡｌＧａＮ膜）をエピタキシャル成長させることによって形成され、半導体レーザ装置に適用される（例えば、特開平１１－１０３１３４号公報参照）。 (2) Second to Fourth Embodiments Conventionally, a semiconductor device in which a doped layer and a channel layer are formed on a substrate made of a semi-insulating silicon carbide single crystal is a high frequency switch, a power amplifier, a low noise amplifier, or the like. Used in the high frequency field. This semiconductor element is formed by epitaxially growing a gallium nitride film (GaN film) or an aluminum gallium nitride film (AlGaN film) on a support substrate made of a silicon carbide single crystal, and is applied to a semiconductor laser device (for example, (See JP-A-11-103134).
　しかしながら、近年の、通信機器の通信速度向上や、半導体レーザ装置の高性能化などの要求に伴って、スイッチング、整流、発振、増幅などに適用される半導体素子の更なる改良が望まれている。 However, with the recent demands for improving the communication speed of communication equipment and improving the performance of semiconductor laser devices, further improvement of semiconductor elements applied to switching, rectification, oscillation, amplification, etc. is desired. .
　そこで、以下では、スイッチング速度を向上することができる半導体素子、及びこの半導体素子の製造方法を説明する。なお、上述した半導体素子１（炭化ケイ素単結晶基板１）と同様の構成は、適宜省略する。 Therefore, hereinafter, a semiconductor element capable of improving the switching speed and a method for manufacturing the semiconductor element will be described. In addition, the structure similar to the semiconductor element 1 (silicon carbide single crystal substrate 1) mentioned above is abbreviate | omitted suitably.
　（２．１）第２実施形態
　図３は、本発明の第２実施形態に係る半導体素子２を説明する断面図である。本実施形態では、半導体素子２は、半絶縁性の支持基板１１１上に、主電流が流れる電子走行層であるチャネル層１１３と、電子供給層であるｎ型のドープ層１１４とが形成されている。また、ドープ層１１４において支持基板１１１が配置された表面の反対側の表面には、ソース電極１２１、ゲート電極１２２、ドレイン電極１２３が形成されている。半導体素子２は、高電子移動度トランジスタ（ＨＥＭＴ）を構成する。 (2.1) Second Embodiment FIG. 3 is a cross-sectional view illustrating a semiconductor element 2 according to a second embodiment of the present invention. In this embodiment, the semiconductor element 2 includes a channel layer 113 that is an electron transit layer through which a main current flows and an n-type doped layer 114 that is an electron supply layer formed on a semi-insulating support substrate 111. Yes. A source electrode 121, a gate electrode 122, and a drain electrode 123 are formed on the surface of the doped layer 114 opposite to the surface on which the support substrate 111 is disposed. The semiconductor element 2 constitutes a high electron mobility transistor (HEMT).
　支持基板１１１は、半絶縁性の炭化ケイ素の単結晶から形成されている。 The support substrate 111 is made of a semi-insulating silicon carbide single crystal.
　チャネル層１１３は、支持基板１１１とドープ層１１４との間に位置する。本実施形態において、チャネル層１１３は、支持基板１１１とドープ層１１４とに接する。チャネル層１１３は、グラフェンが複数積層されて形成される。チャネル層１１３は、複数のグラファイト単層膜から形成されている。すなわち、チャネル層１１３は、グラファイトがシート状に広がった２次元グラファイトシートから構成されている。チャネル層１１３の厚みは、５ｎｍ以下とすることができる。 The channel layer 113 is located between the support substrate 111 and the doped layer 114. In the present embodiment, the channel layer 113 is in contact with the support substrate 111 and the doped layer 114. The channel layer 113 is formed by stacking a plurality of graphenes. The channel layer 113 is formed of a plurality of graphite single layer films. That is, the channel layer 113 is composed of a two-dimensional graphite sheet in which graphite is spread in a sheet shape. The thickness of the channel layer 113 can be 5 nm or less.
　ドープ層１１４は、炭化ケイ素の単結晶又は多結晶で形成されている。ドープ層１１４は、チャネル層１１３の表面にエピタキシャル成長により形成されている。ドープ層１１４の厚みは、１０ｎｍ～２０ｎｍ程度である。 The doped layer 114 is formed of silicon carbide single crystal or polycrystal. The doped layer 114 is formed on the surface of the channel layer 113 by epitaxial growth. The doped layer 114 has a thickness of about 10 nm to 20 nm.
　ソース電極１２１、ゲート電極１２２、及びドレイン電極１２３は、チャネル層１１３が形成されたドープ層１１４の表面とは反対側に位置するドープ層１１４の表面側に形成される。本実施形態において、ソース電極１２１、ゲート電極１２２、及びドレイン電極１２３は、ドープ層１１４の表面に形成される。 The source electrode 121, the gate electrode 122, and the drain electrode 123 are formed on the surface side of the doped layer 114 located on the opposite side to the surface of the doped layer 114 on which the channel layer 113 is formed. In the present embodiment, the source electrode 121, the gate electrode 122, and the drain electrode 123 are formed on the surface of the doped layer 114.
　ゲート電極１２２は、ドープ層１１４の表面に接触し、ショットキー接合を形成する。このとき、ドープ層１１４には、ショットキー接合の空乏層が形成される。 The gate electrode 122 is in contact with the surface of the doped layer 114 to form a Schottky junction. At this time, a depletion layer having a Schottky junction is formed in the doped layer 114.
　ソース電極１２１，ドレイン電極１２３は、ドープ層との間でオーミック接触を得るように形成される。ソース電極１２１及びドレイン電極１２３は、例えば、ＡｕＧｅ合金から構成される。 The source electrode 121 and the drain electrode 123 are formed so as to obtain ohmic contact with the doped layer. The source electrode 121 and the drain electrode 123 are made of, for example, an AuGe alloy.
　（２．２）第３実施形態
　図４は、第３実施形態として示す半導体素子３の断面図である。半導体素子３は、支持基板１１１とチャネル層１１３（グラフェン層）との間に炭化ケイ素から形成されるバッファ層１１２が配置されている。すなわち、バッファ層１１２は、支持基板１１１とチャネル層１１３との間に位置する。バッファ層１１２は、バッファ層１１２は、支持基板１１１とチャネル層１１３とに接する。バッファ層１１２は、支持基板１１１の表面に炭化ケイ素がエピタキシャル成長することによって形成されている。バッファ層１１２は、アンドープ層である。実施形態では、バッファ層１１２の厚みは、０．１～１．０μｍ程度である。 (2.2) Third Embodiment FIG. 4 is a cross-sectional view of a semiconductor element 3 shown as a third embodiment. In the semiconductor element 3, a buffer layer 112 made of silicon carbide is disposed between the support substrate 111 and the channel layer 113 (graphene layer). That is, the buffer layer 112 is located between the support substrate 111 and the channel layer 113. The buffer layer 112 is in contact with the support substrate 111 and the channel layer 113. The buffer layer 112 is formed by epitaxially growing silicon carbide on the surface of the support substrate 111. The buffer layer 112 is an undoped layer. In the embodiment, the thickness of the buffer layer 112 is about 0.1 to 1.0 μm.
　（２．３）第４実施形態
　図５は、第４実施形態として示す半導体素子４の断面図である。半導体素子４は、ドープ層１１４の表面においてソース電極１２１とドレイン電極１２３の間には、ドープ層１１４の表面を被覆する保護層１１５が形成されている。半導体素子４では、ゲート電極１２２は、保護層１１５の表面に形成される。ソース電極１２１及びドレイン電極１２３は、ドープ層１１４の表面に形成される。半導体素子４では、支持基板１１１とチャネル層１１３（グラフェン層）との間に炭化ケイ素から形成されるバッファ層１１２が配置されているが、バッファ層１１２を備えなくてもよい。 (2.3) Fourth Embodiment FIG. 5 is a cross-sectional view of a semiconductor element 4 shown as a fourth embodiment. In the semiconductor element 4, a protective layer 115 covering the surface of the doped layer 114 is formed between the source electrode 121 and the drain electrode 123 on the surface of the doped layer 114. In the semiconductor element 4, the gate electrode 122 is formed on the surface of the protective layer 115. The source electrode 121 and the drain electrode 123 are formed on the surface of the doped layer 114. In the semiconductor element 4, the buffer layer 112 formed of silicon carbide is disposed between the support substrate 111 and the channel layer 113 (graphene layer), but the buffer layer 112 may not be provided.
　（４）半導体素子の製造方法
　図６は、本発明の実施形態に係る半導体素子の製造方法を説明する図である。以下では、バッファ層１１２を形成する半導体素子３を製造する製造方法について説明する。 (4) Manufacturing Method of Semiconductor Device FIG. 6 is a diagram illustrating a manufacturing method of the semiconductor device according to the embodiment of the present invention. Below, the manufacturing method which manufactures the semiconductor element 3 which forms the buffer layer 112 is demonstrated.
　半導体素子３は、化学気相成長法、化学気相蒸着、又は化学蒸着により、半絶縁性の炭化ケイ素の単結晶基板の上に、チャネル層とドープ層とを形成する反応炉を備えた反応装置（ＣＶＤ装置）によって製造される。 The semiconductor element 3 is a reaction including a reaction furnace for forming a channel layer and a doped layer on a semi-insulating silicon carbide single crystal substrate by chemical vapor deposition, chemical vapor deposition, or chemical vapor deposition. Manufactured by an apparatus (CVD apparatus).
　実施形態では、半導体素子３は、図６に示す一連の工程によって製造される。すなわち、工程Ｓ２１において、ＣＶＤ装置にセットされた炭化ケイ素単結晶の支持基板１１１上に、反応ガスと、キャリアガスとが導入される。実施形態では、反応ガスは、ケイ素源としてシラン（ＳｉＨ４）を含むとともに炭素源としてメタン（Ｃ３Ｈ８）を含む。また、キャリアガスは、水素を含む。 In the embodiment, the semiconductor element 3 is manufactured by a series of steps shown in FIG. That is, in step S21, the reaction gas and the carrier gas are introduced onto the silicon carbide single crystal support substrate 111 set in the CVD apparatus. In an embodiment, the reaction gas includes silane (SiH 4 ) as a silicon source and methane (C 3 H 8 ) as a carbon source. The carrier gas contains hydrogen.
　工程Ｓ２１において、炭化ケイ素単結晶の支持基板１１１の表面にエピタキシャル成長によってバッファ層１１２が形成される。 In step S21, the buffer layer 112 is formed by epitaxial growth on the surface of the silicon carbide single crystal support substrate 111.
　続いて、工程Ｓ２２において、反応ガスが導入された後、反応ガス及びキャリアガスの供給を停止し、反応系を温度：１４００℃～１８００℃、真空度：１×１０－４～１×１０－８ｍｂａｒ以下で、２分～１．５時間維持する。この工程Ｓ２２において、チャネル層１１３（グラフェン層）が成長する。 Subsequently, in step S22, after the reaction gas is introduced, the supply of the reaction gas and the carrier gas is stopped, and the temperature of the reaction system is 1400 ° C. to 1800 ° C., and the degree of vacuum is 1 × 10 −4 to 1 × 10 −. Maintain at less than 8 mbar for 2 minutes to 1.5 hours. In this step S22, the channel layer 113 (graphene layer) is grown.
　工程Ｓ２２の後、工程Ｓ２３において、圧力が１ｍｂａｒ以上～５００ｍｂａｒ以内になるように水素ガスと反応ガスとを再度導入し、１～２分維持する。工程Ｓ２３において、チャネル層１１３（グラフェン層）の炭化ケイ素単結晶の支持基板１１１とは反対側の表面にエピタキシャル成長によって炭化ケイ素層が形成される。炭化ケイ素層は、ドープ層１１４を構成する。 After step S22, in step S23, the hydrogen gas and the reactive gas are again introduced so that the pressure becomes 1 mbar to 500 mbar and maintained for 1 to 2 minutes. In step S23, a silicon carbide layer is formed by epitaxial growth on the surface of the channel layer 113 (graphene layer) opposite to the silicon carbide single crystal support substrate 111. The silicon carbide layer constitutes the doped layer 114.
　工程Ｓ２３においてドープ層１１４が形成された後、工程Ｓ２４において、ソース電極１２１、ゲート電極１２２，ドレイン電極１２３は、スパッタリングによりドープ層１１４の表面に形成される。 After the doped layer 114 is formed in step S23, the source electrode 121, the gate electrode 122, and the drain electrode 123 are formed on the surface of the doped layer 114 by sputtering in step S24.
　（５）作用・効果
　実施形態に係る半導体素子２，３，４によれば、チャネル層１１３がケイ素を含まれないグラフェン層で形成されており、グラフェン層が高電子移動層を形成するため、電子の移動度を高めることができ、半導体素子のスイッチング速度を向上させることができる。 (5) Action / Effect According to the semiconductor elements 2, 3, and 4 according to the embodiment, the channel layer 113 is formed of a graphene layer not containing silicon, and the graphene layer forms a high electron transfer layer. Electron mobility can be increased and the switching speed of the semiconductor element can be improved.
　また、半導体素子３，４では、支持基板１１１とチャネル層１１３（グラフェン層）との間に炭化ケイ素から形成されるバッファ層１１２が配置されている。 In the semiconductor elements 3 and 4, the buffer layer 112 formed of silicon carbide is disposed between the support substrate 111 and the channel layer 113 (graphene layer).
　これにより、炭化ケイ素単結晶の支持基板１１１とチャネル層１１３（グラフェン層）との境界における結晶の品位の低下を防ぐことができる。 Thereby, it is possible to prevent deterioration of the crystal quality at the boundary between the silicon carbide single crystal support substrate 111 and the channel layer 113 (graphene layer).
　ドープ層１１４の表面においてソース電極１２１とドレイン電極１２３の間には、ドープ層１１４の表面を被覆する保護層１１５が形成されており、ゲート電極１２２は、保護層１１５の表面に形成される。保護層１１５が形成されることにより、デバイスの劣化を抑制できる。 A protective layer 115 covering the surface of the doped layer 114 is formed between the source electrode 121 and the drain electrode 123 on the surface of the doped layer 114, and the gate electrode 122 is formed on the surface of the protective layer 115. By forming the protective layer 115, deterioration of the device can be suppressed.
　［その他の実施形態］
　上述したように、本発明の実施形態を通じて本発明の内容を開示したが、この開示の一部をなす論述及び図面は、本発明を限定するものであると理解すべきではない。この開示から当業者には様々な代替実施の形態、実施例及び運用技術が明らかとなろう。 [Other Embodiments]
Although the contents of the present invention have been disclosed through the embodiments of the present invention as described above, it should not be understood that the descriptions and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.
　例えば、上述した炭化ケイ素単結晶基板１は、第１炭化ケイ素層１２を有していたが、これに限られない。例えば、支持基板１１とグラフェン層１３とが直接接してもよい。 For example, the silicon carbide single crystal substrate 1 described above has the first silicon carbide layer 12, but is not limited thereto. For example, the support substrate 11 and the graphene layer 13 may be in direct contact.
　本発明は、ここでは記載していない様々な実施の形態などを含むことは勿論である。したがって、本発明の技術的範囲は、上述の説明から妥当な請求の範囲に係る発明特定事項によってのみ定められるものである。 Of course, the present invention includes various embodiments not described herein. Therefore, the technical scope of the present invention is determined only by the invention specifying matters according to the scope of claims reasonable from the above description.
　［実施例］
　（１）炭化ケイ素単結晶基板
　本発明に係る炭化ケイ素単結晶基板を作製し、性能を評価した。 [Example]
(1) Silicon Carbide Single Crystal Substrate A silicon carbide single crystal substrate according to the present invention was produced and performance was evaluated.
　（１－１）炭化ケイ素単結晶基板の作製
　本発明に係る炭化ケイ素単結晶基板を、図２に示す一連の工程によって作製した。工程Ｓ１１において、炭化ケイ素単結晶の支持基板上に、反応ガスとしてシラン（ＳｉＨ４）ガスとメタン（Ｃ３Ｈ８）ガスと含む混合ガスを用いた。また、キャリアガスとしては、水素ガスを用いた。工程Ｓ１１により、第１炭化ケイ素層を作成した。第１炭化ケイ素層の層厚が６μｍまで成長したとき、反応ガスの供給を停止した。 (1-1) Production of Silicon Carbide Single Crystal Substrate A silicon carbide single crystal substrate according to the present invention was produced by a series of steps shown in FIG. In step S11, a mixed gas containing silane (SiH 4 ) gas and methane (C 3 H 8 ) gas as a reaction gas was used on a silicon carbide single crystal support substrate. Moreover, hydrogen gas was used as carrier gas. The 1st silicon carbide layer was created by process S11. When the thickness of the first silicon carbide layer was grown to 6 μm, the supply of the reaction gas was stopped.
　工程Ｓ１２における反応系の条件は、下記の通りに設定した。
　　温度：１６５０℃
　　真空度：１×１０－５ｍｂａｒ
　　反応時間：１．０時間 The reaction system conditions in step S12 were set as follows.
Temperature: 1650 ° C
Degree of vacuum: 1 × 10 −5 mbar
Reaction time: 1.0 hour
　また、工程Ｓ１３では、反応系の圧力が１００ｍｂａｒになるように水素ガスと反応ガスとを再度導入した。 In step S13, hydrogen gas and reaction gas were again introduced so that the pressure of the reaction system was 100 mbar.
　（１－２）炭化ケイ素単結晶基板の評価
　作製された実施例に係る炭化ケイ素単結晶基板の電気移動度をホール測定装置（ｖａｎ　ｄｅｒ　ｐａｕｗ測定法）によって測定した。その結果、実施例の電気移動度は、５００ｃｍ２／Ｖ・ｓであった。また、ＭＯＳＦＥＴなどの従来の方法で炭化ケイ素中に形成されるチャネル層の電気移動度は、１５ｃｍ２／Ｖ・ｓであった。従って、実施例の電気移動度は、従来のチャネル層の電気移動度に比べて優れていることが分かった。 (1-2) Evaluation of Silicon Carbide Single Crystal Substrate The electric mobility of the silicon carbide single crystal substrate according to the manufactured example was measured by a Hall measuring device (van der pauw measurement method). As a result, the electric mobility of the example was 500 cm 2 / V · s. Moreover, the electric mobility of the channel layer formed in silicon carbide by a conventional method such as MOSFET was 15 cm 2 / V · s. Therefore, it was found that the electric mobility of the example is superior to the electric mobility of the conventional channel layer.
　（２）半導体素子
　本発明に係る半導体素子を作製し、性能を評価した。 (2) Semiconductor element The semiconductor element which concerns on this invention was produced, and performance was evaluated.
　（２－１）半導体素子の製造
　図６に示す一連の工程によって半導体素子を製造した。工程Ｓ２１に用いる反応ガスとして、シラン（ＳｉＨ４）ガスとメタン（Ｃ３Ｈ８）ガスと含む混合ガスを用いた。また、キャリアガスとしては、水素ガスを用いた。 (2-1) Manufacturing of Semiconductor Device A semiconductor device was manufactured through a series of steps shown in FIG. As the reaction gas used in step S21, a mixed gas containing silane (SiH 4 ) gas and methane (C 3 H 8 ) gas was used. Moreover, hydrogen gas was used as carrier gas.
　工程Ｓ２２における反応系の条件は、下記の通りに設定した。　
　　温度：１６５０℃
　　真空度：１×１０－５ｍｂａｒ
　　反応時間：１．０時間 The reaction system conditions in step S22 were set as follows.
Temperature: 1650 ° C
Degree of vacuum: 1 × 10 −5 mbar
Reaction time: 1.0 hour
　また、工程Ｓ２３では、反応系の圧力が１００ｍｂａｒになるように水素ガスと反応ガスとを再度導入した。 In step S23, hydrogen gas and reaction gas were again introduced so that the pressure of the reaction system was 100 mbar.
　（２－２）移動度の測定
　作製された半導体素子の移動度をホール測定装置（またはＶａｎ　Ｄｅｒ　Ｐａｕｗ測定法）によって測定した。その結果、図６に示す一連の工程によって製造された半導体素子の移動度は、５００ｃｍ２／Ｖ・ｓであった。一方、比較例として作製した半導体素子の移動度は、２０ｃｍ２／Ｖ・ｓであった。 (2-2) Measurement of mobility The mobility of the manufactured semiconductor element was measured by a Hall measuring device (or Van Der Pauw measurement method). As a result, the mobility of the semiconductor element manufactured by the series of steps shown in FIG. 6 was 500 cm 2 / V · s. On the other hand, the mobility of the semiconductor element manufactured as a comparative example was 20 cm 2 / V · s.
　したがって、本発明に係る半導体素子は、移動度が優れていることが判った。従って、本発明に係る半導体素子によれば、スイッチング速度を向上させることができる。 Therefore, it was found that the semiconductor element according to the present invention has excellent mobility. Therefore, according to the semiconductor element of the present invention, the switching speed can be improved.
　なお、日本国特許出願第２０１１－０１０９７１号（２０１１年１月２１日出願）及び日本国特許出願第２０１１－０２３０７６号（２０１１年２月４日出願）の全内容が、参照により、本願明細書に組み込まれている。 The entire contents of Japanese Patent Application No. 2011-010971 (filed on January 21, 2011) and Japanese Patent Application No. 2011-023076 (filed on February 4, 2011) are incorporated herein by reference. Built in.
　本発明によれば、高速動作を実現する半導体素子として用いることが可能な炭化ケイ素単結晶基板、及び半導体素子の製造方法を提供できる。また、本発明によれば、スイッチング速度を向上することができる半導体素子、及びこの半導体素子の製造方法の提供できる。 According to the present invention, it is possible to provide a silicon carbide single crystal substrate that can be used as a semiconductor element that realizes high-speed operation, and a method for manufacturing a semiconductor element. Further, according to the present invention, it is possible to provide a semiconductor element capable of improving the switching speed and a method for manufacturing the semiconductor element.

Claims (8)

  1. 　エピタキシャル成長によって形成された層を備える炭化ケイ素単結晶基板であって、
    　グラフェンが複数積層されて形成されたグラフェン層と、
    　前記グラフェン層の表面に形成され、エピタキシャル成長によって形成された炭化ケイ素層と、を有し、
    　前記炭化ケイ素層と前記炭化ケイ素単結晶基板との間にグラフェン層が位置する炭化ケイ素単結晶基板。     A silicon carbide single crystal substrate comprising a layer formed by epitaxial growth,
    A graphene layer formed by stacking a plurality of graphenes;
    A silicon carbide layer formed on the surface of the graphene layer and formed by epitaxial growth,
    A silicon carbide single crystal substrate in which a graphene layer is located between the silicon carbide layer and the silicon carbide single crystal substrate.
  2. 　前記炭化ケイ素単結晶基板の表面に形成され、エピタキシャル成長によって形成された基板側炭化ケイ素層を有し、
    　前記基板側炭化ケイ素層は、前記グラフェン層と前記炭化ケイ素単結晶基板との間に位置する請求項１に記載の炭化ケイ素単結晶基板。     A substrate-side silicon carbide layer formed on the surface of the silicon carbide single crystal substrate and formed by epitaxial growth;
    The silicon carbide single crystal substrate according to claim 1, wherein the substrate-side silicon carbide layer is located between the graphene layer and the silicon carbide single crystal substrate.
  3. 　半絶縁性を有する炭化ケイ素単結晶からなる炭化ケイ素単結晶基板と、
    　グラフェンが複数積層されて形成されたチャネル層と、
    　前記チャネル層の表面に形成され、エピタキシャル成長よって形成されたドープ層と、
    　前記チャネル層が形成された前記ドープ層の表面とは反対側に位置する前記ドープ層の表面側に形成されたソース電極、ゲート電極及びドレイン電極と、を有し、
    　前記ドープ層と前記炭化ケイ素単結晶基板との間に前記チャネル層が位置する半導体素子。     A silicon carbide single crystal substrate made of a silicon carbide single crystal having semi-insulating properties, and
    A channel layer formed by stacking a plurality of graphenes;
    A doped layer formed on the surface of the channel layer and formed by epitaxial growth;
    A source electrode, a gate electrode and a drain electrode formed on the surface side of the doped layer located on the opposite side of the surface of the doped layer on which the channel layer is formed,
    A semiconductor device in which the channel layer is located between the doped layer and the silicon carbide single crystal substrate.
  4. 　前記ドープ層は、炭化ケイ素単結晶又は炭化ケイ素多結晶からなる請求項３に記載の半導体素子。 4. The semiconductor element according to claim 3, wherein the doped layer is made of silicon carbide single crystal or silicon carbide polycrystal.
  5. 　前記炭化ケイ素単結晶基板の表面に形成され、エピタキシャル成長によって形成されたバッファ層を有し、
    　前記バッファ層は、前記チャネル層と前記炭化ケイ素単結晶基板との間に位置する請求項３に記載の半導体素子。     A buffer layer formed on the surface of the silicon carbide single crystal substrate and formed by epitaxial growth;
    The semiconductor element according to claim 3, wherein the buffer layer is located between the channel layer and the silicon carbide single crystal substrate.
  6. 　前記ソース電極及び前記ドレイン電極は、前記ドープ層の表面に形成され、
    　前記ソース電極と前記ドレイン電極と間には、前記ドープ層の表面を被覆する保護層が形成され、
    　前記ゲート電極は、前記保護層の表面に形成される請求項３に記載の半導体素子。     The source electrode and the drain electrode are formed on a surface of the doped layer,
    Between the source electrode and the drain electrode, a protective layer covering the surface of the doped layer is formed,
    The semiconductor device according to claim 3, wherein the gate electrode is formed on a surface of the protective layer.
  7. 　化学気相成長法、化学気相蒸着、又は化学蒸着によって炭化ケイ素単結晶からなる炭化ケイ素単結晶基板の上に結晶層を形成する反応炉を備えた反応装置によって半導体素子を製造する半導体素子の製造方法であって、
    　同一の反応炉において、
    　前記炭化ケイ素単結晶基板の表面にエピタキシャル成長によって第１炭化ケイ素層を形成する工程と、
    　前記第１炭化ケイ素層の表面にグラフェンが複数積層されて形成されたグラフェン層を形成する工程と、
    　前記グラフェン層の表面にエピタキシャル成長によって第２炭化ケイ素層を形成する工程と
    　を有し、
    　前記第１炭化ケイ素層は、前記グラフェン層と前記炭化ケイ素単結晶基板との間に位置することを特徴とする半導体素子の製造方法。     A semiconductor device for manufacturing a semiconductor device by a reaction apparatus having a reaction furnace for forming a crystal layer on a silicon carbide single crystal substrate made of silicon carbide single crystal by chemical vapor deposition, chemical vapor deposition, or chemical vapor deposition. A manufacturing method comprising:
    In the same reactor
    Forming a first silicon carbide layer by epitaxial growth on the surface of the silicon carbide single crystal substrate;
    Forming a graphene layer formed by laminating a plurality of graphenes on the surface of the first silicon carbide layer;
    Forming a second silicon carbide layer by epitaxial growth on the surface of the graphene layer,
    The first silicon carbide layer is located between the graphene layer and the silicon carbide single crystal substrate.
  8. 　化学気相成長法、化学気相蒸着、又は化学蒸着により、半絶縁性を有する炭化ケイ素単結晶からなる炭化ケイ素単結晶基板と、グラフェンが複数積層されて形成されたチャネル層と、前記チャネル層の表面に形成され、エピタキシャル成長よって形成されたドープ層と、を有する半導体素子の製造方法であって、
    　前記炭化ケイ素単結晶基板上に、ケイ素源及び炭素源を含有する反応ガス及び水素キャリアガスを導入する工程と、
    　前記反応ガスが導入された後の反応系を温度：１４００℃～１８００℃、真空度：１×１０－４～１×１０－８ｍｂａｒ以下で２分～１．５時間維持する工程と、
    　前記工程の後に、圧力が１ｍｂａｒ以上～５００ｍｂａｒ以上になるように水素ガスと反応ガスとを再度導入する工程と
    　を有する半導体素子の製造方法。     A silicon carbide single crystal substrate made of a silicon carbide single crystal having semi-insulating properties by chemical vapor deposition, chemical vapor deposition, or chemical vapor deposition, a channel layer formed by laminating a plurality of graphenes, and the channel layer And a doped layer formed by epitaxial growth on the surface of the semiconductor device,
    Introducing a reaction gas containing a silicon source and a carbon source and a hydrogen carrier gas onto the silicon carbide single crystal substrate;
    Maintaining the reaction system after introduction of the reaction gas at a temperature of 1400 ° C. to 1800 ° C. and a vacuum of 1 × 10 −4 to 1 × 10 −8 mbar for 2 minutes to 1.5 hours;
    And a step of reintroducing the hydrogen gas and the reactive gas so that the pressure becomes 1 mbar or more to 500 mbar or more after the step.
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