JPWO2016092887A1 - Silicon carbide semiconductor device - Google Patents

Abstract

The silicon carbide epitaxial substrate (3) constituting the silicon carbide semiconductor device (100) has an impurity concentration of 3 × 10 18 cm −3 or more, an silicon carbide substrate (10) having an off angle exceeding 0 °, and an active layer ( 11). The first epitaxial layer (20), the second epitaxial layer (21), and the third epitaxial layer (22) of the active layer (11) have layer thicknesses T1 [μm], T2 [μm], and T3 [μm], respectively. When the impurity concentrations are N1 [cm−3], N2 [cm−3], and N3 [cm−3], N1 ≦ 1 × 1016 cm−3, N2 ≧ 1 × 1017 cm−3, and N3 ≦ 1 × 1016 cm, respectively. −3, T2 ≧ 0.01 μm, and T1 × T2 × N2 ≦ 2.684 × 1017.

Description

  The present invention relates to a silicon carbide epitaxial substrate and a silicon carbide semiconductor device.

  A wide gap semiconductor material such as silicon carbide (SiC) has a higher dielectric breakdown resistance than a silicon (Si) material. Therefore, by using a wide gap semiconductor material as a substrate material, a substrate can be used rather than a silicon material. It is possible to increase the impurity concentration of the substrate and reduce the resistance of the substrate. By reducing the resistance of the substrate, loss in the switching operation of the power element can be reduced. In addition, wide-gap semiconductor materials have higher thermal conductivity and mechanical strength than silicon materials, so they are expected as materials that can realize small, low-loss, and high-efficiency power devices. ing.

  However, in a silicon carbide semiconductor device using silicon carbide as a semiconductor material, there is a well-known reliability problem that the forward voltage (Vf) shifts when a forward current continues to flow through the PIN diode structure. The forward voltage shift occurs as follows.

  When minority carriers are injected into the PIN diode structure, the injected minority carriers recombine with the majority carriers. Due to the recombination energy generated at the time of recombination, defects existing in the silicon carbide crystal are expanded to stacking faults, which are surface defects, starting from line defects such as basal plane dislocations and misfit dislocations. The stacking fault acts as a resistance and hinders the flow of current. Therefore, the flowing current decreases according to the ratio of the stacking fault, the forward voltage shifts, and the device characteristics are deteriorated.

  The stacking fault expands into a triangular shape or a belt shape starting from a line defect such as a basal plane dislocation and a misfit dislocation generated at the interface between the epitaxial layer and the substrate (see, for example, Non-Patent Document 1). Such extension of stacking faults occurs from the interface between the epitaxial layer and the substrate to the surface of the epitaxial layer, along the basal plane, that is, in a direction perpendicular to the step flow direction that is the epitaxial growth direction.

  It has been reported that the forward voltage shift due to stacking faults occurs in the same way even in MOSFETs using silicon carbide (hereinafter sometimes referred to as “SiC-MOSFETs”) (see, for example, Non-Patent Document 2). Since the MOSFET structure has a parasitic diode called a body diode between the source and the drain, if a forward current flows through the body diode, the same degradation as that of the PIN diode is caused.

  As the freewheeling diode in the switching circuit, for example, a Schottky barrier diode having a relatively low forward voltage is used. When a SiC-MOSFET body diode is used as a free-wheeling diode, fluctuations in MOSFET characteristics, for example, a forward voltage shift, are caused, which is a serious problem in reliability.

  Further, the forward voltage shift is proportional to the sum of the areas of expanded stacking faults (hereinafter sometimes referred to as “extended stacking faults”) included in the chip in which the MOSFET is formed. Accordingly, in order to suppress the forward voltage shift, it is very important to reduce the area of the extended stacking fault.

Techniques for suppressing the deterioration of the SiC power device as described above are disclosed in Patent Documents 1 and 2, for example. In the technique disclosed in Patent Document 1, in the epitaxial growth, in order to bend the traveling direction of dislocations inherited from the substrate, at a doping concentration of 1 × 10 ¹⁷ cm ⁻³ or more, the impurity concentration is set at least by changing the growth conditions. An active layer is epitaxially grown on a laminated structure having a thickness of 0.1 μm or more that is changed four times.

  In the technique disclosed in Patent Document 2, an undoped layer that does not include a process of introducing nitrogen, which is an impurity, and a high impurity concentration layer that includes a process of introducing nitrogen are stacked five or more times, and a dislocation caused by a sharp concentration change is performed. After the growth of the layer having the effect of suppressing the propagation of the active layer, the active layer is epitaxially grown.

JP 2007-13154 A JP 2002-329670 A

Journal of ELECTRONIC MATERIALS, Vol. 39, no. 6, “Electrical and Optical Properties of Stacking Faults in 4H-SiC Devices”, 2010 IEEE ELECTRON DEVICE LETTERS, VOL. 28, NO. 7, “A New Degradation Mechanism in High-Voltage SiC Power MOSFETs”, JULY 2007

  In the technique disclosed in Patent Document 1, it is necessary to grow an epitaxial layer that does not originally contribute to device operation as a buffer layer by 0.1 μm or more, and further, it is necessary to change the growth conditions four times or more. It is disadvantageous from the point of view.

  In the technique disclosed in Patent Document 2, it is necessary to provide a layer including an undoped layer in addition to the device active layer region. If epitaxial growth is performed without introducing nitrogen as an impurity, there is a problem that the impurity concentration becomes very low and the on-resistance of the device increases. Further, since the impurity concentration cannot be controlled by controlling the amount of nitrogen introduced, the variation in the impurity concentration between the processing batches becomes large, and the variation as a product becomes large.

  In addition, in the techniques disclosed in Patent Documents 1 and 2, line defects such as misfit dislocations generated at the interface between the active layer and the buffer layer cannot be suppressed. It expands into a stacking fault. The stacking fault easily extends to the surface of the epitaxial layer, resulting in deterioration of device characteristics.

  Further, as disclosed in Patent Documents 1 and 2, in the prior art, before the active layer is epitaxially grown, a layer having an effect of converting dislocations is grown as a buffer layer separately from the active layer, and the active layer is formed. Many methods are used to suppress the progression of dislocations.

  However, in these methods, only dislocations that can be reduced by the buffer layer among the dislocations that are the starting point of the extended stacking fault can be converted, so that there is a problem that deterioration of device characteristics cannot be sufficiently suppressed. . In addition, dislocations that are the starting points of stacking faults also occur in the active layer, but the conventional techniques such as Patent Documents 1 and 2 have a problem that the occurrence of dislocations in the active layer cannot be suppressed.

  An object of the present invention is to suppress the expansion of stacking faults that occur in an epitaxial layer, and to maintain a device breakdown voltage and on-resistance, while suppressing deterioration of device characteristics to such an extent that it does not become a practical problem, and A silicon carbide semiconductor device is provided.

A silicon carbide epitaxial substrate of the present invention includes a silicon carbide substrate, a first epitaxial layer formed by epitaxial growth on a surface on one side in the thickness direction of the silicon carbide substrate, and a surface on one side in the thickness direction of the first epitaxial layer. A second epitaxial layer formed by epitaxial growth; and a third epitaxial layer formed by epitaxial growth on one surface in the thickness direction of the second epitaxial layer. The silicon carbide substrate has an impurity concentration of 3 × 10 ^18. cm ⁻³ or more, an off-angle exceeding 0 °, the layer thickness of the first epitaxial layer is T1 [μm], the layer thickness of the second epitaxial layer is T2 [μm], and the third the thickness of the epitaxial layer and T3 [μm], the impurity concentration of the first epitaxial layer N1 [cm ^- And, when the impurity concentration of the second epitaxial layer and N2 ^{[cm -3],} and the impurity concentration of the third epitaxial layer and ^{N3 [cm -3], N1 ≦} 1 × 10 16 cm -3, N2 ≧ 1 × 10 ¹⁷ cm ⁻³ , N3 ≦ 1 × 10 ¹⁶ cm ⁻³ , T2 ≧ 0.01 μm, T1 × T2 × N2 ≦ 2.684 × 10 ¹⁷ are satisfied.

  The silicon carbide semiconductor device of the present invention includes a semiconductor element including the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer of the silicon carbide epitaxial substrate of the present invention as at least part of an active layer. It is characterized by.

  According to the silicon carbide epitaxial substrate of the present invention, expansion of stacking faults that are generated starting from dislocations and misfit dislocations contained in the first epitaxial layer can be suppressed by the second epitaxial layer. As a result, the deterioration of the device characteristics due to the expansion of the stacking fault can be suppressed to a level that does not cause a practical problem, so that the reliability of the device can be greatly improved.

  In addition, since the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer can all be used as active layers, an active layer including the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer is provided. By using it, it is not necessary to provide a layer other than the active layer. Moreover, the layer thickness of the active layer can be substantially maintained. Therefore, an increase in on-resistance in the silicon carbide semiconductor device is suppressed by configuring the silicon carbide semiconductor device with a semiconductor element including the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer as at least part of the active layer. Can do.

Further, since the first epitaxial layer and the second epitaxial layer satisfy the relationship of T1 × T2 × N2 ≦ 2.684 × 10 ¹⁷ , it is possible to suppress device degradation without greatly reducing the device breakdown voltage.

  From the above, according to the silicon carbide epitaxial substrate of the present invention, the expansion of stacking faults occurring in the epitaxial layer is suppressed, and the deterioration of device characteristics is not a practical problem while maintaining the device breakdown voltage and on-resistance. It is possible to provide a silicon carbide epitaxial substrate that can be suppressed to a low level.

  According to the silicon carbide semiconductor device of the present invention, the semiconductor including the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer of the silicon carbide epitaxial substrate having the excellent effects as described above as at least a part of the active layer. A silicon carbide semiconductor device is configured including the element. Thus, it is possible to obtain a silicon carbide semiconductor device capable of suppressing the expansion of stacking faults generated in the epitaxial layer and suppressing the deterioration of the device characteristics to a level that does not cause a practical problem while maintaining the device breakdown voltage and the on-resistance. it can.

  The objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description and the accompanying drawings.

It is a top view which shows the structure of SiC-MOSFET100 which is an example of the silicon carbide semiconductor device in the 1st Embodiment of this invention. It is sectional drawing which shows the structure of the source pad 2 of the SiC-MOSFET 100 shown in FIG. It is sectional drawing which shows the structure of the SiC epitaxial substrate 3 of the SiC-MOSFET100 shown in FIG. It is sectional drawing which shows the structure of the SiC epitaxial substrate 300 of SiC-MOSFET200 which is an example of the silicon carbide semiconductor device in the 2nd Embodiment of this invention. It is sectional drawing which shows the structure of the SiC epitaxial substrate 310 of SiC-MOSFET210 which is another example of SiC-MOSFET of this invention. It is sectional drawing which shows the structure of SiC epitaxial substrate 300A of SiC-MOSFET200A which is another example of SiC-MOSFET of a premise technique. It is a figure which shows the PL-TOPO image of the sample corresponding to the epitaxial structure of FIGS. It is a figure which shows the PL-TOPO image of the sample corresponding to the epitaxial structure of FIGS. It is a figure which shows the PL-TOPO image of the sample corresponding to the epitaxial structure of FIGS. It is sectional drawing which shows the structure of 100 A of field effect transistors using the silicon carbide of a premise technique. It is a figure for demonstrating the generation | occurrence | production mechanism of the forward voltage shift. It is sectional drawing which shows the structure of SiC-MOSFET101 which is an example of the silicon carbide semiconductor device in the 3rd Embodiment of this invention.

<Prerequisite technology>
FIG. 10 is a cross-sectional view showing a configuration of a field effect transistor 100A using silicon carbide of the base technology. FIG. 10 shows a cross-sectional configuration of a source pad 2A portion of a field effect transistor (hereinafter sometimes referred to as “SiC-MOSFET”) 100A using silicon carbide (SiC).

  SiC-MOSFET 100A is formed on SiC epitaxial substrate 3A in the same manner as SiC-MOSFET 100 according to the first embodiment of the present invention shown in FIG. Gate pad 1 and source pad 2A are arranged on the surface of one side in the thickness direction of SiC epitaxial substrate 3A.

  The SiC epitaxial substrate 3A of the SiC-MOSFET 100A corresponds to the SiC epitaxial substrate 3 in FIG. 1, and the source pad 2A corresponds to the source pad 2 in FIG. The surface on the other side in the thickness direction of SiC epitaxial substrate 3 (hereinafter sometimes referred to as “rear surface”) is used as a drain terminal.

  The SiC-MOSFET 100A has a transistor array structure in which a plurality of cells are connected in parallel and spread uniformly in the source pad 2A portion as shown in FIG. An epitaxially grown first conductivity type active layer 11A is formed on the surface of the first conductivity type SiC substrate 10 on one side in the thickness direction, thereby forming a SiC epitaxial substrate 3A.

  A second conductivity type well region 14 is formed in the active layer 11A. In the center of the well region 14, a second conductivity type well contact region 16 having a relatively high impurity concentration for reducing the contact resistance with the metal electrode is disposed. A source region 15 of the first conductivity type is formed so as to surround the well contact region 16.

  The gate insulating film 12 is formed on the surface of one side in the thickness direction of the active layer 11A so as to overlap the source region 15 of the adjacent cell. That is, the gate insulating film 12 is formed from one source region 15 to the other source region 15 of the source regions 15 of two adjacent cells.

  A gate electrode 13 and an interlayer insulating film 17 are formed on the surface of one side in the thickness direction of the gate insulating film 12. The well contact region 16 and the source region 15 are connected by a source electrode 18 formed of a metal wiring such as an aluminum electrode, and a source pad 2A is formed.

  However, in a silicon carbide semiconductor device using silicon carbide as a semiconductor material, such as the SiC-MOSFET 100A of the base technology, the reliability that the forward voltage (Vf) shifts when a forward current continues to flow through the PIN diode structure. The above problem is well known.

  FIG. 11 is a diagram for explaining a forward voltage shift generation mechanism. FIG. 11 shows a simplified configuration of the SiC-MOSFET 100A of the base technology shown in FIG. The forward voltage shift in the base technology SiC-MOSFET 100A occurs as follows.

  When minority carriers are injected into SiC-MOSFET 100A, the injected minority carriers recombine with the majority carriers. Due to the recombination energy generated at the time of recombination, the defects existing in the silicon carbide crystal are expanded to the stacking fault 30 which is a plane defect starting from a line defect such as a basal plane dislocation or a misfit dislocation. Since the stacking fault 30 acts as a resistance and inhibits the flow of current, the flowing current is reduced according to the ratio of stacking faults, a forward voltage shift occurs, and device characteristics are deteriorated.

  The stacking fault 30 expands into a triangular shape or a belt shape starting from a line defect such as a basal plane dislocation and a misfit dislocation generated at the interface between the epitaxial layer and the substrate. Such an extension of the stacking fault 30 extends from the interface between the active layer 11A as an epitaxial layer and the SiC substrate 10 to the surface of the active layer 11A along the basal plane, that is, in the step flow direction SF that is the epitaxial growth direction. It occurs in a direction perpendicular to the direction.

  As the freewheeling diode in the switching circuit, for example, a Schottky barrier diode having a relatively low forward voltage is used. When a SiC-MOSFET body diode is used as a free-wheeling diode, fluctuations in MOSFET characteristics, for example, a forward voltage shift, are caused, which is a serious problem in reliability.

  The forward voltage shift is proportional to the sum of the areas of expanded stacking faults 30 (hereinafter also referred to as “extended stacking faults”) included in the chip in which the MOSFET is formed. Accordingly, in order to suppress the forward voltage shift, it is very important to reduce the area of the extended stacking fault.

Techniques for suppressing the deterioration of the SiC power device as described above are disclosed in, for example, the aforementioned Patent Documents 1 and 2. In the technique disclosed in Patent Document 1, in the epitaxial growth, in order to bend the traveling direction of dislocations inherited from the substrate, at a doping concentration of 1 × 10 ¹⁷ cm ⁻³ or more, the impurity concentration is set at least by changing the growth conditions. An active layer is epitaxially grown on a laminated structure having a thickness of 0.1 μm or more that is changed four times.

  In the technique disclosed in Patent Document 2, an undoped layer that does not include a process of introducing nitrogen, which is an impurity, and a high impurity concentration layer that includes a process of introducing nitrogen are stacked five or more times, and a dislocation caused by a sharp concentration change is performed. After the growth of the layer having the effect of suppressing the propagation of the active layer, the active layer is epitaxially grown.

  In the technique disclosed in Patent Document 1, it is necessary to grow an epitaxial layer that does not originally contribute to device operation as a buffer layer by 0.1 μm or more, and further, it is necessary to change the growth conditions four times or more. It is disadvantageous from the point of view.

  In the technique disclosed in Patent Document 2, it is necessary to provide a layer including an undoped layer in addition to the device active layer region. If epitaxial growth is performed without introducing nitrogen as an impurity, there is a problem that the impurity concentration becomes very low and the on-resistance of the device increases. Further, since the impurity concentration cannot be controlled by controlling the amount of nitrogen introduced, the variation in the impurity concentration between the processing batches becomes large, and the variation as a product becomes large.

  In addition, in the techniques disclosed in Patent Documents 1 and 2, line defects such as misfit dislocations generated at the interface between the active layer and the buffer layer cannot be suppressed. It expands into a stacking fault. The stacking fault easily extends to the surface of the epitaxial layer, resulting in deterioration of device characteristics.

  Further, as disclosed in Patent Documents 1 and 2, in the prior art, before the active layer is epitaxially grown, a layer having an effect of converting dislocations is grown as a buffer layer separately from the active layer, and the active layer is formed. Many methods are used to suppress the progression of dislocations.

  However, in these methods, only dislocations that can be reduced by the buffer layer among the dislocations that are the origin of the extended stacking fault can be converted, and there is a problem that deterioration of device characteristics cannot be sufficiently suppressed. In addition, dislocations that are the starting points of stacking faults also occur in the active layer, but the conventional techniques such as Patent Documents 1 and 2 have a problem that the occurrence of dislocations in the active layer cannot be suppressed.

  From the above, in the SiC epitaxial substrate such as the SiC epitaxial substrate 3A shown in FIG. 10, the expansion of the stacking fault 30 occurring in the active layer 11A is suppressed, and the device characteristics are deteriorated while maintaining the device withstand voltage and on-resistance. It is required to suppress to a level that does not cause a problem in practice. Therefore, in the present invention, the configurations of the following embodiments are employed.

<First Embodiment>
FIG. 1 is a plan view showing a configuration of SiC-MOSFET 100 which is an example of a silicon carbide semiconductor device according to the first embodiment of the present invention. FIG. 2 is a cross-sectional view showing a configuration of source pad 2 of SiC-MOSFET 100 shown in FIG. FIG. 3 is a cross-sectional view showing a configuration of SiC epitaxial substrate 3 of SiC-MOSFET 100 shown in FIG. In FIG. 1, the step flow direction is represented by a reference sign “SF”.

  As shown in FIG. 1, SiC-MOSFET 100 includes SiC epitaxial substrate 3 and gate pad 1 and source pad 2 formed on the surface of one side in the thickness direction of SiC epitaxial substrate 3.

  The SiC epitaxial substrate 3 includes a first conductivity type SiC substrate 10 and a first conductivity type active layer 11. An epitaxially grown active layer 11 is formed on the surface of one side in the thickness direction of SiC substrate 10.

  The active layer 11 includes three epitaxial layers 20, 21, and 22 that are parallel to the surface on one side in the thickness direction of the SiC substrate 10. Each epitaxial layer 20, 21, 22 will be described later.

  A second conductivity type well region 14 is formed in the active layer 11. In the center of the well region 14, a second conductivity type well contact region 16 having a relatively high impurity concentration for reducing the contact resistance with the metal electrode is disposed. A source region 15 of the first conductivity type is formed so as to surround the well contact region 16.

  The source pad 2 includes a gate insulating film 12, a gate electrode 13, an interlayer insulating film 17 and a source electrode 18. The gate insulating film 12 is formed on the surface on one side in the thickness direction of the active layer 11 so as to overlap the source region 15 of the adjacent cell. That is, the gate insulating film 12 is formed from one source region 15 to the other source region 15 of the source regions 15 of two adjacent cells.

  A gate electrode 13 and an interlayer insulating film 17 are formed on the surface of one side in the thickness direction of the gate insulating film 12. The source electrode 18 is composed of a metal wiring such as an aluminum electrode, and connects the well contact region 16 and the source region 15.

As shown in FIG. 3, SiC epitaxial substrate 3 includes SiC substrate 10, first epitaxial layer 20 formed on the surface of one side in the thickness direction of SiC substrate 10, and one side in the thickness direction of first epitaxial layer 20. A second epitaxial layer 21 formed on the surface and a third epitaxial layer 22 formed on the surface of one side in the thickness direction of the second epitaxial layer 21 are configured. SiC substrate 10 is formed of a 4H-type silicon carbide semiconductor substrate having an impurity concentration of 3 × 10 ¹⁸ cm ⁻³ or more and an off-angle exceeding 0 °.

  The second epitaxial layer 21 functions as a stacking fault extension control layer that controls the extension of stacking faults. Here, “controlling expansion of stacking faults” means, for example, stacking caused by recombination of majority carriers and minority carriers when a forward current flows through the diode structure constituting the body of SiC-MOSFET 100. Defect expansion is stopped in the second epitaxial layer 21 to prevent further expansion of stacking faults.

  The dimension in the thickness direction of the active layer 11 (hereinafter sometimes referred to as “layer thickness”) is determined according to the breakdown voltage and characteristics required for the power device, and is, for example, about 3 μm to 200 μm.

The first epitaxial layer 20, the second epitaxial layer 21, and the third epitaxial layer 22 have layer thicknesses T1 [μm], T2 [μm], and T3 [μm], respectively, and impurity concentrations N1 [cm ⁻³ ], When N2 [cm ⁻³ ] and N3 [cm ⁻³ ] are set, they are designed so as to satisfy the relationships of the following formulas (1) to (5). As a result, the lower end of the depletion layer enters the first epitaxial layer 20 during the operation of the SiC-MOSFET 100 (hereinafter sometimes referred to as “device operation”).
N1 ≦ 1 × 10 ¹⁶ cm ⁻³ (1)
N2 ≧ 1 × 10 ¹⁷ cm ⁻³ (2)
N3 ≦ 1 × 10 ¹⁶ cm ⁻³ (3)
T2 ≧ 0.01 μm (4)
T1 × T2 × N2 ≦ 2.684 × 10 ¹⁷ (5)

  The above formulas (1) to (5) will be described below. Expression (1) defines the impurity concentration N1 of the first epitaxial layer 20. Formula (3) defines the impurity concentration N3 of the third epitaxial layer 22.

In the present embodiment, by satisfying the relations of the expressions (1) and (3), the impurity concentration N1 of the first epitaxial layer 20 and the impurity concentration N3 of the third epitaxial layer 22 are each 1 × 10 ¹⁶ cm ⁻³ or less. If the impurity concentrations N1 and N3 of the first epitaxial layer 20 and the third epitaxial layer 22 exceed 1 × 10 ¹⁶ cm ⁻³ , the impurity concentration is too high to satisfy the required breakdown voltage as a power device. is there.

The impurity concentration N1 of the first epitaxial layer 20 and the impurity concentration N3 of the third epitaxial layer 22 need not be the same. The impurity concentration N1 of the first epitaxial layer 20 and the impurity concentration N3 of the third epitaxial layer 22 are 5 × 10 ¹⁴ cm ⁻³ or more and 1 × 10 ¹⁶ cm ⁻ according to the breakdown voltage and characteristics required for the power device, respectively. It is preferable to design in the range of ³ or less.

In the above formula (2), the impurity concentration N2 of the second epitaxial layer 21 is defined. In the present embodiment, the impurity concentration N2 of the second epitaxial layer 21 is set to 1 × 10 ¹⁷ cm ⁻³ or more. When the impurity concentration N2 of the second epitaxial layer 21 is less than 1 × 10 ¹⁷ cm ⁻³ , the impurity concentration is too low, and the effect of controlling the extension of stacking faults by the second epitaxial layer 21 (hereinafter referred to as “expansion control effect”). This is because it is not possible to obtain sufficient.

The upper limit of the impurity concentration N2 of the second epitaxial layer 21 is not particularly limited from the viewpoint of the stacking fault expansion control effect, but from the viewpoint of the breakdown voltage as a device, the impurity concentration N2 of the second epitaxial layer 21 is 1 ×. 10 ¹⁷ cm ^-3 or more, and preferably in the range of 5 × ¹⁰ 18 ^{cm -3} or less.

If a layer having an impurity concentration of 1 × 10 ¹⁷ cm ⁻³ or more is provided in the active layer 11, the device breakdown voltage may be reduced. The reason why the above range of 1 × 10 ¹⁷ cm ⁻³ or more and 5 × 10 ¹⁸ cm ⁻³ or less is preferable is that when the impurity concentration N2 of the second epitaxial layer 21 exceeds 5 × 10 ¹⁸ cm ⁻³ , the impurity concentration This is because the breakdown voltage as a power device is greatly reduced by providing the second epitaxial layer 21 because it is too high. In order to compensate for this decrease in breakdown voltage, it is necessary to increase the thickness of the active layer 11, which is disadvantageous in terms of productivity.

On the other hand, in the present embodiment, the impurity concentration N2 of the second epitaxial layer 21 is set to 1 × 10 ¹⁷ cm ⁻³ or more and 5 × 10 ¹⁸ cm ⁻³ or less. This can compensate for a decrease in breakdown voltage due to the provision of the second epitaxial layer 21 in the active layer 11 without increasing the thickness of the active layer 11.

  In the above equation (4), the layer thickness T2 of the second epitaxial layer 21 is defined. In the present embodiment, the layer thickness T2 of the second epitaxial layer 21 is set to 0.01 μm or more. This is because if the layer thickness T2 of the second epitaxial layer 21 is less than 0.01 μm, that is, less than 10 nm, the expansion control effect of stacking faults cannot be sufficiently obtained.

  In the expansion control effect of stacking faults, there is no upper limit of the layer thickness T2 of the second epitaxial layer 21, but a range of 10 nm or more and 50 nm or less is preferable. When the layer thickness T2 of the second epitaxial layer 21 exceeds 50 nm, the withstand voltage of the power device is relatively greatly reduced. In order to compensate for this decrease in withstand voltage, the active layer 11 needs to be increased in thickness. This is because it is disadvantageous.

In the above equation (5), the layer thickness T1 of the first epitaxial layer 20, the layer thickness T2 of the second epitaxial layer 21, and the impurity concentration N2 are defined. As shown by the above-described formula (5), in the present embodiment, the layer thickness T1 [μm] of the first epitaxial layer 20, the layer thickness T2 [μm] of the second epitaxial layer 21, and the second epitaxial layer 21 The value obtained by multiplying the impurity concentration of N2 [cm ⁻³ ] must be 2.2684 × 10 ¹⁷ or less. By satisfying the relationship of Expression (5), it is possible to suppress a decrease in the breakdown voltage of the power device due to the provision of the second epitaxial layer 21.

Derivation of the above equation (5) will be described below. The reduced withstand voltage amount ΔV [V] due to the provision of the second epitaxial layer 21 as the stacking fault expansion control layer is expressed by the following equation (6) when the reduced withstand voltage amount is relatively small with respect to the overall withstand voltage. Approximated.
ΔV = (e × N2 × T2 / ε) × T1 (6)

  Here, e represents the elementary amount of electricity, N2 represents the impurity concentration of the second epitaxial layer 21, T2 represents the layer thickness of the second epitaxial layer 21, ε represents the dielectric constant, and T1 represents the first epitaxial layer. A layer thickness of 20 is shown. Specifically, the layer thickness T1 of the first epitaxial layer 20 is a distance from the interface between the SiC substrate 10 and the first epitaxial layer 20 to the second epitaxial layer 21, and indicates the position of the second epitaxial layer 21. In other words.

In the above equation (6), by setting the reduced withstand voltage ΔV to 500 V or less, the expansion of stacking faults can be controlled without impairing device characteristics and productivity. Substituting e = 1.6 × 10 ⁻¹⁹ [C] as the elementary electric quantity e and substituting ε = 8.5845 × 10 ⁻¹¹ as the dielectric constant ε of 4H-type SiC, It can be seen that in order to make ΔV 500 V or less, it is necessary to satisfy the relationship of the above-mentioned formula (5). In this way, the above equation (5) is derived.

The reduced withstand voltage ΔV is more preferably 300 V or less. In order to set the reduced withstand voltage ΔV to 300 or less, it is preferable to satisfy the relationship of the following expression (7).
T1 × T2 × N2 ≦ 1.610 × 10 ¹⁷ (7)

For example, in the present embodiment, for a device having a withstand voltage of 3300 V having an active layer 11 with a layer thickness of 30 μm and an impurity concentration of 3 × 10 ¹⁵ cm ⁻³ , T1 = 5 μm, N1 = 3 × 10 ¹⁵ cm ⁻³ , T2 Consider a case where 0.02 μm, N2 = 1 × 10 ¹⁸ cm ⁻³ , T3 = 25 μm, N3 = 3 × 10 ¹⁵ cm ⁻³ , and T1 × T2 × N2 = 1.00 × 10 ¹⁷ . This is because the layer thickness T2 is 20 nm and the impurity concentration N2 is 5 nm from the interface between the SiC substrate 10 and the first epitaxial layer 20 with respect to the structure of the SiC epitaxial substrate 3A of the base technology shown in FIG. This corresponds to the case where the second epitaxial layer 21 of 1 × 10 ¹⁸ cm ⁻³ is provided as a stacking fault extension control layer.

  In this case, the reduced withstand voltage ΔV of the power device is as small as 186 [V]. Therefore, it is not necessary to significantly increase the layer thickness T1 of the active layer 11 and to significantly reduce the impurity concentration N1 of the active layer 11, and to expand the stacking fault without deteriorating device characteristics such as on-resistance and productivity. It becomes possible to control. Since the second epitaxial layer 21 provided as the stacking fault extension control layer is also a very thin layer having a thickness T2 of 20 nm, the reduction in productivity due to the provision of the second epitaxial layer 21 is extremely small.

In contrast, for similar devices, T1 = 10 μm, N1 = 3 × 10 ¹⁵ cm ⁻³ , T2 = 0.07 μm, N2 = 1 × 10 ¹⁸ cm ⁻³ , T3 = 20 μm, N3 = 3 × 10 ¹⁵ cm. ⁻³ , T1 × T2 × N2 = 7.00 × 10 ¹⁷ is considered. This is because the layer thickness T2 is 70 nm and the impurity concentration N2 is 10 μm from the interface between the SiC substrate 10 and the first epitaxial layer 20 with respect to the structure of the SiC epitaxial substrate 3A of the base technology shown in FIG. This corresponds to the case where the second epitaxial layer 21 of 1 × 10 ¹⁸ cm ⁻³ is provided as a stacking fault extension control layer.

  In this case, since the reduced withstand voltage ΔV of the power device is as large as 1304 [V], in order to maintain the withstand voltage of the power device, it is necessary to increase the thickness of the active layer 11 and reduce the impurity concentration. Therefore, it is difficult to control the expansion of stacking faults while maintaining the device characteristics.

  From the above, by satisfying the relationship of the above-mentioned formula (7), the necessity for a significant increase in the layer thickness T1 of the active layer 11 and a significant reduction in the impurity concentration N1 of the active layer 11 is eliminated. It is possible to control the expansion of stacking faults without deteriorating device characteristics such as on-resistance and productivity. In addition, a decrease in productivity due to the provision of the second epitaxial layer 21 can be suppressed to an extremely small level.

  In the present embodiment, since the first epitaxial layer 20, the second epitaxial layer 21, and the third epitaxial layer 22 all function as the active layer 11, there is no need to provide a layer other than the active layer 11, and The layer thickness of the active layer 11 can also be maintained substantially at the layer thickness that is normally used. Therefore, there is almost no increase in on-resistance.

  As described above, according to the present embodiment, the second epitaxial layer 21 can suppress the extension of stacking faults that are generated from the dislocations and misfit dislocations included in the first epitaxial layer 20. As a result, the deterioration of the device characteristics due to the expansion of the stacking fault can be suppressed to a level that does not cause a practical problem, so that the reliability of the device can be greatly improved.

  In addition, since all of the first epitaxial layer 20, the second epitaxial layer 21, and the third epitaxial layer 22 can be used as active layers, the first epitaxial layer 20, the second epitaxial layer 21, and the third epitaxial layer 22 are included. By using the active layer 11 configured, it is not necessary to provide a layer other than the active layer 11. Further, the layer thickness of the active layer 11 can be substantially maintained.

  Therefore, by forming a silicon carbide semiconductor device with SiC-MOSFET 100 that is a semiconductor element including first epitaxial layer 20, second epitaxial layer 21, and third epitaxial layer 22 as at least a part of active layer 11, a silicon carbide semiconductor is formed. An increase in on-resistance in the device can be suppressed.

In addition, since the first epitaxial layer 20 and the second epitaxial layer 21 satisfy the relationship of T1 × T2 × N2 ≦ 2.684 × 10 ¹⁷ , it is possible to suppress device degradation without greatly reducing the device breakdown voltage. It is.

  As described above, according to the present embodiment, expansion of stacking faults occurring in the epitaxial layers 20, 21, and 22 is suppressed, and degradation of device characteristics is not a practical problem while maintaining device breakdown voltage and on-resistance. The SiC epitaxial substrate 3 which can be suppressed to can be provided.

  In the present embodiment, the example of the epitaxial structure shown in FIG. 2 is shown as an example. However, the configuration of the SiC epitaxial substrate 3 is not limited to this, and the above-described equations (1) to (5) are used. As long as the relationship is satisfied.

  In the present embodiment, the semiconductor including the first epitaxial layer 20, the second epitaxial layer 21, and the third epitaxial layer 22 of the SiC epitaxial substrate 3 having the excellent effects as described above as at least a part of the active layer 11. A silicon carbide semiconductor device is configured by including SiC-MOSFET 100 as an element.

  As a result, expansion of stacking faults occurring in the epitaxial layers 20, 21, and 22 can be suppressed. Therefore, it is possible to obtain a silicon carbide semiconductor device capable of suppressing deterioration of device characteristics to such an extent that it does not become a practical problem while maintaining device breakdown voltage and on-resistance.

  In the present embodiment, first epitaxial layer 20, second epitaxial layer 21, and third epitaxial layer 22 contain any one of nitrogen, aluminum, phosphorus, and boron as an impurity. Thereby, a silicon carbide semiconductor device formed of SiC-MOSFET 100 having excellent device characteristics can be realized.

  In particular, the silicon carbide semiconductor constituted by SiC-MOSFET 100 having particularly excellent device characteristics by making nitrogen as an impurity in first epitaxial layer 20, second epitaxial layer 21, and third epitaxial layer 22. An apparatus can be realized.

  Next, a method for growing epitaxial layers 20, 21, 22 on SiC epitaxial substrate 3 of the present embodiment will be described. In this embodiment, as an example, a case where n-type silicon carbide is epitaxially grown using nitrogen as a dopant will be described.

  First, the first epitaxial layer 20 is epitaxially grown using a known epitaxial growth method. Specifically, the first epitaxial layer 20 constituting the active layer 11 is epitaxially grown on the silicon carbide substrate 10 by using a chemical vapor deposition (abbreviation: CVD) method.

Hydrogen (H ₂ ) is used as a carrier gas, and a silicon-containing gas typified by silane (SiH ₄ ) and disilane (Si ₂ H ₆ ), propane (C ₃ H ₈ ), and methane (CH ₂ ) are used as a source gas. ₄ ) A carbon-containing gas represented by the above is used. The C / Si ratio, which is the flow ratio of these source gases, is set to 0.5 to 1.5. Further, nitrogen (N ₂ ) is added as an impurity dopant gas.

  These carrier gas, source gas, and dopant gas are introduced into a reaction furnace heated to 1400 ° C. to 1800 ° C. with a SiC single crystal substrate as SiC substrate 10, epitaxially grown on the SiC single crystal substrate, and SiC Epitaxial substrate 3 is formed. The growth rate is about 3 μm / h to 100 μm / h. The reactor pressure is set to 1 kPa to 30 kPa. In order to improve the growth rate, a halide-containing gas may be used.

  After the first epitaxial layer 20 having a desired layer thickness and impurity concentration is epitaxially grown, the supply amount of a gas containing nitrogen is increased, and the second epitaxial layer 21 that is a stacking fault extension control layer is epitaxially grown.

  At this time, it is desirable to grow at a growth rate slower than the growth rate of the first epitaxial layer 20 from the viewpoint of layer thickness controllability. Further, the C / Si ratio may be lowered as compared with the growth of the first epitaxial layer 20. This is because nitrogen can be taken up more efficiently.

  Further, the growth temperature and the growth pressure may be changed between the first epitaxial layer 20 and the second epitaxial layer 21. This is also for more efficient nitrogen uptake.

  When changing the growth temperature, the supply of the source gas is temporarily stopped between the first epitaxial layer 20 and the second epitaxial layer 21, and the growth is resumed after completely changing to the desired temperature and pressure. It is desirable to do. This is to prevent the growth rate and impurity concentration from changing due to changes in the growth temperature and growth pressure.

  Alternatively, after the second epitaxial layer 21 having a thickness larger than the desired layer thickness is epitaxially grown, the supply of the source gas may be stopped, and the layer thickness may be reduced by the etching effect of hydrogen to adjust the desired layer thickness.

  After the second epitaxial layer 21 is epitaxially grown, the third epitaxial layer 22 is epitaxially grown. At this time, it is desirable to grow at a growth rate higher than the growth rate of the second epitaxial layer 21 from the viewpoint of productivity. The C / Si ratio may be increased more than the growth conditions of the second epitaxial layer 21.

  Further, the growth temperature and the growth pressure may be changed between the second epitaxial layer 21 and the third epitaxial layer 22. In that case, it is desirable to temporarily stop the supply of the source gas between the second epitaxial layer 21 and the third epitaxial layer 22, completely change the desired temperature and pressure, and then restart the growth. This is to prevent the growth rate and impurity concentration from changing due to changes in the growth temperature and growth pressure.

  The growth conditions of the second epitaxial layer 21 may be the same as or different from the growth conditions of the first epitaxial layer 20. The essence of the present invention lies in a structure that satisfies the relationship of the above formulas (1) to (5), and the effect does not change depending on the growth conditions.

The layer thickness T3 of the third epitaxial layer 22 is desirably twice or more larger than the layer thickness T1 of the first epitaxial layer 20. That is, it is desirable to satisfy the relationship of the following formula (8).
2 × T1 ≦ T3 (8)

  The expansion of stacking faults caused by dislocations and misfit dislocations often starts from the bottom of the active layer 11, that is, the interface between the SiC substrate 10 and the first epitaxial layer 20 and the inside of the first epitaxial layer 20. . Therefore, by extending the second epitaxial layer 21 as the stacking fault extension control layer more epitaxially on the SiC substrate 10 side so as to satisfy the relationship of the above-described formula (8), the stacking fault can be expanded more efficiently. Control and prevent degradation of device characteristics.

  As described above, according to the method for manufacturing SiC epitaxial substrate 3 according to the present embodiment, a plurality of epitaxial layers 20, 21, and 22 constituting active layer 11 can be epitaxially grown in the same furnace. Therefore, the above-described SiC epitaxial substrate 10 can be obtained without significantly reducing the throughput.

<Second Embodiment>
FIG. 4 is a cross sectional view showing a configuration of SiC epitaxial substrate 300 of SiC-MOSFET 200 which is an example of the silicon carbide semiconductor device according to the second embodiment of the present invention.

  In the first embodiment described above, as shown in FIG. 3, the SiC epitaxial substrate 3 is configured by epitaxially growing the first epitaxial layer 20 constituting the active layer 11 directly on the SiC substrate 10.

  In the present embodiment, as shown in FIG. 4, SiC epitaxial substrate 300 in which buffer layer 25 is provided between SiC substrate 10 and active layer 11 is used. By providing the buffer layer 25 between the SiC substrate 10 and the active layer 11, the lattice strain caused by the difference in lattice constant between the SiC substrate 10 and the active layer 11 is controlled, and crystal defects in the active layer 11 are controlled. Can be reduced.

  The impurity concentration of buffer layer 25 is preferably not more than the impurity concentration of SiC substrate 10. The lower limit value of the impurity concentration of the buffer layer 25 can be selected according to the purpose, and may be greater than or equal to the impurity concentration of the first epitaxial layer 20 or less than the impurity concentration of the first epitaxial layer 20.

  When the impurity concentration of the buffer layer 25 is equal to or lower than the impurity concentration of the SiC substrate 10 and equal to or higher than the impurity concentration of the first epitaxial layer 20, lattice distortion can be relaxed, and there is less crystal defects and higher quality. The active layer 11 can be obtained. The buffer layer 25 has a single-layer structure with a uniform impurity concentration, a step-type gradient structure in which the impurity concentration is changed stepwise in the thickness direction of the buffer layer 25, and the impurity concentration is within the above-described concentration range. Any of the continuous inclined structures in which the impurity concentration is continuously changed in the thickness direction of the buffer layer 25 may be used.

  On the contrary, when the impurity concentration of the buffer layer 25 is equal to or lower than the impurity concentration of the SiC substrate 10 and less than the impurity concentration of the first epitaxial layer 20, the lattice strain becomes large. Misfit dislocations occur at the interface between the layer 25 and the SiC substrate 10. By intentionally generating misfit dislocations at the interface between the buffer layer 25 and the SiC substrate 10, it is possible to relieve the stress caused by lattice strain and obtain a higher quality active layer 11 with a low stress.

  In this case, misfit dislocations occur at the interface between the buffer layer 25 and the SiC substrate 10, and the extension of stacking faults due to this can be controlled in the second epitaxial layer 21 that is a stacking fault extension control layer. So degradation is not a problem. Thus, the impurity concentration of the buffer layer 25 can be selected according to the purpose.

  The layer thickness of the buffer layer 25 is preferably 100 nm or more and 10 μm or less. This is because if the thickness of the buffer layer 25 is less than 100 nm, the effect as the buffer layer 25 is insufficient, and if the thickness of the buffer layer 25 exceeds 10 μm, it is disadvantageous in productivity.

  By providing the buffer layer 25 as described above between the SiC substrate 10 and the active layer 11, the device characteristics and the yield can be improved.

  Next, the effect of the second epitaxial layer 21 that is a stacking fault extension control layer will be described. The inventor of the present invention has found that the thin-film high impurity concentration layer has an effect of suppressing the extension of stacking faults while investigating the method of suppressing the extension of stacking faults due to forward conduction of the SiC-MOSFET.

  The inventor produced three types of epitaxial structures shown in FIG. 4 described above and FIGS. 5 and 6 described later on the surface of one side in the thickness direction of the SiC substrate 10 which is a 4H—SiC substrate, and the SiC epitaxial substrate. 300, 310, 300A were manufactured.

  A SiC-MOSFET was fabricated on the surface on one side in the thickness direction of these SiC epitaxial substrates 300, 310, and 300A, and stacking faults expanded by forward energization were evaluated in detail using a PL-TOPO (Photoluminescence topography) method.

  FIG. 5 is a cross-sectional view showing a configuration of a SiC epitaxial substrate 310 of a SiC-MOSFET 210 which is another example of the SiC-MOSFET of the present invention. FIG. 6 is a cross-sectional view showing a configuration of a SiC epitaxial substrate 300A of a SiC-MOSFET 200A that is another example of the SiC-MOSFET of the base technology.

  The SiC epitaxial substrate of the present embodiment shown in FIG. 4 has an epitaxial structure in which the second epitaxial layer 21 which is a thin high impurity concentration layer is provided at the center of the active layer 11.

  SiC epitaxial substrate 310 shown in FIG. 5 has an epitaxial structure in which second epitaxial layer 21 and fourth epitaxial layer 23 which are thin high impurity concentration layers are provided so as to divide active layer 110 into three equal parts. Specifically, SiC epitaxial substrate 310 includes active layer 110 in which fourth epitaxial layer 23 and fifth epitaxial layer 24 are provided on active layer 11 of SiC epitaxial substrate 300 shown in FIG. 4 described above. The second epitaxial layer 21 and the fourth epitaxial layer 23 function as a stacking fault extension control layer.

  An SiC epitaxial substrate 300A shown in FIG. 6 has a configuration in which a buffer layer 25 is provided between the SiC epitaxial substrate 3A of the prerequisite technology shown in FIG. 10 and the active layer 11A, and an epitaxial layer in which no thin high impurity concentration layer is provided. It has a structure.

The layer thickness of each active layer 11, 110 was 30 μm, the thickness of the second epitaxial layers 21, 23, which are thin high impurity concentration layers, was 20 nm, and the impurity concentration was 2 × 10 ¹⁸ cm ⁻³ . Nitrogen was used as a doping impurity. In order to reduce crystal defects in the active layers 11 and 110, the buffer layer 25 was epitaxially grown before the active layers 11 and 110 were epitaxially grown.

In the epitaxial structure shown in FIGS. 4 to 6, the stacking fault is sufficiently expanded at 100 A / cm ² , and after 10 minutes of forward current application, the extended stacking fault is evaluated by the PL-TOPO method using a 750 nm high-pass filter. The results are shown in FIGS.

  7 to 9 are diagrams showing PL-TOPO images of samples corresponding to the epitaxial structures of FIGS. 4 to 6. The white light emitting regions in FIGS. 7 to 9 are stacking faults 30. The stacking fault 30 is observed in all the samples in FIGS. 7 to 9, but it can be seen that the widths of the stacking faults are different. Specifically, the width of the white light emitting region representing the stacking fault 30 is 214 μm in FIG. 7, 147 μm in FIG. 8, and 424 μm in FIG.

  The widths of these light emitting regions correspond to the expanded layer thickness of the stacking fault 30. Taking into account that the off-angle of the SiC substrate 10 used is 4 °, the calculated layer thickness of the stacking fault 30 is 15.0 μm in FIG. 7 and 10.3 μm in FIG. 9 is 29.6 μm.

  These layer thicknesses are 1/2 (1/2) times, 1/3 (1/3) times, and 1 time of the active layers 11 and 110, respectively. 11 and 110 are equal to the layer thickness from the second epitaxial layer 21 which is a thin high impurity concentration layer. From this, it can be seen that expansion of these stacking faults is suppressed by the second epitaxial layer 21 which is a thin high impurity concentration layer.

  Further, by observing the cross section with a transmission electron microscope (abbreviation: TEM), it is clear that the expansion of stacking faults is stopped in the second epitaxial layer 21 which is a thin film high impurity concentration layer. Observed. Further, it was confirmed that the deterioration of the characteristics of the SiC-MOSFET was improved by reducing the area of the stacking fault.

  From the above results, it can be seen that by providing a thin high impurity concentration layer in the active layers 11 and 110, expansion of stacking faults can be suppressed and characteristic deterioration of the SiC-MOSFET can be reduced.

  Here, the reason why expansion of these stacking faults is suppressed in the present invention is considered as follows. In the PN diode structure, slipping phenomenon of basal plane dislocation and misfit dislocation is caused by recombination energy between minority carriers and majority carriers, and stacking faults are expanded.

  However, in a crystal with a high impurity concentration, the interaction between the strain field created by the dislocations and the strain field created by the impurities doped at a high concentration causes the dislocations to stick and cause a greater amount of energy to cause the dislocation slip. Necessary.

  In the present embodiment, since the second epitaxial layer 21 which is a thin high impurity concentration layer is provided in the active layer 11 as described above, dislocations are fixed, and as a result, expansion of stacking faults can be suppressed. it is conceivable that.

  Therefore, after the extension of stacking faults is started by providing the active layer 11 with the second epitaxial layer 21 which is a thin film high impurity concentration layer as a stacking fault extension control layer as in the present embodiment, The expansion can be stopped, thereby improving the degradation characteristics of the SiC-MOSFET.

  In the above-described experiment, the thickness of the second epitaxial layer 21 that is the stacking fault extension control layer was set to 20 nm. The layer thickness of the second epitaxial layer 21 is not limited to this, but is preferably 10 nm or more. If the layer thickness of the second epitaxial layer 21 is 10 nm or more, the expansion of stacking faults can be sufficiently suppressed.

In the above-described experiment, the impurity concentration of the second epitaxial layer 21 was set to 2 × 10 ¹⁸ / cm ³ . The impurity concentration of the second epitaxial layer 21 is not limited to this, but is preferably 1 × 10 ¹⁷ / cm ³ or more. If the impurity concentration of the second epitaxial layer 21 is 1 × 10 ¹⁷ / cm ³ or more, the expansion of stacking faults can be sufficiently suppressed.

  In the present embodiment, as shown in FIG. 6 described above, the second epitaxial layer 21 which is a thin film high impurity concentration layer is provided so as to divide the active layer 11 into two equal parts, but the thin film high impurity concentration layer is provided. The position of the second epitaxial layer 21 is not limited to this. The closer the position of the second epitaxial layer 21 is to the surface of the active layer 11, the greater the influence on the thin film device breakdown voltage. Therefore, in the present embodiment, the position of the second epitaxial layer 21 is defined by the above-described equation (5). By providing the second epitaxial layer 21 so as to satisfy the relationship of the above formula (5), it is possible to suppress the expansion of stacking faults while maintaining the device breakdown voltage.

  In this embodiment mode, nitrogen is used as a doping gas. However, a gas containing another element such as aluminum (Al), phosphorus (P), or boron (B) may be used as a doping gas. Even if any of these impurities is doped, the same effect as when nitrogen is used as a doping gas can be obtained.

  Moreover, in this Embodiment, the silicon carbide semiconductor device is comprised including SiC-MOSFET200 which has the above outstanding effects. As a result, expansion of stacking faults occurring in the epitaxial layers 20, 21, and 22 can be suppressed. Therefore, it is possible to obtain a silicon carbide semiconductor device capable of suppressing deterioration of device characteristics to such an extent that it does not become a practical problem while maintaining device breakdown voltage and on-resistance.

<Third Embodiment>
FIG. 12 is a cross sectional view showing a configuration of SiC-MOSFET 101 which is an example of the silicon carbide semiconductor device according to the third embodiment of the present invention. The SiC-MOSFET 101 of the present embodiment corresponds to a configuration after energizing the body diode of the SiC-MOSFET 100 in the first embodiment described above in the forward direction. SiC-MOSFET 101 of the present embodiment includes extended stacking fault 30 in active layer 11.

  The SiC-MOSFET 101 according to the present embodiment has the same configuration as that of the SiC-MOSFET 100 according to the first embodiment except that the active layer 11 includes the stacking fault 30. A common description may be omitted.

  SiC-MOSFET 101 is similar to SiC-MOSFET 100 in the first embodiment shown in FIG. 1 described above, SiC epitaxial substrate 3, gate pad 1 formed on the surface of one side in the thickness direction of SiC epitaxial substrate 3, and And a source pad 2.

  The SiC epitaxial substrate 3 includes a first conductivity type SiC substrate 10 and a first conductivity type active layer 11. An epitaxially grown active layer 11 is formed on the surface of one side in the thickness direction of SiC substrate 10.

  The active layer 11 includes three epitaxial layers 20, 21, and 22 that are parallel to the surface on one side in the thickness direction of the SiC substrate 10. In the active layer 11, a stacking fault 30 is formed that extends along the basal plane, that is, in a direction perpendicular to the step flow direction SF that is the epitaxial growth direction.

  A second conductivity type well region 14 is formed in the active layer 11. In the center of the well region 14, a second conductivity type well contact region 16 having a relatively high impurity concentration for reducing the contact resistance with the metal electrode is disposed. A source region 15 of the first conductivity type is formed so as to surround the well contact region 16.

  The source pad 2 includes a gate insulating film 12, a gate electrode 13, an interlayer insulating film 17 and a source electrode 18. The gate insulating film 12 is formed on the surface on one side in the thickness direction of the active layer 11 so as to overlap the source region 15 of the adjacent cell. That is, the gate insulating film 12 is formed from one source region 15 to the other source region 15 of the source regions 15 of two adjacent cells.

  A gate electrode 13 and an interlayer insulating film 17 are formed on the surface of one side in the thickness direction of the gate insulating film 12. The source electrode 18 is composed of a metal wiring such as an aluminum electrode, and connects the well contact region 16 and the source region 15.

SiC epitaxial substrate 3 is similar to SiC-MOSFET 100 in the first embodiment shown in FIG. 3 described above, SiC substrate 10 and first epitaxial layer 20 formed on the surface of one side in the thickness direction of SiC substrate 10. A second epitaxial layer 21 formed on the surface on one side in the thickness direction of the first epitaxial layer 20, and a third epitaxial layer 22 formed on the surface on one side in the thickness direction of the second epitaxial layer 21. Composed. SiC substrate 10 is formed of a 4H-type silicon carbide semiconductor substrate having an impurity concentration of 3 × 10 ¹⁸ cm ⁻³ or more and an off-angle exceeding 0 °.

  The stacking fault 30 in the present embodiment will be described below. Specifically, the stacking fault 30 exists in the first epitaxial layer 20 constituting the active layer 11. The width L of the stacking fault 30 shown in FIG. 12 depends on the off angle of the SiC substrate 10 and the layer thickness T1 of the first epitaxial layer 20, and satisfies the following formula (9).

L ≦ T1 / tan (θ) (9)
In equation (9), θ represents the off-angle of SiC substrate 10. That is, when the off-angle of the SiC substrate 10 is θ [°] and the thickness of the first epitaxial layer is T1 [μm], the stacking fault 30 has a width L of T1 / tan (θ) [μm] or less. It is.

  Here, the width L of the stacking fault 30 is a direction obtained by projecting the step flow direction onto the surface on one side in the thickness direction of the SiC substrate 10 when the stacking fault 30 is observed from the surface of the SiC-MOSFET 101. Means the length dimension of the stacking fault 30 in the direction parallel to. The width L of the stacking fault 30 corresponds to the width of the light emitting region shown in FIGS. The width of the light emitting area is the length dimension in the horizontal direction of the light emitting area, and corresponds to the length dimension in the vertical direction toward the paper surface of FIGS.

  The stacking fault 30 satisfying the above-described formula (9) has an area of one third (1/3) or less as compared with the stacking fault expanded by energizing the body diode of the SiC-MOSFET 100A of the base technology. Therefore, in this embodiment, the deterioration of the forward characteristics of the MOSFET can be significantly reduced. The reason why the area of the stacking fault 30 is 1/3 or less is that the layer thickness T1 of the first epitaxial layer 20 satisfies the above-described formula (8).

  The SiC-MOSFET 101 of the present embodiment is a SiC-MOSFET including a stacking fault 30 formed when the SiC-MOSFET 100 in the first embodiment is energized. However, the present invention is not limited to this. For example, even in the SiC-MOSFET including the stacking fault formed when the SiC-MOSFET 200 in the second embodiment is energized, the stacking fault satisfies the above formula (9), and this embodiment The same effect as that of the embodiment can be obtained.

  In the present embodiment, the SiC-MOSFET 101 having the excellent effects as described above is provided to constitute the silicon carbide semiconductor device, thereby suppressing the expansion of stacking faults occurring in the epitaxial layers 20, 21, and 22. can do. Therefore, it is possible to obtain a silicon carbide semiconductor device capable of suppressing deterioration of device characteristics to such an extent that it does not become a practical problem while maintaining device breakdown voltage and on-resistance.

  In the first to third embodiments described above, the MOSFET structure is taken as an example, but any device structure having a PN diode junction is applicable. For example, the present invention can be applied to a PIN diode, an insulated gate bipolar transistor (abbreviated as IGBT), and the like. In addition, the method of forming each element constituting these devices is not different from a known method except for the epitaxial growth method, and thus the description thereof is omitted here.

  In the first to third embodiments, when manufacturing the SiC epitaxial substrates 3 and 300, the second epitaxial layer 21 that is a stacking fault extension control layer is formed only by epitaxial growth. The second epitaxial layer 21 that is the stacking fault extension control layer is not limited to this, and may be formed by implanting impurities by, for example, an ion implantation method. Thereby, a high concentration impurity can be added with better control.

  The present invention can be freely combined with each embodiment within the scope of the invention. In addition, any component in each embodiment can be changed or omitted as appropriate.

  Although the present invention has been described in detail, the above description is illustrative in all aspects, and the present invention is not limited thereto. It is understood that countless variations that are not illustrated can be envisaged without departing from the scope of the present invention.

  DESCRIPTION OF SYMBOLS 1 Gate pad, 2,2A source pad, 3,300,300A, 310 SiC epitaxial substrate, 10 SiC substrate, 11,110 active layer, 12 gate insulating film, 13 gate electrode, 14 well region, 15 source region, 16 well Contact region, 17 interlayer insulating film, 18 source electrode, 20 first epitaxial layer, 21 second epitaxial layer (stacking defect expansion control layer, thin film high impurity concentration layer), 22 third epitaxial layer, 23 fourth epitaxial layer (laminated) (Defect extension control layer, thin film high impurity concentration layer), 24 fifth epitaxial layer, 25 buffer layer, 30 stacking fault, 100, 101, 100A, 200, 200A, 210 SiC-MOSFET.

A silicon carbide epitaxial substrate of the present invention includes a silicon carbide substrate, a first epitaxial layer formed by epitaxial growth on a surface on one side in the thickness direction of the silicon carbide substrate, and a surface on one side in the thickness direction of the first epitaxial layer. A second epitaxial layer formed by epitaxial growth; and a third epitaxial layer formed by epitaxial growth on one surface in the thickness direction of the second epitaxial layer. The silicon carbide substrate has an impurity concentration of 3 × 10 ^18. cm ⁻³ or more, an off-angle exceeding 0 °, the layer thickness of the first epitaxial layer is T1 [μm], the layer thickness of the second epitaxial layer is T2 [μm], and the third the thickness of the epitaxial layer and T3 [μm], the impurity concentration of the first epitaxial layer N1 [cm ^- And, when the impurity concentration of the second epitaxial layer and N2 ^{[cm -3],} and the impurity concentration of the third epitaxial layer and ^{N3 [cm -3], N1 ≦} 1 × 10 16 cm -3, N2 ^{≧ 1 × 10 17 cm -3,} N3 ≦ 1 × 10 16 cm -3, T2 ≧ 0.01μm, meets the relationship of T1 × T2 × N2 ≦ 2.684 × 10 17, the first epitaxial layer, The stacking fault includes a stacking fault, and when the off-angle of the silicon carbide substrate is θ [°], the step flow direction that is the epitaxial growth direction of the first epitaxial layer is on one side in the thickness direction of the silicon carbide substrate. A width which is a length dimension in a direction parallel to a direction obtained by projecting on the surface is T1 / tan (θ) [μm] or less .

In the silicon carbide semiconductor device of the present invention, the silicon carbide epitaxial substrate of the present invention includes the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer including the stacking fault as at least a part of an active layer. A semiconductor element is included.

According to the silicon carbide semiconductor device of the present invention, the first epitaxial layer including the stacking fault , the second epitaxial layer, and the third epitaxial layer of the silicon carbide epitaxial substrate having the excellent effects as described above are provided at least as active layers. A silicon carbide semiconductor device is configured by including a semiconductor element included as a part. Thus, it is possible to obtain a silicon carbide semiconductor device capable of suppressing the expansion of stacking faults generated in the epitaxial layer and suppressing the deterioration of the device characteristics to a level that does not cause a practical problem while maintaining the device breakdown voltage and the on-resistance. it can.

The present invention relates to a carbonization silicon semiconductor device.

An object of the present invention is to suppress the extension of the stacking faults that occur in the epitaxial layer, the device breakdown voltage and while maintaining the on-resistance, the device characteristics practical problem and carbonization silicon semiconductor that can be suppressed enough not to degrade the Is to provide a device.

A silicon carbide semiconductor device of the present invention includes a silicon carbide substrate, a first epitaxial layer formed by epitaxial growth on a surface on one side in the thickness direction of the silicon carbide substrate, and a surface on one side in the thickness direction of the first epitaxial layer. a second epitaxial layer formed by epitaxial growth, comprising the second third silicon carbide epitaxial substrate Ru and an epitaxial layer formed by epitaxial growth in one side in the thickness direction of the surface of the epitaxial layer, the silicon carbide substrate, The impurity concentration is 3 × 10 ¹⁸ cm ⁻³ or more, the off-angle exceeds 0 °, the layer thickness of the first epitaxial layer is T1 [μm], and the layer thickness of the second epitaxial layer is T2 [ μm], the thickness of the third epitaxial layer is T3 [μm], and the thickness of the first epitaxial layer is When the impurity concentration is N1 [cm ⁻³ ], the impurity concentration of the second epitaxial layer is N2 [cm ⁻³ ], and the impurity concentration of the third epitaxial layer is N3 [cm ⁻³ ], N1 ≦ 1 × 10 ¹⁶ cm ⁻³ , N2 ≧ 1 × 10 ¹⁷ cm ⁻³ , N3 ≦ 1 × 10 ¹⁶ cm ⁻³ , T2 ≧ 0.01 μm, T1 × T2 × N2 ≦ 2.684 × 10 ¹⁷ The first epitaxial layer includes a stacking fault, and the stacking fault has a step flow direction that is an epitaxial growth direction of the first epitaxial layer when the off angle of the silicon carbide substrate is θ [°]. width is a length dimension in the direction parallel to the direction obtained by projecting the substrate one side in the thickness direction of the surface of, T1 / tan (θ) [ μm] Ri der less; with the stacking fault Serial first epitaxial layer, said second epitaxial layer and said third epitaxial layer, and wherein the Rukoto includes a semiconductor device comprising as at least part of the active layer.

According to the silicon carbide semiconductor device of the present invention, expansion of stacking faults that are generated starting from dislocations and misfit dislocations contained in the first epitaxial layer can be suppressed by the second epitaxial layer. As a result, the deterioration of the device characteristics due to the expansion of the stacking fault can be suppressed to a level that does not cause a practical problem, so that the reliability of the device can be greatly improved.

From the above, to suppress the extension of the stacking faults that occur in epitaxial layer, while maintaining the device breakdown voltage and on-resistance, the silicon carbide epitaxial substrate can be suppressed to the extent that no practical problem deterioration of device characteristics Can be provided.

The first epitaxial layer of silicon carbide epitaxial substrate having excellent effects on the following, a second epitaxial layer and the third epitaxial layer, includes a semiconductor device comprising as at least part of the active layer, the silicon carbide semiconductor device Composed. Thus, it is possible to obtain a silicon carbide semiconductor device capable of suppressing the expansion of stacking faults generated in the epitaxial layer and suppressing the deterioration of the device characteristics to a level that does not cause a practical problem while maintaining the device breakdown voltage and the on-resistance. it can.

Claims (8)

A silicon carbide substrate (10);
A first epitaxial layer (20) formed by epitaxial growth on the surface on one side in the thickness direction of the silicon carbide substrate (10);
A second epitaxial layer (21) formed by epitaxial growth on the surface of one side in the thickness direction of the first epitaxial layer (20);
A third epitaxial layer (22) formed by epitaxial growth on the surface of one side in the thickness direction of the second epitaxial layer (21),
The silicon carbide substrate (10) has an impurity concentration of 3 × 10 ¹⁸ cm ⁻³ or more and an off-angle exceeding 0 °,
The layer thickness of the first epitaxial layer (20) is T1 [μm], the layer thickness of the second epitaxial layer (21) is T2 [μm], and the layer thickness of the third epitaxial layer (22) is T3 [μm]. μm], the impurity concentration of the first epitaxial layer (20) is N1 [cm ⁻³ ], the impurity concentration of the second epitaxial layer (21) is N2 [cm ⁻³ ], and the third epitaxial layer ( 22) When the impurity concentration is N3 [cm ⁻³ ],
N1 ≦ 1 × 10 ¹⁶ cm ⁻³ ,
N2 ≧ 1 × 10 ¹⁷ cm ⁻³ ,
N3 ≦ 1 × 10 ¹⁶ cm ⁻³ ,
T2 ≧ 0.01 μm,
T1 × T2 × N2 ≦ 2.684 × 10 ¹⁷
A silicon carbide epitaxial substrate characterized by satisfying the relationship: The layer thickness T1 [μm] of the first epitaxial layer (20) and the layer thickness T3 [μm] of the third epitaxial layer (22) are:
2 × T1 ≦ T3
The silicon carbide epitaxial substrate according to claim 1, wherein the relationship is satisfied. The layer thickness T1 [μm] of the first epitaxial layer (20), the layer thickness T2 [μm] of the second epitaxial layer (21), and the impurity concentration N2 [cm ⁻³ ] of the second epitaxial layer (21) are: ,
T1 × T2 × N2 ≦ 1.610 × 10 ¹⁷
The silicon carbide epitaxial substrate according to claim 1, wherein the relationship is satisfied.   The said 1st epitaxial layer (20), the said 2nd epitaxial layer (21), and the said 3rd epitaxial layer (22) contain any one of nitrogen, aluminum, phosphorus, and boron as an impurity. 2. The silicon carbide epitaxial substrate according to 1. A buffer layer (25) formed by epitaxial growth between the silicon carbide substrate (10) and the first epitaxial layer (20);
The impurity concentration of the buffer layer (25) is not more than the impurity concentration of the silicon carbide substrate (10) and not less than the impurity concentration of the first epitaxial layer (20). Silicon carbide epitaxial substrate. A buffer layer (25) formed by epitaxial growth between the silicon carbide substrate (10) and the first epitaxial layer (20);
The impurity concentration of the buffer layer (25) is less than or equal to the impurity concentration of the silicon carbide substrate (10) and less than the impurity concentration of the first epitaxial layer (20). Silicon carbide epitaxial substrate. The first epitaxial layer (20) includes a stacking fault (30),
The stacking fault (30) has a step flow direction that is an epitaxial growth direction of the first epitaxial layer (20) when the off-angle of the silicon carbide substrate (10) is θ [°]. ) In the direction parallel to the direction obtained by projecting on the surface on one side in the thickness direction, the width (L) is T1 / tan (θ) [μm] or less. The silicon carbide epitaxial substrate according to claim 1.   The silicon carbide epitaxial substrate (10) according to any one of claims 1 to 7, wherein the first epitaxial layer (20), the second epitaxial layer (21) and the third epitaxial layer (22) are activated. A silicon carbide semiconductor device comprising a semiconductor element (100, 100A, 200, 200A, 210) included as at least a part of a layer (11, 110).