JP2016213473A - Silicon carbide semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To inhibit diffusion of stacking fault of a drift layer of a silicon carbide semiconductor device.SOLUTION: A silicon carbide semiconductor device comprises a silicon carbide semiconductor substrate, a first conductivity type first silicon carbide semiconductor layer and a second conductivity type second silicon carbide semiconductor on the first silicon carbide semiconductor layer, which has the conductivity type opposite to the first conductivity type. The first silicon carbide semiconductor layer includes a high-concentration layer having a donor impurity at a concentration of ND and an acceptor impurity at a concentration of NA, in which a sum of ND and NA is equal to or higher than 1×10cmand an absolute value of a difference between ND and NA is not less than 5×10cmand not more than 1×10cm. And the first silicon carbide semiconductor layer functions as a drift layer of the semiconductor device.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a silicon carbide semiconductor device.

  Silicon carbide (SiC), which is a wide band gap semiconductor, has a higher dielectric breakdown resistance than silicon (Si) materials. For this reason, when silicon carbide is used as the material of the epitaxial substrate used for manufacturing a semiconductor device, the impurity concentration of the substrate can be increased while avoiding a significant decrease in breakdown voltage compared to the case where a silicon substrate is used. The electrical resistance can be reduced. By reducing the resistance, the power loss of the semiconductor device, particularly the power device, can be reduced.

  As a technique intended to reduce resistance in a SiC epitaxial wafer, for example, there is a technique described in Patent Document 1 below. According to this technique, when the SiC epitaxial layer is p-type, when the p-type impurity contained in the SiC epitaxial layer is “element A” and the n-type impurity is “element D”, the element A having the concentration of element D is used. The ratio to the concentration is greater than 0.33 and less than 1.0. When the SiC epitaxial layer is n-type, the ratio of the concentration of element D to the concentration of element A is greater than 0.40 and less than 0.95.

  On the other hand, in silicon carbide crystals, there are generally some line defects such as basal plane dislocations or misfit dislocations occurring at the interface between the single crystal substrate and the epitaxial layer. When the silicon carbide semiconductor device has a pn diode structure, a stacking fault that is a plane defect starts from the line defect due to recombination energy generated when minority carriers injected into the pn diode structure recombine with majority carriers. Expand. The stacking fault starts from a line defect and extends in a triangular shape or in a strip shape along the base surface and in a direction perpendicular to the step flow direction during epitaxial growth (for example, see Non-Patent Document 1 below). Since the stacking fault acts as a resistance that inhibits the flow of current, the forward voltage (so-called Vf) increases as the stacking fault increases. This causes deterioration of device characteristics.

  It has been reported that the forward voltage shift due to stacking faults occurs similarly in SiC-MOSFET (Metal Oxide Semiconductor Field Effect Transistor) (for example, see Non-Patent Document 2 below). The MOSFET structure has a parasitic diode called a body diode between a source and a drain. Therefore, if a forward current continues to flow through the body diode, the same deterioration as described above is caused. For this reason, when a body diode is used as a free-wheeling diode of a switching circuit using a MOSFET, fluctuations in MOSFET characteristics, for example, a forward voltage shift, are caused, thereby causing a problem in reliability. Although this problem can be alleviated by providing a Schottky barrier diode having a relatively low forward voltage as a freewheeling diode, it is difficult to completely prevent the forward current from flowing through the parasitic diode. The forward voltage shift is proportional to the sum of the areas of the extended stacking faults included in the chip in which the MOSFET is formed. Therefore, in order to suppress the shift of the forward voltage, it is necessary to suppress this area.

JP 2014-185048 A

Journal of ELECTRONIC MATERIALS, Vol. 39, no. 6, pp. 684-687 (2010) “Electrical and Optical Properties of Stacking Faults in 4H-SiC Devices” IEEE ELECTRON DEVICE LETTERS, Vol. 28, no. 7, pp. 587-589 (2007) "A New Degradation Mechanism in High-Voltage SiC Power MOSFETs"

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a silicon carbide epitaxial substrate and a silicon carbide semiconductor device capable of suppressing expansion of stacking faults while avoiding a significant decrease in breakdown voltage. Is to provide.

A silicon carbide semiconductor device of the present invention includes a silicon carbide semiconductor substrate, a first conductivity type first silicon carbide semiconductor layer, and a second conductivity type opposite to the first conductivity type on the first silicon carbide semiconductor layer. A first silicon carbide semiconductor layer including a high-concentration layer having a donor impurity having a concentration of ND and an acceptor impurity having a concentration of NA, and the sum of ND and NA is 1 × 10 ¹⁸ cm ⁻³ or more, the absolute value of the difference between ND and NA is 5 × 10 ¹⁴ cm ⁻³ or more and 1 × 10 ¹⁷ cm ⁻³ or less, and the first silicon carbide semiconductor layer is the drift layer of the semiconductor device Work as.

  According to the silicon carbide semiconductor device of the present invention, expansion of stacking faults can be suppressed while avoiding a significant decrease in breakdown voltage.

1 is a plan view schematically showing a configuration of a silicon carbide semiconductor device in a first embodiment of the present invention. FIG. 2 is a schematic partial sectional view taken along line II-II in FIG. 1. 1 is a cross sectional view schematically showing a configuration of a silicon carbide epitaxial substrate in a first embodiment of the present invention. It is a fragmentary sectional view which shows typically the example of the extension of the stacking fault in the silicon carbide epitaxial substrate of the silicon carbide semiconductor device of the comparative example whose characteristic deteriorated by use. It is a fragmentary sectional view which shows schematically the structure of the silicon carbide semiconductor device in Embodiment 2 of this invention. It is sectional drawing which shows schematically the structure of the silicon carbide epitaxial substrate in Embodiment 2 of this invention. It is the 1st modification of FIG. It is the 2nd modification of FIG. It is the 3rd modification of FIG. FIG. 11 is a cross sectional view schematically showing a configuration of a silicon carbide epitaxial substrate used for observation of stacking faults in a silicon carbide semiconductor device in a third embodiment of the present invention. It is a transmission electron micrograph which shows the observation result of the stacking fault of the silicon carbide semiconductor device in Embodiment 3 of this invention. FIG. 10 is a partial cross sectional view schematically showing a configuration of a silicon carbide semiconductor device in a fourth embodiment of the present invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<Embodiment 1>
(Configuration of silicon carbide semiconductor device)
Referring to FIGS. 1 and 2, MOSFET 100 (silicon carbide semiconductor device) of the present embodiment includes an epitaxial substrate 51P, a gate insulating film 12, a gate electrode 13, a source electrode 2, a drain electrode 32, And a gate pad 1. Epitaxial substrate 51P has n type. Epitaxial substrate 51P is made of silicon carbide. Epitaxial substrate 51P has a hexagonal crystal structure, for example, polytype 4H.

Epitaxial substrate 51P includes single crystal substrate 10 (silicon carbide single crystal substrate) and epitaxial layer 41P. Single crystal substrate 10 has an impurity concentration of 3 × 10 ¹⁸ cm ⁻³ or more. The plane orientation of one surface (upper surface in FIG. 2) of single crystal substrate 10 has an off angle exceeding 0 ° with respect to the c-plane ({0001} plane). The c surface may be either a carbon surface (C surface) or a silicon surface (Si surface). The off angle is preferably 1 ° or more and 8 ° or less. Epitaxial layer 41 </ b> P is provided on the upper surface of single crystal substrate 10. The plane orientation of the main surface (upper surface in FIG. 2) of epitaxial layer 41P is the same as the plane orientation of the upper surface of single crystal substrate 10.

  Epitaxial layer 41 </ b> P has drift layer 11, well region 14 (impurity region), source region 15, and well contact region 16. A cell structure in which cells each having a MOS structure are periodically arranged is formed on one surface (upper surface in FIG. 2) of the epitaxial layer 41P. Each cell is connected in parallel to form a transistor array structure. Hereinafter, a more detailed structure will be described.

  Drift layer 11 is provided on the upper surface of single crystal substrate 10. The drift layer 11 is a region (active layer) in which a depletion layer from the pn junction can extend when the rated voltage is applied between the source / drain electrodes during device operation, and is thereby applied to the MOSFET 100 in the off state. The voltage between the source / drain electrodes (between the main electrodes) is maintained. In the present embodiment, a region where a depletion layer from the pn junction between the drift layer 11 and the p-type well region 14 can extend is called a drift layer 11. The thickness of drift layer 11 (the vertical dimension in FIG. 2) is determined according to the breakdown voltage and characteristics required for the power device, and is, for example, about 3 μm to 200 μm.

  In the present embodiment, the drift layer 11 is composed of the high concentration layer 21. In other words, the drift layer 11 includes only the high concentration layer 21.

The high concentration layer 21 includes a donor impurity having a concentration ND and an acceptor impurity having a concentration NA. The sum of ND and NA is 1 × 10 ¹⁸ cm ⁻³ or more. Since carrier generation by the donor impurity and carrier generation by the acceptor impurity cancel each other, the effective impurity concentration of the high concentration layer 21 corresponds to the absolute value of the difference between ND and NA. The absolute value of the difference between ND and NA is 5 × 10 ¹⁴ cm ⁻³ or more and 1 × 10 ¹⁷ cm ⁻³ or less, and preferably 1 × 10 ¹⁶ cm ⁻³ or less. The specific value of the absolute value can be selected according to the breakdown voltage and characteristics required for the MOSFET 100. In the present embodiment, when ND> NA is satisfied, the drift layer 11, that is, the high concentration layer 21 has an n-type. Therefore, MOSFET 100 is an n-channel type. Thereby, MOSFET100 can utilize an electron with high mobility as a carrier.

As the donor impurity, one or more kinds of atoms of nitrogen (N), phosphorus (P), arsenic (As), and antimony (Sb) can be used. As the acceptor impurity, one or more kinds of atoms of aluminum (Al), boron (B), gallium (Ga), and indium (In) can be used. For example, N atoms of 6 × 10 ¹⁷ cm ⁻³ as donor impurities and Al atoms of 5.5 × 10 ¹⁷ cm ⁻³ as acceptor impurities are both added to the high concentration layer 21. In this case, the total impurity concentration is 1.15 × 10 ¹⁸ cm ⁻³ and the effective impurity concentration is 5 × 10 ¹⁶ cm ⁻³ . Thus, in the high concentration layer 21, the total impurity concentration is increased while the effective impurity concentration is decreased. In the high-concentration layer 21, NA, NB, and the difference between NA and NB do not necessarily have to be uniform, and may vary, for example, in the thickness direction (vertical direction in FIG. 2). .

  Well region 14 is provided on drift layer 11 and is separated from single crystal substrate 10 by drift layer 11. The well region 14 has a p-type that is the conductivity type opposite to the n-type that is the conductivity type of the drift layer 11. Drift layer 11 which is a first silicon carbide semiconductor layer of the first conductivity type (here n-type) and a well which is a second silicon carbide semiconductor region of the second conductivity type (here p-type) which is the opposite conductivity type. The region 14 is joined to thereby provide a pn diode structure including the drift layer 11 and the well region 14.

  The well contact region 16 is provided on the well region 14. The well contact region 16 has the same conductivity type as that of the well region 14 and has an impurity concentration and a carrier concentration higher than the impurity concentration of the well region 14. Thereby, the well contact region 16 is connected to the source electrode 2 with a small contact resistance. The source region 15 is provided on the well region 14 and is separated from the drift layer 11 by the well region 14. The source region 15 has n-type similarly to the drift layer 11. The source region 15 is formed so as to surround the well contact region 16 in a plan view, for example.

  The gate insulating film 12 covers the well region 14 between the source region 15 and the drift layer 11 on the epitaxial layer 41P. The gate insulating film 12 has an opening that exposes the well contact region 16 and a part of the source region 15. In FIG. 2, the gate insulating film 12 is formed between one source region 15 and the other source region 15 of two adjacent cells. The gate electrode 13 is provided on the gate insulating film 12 and faces the well region 14 with the gate insulating film 12 interposed therebetween. The interlayer insulating film 17 covers the gate electrode 13. The source electrode 2 is provided on the epitaxial layer 41P on which the gate insulating film 12, the gate electrode 13, and the interlayer insulating film 17 are provided. Source electrode 2 is in contact with source region 15 and well contact region 16, and is separated from gate electrode 13 by interlayer insulating film 17. The source electrode 2 has a portion exposed on one surface (upper surface in FIG. 2) of the MOSFET 100, and thereby functions as a source pad. Source electrode 2 is, for example, an aluminum electrode. Drain electrode 32 is provided on the other surface (lower surface in FIG. 2) of single crystal substrate 10. The gate pad 1 is connected to the gate electrode 13 and is exposed on one surface of the MOSFET 100.

(Configuration and manufacturing method of silicon carbide epitaxial substrate)
Next, epitaxial substrate 51 (silicon carbide epitaxial substrate) used for manufacturing MOSFET 100 will be described with reference to FIG. Epitaxial substrate 51 includes single crystal substrate 10 and epitaxial layer 41. Epitaxial layer 41 is provided on single crystal substrate 10. The epitaxial layer 41 is configured by the high concentration layer 21 described above. In other words, in the present embodiment, the epitaxial layer 41 includes only the high concentration layer 21. When manufacturing the MOSFET 100 (FIG. 2) from the epitaxial substrate 51 (FIG. 3), the epitaxial layer 41P is formed from the epitaxial layer 41 by selective ion implantation using an implantation mask. A part of the epitaxial layer 41, that is, the high concentration layer 21 is used as the drift layer 11 of the MOSFET 100 as it is.

  Next, a manufacturing method of the epitaxial substrate 51, that is, a method of forming the epitaxial layer 41 on the single crystal substrate 10 will be described. Epitaxial layer 41 is formed on single crystal substrate 10 using a CVD (Chemical Vapor Deposition) method. In the following specific description, the case where N atoms and Al atoms are used as the donor impurity and the acceptor impurity will be described, but the types of impurities are not limited to these.

  First, the single crystal substrate 10 is placed in a reaction furnace and heated from 1400 ° C. to 1800 ° C. Next, by introducing a process gas, epitaxial growth of silicon carbide on single crystal substrate 10 is performed. The growth rate is about 3 μm / h to 100 μm / h. The reactor pressure is about 1 kPa to 30 kPa.

As the process gas, a carrier gas mixed with a source gas and a dopant gas is used. For example, hydrogen (H ₂ ) is used as the carrier gas, and the raw material gas includes a silicon-containing gas typified by silane (SiH ₄ ) and disilane (Si ₂ H ₆ ), propane (C ₃ H ₈ ), and A carbon-containing gas typified by methane (CH ₄ ) is used. The ratio of C atoms and Si atoms in the source gas, that is, the C / Si ratio, is set to 0.5 to 1.5.

In order to form the high-concentration layer 21 as the epitaxial layer 41, as a dopant gas, nitrogen (N ₂ ) gas for adding N atoms as donor impurities and Al atoms as acceptor impurities are added. A gas containing Al atoms is used at the same time. The gas containing Al atoms is obtained, for example, by bubbling trimethylaluminum (TMAl) with hydrogen as a carrier gas. A halide-containing gas may be used to improve the growth rate. The flow rate of each gas is preferably precisely controlled by a mass flow controller so that a high concentration layer 21 having a desired C / Si ratio and impurity concentration can be obtained.

  In order to make the thickness and impurity concentration of the epitaxial layer 41 more uniform in the epitaxial layer 41, it is desirable that the single crystal substrate 10 be rotated, revolved or revolved during film formation. Further, the gas flow rate may be adjusted during growth in order to obtain a desired impurity concentration distribution in the thickness direction. Such adjustment can be performed for the purpose of responding to changes in the furnace environment even when a uniform impurity concentration is required in the thickness direction.

(Comparative example)
FIG. 4 partially shows an epitaxial substrate 51Z included in the MOSFET of the comparative example. Epitaxial substrate 51Z has single crystal substrate 10 and epitaxial layer 41Z. The drift layer 11Z of the MOSFET of the comparative example is configured by a low concentration layer 20 having a total impurity concentration of less than 1 × 10 ¹⁸ cm ⁻³ . Although the donor is added to the low concentration layer 20, no acceptor is added. Therefore, the total impurity concentration and the effective impurity concentration of the low concentration layer 20 are both substantially the same as the donor impurity concentration. Since the low concentration layer 20 constitutes the drift layer 11Z, it needs to have a relatively low effective impurity concentration. This means that the total impurity concentration is also relatively low.

  In the silicon carbide crystal of the epitaxial layer 41Z, there are generally some line defects such as basal plane dislocations or misfit dislocations generated at the interface between the single crystal substrate 10 and the epitaxial layer 41Z. Due to the recombination energy generated when minority carriers injected into the parasitic pn diode structure of the MOSFET recombine with the majority carriers, the stacking fault 30 which is a surface defect expands starting from the line defect. The stacking fault 30 starts from a line defect as a starting point, extends along a basal plane perpendicular to the c-axis CA, and extends along a direction perpendicular to the step flow direction during epitaxial growth into a triangular shape or a strip shape. Therefore, as long as the off-angle of epitaxial substrate 51Z is not zero, stacking fault 30 extends to the surface of epitaxial layer 41Z, and extends to the interface with single crystal substrate 10 when the starting point is located inside epitaxial layer 41Z. Since the stacking fault 30 acts as a resistance that inhibits the flow of current, the forward voltage increases as the stacking fault 30 increases. This causes deterioration of the characteristics of the MOSFET.

(effect)
According to MOSFET 100 (FIG. 2) of the present embodiment, expansion of stacking faults in drift layer 11 is suppressed by high concentration layer 21 having a total impurity concentration of 1 × 10 ¹⁸ cm ⁻³ or more. Further, since the high concentration layer 21 has an effective impurity concentration of 5 × 10 ¹⁴ cm ⁻³ or more, the high concentration layer 21 is 1 × 10 ¹⁷ cm while imparting sufficient conductivity as the drift layer 11 to the high concentration layer 21. By having an effective impurity concentration of ⁻³ or less, preferably 1 × 10 ¹⁶ cm ⁻³ or less, a significant decrease in breakdown voltage can be avoided. From the above, the expansion of stacking faults can be suppressed while avoiding a significant decrease in breakdown voltage.

  Note that “suppressing extension of stacking faults” means, for example, preventing extension of stacking faults caused by recombination of majority carriers and minority carriers when forward current flows through the body diode of MOSFET 100, or This means that the further expansion of the stacking fault is prevented by stopping the expansion.

If a silicon carbide semiconductor device is manufactured using epitaxial substrate 51 (FIG. 3) of the present embodiment, the extension of stacking faults in epitaxial layer 41 is a high concentration layer having a total impurity concentration of 1 × 10 ¹⁸ cm ⁻³ or more. 21 is suppressed. In addition, since the high concentration layer 21 has an effective impurity concentration of 5 × 10 ¹⁴ cm ⁻³ or more, the high concentration layer 21 is 1 × 10 ¹⁷ while imparting conductivity highly useful as an impurity layer to the high concentration layer 21. By having an effective impurity concentration of cm ⁻³ or less, preferably 1 × 10 ¹⁶ cm ⁻³ or less, a significant decrease in breakdown voltage can be avoided. From the above, the expansion of stacking faults can be suppressed while avoiding a significant decrease in breakdown voltage.

  In the present embodiment, the case where the epitaxial layer 41 (drift layer 11) is directly formed on the single crystal substrate 10 has been described. However, the single crystal substrate 10, the epitaxial layer 41 (drift layer 11), The buffer layer 23 of the same first conductivity type as that of the epitaxial layer 41 may be provided. In the silicon carbide semiconductor device provided with the buffer layer 23 as well as without the buffer layer 23, expansion of stacking faults can be suppressed while avoiding a significant decrease in breakdown voltage.

<Embodiment 2>
(Configuration of silicon carbide semiconductor device)
Referring to FIG. 5, MOSFET 110 (silicon carbide semiconductor device) of the present embodiment has an epitaxial substrate 52P instead of epitaxial substrate 51P (FIG. 2) of the first embodiment. The epitaxial substrate 52P has an epitaxial layer 42P instead of the epitaxial layer 41P. Epitaxial layer 42P has low concentration layers 20A and 20B and high concentration layer 21 located between them. Each of the low concentration layers 20A and 20B has thicknesses TA and TB. In the present embodiment, approximately TA = TB is satisfied. High concentration layer 21 extends in parallel with single crystal substrate 10. In other words, the epitaxial layer 42P has a laminated film that is laminated on the single crystal substrate 10 in the order of the low concentration layer 20A / the high concentration layer 21 / the low concentration layer 20B.

  In epitaxial layer 42P, drift layer 11 includes low concentration layers 20A and 20B in addition to high concentration layer 21. Therefore, each of the low concentration layers 20 </ b> A and 20 </ b> B has an n-type like the high concentration layer 21. The well region 14 is provided away from the high concentration layer 21 on the low concentration layer 20B.

  In the thickness direction of the drift layer 11, the proportion of the high concentration layer 21 is preferably smaller than the proportion of the low concentration layers 20 </ b> A and 20 </ b> B. The thickness of the high concentration layer 21 is preferably 1 μm or less.

Each of the low concentration layers 20A and 20B has a total impurity concentration of less than 1 × 10 ¹⁸ cm ⁻³ . Therefore, the total impurity concentration of each of the low concentration layers 20A and 20B is lower than the total impurity concentration of the high concentration layer 21. Each of the low concentration layers 20A and 20B preferably has an effective impurity concentration of 5 × 10 ¹⁴ cm ⁻³ or more and 1 × 10 ¹⁶ cm ⁻³ or less. The low concentration layers 20A and 20B preferably have only the former of the donor impurity and the acceptor impurity. In this case, the effective impurity concentration is substantially the same as the concentration of the donor impurity. Note that unlike the present embodiment, when the low concentration layer is p-type, the low concentration layer preferably has only the latter of the donor impurity and the acceptor impurity. In this case, the effective impurity concentration is substantially equal to the acceptor impurity concentration. Are the same.

  The specific values of the thickness of the drift layer 11, the thickness and effective impurity concentration of the low concentration layers 20 </ b> A and 20 </ b> B, the thickness of the high concentration layer 21, the effective impurity concentration and the total impurity concentration are described in the MOSFET 110. It can be set according to the required pressure resistance and characteristics. Depending on the required breakdown voltage and characteristics, the impurity concentration does not need to be constant in the low concentration layers 20A and 20B. For example, the impurity concentration of the low concentration layer 20A may be different from the impurity concentration of the low concentration layer 20B. Further, the impurity concentration may be changed in at least one of the low concentration layers 20A and 20B, and this change may be a continuous change.

  Since the configuration other than the above is substantially the same as the configuration of MOSFET 100 of the first embodiment, the same or corresponding elements are denoted by the same reference numerals, and description thereof will not be repeated.

(Configuration and manufacturing method of silicon carbide epitaxial substrate)
Next, epitaxial substrate 52 (silicon carbide epitaxial substrate) used for manufacturing MOSFET 110 will be described with reference to FIG. Epitaxial substrate 52 includes single crystal substrate 10 and epitaxial layer 42. Epitaxial layer 42 is provided on single crystal substrate 10. The epitaxial layer 42 is composed of the high-concentration layer 21 and the low-concentration layers 20A and 20B described above. When manufacturing the MOSFET 110 (FIG. 5) from the epitaxial substrate 52 (FIG. 6), the epitaxial layer 42P is formed from the epitaxial layer 42 by selective ion implantation using an implantation mask. A part of the epitaxial layer 42, that is, the high concentration layer 21 and the low concentration layers 20 </ b> A and 20 </ b> B is used as the drift layer 11 of the MOSFET 110 as it is. Specifically, the high concentration layer 21 and the low concentration layer 20A are used as they are as the drift layer 11, and the low concentration layer 20B is partially used as the drift layer 11. A well region 14, a source region 15, and a well contact region 16 are formed away from the high concentration layer 21 on the surface side of the low concentration layer 20B (upper surface side in FIG. 5).

  Next, a manufacturing method of the epitaxial substrate 52, that is, a method of forming the epitaxial layer 42 on the single crystal substrate 10 will be described. In the following specific description, the case where N atoms and Al atoms are used as the donor impurity and the acceptor impurity will be described, but the types of impurities are not limited to these.

  First, the low concentration layer 20 </ b> A is formed on the single crystal substrate 10. As a formation method, almost the same method as the CVD method described in the first embodiment can be used, but the conditions of the dopant gas are different in order to suppress the total impurity amount of the low concentration layer 20A. Specifically, as a dopant gas, a gas for adding N atoms as donor impurities is used, while a gas for adding Al atoms as acceptor impurities is only a small amount compared to the first embodiment. It is not used or not used at all.

  Next, the high concentration layer 21 is formed on the low concentration layer 20A by the same method as in the first embodiment. However, in the present embodiment, since the high concentration layer 21 is a part rather than the whole epitaxial layer 42, the thickness of the high concentration layer 21 may be relatively small. In such a case, in order to control the thickness of the high concentration layer 21 more precisely, it is preferable that the growth rate of the high concentration layer 21 is made slower than the growth rate of the low concentration layer 20A.

  In order to enhance the efficiency and controllability of dopant incorporation into the high concentration layer 21, a C / Si ratio different from that during the growth of the low concentration layers 20A and 20B may be used. Specifically, N atom incorporation efficiency is increased by lowering the C / Si ratio, and Al atom incorporation efficiency is increased by increasing the C / Si ratio. Therefore, by adjusting the C / Si ratio according to a desired impurity concentration, the high concentration layer 21 can be grown more efficiently and with high controllability. For the same purpose, at least one of a growth temperature and a growth pressure different from those during the growth of the low concentration layers 20A and 20B may be used. In this case, it is preferable that the supply of the source gas is once stopped after the formation of the low concentration layer 20A. After the supply of the source gas is stopped, the growth of the high concentration layer 21 is started after the change to the desired temperature and pressure is completed. This is to prevent unintentional fluctuations in the growth rate and impurity concentration due to the unstable growth temperature and pressure.

  Further, in the manufacturing process, the high concentration layer may be epitaxially grown thicker than the thickness of the high concentration layer 21 in the finally formed epitaxial substrate 52. After the supply of the source gas is stopped when the thick and high concentration layer grows in this way, the final thickness is adjusted by reducing the thickness of the high concentration layer 21 by etching. This etching can be performed by etching with hydrogen gas. The introduction of the hydrogen gas as the etching gas can be performed by continuing the introduction of the hydrogen gas as the carrier gas in forming the high concentration layer 21 even after the supply of the raw material gas is stopped.

  Next, the low concentration layer 20B is formed on the high concentration layer 21 by a method substantially similar to the formation of the low concentration layer 20A. Thus, the epitaxial substrate 52 is obtained.

  Note that, instead of the above method, after an epitaxial layer is formed on the single crystal substrate 10 using a low-concentration film forming condition, an acceptor impurity is added by ion implantation, so that a part of the epitaxial layer is formed at a high concentration. The layer 21 may be used, and the other portions may be the low concentration layers 20A and 20B. Further, the entire epitaxial layer may be made into the high concentration layer 21 by ion implantation, and in this case, the same thing as the epitaxial substrate 51 (FIG. 3) of the first embodiment is obtained.

(effect)
Also with the silicon carbide semiconductor device of the present embodiment, the expansion of stacking faults can be suppressed while avoiding a significant decrease in breakdown voltage, as in the first embodiment. In order to more reliably suppress the expansion of stacking faults, the thickness of the high concentration layer 21 is preferably 10 nm or more.

  Furthermore, according to the present embodiment, by providing the low concentration layers 20A and 20B (FIG. 6), it is possible to reduce the thickness of the high concentration layer 21, which is relatively difficult to form. Therefore, the epitaxial substrate 52 can be manufactured more easily. When the thickness of the high concentration layer 21 is 1 μm or less, the robustness of epitaxial growth of the high concentration layer 21 is particularly high.

Further, by providing the low concentration layers 20A and 20B, even if the effective impurity concentration of the high concentration layer 21 is high to some extent (for example, a value close to 1 × 10 ¹⁷ cm ⁻³ ), it is possible to suppress a decrease in breakdown voltage caused by the high concentration layer 21. . This is because the decrease in breakdown voltage can be suppressed by suppressing the effective impurity concentration of the low-concentration layers 20A and 20B constituting the drift layer 11 together with the high-concentration layer 21 to 1 × 10 ¹⁶ cm ⁻³ or less. is there. The greater the proportion of the low concentration layers 20A and 20B in the drift layer 11, the smaller the influence of the high concentration layer 21 on the breakdown voltage.

Moreover, when the effective impurity concentration of the low concentration layers 20A and 20B is 5 × 10 ¹⁴ cm ⁻³ or more, sufficient conductivity as the drift layer 11 can be imparted to the low concentration layers 20A and 20B. When the effective impurity concentration of the low-concentration layers 20A and 20B is 1 × 10 ¹⁶ cm ⁻³ or less, a significant decrease in breakdown voltage can be avoided.

  When the low concentration layers 20A and 20B have only donor impurities, the total impurity concentration of the low concentration layers 20A and 20B can be minimized under the condition of a predetermined effective impurity concentration. In this case, the low-concentration layers 20A and 20B can be formed more easily because the total impurity concentration is suppressed and the addition of acceptor impurities is unnecessary.

(Modification)
A modification of the epitaxial substrate 52 (FIG. 6) will be described below.

  Referring to FIG. 7, epitaxial layer 42 a of epitaxial substrate 52 a (silicon carbide epitaxial substrate) satisfies thickness TB> TA, and thereby, near the interface between epitaxial layer 42 a and single crystal substrate 10. The generated stacking fault can be more effectively suppressed. More specifically, the expansion can be stopped at an early stage before the stacking fault grows greatly. Conversely, TA> TB may be satisfied, whereby the stacking faults that occur near the surface of the epitaxial layer 42a (the upper surface in FIG. 7) can be more effectively suppressed.

  Referring to FIG. 8, in epitaxial layer 42 b of epitaxial substrate 52 b (silicon carbide epitaxial substrate), high concentration layer 21 is provided directly on single crystal substrate 10, and low concentration layer 20 is provided on high concentration layer 21. Provided. Thereby, stacking faults generated near the interface between the epitaxial layer 42b and the single crystal substrate 10 can be particularly effectively suppressed. Conversely, the low concentration layer 20 is provided directly on the single crystal substrate 10, the high concentration layer 21 is provided on the low concentration layer 20, and the high concentration layer 21 constitutes the surface of the epitaxial layer 42b (upper surface in FIG. 8). May be. Thereby, the stacking fault generated near the surface of the epitaxial layer 42b can be particularly effectively suppressed.

  Referring to FIG. 9, epitaxial layer 42 c of epitaxial substrate 52 c (silicon carbide epitaxial substrate) has a plurality of low concentration layers 20 and a plurality of high concentration layers 21. The low concentration layer 20 and the high concentration layer 21 are alternately stacked on the single crystal substrate 10. In this case, the stacking fault can be effectively suppressed regardless of the position of the starting point of the stacking fault in the epitaxial layer 42c. Although three high concentration layers 21 are shown in the drawing, the number of high concentration layers 21 is not particularly limited, and may be two layers or four layers, for example. As the number of layers increases, stacking faults can be more effectively suppressed. The position of the high concentration layer 21 in the epitaxial layer 42c is not particularly limited.

<Embodiment 3>
In the present invention, as the donor impurity, one or more kinds of atoms of nitrogen (N), phosphorus (P), arsenic (As), and antimony (Sb) can be used, and as the acceptor impurity, Any one or a plurality of atoms of aluminum (Al), boron (B), gallium (Ga), and indium (In) can be used, but nitrogen and gallium, and further nitrogen compared to the combination of nitrogen and aluminum The combination of boron and boron can obtain the effect of the present invention more. Further, the combination of phosphorus and gallium, and further the combination of phosphorus and boron can obtain the effects of the present invention more than the combination of phosphorus and aluminum. In this embodiment mode, a combination of nitrogen and gallium or a combination of phosphorus and boron is selected as a combination of a donor impurity and an acceptor impurity. This is a feature of the present embodiment, and the other points are the same as in the first and second embodiments.

  For example, the donor level of nitrogen is caused by the introduction site of the nitrogen atom, but it is about 0.04 meV to 0.08 meV, and the donor level of phosphorus is 0.05 meV to 0.93 meV, which is almost equivalent ionization energy. It can be said that the level. On the other hand, the ionization energies of acceptor impurities such as aluminum, gallium, and boron are approximately 0.2 meV, 0.3 meV, and 0.6 meV, respectively, and vary greatly depending on the impurity element. Generally, the ionization rate of impurities depends on the ionization energy of each impurity, and the ionization rate tends to be smaller as the ionization energy is higher. That is, the lower the ionization rate, the higher the concentration of impurities with the same carrier concentration. Therefore, the effect of the present invention can be more effectively obtained by using gallium and boron as one of the acceptor impurity combinations than aluminum. In addition, since the ionization energy varies depending on the impurity concentration and temperature, the effects of the present invention can be obtained more effectively by selecting the impurity element in consideration of them.

(Experimental result)
While investigating a method for suppressing the extension of stacking faults due to the application of forward current to the pn diode structure, the inventors have studied a phenomenon in which the extension of stacking faults is hindered by a layer having a high impurity concentration. I found it. Hereinafter, the experimental results will be described.

Referring to FIG. 10, single crystal substrate 10 made of polytype 4H silicon carbide was prepared. A buffer layer 23 was formed on the single crystal substrate 10. An epitaxial layer 42 </ b> X was formed on the buffer layer 23. Thereby, epitaxial substrate 52X made of silicon carbide was produced. The buffer layer 23 is for reducing crystal defects in the epitaxial layer 42X. Specifically, the epitaxial layer 42X was formed by forming the low concentration layer 20A, the high concentration layer 22 and the low concentration layer 20B in this order. The thickness of each of the low concentration layers 20A and 20B was approximately the same. The thickness of the high concentration layer 22 was 20 nm. The doping to the high-concentration layer 22 was performed only with nitrogen atoms at a concentration of 5 × 10 ¹⁸ cm ⁻³ .

Using the epitaxial substrate 52X obtained as described above, a MOSFET having a MOS structure substantially similar to the MOSFET 100 (FIG. 2) and the MOSFET 110 (FIG. 5) was produced. The MOSFET was energized at 100 A / cm ² for 10 minutes.

  Referring to FIG. 11, after the energization, a cross section of epitaxial substrate 52X was observed by a TEM (Transmission Electron Microscope) method. On this cross section, the expansion of stacking faults was observed from the position of arrow S to the position of arrow E. Further, it was determined by SIMS (Secondary Ion Mass Spectrometry) measurement that the high concentration layer 22 is located in a broken line portion in the figure. The arrow E is located on the high concentration layer 22, which is considered to indicate that the extension of stacking faults via the position of the arrow S stopped when reaching the high concentration layer 22. .

  Furthermore, the present inventors investigated in detail the relationship between the area of stacking faults and the rate of characteristic deterioration of the SiC-MOSFET. As a result, it was confirmed that the smaller the area of the stacking fault, the smaller the characteristic deterioration.

  From the above results, it has been experimentally found that by providing a layer having a high impurity concentration in the drift layer, expansion of stacking faults can be suppressed, thereby reducing deterioration of MOSFET characteristics. The present inventors theoretically consider that this effect is caused by the following mechanism.

  The recombination energy between minority carriers and majority carriers in the pn diode structure causes a basal plane dislocation and misfit dislocation slip phenomenon, thereby extending stacking faults. However, in a crystal having a high impurity concentration, the dislocation is fixed by the interaction between the strain field created by the dislocation and the strain field created by the impurity doped at a high concentration. Therefore, more energy is required to cause dislocation slip in a crystal with a high impurity concentration. If this energy is larger than the recombination energy, stacking faults are suppressed. That is, the factor that suppresses the expansion of stacking faults is that the impurity concentration in the crystal is high, and a general dopant can be used as the type of impurity. Specifically, nitrogen, phosphorus, arsenic, antimony, aluminum, boron, gallium, indium, or the like can be used.

  In the above experiment, only nitrogen as an impurity was added to the high concentration layer 22 at a high concentration. In this case, since a high concentration of nitrogen acts as a donor to increase the carrier concentration, a decrease in breakdown voltage becomes a problem. Therefore, in the high concentration layer 21 of each of the above embodiments, not only a donor impurity but also an acceptor impurity is added as an impurity, thereby causing carrier compensation. As a result, the substantial carrier concentration is reduced, so that a decrease in breakdown voltage is suppressed.

Moreover, in the said experiment, although the thickness of the high concentration layer 22 which is a layer for suppressing the expansion | extension of a stacking fault was 20 nm, sufficient effect will be seen if it is 10 nm or more. Further in the above experiment was a total impurity concentration of the high concentration layer 22 and 5 × ¹⁰ 18 ^{cm -3,} sufficient effect is observed if 1 × ¹⁰ 18 ^{cm -3} or higher.

<Embodiment 4>
In each of the above embodiments, MOSFETs have been mainly described as examples of the silicon carbide semiconductor device. However, a high concentration layer may be included in the drift layer of the PiN diode. Referring to FIG. 12, PiN diode 200 of the present embodiment has an epitaxial substrate 53 </ b> P, an anode electrode 18, and a cathode electrode 19. Epitaxial substrate 53P is made of silicon carbide. The epitaxial substrate 51P has a hexagonal crystal structure, for example, polytype 4H.

Epitaxial substrate 51P has single crystal substrate 10 and epitaxial layer 43P. Single crystal substrate 10 has n-type conductivity. Single crystal substrate 10 has an impurity concentration of 3 × 10 ¹⁸ cm ⁻³ or more. The plane orientation of one surface (upper surface in FIG. 2) of single crystal substrate 10 has an off angle exceeding 0 ° with respect to the c-plane ({0001} plane). The c surface may be either a carbon surface (C surface) or a silicon surface (Si surface). The off angle is preferably 1 ° or more and 8 ° or less. Epitaxial layer 43 </ b> P is provided on the upper surface of single crystal substrate 10. The plane orientation of the main surface (upper surface in FIG. 2) of epitaxial layer 43P is the same as the plane orientation of the upper surface of single crystal substrate 10.

  Epitaxial layer 43 </ b> P has first silicon carbide layer 24, second silicon carbide layer 25, third silicon carbide layer 26, and termination region 18.

  First silicon carbide layer 24 (first silicon carbide semiconductor layer) is provided by epitaxial growth on single crystal substrate 10, has an n-type conductivity type, and functions as drift layer 11 during device operation. The thickness of the drift layer 11 is determined according to the breakdown voltage and characteristics required for the power device, and is, for example, about 3 μm to 200 μm.

  The termination region 18 is a region formed on the surface of the drift layer 11. The termination region 18 alleviates electric field concentration that occurs at the end of the anode electrode 33.

  Second silicon carbide layer 25 (second silicon carbide semiconductor layer) has p-type conductivity and is a layer that is epitaxially grown in a region sandwiched between termination region 18 on drift layer 11. A drift layer 11 which is a first silicon carbide semiconductor layer of a first conductivity type (here n-type) and a second silicon carbide semiconductor region which is a second conductivity type (here p-type) which is the opposite conductivity type. The two semiconductor layers 25 are joined together, whereby a pn diode structure including the drift layer 11 and the second semiconductor layer 25 is provided.

  Third silicon carbide layer 26 has a p-type conductivity and is a layer epitaxially grown on second silicon carbide layer 25. The third silicon carbide layer 26 forms a low ohmic contact with the anode electrode 18.

  The anode electrode 33 is an electrode formed on the third silicon carbide layer 26. The cathode electrode 34 is an electrode formed on the back surface of the single crystal substrate 10.

  The semiconductor device according to this embodiment has a pn junction, and becomes a rectifying semiconductor in which a forward current flows when the anode side is a positive electrode and the cathode side is a negative electrode. The pn junction is formed of the first silicon carbide layer 24, that is, the drift layer 11 and the second silicon carbide layer.

According to the present embodiment, first silicon carbide layer 24, that is, drift layer 11 includes high concentration layer 21. The high concentration layer 21 includes a donor impurity having a concentration ND and an acceptor impurity having a concentration NA. The sum of ND and NA is 1 × 10 ¹⁸ cm ⁻³ or more. The details of the effect of the high concentration layer 21, the manufacturing method, and the like are the same as those described in the above embodiments, and are omitted here.

  In the present embodiment, the high concentration layer 21 may be provided on the entire drift layer 11 or may be provided on a part of the drift layer 11. When the high concentration layer 21 is provided on the entire drift layer 11, the entire drift layer becomes the high concentration layer 21 and the high concentration layer 21 becomes the drift layer 11 as in the MOSFET 100 described in the first embodiment of the present invention. Is provided in a part of the drift layer 11 as the MOSFET 110 described in the second embodiment of the present invention. When the high concentration layer 21 is provided in a part of the drift layer 11, the thickness of the high concentration layer 21 is preferably 10 nm or more as described in the second embodiment of the present invention. Further, the position and the number of layers in which the high-concentration layer 21 is provided are not limited to one as described in the second embodiment of the present invention and the modifications thereof, and an arbitrary number of sheets can be set at an arbitrary position. May be provided.

  In the description of the present embodiment, an n-type PiN diode has been described as an example. However, the p-type and n-type may be interchanged to form a p-type PiN diode.

(Appendix)
The relationship between n-type and p-type in each of the above embodiments may be interchanged, and in that case, the relationship between donor impurities and acceptor impurities is also interchanged. In that case, a p-channel type semiconductor device and a p-type silicon carbide epitaxial substrate used for manufacturing the same are obtained. Depending on the application, the conductivity type of the silicon carbide single crystal substrate and the conductivity type of the high concentration layer may be different from each other. Further, depending on the application, the conductivity type of the high concentration layer and the conductivity type of the low concentration layer may be different from each other. Although the MOSFET has been mainly described as the semiconductor device, a MISFET (Metal Insulator Semiconductor Field Effect Transistor) other than the MOSFET can be obtained by using a material other than an oxide as the gate insulating film. Further, the semiconductor device only needs to have a pn diode structure, and may be, for example, an IGBT (Insulated Gate Bipolar Transistor). In order to obtain the IGBT, for example, a collector region having a conductivity type opposite to that of the single crystal substrate 10 is provided between the single crystal substrate 10 and the drain electrode 32 in the MOSFET 100 (FIG. 2) or the MOSFET 110 (FIG. 5). Alternatively, the single crystal substrate 10 itself may be the collector region by reversing the conductivity type of the single crystal substrate 10. In this case, the source electrode 2 and the drain electrode 32 function as an emitter electrode and a collector electrode, respectively.

  The present invention can be freely combined with each embodiment within the scope of the invention. In addition, any component in each embodiment can be changed or omitted as appropriate.

  DESCRIPTION OF SYMBOLS 1 Gate pad, 2 source electrode, 10 single crystal substrate (silicon carbide single crystal substrate), 11 drift layer, 12 gate insulating film, 13 gate electrode, 14 well region, 15 source region, 16 well contact region, 17 interlayer insulating film , 18 termination region, 20, 20A, 20B low concentration layer, 21 high concentration layer, 23 buffer layer, 24 first silicon carbide layer, 25 second silicon carbide layer, 26 third silicon carbide layer, 30 stacking fault, 32 drain Electrode, 33 anode electrode, 34 cathode electrode, 41, 41P, 42, 42a to 42c, 42P, 43P epitaxial layer, 51, 52, 52a to 52c epitaxial substrate (silicon carbide epitaxial substrate), 51P, 52P, 53P epitaxial substrate, 100, 110 MOSFET (silicon carbide semiconductor device), 2 0 PiN diode (silicon carbide semiconductor device).

Claims (15)

A silicon carbide semiconductor device,
A silicon carbide semiconductor substrate, a first conductivity type first silicon carbide semiconductor layer, and a second conductivity type second silicon carbide semiconductor having a conductivity type opposite to the first conductivity type on the first silicon carbide semiconductor layer. With areas,
The first silicon carbide semiconductor layer includes a high-concentration layer having a donor impurity of a concentration ND and an acceptor impurity of a concentration NA, and the sum of ND and NA is 1 × 10 ¹⁸ cm ⁻³ or more. The absolute value of the difference is 5 × 10 ¹⁴ cm ⁻³ or more and 1 × 10 ¹⁷ cm ⁻³ or less,
The silicon carbide semiconductor device, wherein the first silicon carbide semiconductor layer functions as a drift layer of the semiconductor device.   The silicon carbide semiconductor device according to claim 1, further comprising a buffer layer made of silicon carbide between the silicon carbide single crystal substrate and the drift layer.   The silicon carbide semiconductor device according to claim 1, wherein the silicon carbide semiconductor device is any one of a MOSFET, an IGBT, and a PiN diode.   The donor impurity includes at least one atom selected from the group consisting of nitrogen, phosphorus, arsenic, and antimony, and the acceptor impurity is at least one type selected from the group consisting of aluminum, boron, gallium, and indium. The silicon carbide semiconductor device according to claim 1, comprising an atom.   The silicon carbide semiconductor device according to claim 4, wherein the acceptor impurity is aluminum and the donor impurity is nitrogen.   The silicon carbide semiconductor device according to claim 4, wherein the acceptor impurity is gallium and the donor impurity is nitrogen.   The silicon carbide semiconductor device according to claim 4, wherein the acceptor impurity is boron and the donor impurity is nitrogen.   The silicon carbide semiconductor device according to claim 4, wherein the acceptor impurity is gallium and the donor impurity is phosphorus.   The silicon carbide semiconductor device according to claim 4, wherein the acceptor impurity is boron and the donor impurity is phosphorus. The silicon carbide semiconductor device according to claim 1, wherein the absolute value is 1 × 10 ¹⁶ cm ⁻³ or less.   The silicon carbide semiconductor device according to claim 1, wherein said high concentration layer has a thickness of 10 nm or more.   The silicon carbide semiconductor device according to claim 11, wherein the thickness of the high concentration layer is 1 μm or less. The first silicon carbide semiconductor layer includes the high concentration layer and a low concentration layer of a first conductivity type having a total impurity concentration of less than 1 × 10 ¹⁸ cm ^−3. The silicon carbide semiconductor device according to item. ^{14. The} silicon carbide semiconductor device according to claim 13, wherein the low concentration layer has a concentration of 5 × 10 ¹⁴ cm ⁻³ or more and 1 × 10 ¹⁶ cm ⁻³ or less and includes only one of a donor impurity and an acceptor impurity.   The silicon carbide semiconductor device according to claim 1, wherein said first silicon carbide semiconductor layer has an n-type conductivity type.