JP2005285955A - Semiconductor device having active high resistive semiconductor layer and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an active high resistive semiconductor layer at a high resistance and in a short lifetime. <P>SOLUTION: In a semiconductor device comprising the active high resistive semiconductor layer and its manufacturing method, in a p-type and n-type impurity of an impurity density or above in which a carrier lifetime is reduced compared with the time when an impurity density is not included in a semiconductor layer, or the impurity density is minute, two kinds or more of p-type and n-type impurities are mixedly present by a substantially equivalent amount for each, or the active high resistive semiconductor layer 10 contains still another impurity materializing a strain compensation between lattices to be entirely or selectively disposed on one face or both faces of a semiconductor substrate 1. Further, the active high resistive semiconductor layer can be adaptable to a diode structure, a transistor structure, a thyristor structure and an insulating gate type device structure. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having an active high-resistance semiconductor layer (active intrinsic layer: AIL) that has a high resistance and can shorten a carrier life, and a manufacturing method thereof.

  Static induction thyristors and static induction transistors have been developed and put into practical use as power semiconductor elements. In order to increase the speed, lifetime control is performed by means such as electron beam irradiation or heavy metal doping. In a high-resistance semiconductor layer to which no impurity is added, the lifetime is generally longer as the crystal is complete. Therefore, in a device having a high-resistance semiconductor layer such as an electrostatic induction thyristor or an electrostatic induction transistor, a semiconductor The characteristic control by the element structure becomes easy, and there is an advantage that the performance determined by the original device structure can be obtained.

When an impurity is added to such a high-resistance semiconductor layer, the lattice constant of the impurity atoms and the lattice constant of the high-resistance semiconductor layer are different, so that distortion occurs in the crystal, and dislocations such as misfit dislocations are likely to occur.

  The examination of the lattice strain generated by the difference in impurity density between the semiconductor substrate and the growth layer has been performed by the vapor phase growth method of Si by Nishizawa et al. (Non-patent Document 1).

Since Si atoms are regularly arranged in Si single crystals, when an impurity added to Si is replaced by Si atoms, atoms having a smaller covalent bond radius than Si, such as boron (B) and phosphorus (P), are adjacent to each other. Since the distance to the Si atoms to be performed is smaller than the distance between Si, the lattice constant of the crystal in which B and P are added to a high impurity density is smaller than the lattice constant of the intrinsic Si single crystal. The opposite is true when an impurity having a larger covalent bond radius than Si atoms, such as arsenic (As) and antimony (Sb), is added. FIGS. 26 and 27 show typical atomic covalent bond radii by polling (Non-Patent Document 2).
Junichi Nishizawa, Ken Terasaki, Kunihiro Yaki, Nobuo Miyamoto (J. Nishizawa, T. Terasaki, K. yagi, and N. Miyamoto), “Perfect Crystal Growth of Silicon by Vapor Phase Epitaxy ), "J. Electrochemical Society, Vol. 122, No. 5, p. 664-P. 669, 1975 Linus Pauling, “The Nature Of Chemical Bonding”, Cornell University Press, 1960, p.205.

  The object of the present invention is to reduce the lifetime by forming p-type and n-type impurities at substantially the same location with a high impurity density, and at the same time, with the compensation effect of the p-type and n-type impurities, the resistance is substantially high. Another object of the present invention is to provide an active high resistance layer (AIL) capable of shortening the carrier life.

  In addition, in a diode, transistor, thyristor, or insulated gate type device, a semiconductor having an active high-resistance semiconductor layer that can realize high-speed switching, low loss, and low on-resistance by including such an AIL layer. It is in providing an apparatus and its manufacturing method.

  In order to achieve the above object, the first feature of the present invention is that two types of p-type and n-type impurities, which are more than impurities whose carrier lifetime in the semiconductor layer is lower than when no impurity is contained in the semiconductor layer, are used. The gist of the present invention is a semiconductor device having active high-resistance semiconductor layers mixed in substantially equal amounts.

  The second feature of the present invention is that two or more types of p-type and n-type impurities having a density lower than the carrier lifetime in the semiconductor layer are mixed in almost equal amounts compared to when the impurity density in the semiconductor layer is very small. The gist is that the semiconductor device has an active high-resistance semiconductor layer.

  According to a third aspect of the present invention, there is provided an active high-resistance semiconductor layer including a step of forming an active high-resistance semiconductor layer on the entire surface of a semiconductor substrate by epitaxial growth using an epitaxial growth gas containing p-type impurities and n-type impurities. The gist of the present invention is a method for manufacturing a semiconductor device.

  According to a fourth aspect of the present invention, there is provided an active high-resistance semiconductor layer including a step of selectively forming an active high-resistance semiconductor layer by epitaxial growth on a semiconductor substrate using an epitaxial growth gas containing a p-type impurity and an n-type impurity. The gist of the present invention is a method of manufacturing a semiconductor device having

  The fifth feature of the present invention is that (a) an ion implantation step in which equal amounts of p-type impurities and n-type impurities are formed on the entire surface of the semiconductor substrate, and (b) ion implantation formed on the entire surface of the semiconductor substrate after the ion implantation step. The present invention is summarized as a method for manufacturing a semiconductor device having an active high-resistance semiconductor layer including a heat treatment step for increasing the resistance of the layer.

  The sixth feature of the present invention is that (a) an ion implantation step for selectively forming equal amounts of p-type impurities and n-type impurities in a semiconductor substrate; and (b) after the ion implantation step, selectively formed on the semiconductor substrate. The present invention is summarized as a method for manufacturing a semiconductor device having an active high-resistance semiconductor layer including a heat treatment step for increasing the resistance of the ion-implanted layer.

  The seventh feature of the present invention is that (a) a high-resistance semiconductor layer, (b) an anode region disposed on the main surface of the high-resistance semiconductor layer, and (c) disposed on another main surface of the high-resistance semiconductor layer. A semiconductor device having an active high-resistance semiconductor layer comprising: an active cathode region; and (d) an active high-resistance semiconductor layer disposed between the high-resistance semiconductor layer and the anode region. And

  The eighth feature of the present invention is that (a) a high resistance semiconductor layer, (b) an anode region repeatedly disposed on the main surface of the high resistance semiconductor layer, (c) an anode electrode in contact with the anode region, (D) a cathode region disposed on another main surface of the high-resistance semiconductor layer; (e) a cathode electrode in contact with the cathode region; (f) an anode region and an anode electrode disposed in the anode region disposed repeatedly. A semiconductor device having an active high-resistance semiconductor layer comprising: an anode short-circuit region that is short-circuited by the semiconductor device; and (g) an active high-resistance semiconductor layer disposed between the high-resistance semiconductor layer and the anode short-circuit region. It is a summary.

  The ninth feature of the present invention is that (a) a high-resistance semiconductor layer, (b) an anode region disposed on the main surface of the high-resistance semiconductor layer and having a channel structure, and (c) another high-resistance semiconductor layer A semiconductor device having an active high-resistance semiconductor layer comprising: a cathode region disposed on a main surface; and (d) an active high-resistance semiconductor layer disposed in a channel structure in the vicinity of the high-resistance semiconductor layer and the anode region. It is a summary.

  The tenth feature of the present invention is that (a) a high-resistance semiconductor layer, (b) a gate region repeatedly disposed on the main surface of the high-resistance semiconductor layer, (c) a gate electrode in contact with the gate region, (D) a drain region disposed on another main surface of the high-resistance semiconductor layer; (e) a drain electrode in contact with the drain region; (f) a source region disposed between the repeatedly disposed gate regions; G) a source electrode disposed adjacent to the gate electrode on the main surface and in contact with the source region; and (h) an active high resistance semiconductor layer disposed between the high resistance semiconductor layer and the source region. The gist of the invention is a semiconductor device having an active high-resistance semiconductor layer.

  The eleventh feature of the present invention is: (a) a high-resistance semiconductor layer, (b) a gate region having a channel structure, which is repeatedly arranged near the main surface of the high-resistance semiconductor layer, and (c) a contact with the gate region. A gate electrode, (d) an anode region disposed on another main surface of the high-resistance semiconductor layer, (e) an anode electrode in contact with the anode region, and (f) a gate region disposed repeatedly. (G) a cathode electrode disposed adjacent to the gate electrode on the main surface and in contact with the cathode region; and (h) an active layer disposed between the high-resistance semiconductor layer and the anode region. The present invention is summarized as a semiconductor device having an active high-resistance semiconductor layer including an active high-resistance semiconductor layer.

  The twelfth feature of the present invention is that (a) an n base layer, (b) a p base region having a channel structure and repeatedly disposed in the vicinity of the main surface of the n base layer, and (c) in the p base layer Between the n emitter region arranged near the main surface, (d) the emitter electrode which is in contact with the n emitter region and short-circuited with the p base region and arranged on the main surface, and (e) the p base region arranged repeatedly An active high-resistance semiconductor layer disposed in the channel structure, (f) the active high-resistance semiconductor layer and a gate insulating layer disposed on the adjacent p base region and n emitter region, and (g) a gate insulating layer A gate electrode disposed above, (h) a p collector region disposed on another main surface of the n base layer, (li) a collector electrode in contact with the p collector region, (nu) an n base layer and p Between the collector region And summarized in that a semiconductor device having an active high-resistance semiconductor layer and a separate active high-resistance semiconductor layer.

  According to the present invention, the p-type and n-type impurities are formed at substantially the same location with a high impurity density, thereby reducing the lifetime, and at the same time, the high-resistance layer is substantially formed by the compensation effect of the p-type and n-type impurities. An active high resistance layer (AIL) can be realized. Furthermore, in a diode, transistor, thyristor, or insulated gate type device having such an AIL layer, high-speed switching, low loss, and low on-resistance can be realized. That is, a semiconductor device having such a high-performance active high-resistance semiconductor layer and a method for manufacturing the same can be provided.

  Next, first to fifth embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  Further, the following first to fifth embodiments exemplify apparatuses and methods for embodying the technical idea of the present invention, and the technical idea of the present invention is the component parts. The material, shape, structure, arrangement, etc. are not specified below. The technical idea of the present invention can be variously modified within the scope of the claims.

(First embodiment)
[AIL layer]
FIG. 1 is a diagram illustrating the principle of the present invention. (A) Resistance in a p-type semiconductor, relationship between lifetime and impurity density, (b) Resistance in an n-type semiconductor, relationship between lifetime and impurity density, (C) Represents the relationship between the resistance, lifetime and impurity density in the AIL layer of the present invention. As shown in FIG. 1A, in the relationship between resistance, lifetime and impurity density in a p-type semiconductor, the resistivity R decreases as the impurity density increases, and the lifetime of electrons τ _e , The lifetime τ _h also tends to decrease. Similarly, in the relationship between resistance, lifetime and impurity density in an n-type semiconductor, as shown in FIG. 1B, the resistivity R decreases as the impurity density increases, and the lifetime of electrons τ _e , The lifetime τ _{h of} holes also tends to decrease. On the other hand, in the active high-resistance semiconductor layer (AIL layer) of the present invention, as shown in FIG. 1C, the concentration compensation effect of n-type impurities and p-type impurities against the increase in impurity density. Therefore, the resistivity R hardly changes and remains almost constant. On the other hand, the lifetime τ _{e of} electrons and the lifetime τ _{h of} holes show a tendency to decrease as the impurity density increases.

  The semiconductor device having the active high-resistance semiconductor layer according to the first embodiment of the present invention has a p-type or higher impurity that lowers the carrier lifetime in the semiconductor layer compared to when no impurity is contained in the semiconductor layer. This is a semiconductor device having an active high-resistance semiconductor layer in which two or more types of n-type impurities are mixed in substantially equal amounts.

  In addition, an active high-resistance semiconductor layer in which two or more types of p-type and n-type impurities having a density lower than the carrier lifetime in the semiconductor layer are mixed in almost equal amounts compared to when the impurity density in the semiconductor layer is very small. You may have.

  The active high-resistance semiconductor layer may further include another impurity that realizes strain compensation between lattices other than the p-type impurity and the n-type impurity.

  Further, the active high-resistance semiconductor layer may be disposed on the entire surface of one surface of the substrate of the semiconductor device.

  The active high-resistance semiconductor layer may be selectively disposed locally on one side of the substrate of the semiconductor device.

  Further, the active high resistance semiconductor layer may be disposed on the entire surface of both sides of the substrate of the semiconductor device.

  The active high resistance semiconductor layer may be selectively disposed locally on both sides of the substrate of the semiconductor device.

The active high resistance semiconductor layer may be formed of any one of Si, SiC, diamond, or GaN.

  As described above, in the active high resistance semiconductor layer according to the first embodiment of the present invention, the lifetime can be reduced while maintaining the high resistance.

(Lifetime simulation)
The lifetime equation according to the Shockley Reed Hall (SRH) model can be expressed as equation (1).

τ _dop (N _i ) = τ _min + (τ _max −τ _min ) / [1+ (N _i / N _ref ) ^γ ] (1)
Here, τ _max is the maximum lifetime, and is set to 1 × 10 ⁻⁵ (sec) for electrons and 3 × 10 ⁻⁶ (sec) for holes. τ _min is the minimum lifetime, and is set to 0 (sec) for both electrons and holes. N _ref is the reference impurity density, and was set to 1 × 10 ¹⁶ (cm ⁻³ ) for both electrons and holes. _Ni is the impurity density of the active high-resistance semiconductor layer. The value of γ was set to 1. Based on the above results, the lifetime τ _e of electrons and the lifetime τ _{h of} holes in the active high-resistance semiconductor layer are expressed by equations (2) and (3), respectively.

τ _e = 1 × 10 ⁻⁵ / [1+ (N _i / 1 × 10 ¹⁶ )] (2)
τ _e = 3 × 10 ⁻⁶ / [1+ (N _i / 1 × 10 ¹⁶ )] (3)
FIG. 2 shows the relationship between the lifetime and the impurity density in the AIL layer of the present invention obtained from the equations (2) and (3) when the impurity density of the n-type substrate is 10 ¹³ cm ⁻³ .

FIG. 3 shows the relationship between the lifetime, impurity density, and substrate thickness in the AIL layer of the present invention. As the impurities, P and B are assumed, and the thickness of the substrate is changed in the range of 0 to 200 μm. As apparent from FIGS. 2 and 3, in the AIL layer according to the first embodiment of the present invention, both the electron lifetime τ _e and the hole lifetime τ _{h have} an impurity density of 10 ¹⁵ cm ^{−. When it is 3} or more, it shows a decreasing trend. Further, when the substrate thickness is 100 μm or less, both the electron lifetime τ _e and the hole lifetime τ _h tend to decrease. In FIG. 3, the impurity density distribution of B and P is also shown, but since the impurity density of the n-type substrate is 10 ¹³ cm ⁻³ ,
When the substrate thickness is 100 μm or more, it is almost constant.

(Comparative example)
FIG. 4 shows the relationship between lifetime and impurity density in the comparative example of the present invention, and FIG. 5 shows the relationship between lifetime, impurity density and substrate thickness in the comparative example of the present invention. In the comparative example, it is assumed that the impurity density of the n-type substrate is 10 ¹³ cm ⁻³ and the case of inclined junction is used. In the comparative example of the present invention, the tendency that the lifetime decreases as the impurity density increases is the same as that of the AIL layer according to the first embodiment of the present invention. However, as is apparent from FIG. As shown in FIGS. 1 (a) and 1 (b), the resistivity tends to decrease as the impurity density increases, as shown in FIGS. 1 (a) and 1 (b). .

(AIL layer forming method 1)
FIG. 6 is an explanatory diagram of a method for forming an AIL layer according to the first embodiment of the present invention.

(A) First, as shown in FIG. 6A, a substrate is prepared from the high-resistance semiconductor layer 1. The distribution of resistivity R is as shown in FIG.

(B) Next, as shown in FIG. 6B, P ions are implanted as impurity atoms into the surface of the high resistance semiconductor layer 1 to form the ion implanted layer 2. Due to the impurity addition of P, the resistivity in the ion implantation layer 2 tends to decrease as shown in FIG.

(C) Next, as shown in FIG. 6C, B is ion-implanted to form the ion-implanted layer 3. Due to the impurity addition of B, the resistivity in the ion implantation layer 3 tends to decrease as shown in FIG.

(D) Next, as shown in FIG. 6D, high-temperature heat treatment is performed in a very short time by flash lamp annealing or the like to form the active high-resistance semiconductor layer 10.

In the ion-implanted layers 2 and 3 where B and P are substantially at the same place, the resistance is increased due to the effect of compensating the impurity density by forming the ion-implanted layers 2 and 3 with substantially the same impurity density. A shallow junction can be formed while suppressing the spread of the diffusion layer by high-temperature and short-time annealing such as flash lamp annealing. As a result, as shown in FIG. 6H, the resistance is increased and an active high resistance semiconductor layer (AIL) 10 can be realized.

(Method 2 for forming AIL layer)
FIG. 7 is an explanatory diagram of another method for forming an AIL layer according to the first embodiment of the present invention.

(A) First, as shown in FIG. 7A, a substrate is prepared from the high-resistance semiconductor layer 1. The distribution of resistivity R is as shown in FIG.

(B) Next, simultaneous epitaxial growth of p-type and n-type impurities is performed to form an n ⁺ , p ⁺ high-concentration epitaxial layer 4. For example, in the case of Si, B as p-type impurity, P, arsenic (As), and antimony (Sb) can be applied as n-type impurities. For gallium nitride (GaN), for example, magnesium (Mg) can be used as the p-type impurity, and Si can be used as the n-type impurity. For silicon carbide (SiC), for example, aluminum (Al) can be used as the p-type impurity, and nitrogen (N) can be used as the n-type impurity.

The active high resistance semiconductor layer 10 can be realized by the compensation effect of high concentration n ⁺ , p ⁺ impurities in the n ⁺ , p ⁺ high concentration epitaxial layer 4. Since the high resistance layer is formed, the distribution of the resistivity R is as shown in FIG.

Further, the p anode region 5 is formed by epitaxial growth.

(C) As a result, as shown in FIG. 7C, a pin structure laminated with the AIL layer 10 interposed therebetween is realized.

(Lattice distortion compensation)
In general, the lattice constant of a Si single crystal doped with impurities is expressed as a lattice constant relatively changed by the addition of impurities from the value of the lattice constant of a high-purity Si single crystal. That is, the lattice constant of Si in the case of doping a _d, the case of undoped and a _i, relation between a _d and a _i is expressed by equation (4).

a _d = a _i [1- (R _Si ³ (N _Si −N _i ) + R _i ³ N _i ) / R _Si ³ N _Si ] ^1/3 (4)
Here, R _Si represents the Si shared radius, R _i represents the covalent bond radius of the added impurity atoms, N _Si represents the Si atomic density, and _Ni represents the impurity density. Here, when the deviation of the lattice constant and Δa = a _i -a _d, volume change rate is expressed by the equation (5).

(a _d ³ −a _i ³ ) / a _i ³ =
[R _Si ³ (N _Si —N _i ) + R _i ³ N _i —R _Si ³ N _i ] / R _Si ³ N _Si (5)
Here, if the second-order or higher term of Δa is ignored, the relative change rate ε = Δa / a _i of the lattice constant is approximately expressed by equation (6).

ε = Δa / a _i = (1/3) · [1- (R _i / R _Si ) ³ ] (N _i / N _Si ) (6)
FIG. 28 shows the relationship between the impurity density and the lattice constant shift. In FIG. 28, the expansion of the lattice is shown in the downward direction and the contraction of the lattice is shown in the upward direction. As is apparent from FIG. 28, when both B and P are added at 10 ¹⁹ cm ^−3, a deviation from the lattice constant of high purity Si occurs by about 10 ⁻⁴ . That is, in the case of device fabrication by vapor phase growth, the lattice constant differs between the substrate to which impurities are added at a high concentration and the i layer.

  Next, the lattice distortion due to the difference in lattice constant will be described. When the x and y axes are taken in the direction parallel to the interface between the substrate and the growth layer, and the z axis is taken in the direction perpendicular to the substrate, the internal stress is expressed by equation (7).

σ _xx = σ _yy = σ
σ _yz = 0 (7)
Accordingly, the lattice strain caused by the stress expressed by the equation (7) is expressed by the following equation:
ε _xx = ε _yy = [σ / E] (1−v) = − ε
ε _zz = −2σv / E (8)
Therefore, if the equation (6) is used, the internal stress is given by the equation (9).

σ _xx = σ _yy = βN _i E / (1-v)
σ _zz = βN _i E / 2v (9)
β = (1/3) · [1- (R _i / R _Si ) ³ ] / N _Si
When the difference in lattice constant between the substrate doped with a high concentration impurity and the growth layer close to intrinsic conduction becomes significant, the semiconductor layer is bent due to internal stress.

  The curvature of the curvature of the semiconductor layer due to the difference in lattice constant is given by equation (10) by using the misfit coefficient f = Δa / a.

1 / R = 6t _r t _S f / (t _r + t _S ) ³ (10)
Here, R represents the radius of curvature, t _r is the thickness of the growth layer, t _S is the thickness of the substrate.

For example, the radius of curvature in the case of an i layer having a thickness of 300 μm, a diameter of 75 mm, and a thickness of 10 μm on a semiconductor substrate to which P is added as an impurity is 1 × 10 ¹⁹ cm ⁻³ is 1.47 × 10 ⁴ cm, For example, when placed on a horizontal plane, the outer periphery rises about 5 μm. When a substrate to which B is added under the same conditions is used, the outer periphery of about 16 μm is lifted. When the difference in lattice constant further increases and the internal stress expressed by the formula (9) exceeds the critical value for breaking the bonds of the atoms in the crystal, misfit dislocations are introduced to alleviate the internal stress. Will be. In the case of the p-type, the misfit coefficient f = | Δa / a | = 3.83 × 10 ⁻⁵ in the i layer on the B-added 1 × 10 ¹⁹ cm ⁻³ semiconductor substrate. Usually, in a heterojunction of a compound semiconductor such as GaAs, misfit dislocation is observed when f is 1 × 10 ⁻³ or more.

Also in the active high resistance semiconductor layer according to the first embodiment of the present invention, the generation of internal stress is reduced by performing lattice strain compensation, and the high impurity density compensation effect of n-type and p-type is high. It is possible to realize a high resistance layer whose lifetime is reduced by resistance.

(Second Embodiment)
[Diode structure]
FIG. 8A shows a schematic cross-sectional structure of a diode including an AIL layer according to the second embodiment of the present invention. FIG. 8B shows a schematic cross-sectional structure of a diode including an AIL layer according to Modification 1 of the second embodiment of the present invention. Further, FIG. 8C shows a resistance distribution corresponding to FIGS. 8A and 8B.

  A semiconductor device having an active high-resistance semiconductor layer according to the second embodiment of the present invention is disposed on the high-resistance semiconductor layer 1 and the anode-side main surface of the high-resistance semiconductor layer 1 as shown in FIG. P anode region 5, n cathode region 12 disposed on the cathode-side main surface, which is another main surface of high resistance semiconductor layer 1, and high resistance semiconductor layer 1 and p anode region 5. The active high resistance semiconductor layer 10 to be disposed, an anode electrode 16 in contact with the p anode region 5, and a cathode electrode 14 in contact with the n cathode region 12 are provided. FIG. 8A shows an example in which the thickness of the AIL layer 10 is Wa1, and Modification 1 in FIG. 8B shows an example of Wa2 in which the thickness of the AIL layer 10 is set to be thicker than Wa1. FIG. 8C shows a distribution of resistivity R corresponding to the structures of FIGS. 8A and 8B. It can be seen that the resistivity rapidly increases in the vicinity of the active high resistance semiconductor layer 10.

9A shows the relationship between the reverse recovery loss Pr and the forward voltage drop V _FM of the diode corresponding to FIG. 8, and FIG. 9B shows the switching voltage V, the switching current I, the on loss Pon, and the reverse recovery loss. The relationship between Pr and time is shown. As apparent from FIG. 9A, the relationship between the reverse recovery loss Pr of the diode and the forward voltage drop V _FM is in a trade-off relationship with each other. However, by changing the thickness of the AIL layer 10, the trade The off relationship has changed. AILt corresponds to the case where the AIL layer 10 is relatively thin, and AILw corresponds to the case where the AIL layer 10 is relatively thick. It can be seen that the characteristics of the trade-off relationship are better when the thickness of the AIL layer 10 is thinner.

(Modification of the second embodiment)
FIG. 10A is a schematic cross-sectional structure of a diode including an AIL layer according to the second modification of the second embodiment of the present invention, and FIG. 10B is a diagram of the second embodiment of the present invention. FIG. 10C is a schematic cross-sectional structure of a diode including an AIL layer according to Modification 4 of the second embodiment of the present invention. Show.

(Modification 2)
A semiconductor device having an active high resistance semiconductor layer according to Modification 2 of the second embodiment of the present invention includes a high resistance semiconductor layer 1 and a high resistance semiconductor layer 1 as shown in FIG. A p anode region 5 disposed on the main surface, an n cathode region 12 disposed on another main surface of the high resistance semiconductor layer 1, and interposed between the high resistance semiconductor layer 1 and the p anode region 5. The active high resistance semiconductor layer 10 and the p anode region 5 have substantially the same junction depth measured from the anode side surface, and the p anode region 5 has a channel structure. Prepare.

(Modification 3)
A semiconductor device having an active high-resistance semiconductor layer according to Modification 3 of the second embodiment of the present invention includes a high-resistance semiconductor layer 1 and a high-resistance semiconductor layer 1 as shown in FIG. A p anode region 5 disposed on the main surface, an n cathode region 12 disposed on another main surface of the high resistance semiconductor layer 1, and interposed between the high resistance semiconductor layer 1 and the p anode region 5. The active high resistance semiconductor layer 10 is arranged such that the active high resistance semiconductor layer 10 has a deeper junction depth measured from the anode side surface than the p anode region 5, and the p anode region 5 has a channel structure. Prepare.

(Modification 4)
A semiconductor device having an active high-resistance semiconductor layer according to Modification 4 of the second embodiment of the present invention includes a high-resistance semiconductor layer 1 and a high-resistance semiconductor layer 1 as shown in FIG. A p anode region 5 disposed on the main surface, an n cathode region 12 disposed on another main surface of the high resistance semiconductor layer 1, and interposed between the high resistance semiconductor layer 1 and the p anode region 5. Active high resistance semiconductor layer 10, and active high resistance semiconductor layer 10 has a channel structure.

11A shows the relationship between the reverse recovery loss Pr and the impurity density of the reverse leakage current Ir in the steady state, and FIG. 11B shows the relationship between the reverse recovery loss Pr and the forward voltage drop V _FM. Is shown schematically. Although the horizontal axis of FIG. 11A is expressed by the impurity density, the same tendency appears when expressed by the reciprocal of the lifetime. In FIG. 11 (a), AIL (a) corresponds to the structure of FIG. 10 (a), AIL (b) corresponds to the structure of FIG. 10 (b), and AIL (c) corresponds to the structure of FIG. 10 (c). Corresponds to the structure. The reverse leakage current Ir in the steady state tends to decrease in the order of AIL (a), AIL (b), and AIL (c).

(Modification 5)
FIG. 12 shows a schematic cross-sectional structure of a diode including an AIL layer according to Modification 5 of the second embodiment of the present invention.

  A semiconductor device having an active high-resistance semiconductor layer according to Modification 5 of the second embodiment of the present invention has a high-resistance semiconductor layer 1 and main surfaces of the high-resistance semiconductor layer 1 as shown in FIG. Repeatedly arranged p anode region 5, anode electrode 16 in contact with p anode region 5, n cathode region 12 disposed on another main surface of high resistance semiconductor layer 1, and cathode in contact with n cathode region 12 An electrode 14, an anode short-circuit region 18 that is disposed in the p-anode region 5 that is repeatedly disposed and short-circuited by the p-anode region 5 and the anode electrode 16, and is interposed between the high-resistance semiconductor layer 1 and the anode short-circuit region 18. Active high resistance semiconductor layer 10.

  In the structure shown in FIG. 12, the anode short-circuit region 18 may of course be configured as an electrostatic induction (SI) anode short-circuit region. Between the p anode region 5 and the electrostatic induction (SI) anode short-circuit region 18, not only the active high resistance semiconductor layer 10 but also a simple high resistance layer 19 may be disposed.

  According to the semiconductor device having an active high-resistance semiconductor layer according to the fifth modification of the second embodiment of the present invention, a planar structure diode can be realized with a relatively simple configuration.

(Modification 6)
FIG. 13D shows a schematic cross-sectional structure of a diode including an AIL layer according to Modification 6 of the second embodiment of the present invention.

  A semiconductor device having an active high-resistance semiconductor layer according to Modification 6 of the second embodiment of the present invention includes a high-resistance semiconductor layer 1 and a high-resistance semiconductor layer 1 as shown in FIG. A p anode region 5 having a channel structure disposed on the main surface, an n cathode region 12 disposed on another main surface of the high resistance semiconductor layer 1, and a channel in the vicinity of the high resistance semiconductor layer 1 and the p anode region 5. And an active high resistance semiconductor layer 10 disposed in the structure.

(Structure used for simulation)
13A shows a schematic cross-sectional structure of a bulk pn diode as a comparative example of the present invention, and FIG. 13B shows the second embodiment of the present invention shown in FIG. FIG. 13 (c) shows a schematic cross-sectional structure of an electrostatic induction diode as a comparative example of the present invention, and FIG. 13 (d) shows a second cross-section of the present invention. FIG. 13E shows a schematic cross-sectional structure of an electrostatic induction diode having an AIL layer according to a sixth modification of the embodiment, and FIG. 13E shows the second embodiment of the present invention shown in FIG. 9 shows a schematic cross-sectional structure of a diode having an AIL layer corresponding to the structure according to the modified example 4 of FIG.

Further, FIG. 14, FIG. 10 the relationship between the reverse recovery loss Pr and the ON voltage _{V FM (a), (b} ), (c), a representation for the structure of (e). Compared to the bulk pn diode, improving the trade-off is seen clearly in relationship between the reverse recovery loss Pr and the ON voltage V _FM is a diode having an AIL layer according to a second embodiment of the present invention.

FIG. 15 shows the relationship between the reverse recovery loss Pr and the on-voltage V _FM for the structures of FIGS. 10 (c) and 10 (d). When comparing the electrostatic induction diode and the electrostatic induction diode having the AIL layer according to the modified example 6 of the second embodiment of the present invention, the trade-off between the reverse recovery loss Pr and the on-voltage V _FM is substantially the same. The electrostatic induction diode having an AIL layer according to the sixth modification of the second embodiment of the present invention, which is on the curve, increases the on-voltage V _FM but has a reverse recovery loss Pr of almost one digit. There is a possibility of improvement.

FIG. 16 is a diagram comparing the relationship between the reverse leakage current Ir in a steady state and the on-voltage V _FM when 2500 V is applied with respect to the structures of FIGS. 10 (a), 10 (b), and 10 (c). It is apparent that the reverse leakage current Ir is lowest in the case of the bulk pn diode, but is also kept low in the case of the diode having the AIL layer according to the second embodiment of the present invention. On the other hand, in the electrostatic induction diode structure, since there is a current component that conducts through the channel portion, a relatively large reverse leakage current Ir appears.

According to the semiconductor device having an active high-resistance semiconductor layer according to the second embodiment of the present invention, an improvement in trade-off is seen in the relationship between the reverse recovery loss Pr and the on-voltage V _FM, and the reverse of the steady state A diode in which the direction leakage current Ir is also reduced can be provided.

(Third embodiment)
[Transistor structure]
FIG. 17 shows a schematic cross-sectional structure of a transistor including an AIL layer according to the third embodiment of the present invention.

A semiconductor device having an active high-resistance semiconductor layer according to the third embodiment of the present invention is repeatedly arranged on the main surface of the high-resistance semiconductor layer 20 and the high-resistance semiconductor layer 20 as shown in FIG. p ⁺ gate region 24, gate electrode (G) 30 in contact with p ⁺ gate region 24, n ⁺ drain region 22 disposed on another main surface of high-resistance semiconductor layer 20, and contact with n ⁺ drain region Drain electrode 28, n ⁺ source region 26 disposed between p ⁺ gate regions 24 repeatedly disposed, and adjacent to gate electrode (G) 30 on the main surface and in contact with n ⁺ source region 26 Source electrode (S) 32 and active high resistance semiconductor layer 10 disposed between high resistance semiconductor layer 20 and n ⁺ source region 26.

Between the p ⁺ gate region 24 and the n ⁺ source region 26, not only the active high resistance semiconductor layer 10 but also a simple high resistance layer 34 may be disposed.

  According to the semiconductor device having the active high-resistance semiconductor layer according to the third embodiment of the present invention, a planar structure electrostatic induction transistor or bipolar transistor can be realized with a relatively simple configuration.

(Modification of the third embodiment)
FIG. 18 shows a schematic cross-sectional structure of a transistor including an AIL layer according to a modification of the third embodiment of the present invention.

A semiconductor device having an active high-resistance semiconductor layer according to a modification of the third embodiment of the present invention is repeatedly provided on the main surface of the high-resistance semiconductor layer 20 and the high-resistance semiconductor layer 20 as shown in FIG. a p ⁺ gate regions 24 which are arranged, and the gate electrode (G) 30 in contact with the arranged embedded in p ⁺ gate region 24 and p ⁺ gate region 24, to another main surface of the high-resistance semiconductor layer 20 N ⁺ drain region 22 arranged, drain electrode 28 in contact with n ⁺ drain region, n ⁺ source region 26 arranged between p ⁺ gate regions 24 repeatedly arranged, and gate electrode (G on the main surface) ) Disposed via an insulating layer 36 disposed on 30, interposed between the source electrode (S) 32 contacting the n ⁺ source region 26, and the high resistance semiconductor layer 20 and the n ⁺ source region 26. Active high deployed And a anti semiconductor layer 10.

Between the p ⁺ gate region 24 and the n ⁺ source region 26, not only the active high resistance semiconductor layer 10 but also a simple high resistance layer 34 may be disposed.

  According to the semiconductor device having the active high resistance semiconductor layer according to the modification of the third embodiment of the present invention, it is possible to realize an electrostatic induction transistor or bipolar transistor having a planar structure with a relatively simple configuration. .

(Fourth embodiment)
[Thyristor structure]
FIG. 19A shows a schematic cross-sectional structure of a thyristor including an AIL layer according to the fourth embodiment of the present invention.

A semiconductor device having an active high-resistance semiconductor layer according to the fourth embodiment of the present invention includes a high-resistance semiconductor layer 1 and a channel structure, as shown in FIG. P ⁺ gate region 24 repeatedly arranged in the vicinity of the main surface, gate electrode (G) 30 in contact with the p ⁺ gate region, p anode region 5 disposed on another main surface of high resistance semiconductor layer 1, , An anode electrode 16 in contact with the p anode region 5, an n cathode region 12 disposed between repeatedly arranged p ⁺ gate regions, a gate electrode 30 disposed on the main surface, and an n cathode region 12 A cathode electrode (K) 14 that is in contact with each other and an active high resistance semiconductor layer 10 disposed between the high resistance semiconductor layer 1 and the p anode region 5 are provided. FIG. 19B shows the distribution of resistivity R in the cross-sectional structure taken along the line II in FIG. As in the case of the diode structure shown in FIG. 8C, a rapid increase in the resistivity R is observed in the vicinity of the active high resistance semiconductor layer 10.

(Modification 1)
FIG. 19 (c) shows a schematic cross-sectional structure of a thyristor including an AIL layer according to Modification 1 of the fourth embodiment of the present invention.

A semiconductor device having an active high-resistance semiconductor layer according to Modification 1 of the fourth embodiment of the present invention includes a high-resistance semiconductor layer 1 and a channel structure as shown in FIG. The p ⁺ gate region 24 repeatedly arranged in the vicinity of the main surface of the resistance semiconductor layer 1, the gate electrode (G) 30 in contact with the p ⁺ gate region 24, and another main surface of the high resistance semiconductor layer 1 p anode region 5, anode electrode 16 in contact with p anode region 5, n cathode region 12 disposed between p ⁺ gate regions 24 repeatedly disposed, and gate electrode 30 disposed on the main surface. , An active high-resistance semiconductor layer 10 that is disposed between the high-resistance semiconductor layer 1 and the p-anode region 5 and has another channel structure. And be prepared That.

FIG. 20A shows the relationship between the turn-off energy loss E _off and the forward voltage drop V _TM . In the drawing, “large AIL1Wa” and “small AIL1Wa” correspond to the case where the thickness Wa of the active high-resistance semiconductor layer 10 is relatively thick and thin in the structure of FIG. “AIL2” corresponds to the structure of Modification 1 shown in FIG. The trade-off relationship between the turn-off energy loss E _off and the forward voltage drop V _TM becomes better as the thickness Wa of the AIL layer 10 is thinner in the structure of FIG. Further, as shown in Modification 1 with respect to the structure of FIG. 19A, when the AIL layer 10 has a channel structure, the trade-off relationship between the turn-off energy loss E _off and the forward voltage drop V _TM is Further improvements have been made.

FIG. 20B shows the relationship between the turn-on energy loss E _on and the on-voltage V _on . The trade-off relationship between the turn-on energy loss E _on and the on-voltage V _on becomes better as the thickness Wa of the AIL layer 10 is thinner in the structure of FIG. Further, as shown in Modification 1 with respect to the structure of FIG. 19A, when the AIL layer 10 has a channel structure, the trade-off relationship between the turn-on energy loss E _on and the on-voltage V _on is further improved. Has been.

(Modification 2)
FIG. 21A shows a schematic cross-sectional structure of a thyristor including an AIL layer according to Modification 2 of the fourth embodiment of the present invention.

A semiconductor device having an active high-resistance semiconductor layer according to Modification 2 of the fourth embodiment of the present invention includes a high-resistance semiconductor layer 1 and a channel structure as shown in FIG. The p ⁺ gate region 24 repeatedly arranged in the vicinity of the main surface of the resistance semiconductor layer 1, the gate electrode (G) 30 in contact with the p ⁺ gate region 24, and another main surface of the high resistance semiconductor layer 1 p anode region 5, anode electrode 16 in contact with p anode region 5, n cathode region 12 disposed between p ⁺ gate regions 24 repeatedly disposed, and gate electrode 30 disposed on the main surface. , A cathode electrode (K) 14 in contact with the n cathode region 12, an active high resistance semiconductor layer 10 disposed between the high resistance semiconductor layer 1 and the p anode region 5, and a p ⁺ gate region 24. And n cathode Further comprising a separate active high-resistance semiconductor layer 10 is disposed between the band 12.

(Modification 3)
FIG. 21B shows a schematic cross-sectional structure of a thyristor having an AIL layer according to Modification 3 of the fourth embodiment of the present invention.

A semiconductor device having an active high-resistance semiconductor layer according to Modification 3 of the fourth embodiment of the present invention includes a high-resistance semiconductor layer 1 and a channel structure as shown in FIG. The p ⁺ gate region 24 repeatedly arranged in the vicinity of the main surface of the resistance semiconductor layer 1, the gate electrode (G) 30 in contact with the p ⁺ gate region 24, and another main surface of the high resistance semiconductor layer 1 p anode region 5, anode electrode 16 in contact with p anode region 5, n cathode region 12 disposed between p ⁺ gate regions 24 repeatedly disposed, and gate electrode 30 disposed on the main surface. , An active high-resistance semiconductor layer 10 that is disposed between the high-resistance semiconductor layer 1 and the p-anode region 5 and has another channel structure. And p ⁺ Further comprising a further active high-resistance semiconductor layer 10 is disposed between the gate region 24 and the n cathode region 12.

FIG. 22 (a) shows the relationship between the accumulation time t _s and the impurity density. FIG. 22B shows the waveforms of the switching voltage V and the switching current I and the definition of each part. I _T represents the anode-cathode current waveform, V _D represents the anode-cathode voltage waveform, and I _G represents the gate current waveform during turn-off. t _s is an accumulation time, t _f is a falling time, and t _gq is a turn-off time represented by the sum of t _s and t _f .

As is apparent from FIG. 22 (a), a semiconductor having an active high-resistance semiconductor layer according to Modification 2 or Modification 3 of the fourth embodiment of the present invention shown in FIG. 21 (a) or (b). In the case of the device, the accumulation time t _s decreases as the impurity density of the active high resistance semiconductor layer 10 disposed between the p ⁺ gate region 24 and the n cathode region 12 is increased, for example, to 10 ¹⁶ cm ^−3. The tendency to do is seen.

According to the semiconductor device having the active high-resistance semiconductor layer according to the fourth embodiment of the present invention, the turn-off energy loss E _off and the forward voltage are arranged by disposing the active high-resistance semiconductor layer in the vicinity of the anode region. It is possible to provide a thyristor in which the trade-off relationship with the drop V _TM is improved and the trade-off relationship between the turn-on energy loss E _on and the on-voltage V _on is also improved. Furthermore, by placing another active high-resistance semiconductor layer in the vicinity of the cathode region, it is also possible to provide a thyristor which storage time t _s is reduced.

(Modification 4)
FIG. 23 shows a schematic cross-sectional structure of a thyristor including an AIL layer according to Modification 4 of the fourth embodiment of the present invention.

As shown in FIG. 23, a semiconductor device having an active high-resistance semiconductor layer according to Modification 4 of the fourth embodiment of the present invention includes a high-resistance semiconductor layer 1 and a channel structure, and includes a high-resistance semiconductor layer. A p ⁺ gate region 24 having a buried structure repeatedly disposed in the vicinity of one main surface, a p anode region 5 disposed on another main surface of the high-resistance semiconductor layer, and the p ⁺ gate region repeatedly disposed The n cathode region 12 is disposed, and the high resistance semiconductor layer 1 between the p ⁺ gate region 24 of the buried structure and the active high resistance semiconductor layer 10 disposed between the n cathode region 12 are provided.

  Furthermore, another active high resistance semiconductor layer 10 disposed between the high resistance semiconductor layer 1 and the p anode region 5 may be provided.

Furthermore, the active high resistance semiconductor layer 10 disposed between the high resistance semiconductor layer 1 and the p anode region 5 may have a channel structure different from that of the buried gate region 24.

(Production method)
24A and 24B are schematic views of a manufacturing process of a thyristor including an AIL layer according to Modification 4 of the fourth embodiment of the present invention. FIG. 24A is an epitaxial process, and FIG. A cathode formation process is shown.

(A) As shown in FIG. 24A, after the p ⁺ gate region 24 is formed on the high resistance semiconductor layer 1 by a diffusion process, the active high resistance semiconductor layer 10 is formed by vapor phase epitaxial growth containing P and Si. Form. Since boron (B) atoms in the p ⁺ gate region 24 jump out into the vapor phase in the process of vapor phase epitaxial growth including P and Si, vapor phase epitaxial growth including B, P and Si may be performed. . Lattice strain compensation may be taken into account when forming high impurity density n-type and p-type epitaxial growth layers. As a result, the active high-resistance semiconductor layer 10 having a high resistance and a shortened lifetime can be formed.

(B) Next, an n cathode region 12 is formed on the active high resistance semiconductor layer 10 by epitaxial growth.

According to the semiconductor device having the active high-resistance semiconductor layer according to the fourth modification of the fourth embodiment of the present invention, since the embedded gate structure is provided, it is easy to increase the breakdown voltage between the gate and the cathode, and the anode By arranging an active high-resistance semiconductor layer in the vicinity of the region, the trade-off relationship between the turn-off energy loss E _off and the forward voltage drop V _TM is improved, and the trade-off between the turn-on energy loss E _on and the on-voltage V _on. It is possible to provide a buried gate structure thyristor having an improved relationship. Furthermore, by placing another active high-resistance semiconductor layer in the vicinity of the cathode region, accumulation time t _s is reduced, it is also possible to provide a thyristor of buried gate structure.

(Fifth embodiment)
[Insulated gate device]
FIG. 25 shows a schematic structure of an insulated gate device as a semiconductor device including an AIL layer according to the fifth embodiment of the present invention. The structure shown in FIG. 25 corresponds to the configuration of an insulated gate bipolar transistor (IGBT).

As shown in FIG. 25, the semiconductor device according to the fifth embodiment of the present invention
An n base layer 40, a p ⁺ base region 44 having a channel structure and repeatedly disposed near the main surface of the n base layer 40, and an n ⁺ emitter region 46 disposed near the main surface in the p ⁺ base region 44. If, in contact with n ⁺ emitter region 46, an emitter electrode (E) 48 disposed on the main surface and short-circuited to the p ⁺ base region 44, is positioned in a channel structure between the p ⁺ base region 44 are repeatedly arranged Active high resistance semiconductor layer 10, gate insulating layer 54 disposed on active high resistance semiconductor layer 10 and adjacent p ⁺ base region 44 and n ⁺ emitter region 46, and gate insulating layer 54. A gate electrode (G) 50, a p ⁺ collector region 42 disposed on another main surface of the n base layer 40, a collector electrode 52 in contact with the p ⁺ collector region 42,
Another active high resistance semiconductor layer 10 disposed between the n base layer 40 and the p collector region is provided.

According to the semiconductor device having the active high resistance semiconductor layer according to the fifth embodiment of the present invention, the lifetime in the vicinity of the channel can be reduced by providing the active high resistance semiconductor layer 10 in the vicinity of the channel. , Turn-on loss can be reduced. Further, another active high-resistance semiconductor layer 10 disposed in the vicinity of the p ⁺ collector region 42 makes it possible to reduce the tail current at the time of turn-off and to reduce the turn-off loss. Accordingly, it is possible to provide an insulated gate device such as an IGBT with reduced loss as a whole.

(Other embodiments)
As described above, the present invention has been described according to the first to fifth embodiments. However, it should not be understood that the description and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  As described above, the present invention naturally includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.

It is a principle explanatory view of the present invention, (a) resistance in p-type semiconductor, relationship between lifetime and impurity density, (b) resistance in n-type semiconductor, relationship between lifetime and impurity density, (c) Relationship between resistance, lifetime and impurity density in the AIL layer of the present invention. Relationship between lifetime and impurity density in the AIL layer of the present invention. Relationship between lifetime, impurity density and substrate thickness in the AIL layer of the present invention. The relationship between the lifetime and impurity density in the comparative example of this invention. The relationship between the lifetime, impurity density, and board | substrate thickness in the comparative example of this invention. It is explanatory drawing of the method of forming the AIL layer based on the 1st Embodiment of this invention, Comprising: (a) A board | substrate, (b) Phosphorus ion implantation process, (c) Boron ion implantation process, (d) By heat processing process AIL layer forming step, resistance distribution corresponding to (e) and (a), resistance distribution corresponding to (f) and (b), resistance distribution corresponding to (g) and (c), corresponding to (h) and (d) Resistance distribution. It is explanatory drawing of another method of forming the AIL layer based on the 1st Embodiment of this invention, Comprising: (a) Substrate, (b) Simultaneous epitaxial process of p-type and n-type impurity, (c) AIL layer (D) Silicon epitaxial process, (e) AIL layer forming process, (d) Resistance distribution corresponding to (a), (e) Resistance distribution corresponding to (b). (A) Schematic cross-sectional structure diagram of a diode including an AIL layer according to the second embodiment of the present invention, (b) of a diode including an AIL layer according to Modification 1 of the second embodiment of the present invention. Typical cross-section diagram, (c) Resistance distribution corresponding to (a), (b). (A) Relationship between reverse recovery loss and forward voltage drop of the diode corresponding to FIG. 8, (b) Relationship between switching voltage, current, loss and time. (A) Schematic cross-sectional structure diagram of a diode including an AIL layer according to Modification 2 of the second embodiment of the present invention, (b) AIL layer according to Modification 3 of the second embodiment of the present invention (C) The typical cross-section figure of a diode provided with the AIL layer which concerns on the modification 4 of the 2nd Embodiment of this invention. (A) Relationship between reverse recovery loss Pr and impurity density of steady-state reverse leakage current Ir, (b) Relationship between reverse recovery loss Pr and forward voltage drop V _FM . The typical cross-section figure of a diode provided with the AIL layer concerning the modification 5 of the 2nd Embodiment of this invention. (A) Schematic cross-sectional structure diagram of a bulk pn diode as a comparative example of the present invention, (b) Schematic of a diode provided with an AIL layer according to the second embodiment of the present invention shown in FIG. 8 (a) Cross-sectional structure diagram, (c) A schematic cross-sectional structure diagram of an electrostatic induction diode as a comparative example of the present invention, (d) Static induction including an AIL layer according to Modification 6 of the second embodiment of the present invention. The typical cross-section figure of a diode, (e) The typical cross-section figure of a diode provided with the AIL layer which concerns on the modification 4 of the 2nd Embodiment of this invention. Relationship between reverse recovery loss and on-voltage. Relationship between reverse recovery loss and on-voltage. Relationship between reverse leakage current and on-voltage. The typical cross-section figure of the transistor provided with the AIL layer concerning a 3rd embodiment of the present invention. The typical cross-section figure of the transistor provided with the AIL layer concerning the modification of the 3rd Embodiment of this invention. (A) Schematic cross-sectional structure diagram of a thyristor provided with an AIL layer according to a fourth embodiment of the present invention, (b) resistance distribution in the layer cross-sectional direction along the line II in (a), (c) the present invention The typical cross-section figure of a thyristor provided with the AIL layer which concerns on the modification 1 of 4th Embodiment of this. (A) Relationship between turn-off energy loss and forward voltage drop, (b) Relationship between turn-on energy loss and on-voltage. (A) Schematic cross-sectional structure diagram of a thyristor including an AIL layer according to Modification 2 of the fourth embodiment of the present invention, (b) AIL layer according to Modification 3 of the fourth embodiment of the present invention. The typical cross-section figure of a thyristor provided with. (A) Relationship between accumulation time and impurity density, (b) Switching voltage waveform and switching current waveform. The typical cross-section figure of a thyristor provided with the AIL layer which concerns on the modification 4 of the 4th Embodiment of this invention. It is a schematic diagram of the manufacturing process of a thyristor provided with the AIL layer which concerns on the modification 4 of the 4th Embodiment of this invention, Comprising: (a) Epitaxial process, (b) Cathode formation process. The typical structure figure of the insulated gate device provided with the AIL layer concerning a 5th embodiment of the present invention. Typical atomic bond radius. Changes in the radius of covalent bonds by atoms. Relationship between impurity density and lattice constant deviation.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,20 ... High resistance semiconductor layer 2, 3 ... Ion implantation layer 4 ... n ^<+> , p ⁺ high density epitaxial layer 5 ... p anode region 10 ... Active high resistance semiconductor layer 12 ... n cathode region 14 ... Cathode electrode 16 ... Anode electrode 18 ... Static induction (SI) anode short-circuit region 19, 34 ... high resistance region 22 ... n ⁺ drain region 24 ... p ⁺ gate region 26 ... n ⁺ source region 28 ... drain electrode 30 ... gate electrode 32 ... source electrode 40 ... n base layer 42 ... p ⁺ collector region 44 ... p ⁺ base region 46 ... n emitter region 48 ... emitter electrode 50 ... gate electrode 52 ... collector electrode 54 ... gate insulating layer

Claims (26)

  The active layer is characterized in that two or more types of p-type and n-type impurities having a lower carrier lifetime in the semiconductor layer than in the case where no impurity is contained in the semiconductor layer are mixed in substantially equal amounts. A semiconductor device having a resistive semiconductor layer.   Compared with the case where the impurity density in the semiconductor layer is very small, two or more types of p-type and n-type impurities having a density equal to or lower than the density at which the carrier lifetime in the semiconductor layer is reduced are mixed together. A semiconductor device having a resistive semiconductor layer.   3. The active high resistance semiconductor layer according to claim 1, wherein the active high-resistance semiconductor layer further includes another impurity that realizes strain compensation between lattices other than the p-type impurity and the n-type impurity. Device having a high resistance semiconductor layer.   The active high-resistance semiconductor layer according to any one of claims 1 to 3, wherein the active high-resistance semiconductor layer is disposed on one side of a substrate of a semiconductor device. A semiconductor device.   4. The active high resistance semiconductor layer according to claim 1, wherein the active high resistance semiconductor layer is selectively disposed locally on one side of a substrate of a semiconductor device. 5. A semiconductor device having a high-resistance semiconductor layer.   The active high-resistance semiconductor layer according to any one of claims 1 to 3, wherein the active high-resistance semiconductor layer is disposed on both sides of the substrate of the semiconductor device. A semiconductor device.   4. The active high resistance semiconductor layer according to claim 1, wherein the active high resistance semiconductor layer is selectively disposed locally on both sides of the substrate of the semiconductor device. 5. A semiconductor device having a high-resistance semiconductor layer.   The active high-resistance semiconductor layer according to any one of claims 1 to 7, wherein the active high-resistance semiconductor layer is formed of any one of Si, SiC, diamond, or GaN. A semiconductor device having a layer.   Manufacturing of a semiconductor device having an active high-resistance semiconductor layer, comprising the step of forming an active high-resistance semiconductor layer on the entire surface of a semiconductor substrate by epitaxial growth using an epitaxial growth gas containing a p-type impurity and an n-type impurity Method.   A semiconductor device having an active high-resistance semiconductor layer, characterized by comprising a step of selectively forming an active high-resistance semiconductor layer on a semiconductor substrate by epitaxial growth using an epitaxial growth gas containing a p-type impurity and an n-type impurity. Manufacturing method. an ion implantation step of forming equal amounts of p-type impurities and n-type impurities over the entire surface of the semiconductor substrate;
A method of manufacturing a semiconductor device having an active high resistance semiconductor layer, comprising: a heat treatment step for increasing resistance of an ion implantation layer formed on the entire surface of the semiconductor substrate after the ion implantation step. an ion implantation step of selectively forming equal amounts of p-type impurities and n-type impurities in a semiconductor substrate;
A method of manufacturing a semiconductor device having an active high-resistance semiconductor layer, comprising: a heat treatment step for high resistance of an ion implantation layer selectively formed in the semiconductor substrate after the ion implantation step.   The semiconductor having an active high-resistance semiconductor layer according to any one of claims 9 to 12, wherein the semiconductor substrate is formed of any one of Si, SiC, diamond, and GaN. Device manufacturing method. A high resistance semiconductor layer;
An anode region disposed on the main surface of the high-resistance semiconductor layer;
A cathode region disposed on another main surface of the high-resistance semiconductor layer;
A semiconductor device having an active high resistance semiconductor layer, comprising: an active high resistance semiconductor layer disposed between the high resistance semiconductor layer and the anode region.
  15. The active high resistance semiconductor layer according to claim 14, wherein the active high resistance semiconductor layer and the anode region have substantially the same junction depth measured from the anode side surface, and the anode region has a channel structure. A semiconductor device having a semiconductor layer.   15. The active high resistance semiconductor layer according to claim 14, wherein the active high resistance semiconductor layer has a junction depth measured from the anode side surface deeper than the anode region, and the anode region has a channel structure. A semiconductor device having a semiconductor layer.   15. The semiconductor device having an active high resistance semiconductor layer according to claim 14, wherein the active high resistance semiconductor layer has a channel structure. A high resistance semiconductor layer;
An anode region repeatedly disposed on the main surface of the high-resistance semiconductor layer;
An anode electrode in contact with the anode region;
A cathode region disposed on another main surface of the high-resistance semiconductor layer;
A cathode electrode in contact with the cathode region;
An anode short-circuit region disposed in the anode region repeatedly disposed, and short-circuited by the anode region and the anode electrode;
A semiconductor device having an active high resistance semiconductor layer, comprising: an active high resistance semiconductor layer disposed between the high resistance semiconductor layer and the anode short-circuit region. A high resistance semiconductor layer;
An anode region disposed on a main surface of the high-resistance semiconductor layer and having a channel structure;
A cathode region disposed on another main surface of the high-resistance semiconductor layer;
A semiconductor device having an active high-resistance semiconductor layer, comprising: an active high-resistance semiconductor layer disposed in the channel structure in the vicinity of the high-resistance semiconductor layer and the anode region. A high resistance semiconductor layer;
A gate region repeatedly disposed on the main surface of the high-resistance semiconductor layer;
A gate electrode in contact with the gate region;
A drain region disposed on another main surface of the high-resistance semiconductor layer;
A drain electrode in contact with the drain region;
A source region disposed between the repeatedly disposed gate regions;
A source electrode disposed adjacent to the gate electrode on the main surface and in contact with a source region;
A semiconductor device having an active high resistance semiconductor layer, comprising: an active high resistance semiconductor layer disposed between the high resistance semiconductor layer and the source region.   21. The active high resistance semiconductor according to claim 20, wherein the gate electrode is disposed so as to be embedded in the gate region, and the source electrode is disposed through an insulating layer disposed on the gate electrode. A semiconductor device having a layer. A high resistance semiconductor layer;
A gate region having a channel structure and repeatedly arranged in the vicinity of the main surface of the high-resistance semiconductor layer;
A gate electrode in contact with the gate region;
An anode region disposed on another main surface of the high-resistance semiconductor layer;
An anode electrode in contact with the anode region;
A cathode region disposed between the repeatedly disposed gate regions;
A cathode electrode disposed adjacent to the gate electrode on the main surface and in contact with the cathode region;
A semiconductor device having an active high resistance semiconductor layer, comprising: an active high resistance semiconductor layer disposed between the high resistance semiconductor layer and the anode region.   23. The semiconductor device having an active high resistance semiconductor layer according to claim 22, wherein the active high resistance semiconductor layer further includes another channel structure.   24. The semiconductor device having an active high-resistance semiconductor layer according to claim 22, further comprising another active high-resistance semiconductor layer between the gate region and the cathode region.   The active high-resistance semiconductor layer according to any one of claims 22 to 24, wherein the gate region repeatedly disposed in the vicinity of the main surface of the high-resistance semiconductor layer has a buried structure. Semiconductor device. an n base layer;
A p base region having a channel structure and repeatedly arranged in the vicinity of the main surface of the n base layer;
An n-emitter region disposed near the main surface in the p-base layer;
An emitter electrode that is in contact with the n emitter region and is short-circuited with the p base region and disposed on the main surface;
An active high resistance semiconductor layer disposed in the channel structure between the repeatedly disposed p base regions;
A gate insulating layer disposed on the active high resistance semiconductor layer and the adjacent p base region and n emitter region;
A gate electrode disposed on the gate insulating layer;
A p collector region disposed on another main surface of the n base layer;
A collector electrode in contact with the p collector region;
A semiconductor device having an active high-resistance semiconductor layer, comprising: another active high-resistance semiconductor layer disposed between the n base layer and the p collector region.

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