JP2009054659A - Manufacturing method of gallium nitride semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a gallium nitride semiconductor device capable of easily manufacturing a vertical element where a current flows in the thickness direction of a substrate regardless of resistance of a gallium nitride growth layer and a buffer layer. <P>SOLUTION: The manufacturing method has processes of: forming a silicon substrate 1, the buffer layer 2 formed on the silicon substrate, and a gallium nitride semiconductor layer on top of it; forming a trench of a depth reaching the gallium semiconductor layer by penetrating the silicon substrate and the buffer layer 2 from the back surface of the silicon substrate 1; and embedding a conductive material in the trench. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a vertical semiconductor device using a gallium nitride semiconductor.

Conventionally, a silicon single crystal has been used as a material of a power semiconductor element that controls a high breakdown voltage and a large current. There are many types of power semiconductor devices that are produced, but each has its advantages and disadvantages, and the current situation is that it is properly used according to the application. For example, bipolar transistors and IGBTs (insulated gate bipolar transistors) have a limit in high-speed switching although a large current density can be obtained. The use limit is said to be a frequency of several kHz for bipolar transistors and 20-30 kHz for IGBTs. On the other hand, power MOSFETs and Schottky barrier diodes cannot be used for large currents, but can be used at higher speeds up to a high frequency range of several MHz. However, there is a strong demand for power devices having both high current and high speed in the market. For this reason, efforts have been made to improve switching speed particularly in IGBTs and power MOSFETs. As a result, it is said that the switching speed close to the above-mentioned material limit has been reached at present, but it cannot be said that the required level has been sufficiently reached.
On the other hand, gallium nitride (GaN) semiconductors have a high energy gap of 3 eV or more, and conventionally, optical devices such as blue LEDs (light emitting diodes) and LDs (laser diodes) have been mainly developed. In recent years, however, gallium nitride (GaN) semiconductors have the characteristics that their breakdown electric field is high and the maximum electric field strength is one order of magnitude higher than that of silicon, so that they are power devices used for low on-resistance and high-speed switching. Therefore, research and development related to application to such power devices has been actively conducted. Until now, as a switching device using a gallium nitride (GaN) material, a HEMT (high electron mobility transistor) element in which GaN is grown on a sapphire substrate is generally known. This HEMT device has a feature that the on-resistance is extremely low because of its high mobility characteristics, but since the sapphire substrate that is an insulator is used, the current extraction electrode is entirely on the surface of the GaN layer. Must be installed on the side. Therefore, this HEMT element necessarily has a lateral device structure (Patent Document 1).

As described above, since the HEMT element has a lateral device structure, it is possible to increase the withstand voltage. However, regarding the current, the current flows only in the vicinity of the element surface and tends to have a non-uniform current distribution. It is difficult to flow a large current because the resistance component tends to increase. Therefore, the above-described gallium nitride is an element in the power device field, in which a vertical structure in which current extraction electrodes are installed on the front and back surfaces and current flows uniformly in the vertical (thickness) direction in the element is most suitable. It must be said that the (GaN) semiconductor has an unsuitable structure. However, for example, a vertical HEMT device in which a GaN layer is epitaxially grown on a GaN substrate and a HEMT structure is formed therein has been studied (Non-Patent Document 1).
However, since the GaN substrate used in the vertical HEMT device described in Non-Patent Document 1 is very expensive and has a difficulty in increasing the diameter of the wafer, it is extremely difficult for mass production on the premise of a large diameter. There is a disadvantage that it is unsuitable. Therefore, many attempts have been made to develop a semiconductor element using a substrate obtained by growing GaN on a silicon substrate that is inexpensive and can have a large diameter. If this development is successful, a high-performance semiconductor having the same mass productivity as the current silicon power semiconductor will be possible. However, since the crystal lattice constants of silicon crystal and GaN crystal are different at present, when GaN is grown on the silicon substrate as it is, crystal defects are generated in the GaN crystal and dislocations enter the GaN crystal from the interface. There is a fatal problem as an electronic device such that a very large leakage current is generated in the off state of the element due to dislocation. To solve this problem, a method is known in which a buffer layer such as an AlN layer is provided between the silicon and the GaN layer to improve the crystallinity of the GaN layer and to avoid the problem of the large leakage current (patent) References 2, 3).

Furthermore, a manufacturing method characterized in that an n ⁻ GaN layer is formed after a trench is previously formed in a silicon semiconductor substrate is disclosed. This document describes that GaN has the effect of reducing the occurrence of dislocations due to the difference in lattice constant by forming the top of the trench by the lateral selective growth method during crystal growth (Patent Document 4). .
JP 2004-31896 A JP 2003-60212 A JP-A-5-343741 JP 2006-165191 A “Vertical operation of insulated gate AlGaN / GaN-HFET” IEEJ Technical Committee EDD-06-104 2006.

However, in the buffer layer using the AlN layer, the band gap is extremely high (6.2 eV), and thus the resistance becomes high. As a result, when current flows in the vertical direction, almost no current flows in the AlN layer and There arises a new problem that the resistance, that is, the ON voltage becomes extremely large.
Further, in the manufacturing method described in Patent Document 4, since the trench 6 is already provided on the surface of the semiconductor substrate 1 on which the GaN layer 5 is epitaxially grown as shown in FIG. It is formed not only on the surface of the trench 6 but also on the sidewall of the trench 6. However, when the silicon substrate 1 is used, for example, a wafer having a (111) plane as a main surface is used because of lattice constant matching, but the silicon surface on the side wall of the trench 6 is not (111), so it is formed on the side wall. Many crystal defects are likely to occur in the GaN layer 5-1. There is a high possibility that the GaN layer 5-1 on the side surface of the trench 6 will remain in the device until the end, and the dislocation generated in the GaN layer 5-1 on the side surface of the trench 6 may become a source of leakage current. . Further, in the GaN crystal formed by the lateral selective growth method, as shown in the cross-sectional view of FIG. 4, a so-called grain boundary 11 is generated on the surface where the adjacent lateral growth layers collide with each other on the substrate surface. Therefore, when the metal 7 is buried in the trench in the subsequent process, the metal reaches the surface of the n ⁻ GaN layer 5 through the grain boundary 11, which may cause a short circuit failure between the electrodes.

  The present invention has been made in view of the above points, and an object of the present invention is to facilitate a vertical element in which a current flows in the thickness direction of the substrate regardless of the resistance of the gallium nitride growth layer and the buffer layer. Another object of the present invention is to provide a method of manufacturing a gallium nitride semiconductor device that can be produced.

According to the first aspect of the present invention, the crystal structure conversion between the substrate and the gallium nitride semiconductor layer grown on the substrate and the crystal quality improvement on one surface of the insulator substrate or the semiconductor substrate. Forming a plurality of trenches having a depth reaching the gallium nitride semiconductor layer from the other surface of the insulator substrate or the semiconductor substrate; A method of manufacturing a gallium nitride semiconductor device includes a step of embedding a conductive material therein and forming electrodes on the surface of the gallium nitride semiconductor layer and the other surface of the substrate.
According to the second aspect of the present invention, the gallium nitride semiconductor device manufacturing method according to the first aspect of the present invention is such that the substrate is silicon.
According to a third aspect of the present invention, there is provided a method for manufacturing a gallium nitride semiconductor device according to the first aspect, wherein the substrate is sapphire.
According to the invention of claim 4, before forming a plurality of trenches having a depth reaching the gallium nitride semiconductor layer from the other surface of the insulator substrate or semiconductor substrate, the insulator substrate or 4. The method for manufacturing a gallium nitride semiconductor device according to claim 1, wherein a plurality of the trenches are formed after the other surface side of the semiconductor substrate is polished to reduce the thickness. 5. .

According to a fifth aspect of the present invention, the gallium nitride semiconductor device manufacturing method according to the fourth aspect of the present invention is such that the conductive material embedded in the trench is aluminum.
According to a sixth aspect of the present invention, in the method for manufacturing a gallium nitride semiconductor device according to the fourth aspect, the conductive material embedded in the trench is polysilicon having a high impurity concentration. .
In order to achieve the above object, a method of manufacturing a gallium nitride semiconductor device according to the present invention includes a silicon substrate 1, a buffer layer 2 formed on the silicon substrate, and a gallium nitride semiconductor layer formed thereon, and the silicon substrate. Forming a trench having a depth reaching the gallium nitride semiconductor layer from the back surface of 1 through the silicon substrate and the buffer layer 2, and embedding a conductor in the trench. On the gallium nitride semiconductor substrate thus formed, for example, a Schottky barrier electrode is formed on the surface of the gallium nitride semiconductor layer to form a Schottky barrier diode, and a back surface of the silicon substrate 1 in which a conductor is embedded in the trench. Gallium nitride Schottky barrier diode that suppresses an increase in on-voltage and can be easily manufactured even if it has a buffer layer including a high-resistance layer as a vertical element. Is obtained.

  According to the present invention, it is possible to provide a method for manufacturing a gallium nitride semiconductor device capable of easily creating a vertical element in which a current flows in the thickness direction of the substrate regardless of the resistance of the gallium nitride growth layer and the buffer layer. It becomes.

Hereinafter, a method for manufacturing a gallium nitride semiconductor device according to the present invention will be described in detail with reference to the drawings. The present invention is not limited to the description of the examples described below unless it exceeds the gist.
FIG. 1 is a cross-sectional view of a GaN Schottky barrier diode according to Example 1 of the present invention. 2 and 3 are cross-sectional views of a GaN Schottky barrier diode manufacturing process according to Embodiment 1 of the present invention. FIG. 5 is an IV characteristic diagram of the GaN Schottky barrier diode according to Example 1 of the present invention. FIG. 6 is a breakdown voltage characteristic diagram of the GaN Schottky barrier diode according to Example 1 of the present invention.

Hereinafter, Example 1 concerning the manufacturing method of the gallium nitride semiconductor device of this invention is demonstrated in detail with reference to FIGS. 1-3. In Example 1, a Schottky barrier diode having a withstand voltage of 600 V is shown as the vertical element. FIG. 1 is a schematic cross-sectional view of the gallium nitride Schottky barrier diode according to the first embodiment. As shown in this figure, the gallium nitride Schottky barrier diode of Example 1 has a silicon substrate 1 and two buffer layers 2 and 3 made of AlN / GaN formed on the silicon substrate 1 and laminated thereon. The high (impurity) concentration n ⁺ GaN layer 4 and the low (impurity) concentration n ⁻ GaN layer 5 are provided. Furthermore, the silicon substrate 1 has a trench 6 that reaches the n ⁺ GaN layer 4 from the back surface, and the trench 6 is filled with a conductive material 7 mainly composed of aluminum or the like. The conductive material 7 made of aluminum or the like is formed on the back surface side of the silicon substrate 1, and further, a cathode electrode 8 such as Ni-Au is formed on the entire back surface of the silicon substrate so as to be in contact with the aluminum film formed on the entire surface of the back surface. Is formed. As such a conductive material, high-concentration polysilicon can also be used. Further, a silicon oxide film 10 is formed on the surface of the n ⁻ GaN layer between the Schottky barrier electrode film 9 and an electric field relaxation when a reverse voltage is applied.
Next, the manufacturing method of a Schottky barrier diode is demonstrated using FIG. 2, FIG. First, a silicon substrate 1 whose main surface is a (111) plane is prepared, and an AlN layer 2 and a non-doped GaN layer 3 are formed thereon using a well-known technique, metal organic chemical vapor deposition (MOCVD). They are formed in this order. Since the lattice constant of the silicon surface (111) is 0.3840 nm and the lattice constant of the GaN surface is 0.3819 nm, which is a relatively close value, the silicon (111) surface was selected. The silicon substrate 1 had a diameter of 200 mm and a thickness of 500 μm, the AlN layer 2 formed thereon had a thickness of 15 nm, and the non-doped GaN layer 3 had a thickness of 200 nm. The AlN layer 2 is deposited for conversion of the crystal structure between the silicon substrate and the GaN layer, and the GaN layer 3 is formed as a layer for improving the quality of the crystal. Further, an n-type high concentration n ⁺ GaN layer 4 is epitaxially grown to a thickness of 3 μm and an n-type low concentration n ⁻ GaN layer 5 is epitaxially grown to a thickness of 6 μm. The impurity concentrations of the two GaN layers were 5 × 10 ¹⁹ cm ⁻³ and 2 × 10 ¹⁶ cm ⁻³ , respectively. Trimethylgallium was used as the gallium material during the epitaxial growth, and ammonia gas was used as the nitrogen material. Monosilane was used as a dopant material for making the gallium nitride layer n-type. Through the steps so far, the basic layer structure of the gallium nitride semiconductor substrate is completed as shown in the cross-sectional view of FIG.

Next, a Schottky barrier electrode film 9 is formed on the surface of the n ⁻ GaN layer 5 as shown in FIG. This electrode film was formed by laminating Ni and Al by a well-known vapor deposition method. At this time, the silicon oxide film 10 was formed by CVD before depositing the Schottky barrier electrode film, and the Schottky barrier electrode film 9 was deposited after patterning. Since the Schottky barrier electrode film 9 on the silicon oxide film 10 serves as a field plate, stable breakdown voltage characteristics can be obtained. Next, the silicon substrate 1 having a thickness of 500 μm is back-ground (rear surface polishing) from the back surface to a total thickness of 80 μm. Since the silicon substrate 1 is usually as thick as about 500 μm, back grinding is performed in the first embodiment in order to simplify the subsequent trench etching process. However, if the original substrate is sufficiently thin, the back grinding process may be omitted. good. Thereafter, an oxide film having a thickness of 1.6 μm is grown on the back surface of the silicon substrate 1 and an oxide film mask having a width of 5 μm is formed every 5 μm by photolithography and etching. A trench having a depth reaching the n ⁺ GaN layer 4 through the GaN buffer layers 2 and 3 is formed. As a result, a high concentration n ⁺ GaN layer 4 appears at the bottom of the trench. Next, aluminum Al is embedded in the trench as a conductive material by a plating method. Thereafter, a Ti / Ni / Au metal film is formed in this order on the entire back surface of the silicon substrate 1 so as to be in contact with Al buried in the trench. By doing so, a vertical Schottky barrier diode is completed.

In the manufacturing method described in Patent Document 4, as described above, GaN formed on the trench sidewall may leak and become a current generation source. Furthermore, there is a concern that the metal embedded in the trench may reach the element surface via the grain boundary generated when the formed GaN crystal is laterally selective grown, resulting in a short circuit failure. According to the manufacturing method of the device, the GaN layer is not formed on the trench side wall, and the grain boundary is not formed.
In the current-voltage characteristic diagram of FIG. 5, a solid line shows an IV (current-voltage) waveform at room temperature (RT) of a gallium nitride Schottky barrier diode prepared according to the manufacturing method described in the first embodiment. . The chip size of the Schottky barrier diode used for this measurement was 5 mm × 5 mm, and the rated current was 100 A (current density was 452.7 A / cm ² ). For comparison, FIG. 5 also shows the IV waveform of a silicon pn diode having a normal 600 V / 100 A characteristic by dot lines. In the Schottky barrier diode according to the present invention, a sufficiently low on-voltage almost equal to that of a silicon pn diode is obtained even in an on-voltage of 1.6 V / 100 A and a large current region. Further, from the IV waveform in FIG. 5, the resistance does not increase even when a current more than twice the rated current (200 A) flows. From this, it can be seen that, like a silicon vertical pn diode, it functions sufficiently as a vertical device.

  Further, when the reverse recovery characteristic is measured, as shown in Table 1, the reverse recovery loss of the gallium nitride Schottky barrier diode of the present invention is 0.40 mJ, which is about 1/10 compared with 4.42 mJ of the silicon pn diode. It can be seen that the reverse recovery loss is low, and that low loss and high speed are achieved.

さらに、図６に示すように、本発明の実施例１にかかるショットキバリアダイオードの耐圧特性を測定したところ、素子耐圧７１０Ｖとなり、６００Ｖ耐圧クラスのショットキバリアダイオード素子として十分な阻止特性を示していることがわかる。
以上説明した実施例１の素子構造とすることにより、高抵抗層であるバッファ層２、３ならびにシリコン基板１またはサファイヤ等の絶縁基板の抵抗に関係なく、電流はトレンチ６内に埋め込まれた導電体７を流れることとなり、大電流が許容範囲内の小さいオン電圧であって、逆回復損失が通常のｐｎダイオードに比べて約１０分の１程度の極めて小さい縦型ショットキバリアダイオード素子が完成する。

Furthermore, as shown in FIG. 6, when the breakdown voltage characteristic of the Schottky barrier diode according to Example 1 of the present invention was measured, the element breakdown voltage was 710 V, which showed a sufficient blocking characteristic as a Schottky barrier diode element of the 600 V breakdown voltage class. I understand that.
With the element structure of the first embodiment described above, the current is conducted in the trench 6 regardless of the resistance of the buffer layers 2 and 3 which are high resistance layers and the insulating substrate such as the silicon substrate 1 or sapphire. Thus, a vertical Schottky barrier diode element is completed in which a large current is a small ON voltage within an allowable range and a reverse recovery loss is about one-tenth that of a normal pn diode. .

A sapphire substrate may be used instead of the silicon substrate used in the gallium nitride Schottky barrier diode of the first embodiment. On the sapphire substrate, an AlN layer having a thickness of 15 nm and a non-doped GaN layer having a thickness of 200 nm are formed as buffer layers in the same manner as in the first embodiment. Further, an n ⁺ GaN layer is epitaxially grown thereon to a thickness of 3 μm and an n ⁻ GaN layer is grown to a thickness of 6 μm. The impurity concentrations were 5 × 10 ¹⁹ cm ⁻³ and 2 × 10 ¹⁶ cm ⁻³ , respectively. At this time, as in Example 1, trimethylgallium was used as the gallium material, and ammonia gas was used as the nitrogen material. Moreover, monosilane was used as a dopant material in order to make it n-type. Thereafter, a Schottky barrier diode was formed in the same process as in Example 1. As in Example 1, the characteristics of an on voltage of 1.6 V and a breakdown voltage of 710 V were exhibited. When the reverse recovery characteristic was measured under the same conditions, it was found that the reverse recovery loss was 0.41 mJ, which was sufficiently smaller than the above-mentioned silicon pn diode of 4.42 mJ. The trench width at this time was set to 2 μm as in the first embodiment.

A trench having a depth reaching the n ⁺ GaN layer 4 from the back surface was formed in a silicon substrate having a basic layer structure of a gallium nitride semiconductor substrate, and then this trench was phosphorus-doped at a high concentration instead of aluminum in Example 1. When conductive polysilicon was embedded by CVD, and then a cathode electrode was formed in the same manner as in Example 1 to form a Schottky barrier diode, characteristics of an on voltage of 1.68 V and a withstand voltage of 713 V were shown. Similarly, when the reverse recovery characteristic was measured, it was found that the loss was 0.38 mJ, which was sufficiently smaller than the above-mentioned silicon pn diode of 4.42 mJ. The trench width at this time was set to 5 μm as in the first embodiment. In Examples 1, 2, and 3, a vertical element is formed by a Schottky barrier diode. However, a p-type well layer is formed on the surface layer of the n ⁻ GaN layer, and an n ⁺ source layer is formed in the p-type well layer. By adding a well-known process such as forming a gate oxide film and a gate electrode on the n ⁻ GaN layer, a semiconductor device such as a vertical MOSFET or IGBT can be formed.

Hereinafter, Example 4 concerning the manufacturing method of the gallium nitride semiconductor device of this invention is demonstrated in detail with reference to FIGS. In Example 4 described below, a MOSFET having a withstand voltage of 600 V was taken as the vertical element.
FIG. 7 is a schematic cross-sectional view of the gallium nitride MOSFET according to the fourth embodiment. The gallium nitride MOSFET shown in FIG. 7 includes a silicon substrate 1 and buffer layers 2 and 3 made of two layers of AIN / GaN formed thereon, and a high concentration n ⁺ GaN layer 4 formed thereon. The low concentration n ⁻ GaN layer 5 is laminated in this order. Furthermore, a trench reaching the n ⁺ GaN layer 4 from the back surface is dug in the silicon substrate 1 thinned as necessary, and a metal film 12 covers the bottom and side surfaces of the trench and the back surface of the silicon substrate 1. Is the drain electrode 20.
Next, with reference to FIGS. 8 and 9, a method for manufacturing the gallium nitride MOSFET according to Example 4 will be described.
First, a silicon substrate 1 whose principal surface is a (111) surface is prepared, and an AIN layer 2 and a non-doped GaN layer 3 are formed on the principal surface by using a metal organic chemical vapor deposition method (MOCVD) which is a well-known technique. Form. Since the lattice constant of the silicon surface (111) is 0.3840 and that of GaN is 0.3819, which is a relatively close value, the silicon (111) surface was selected. A silicon substrate having a diameter of 200 mm and a thickness of 500 mm is used, the AIN layer 2 formed thereon has a thickness of 15 nm, and the non-doped GaN layer 3 has a thickness of 200 mm. The AIN layer 2 is formed as a layer for converting the crystal structure, and the GaN layer 3 is formed as a layer for improving the quality of the crystal. Further, an n ⁺ GaN layer 4 and an n ⁻ GaN layer 5 are epitaxially grown to a thickness of 3 μm and 6 μm, respectively. The impurity concentrations were 5 × 10 ¹⁹ cm ⁻³ and 2 × 10 ¹⁶ cm ⁻³ , respectively. At this time, trimethylgallium was used as the gallium material and ammonia was used as the nitrogen material. Moreover, monosilane was used as a dopant material in order to make it n-type. On top of this, the p ⁻ GaN layer 13 is epitaxially grown to a thickness of 2 μm. The impurity concentration was 2 × 10 ¹⁷ cm ⁻³ and magnesium was used as the dopant material. As a result, the basic layer structure shown in FIG. 8 is completed.

Next, a silicon oxide (SiO ₂ ) film 10 is formed on the surface of the p ⁻ GaN layer 13, and a p ⁺ layer 14 is formed after patterning (FIG. 9). The p ⁺ layer 14 was ion-implanted with magnesium at an acceleration voltage of 45 keV, and the impurity concentration was 2 × 10 ¹⁷ cm ⁻³ . Thereafter, the mask oxide (SiO ₂ ) film 10 is removed, and an SiO ₂ film is selectively formed again to form an n ⁺ layer 15 (FIG. 10). The n ⁺ layer 15 was formed by ion implantation using silicon and aluminum as impurities. The impurity concentration at that time was 2 × 10 ¹⁸ cm ⁻³ . Then, after forming a trench 16 having a depth of 3 μm from the surface, a gate oxide film 17 is formed with a thickness of 100 nm. Thereafter, a low resistance polysilicon 18 doped with impurities is buried to form a gate electrode. Further, titanium / aluminum is formed as the source electrode 19 so as to be in ohmic contact with the surfaces of the n ⁺ layer 15 and the p ⁺ layer 14 in common (FIG. 11).
Next, the silicon substrate 1 having a thickness of 500 nm is back-grinded from the back surface so that the total thickness becomes 80 μm. Since the silicon substrate 1 is normally as thick as 500 μm, back grinding is performed in Example 4 in order to simplify the subsequent trench etching process. However, the back grinding may be omitted if the original silicon substrate is sufficiently thin. Although the silicon substrate 1 of FIG. 7 looks thick in the drawing, the layer thickness of each layer in this figure is not accurate. Although not shown in FIG. 11, an oxide film having a thickness of 1.6 μm is grown on the back surface of the silicon substrate, and an oxide film mask having a width of 6 μm is formed every 6 μm by photolithography and etching. The silicon substrate 1 and the buffer layers 2 and 3 made of AIN / GaN are sequentially removed by etching. At that time, the high-concentration n ⁺ GaN layer 4 appears at the tip of the trench by digging to reach the n ⁺ GaN layer 4. Aluminum is buried in this trench by the Mikki method. Thereafter, as shown in FIG. 7, a drain electrode 20 is formed by sequentially laminating a metal film 12 made of Ti / Ni / Au so as to be in contact with Al buried in the trench over the entire back surface of the silicon substrate 1. .

12 and 13 show the breakdown voltage characteristics and the IV characteristics in the on state of the gallium nitride MOSFET according to Example 4 described above. As shown in FIG. 12, this gallium nitride MOSFET has a withstand voltage characteristic of 670 V, and it can be seen that the gallium nitride MOSFET has sufficient blocking withstand voltage characteristics as a 600 V class withstand voltage element. The chip size of this gallium nitride MOSFET was 5 mm × 5 mm, the rated current was 50 A (active region area = 0.2 cm ² , current density was 250.0 A / cm ² ). For comparison, FIG. 13 also shows a normal 600 C / 50 A silicon IGBT and an on-state IV waveform of the silicon MOSFET (area of the active region = 0.2 cm ² , current density is 250.0 A / cm, respectively). Same conditions as in ² ). From FIG. 13, the on-voltage of the gallium nitride MOSFET according to Example 4 is 0.45 V / 50 A, and even when a current more than twice the rated current (100 A or more) flows compared to the silicon IGBT or silicon MOSFET. It can be seen that the voltage / current or resistance is constant and small. From this, it can be seen that the characteristics are superior to those of the silicon vertical IGBT and the silicon MOSFET, and that it functions sufficiently as a vertical device.
Further, when the turn-off characteristics are measured, as shown in Table 2, it can be seen that the turn-off time is about one-sixth that of the silicon IGBT, and low loss and high speed are achieved.

以上に説明したような窒化ガリウムショットキバリアダイオードの製造方法を含む窒化ガリウム半導体装置の製造方法によれば、既存シリコン縦型半導体なみの大電流におけるオン電圧特性を有し、かつシリコン半導体装置より高速性に優れた高耐圧縦型窒化ガリウム系半導体装置の製造方法を提供することができる。また、本発明にかかる製造方法により作成されたＧａＮ半導体装置では、トレンチ内に埋め込んだ金属等の導電物により、オン電流によりＧａＮ半導体層内で発生した熱の放熱性に優れるという効果も有している。

According to the manufacturing method of the gallium nitride semiconductor device including the manufacturing method of the gallium nitride Schottky barrier diode as described above, it has an on-voltage characteristic at a large current similar to that of the existing silicon vertical semiconductor, and is faster than the silicon semiconductor device. It is possible to provide a method for manufacturing a high-breakdown-voltage vertical gallium nitride semiconductor device that is excellent in performance. In addition, the GaN semiconductor device created by the manufacturing method according to the present invention has an effect of being excellent in heat dissipation of the heat generated in the GaN semiconductor layer due to the on-current due to the conductive material such as metal embedded in the trench. ing.

It is sectional drawing of the GaN Schottky barrier diode concerning Example 1 of this invention. It is sectional drawing of the GaN Schottky barrier diode manufacturing process (the 1) concerning Example 1 of this invention. It is sectional drawing of the GaN Schottky barrier diode manufacturing process (the 2) concerning Example 1 of this invention. It is a schematic sectional drawing of the semiconductor substrate which made GaN epitaxially grow on the conventional silicon substrate. It is an IV characteristic view of the GaN Schottky barrier diode according to Example 1 of the present invention. It is a pressure | voltage resistant characteristic view of the GaN Schottky barrier diode concerning Example 1 of this invention. It is a schematic sectional drawing of GaN-MOSFET concerning Example 4 of this invention. It is a schematic sectional drawing which shows the manufacturing method of the GaN-MOSFET concerning Example 4 of this invention (the 1). It is a schematic sectional drawing which shows the manufacturing method of GaN-MOSFET concerning Example 4 of this invention (the 2). It is a schematic sectional drawing which shows the manufacturing method of GaN-MOSFET concerning Example 4 of this invention (the 3). It is a schematic sectional drawing which shows the manufacturing method of GaN-MOSFET concerning Example 4 of this invention (the 4). It is a withstand voltage characteristic figure of GaN-MOSFET concerning Example 4 of the present invention. It is an IV characteristic view of GaN-MOSFET concerning Example 4 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon semiconductor substrate 2 AlN layer, buffer layer 3 Non-doped GaN layer, buffer layer 4 High concentration n ⁺ GaN layer 5 Low concentration n ⁻ GaN layer 6 Trench 7 Conductor, aluminum, conductive polysilicon 8 Cathode electrode 9 Anode electrode 10 Silicon oxide film 12 Trench 13 p-GaN layer 14 p ⁺ layer 15 n ⁺ layer 16 Trench 17 Gate oxide film 18 Low resistance polysilicon.

Claims (6)

A gallium nitride semiconductor layer is formed on one surface of an insulator substrate or a semiconductor substrate via a buffer layer provided for crystal structure conversion and crystal quality improvement between the substrate and a gallium nitride semiconductor layer grown on the substrate. And then forming a plurality of trenches having a depth reaching the gallium nitride semiconductor layer from the other surface of the insulator substrate or the semiconductor substrate, and burying a conductive material in the trench, and the surface of the gallium nitride semiconductor layer and the substrate A method of manufacturing a gallium nitride semiconductor device, comprising the step of forming an electrode on the other surface. 2. The method of manufacturing a gallium nitride semiconductor device according to claim 1, wherein the substrate is silicon. 2. The method of manufacturing a gallium nitride semiconductor device according to claim 1, wherein the substrate is sapphire. Before forming a plurality of trenches having a depth reaching the gallium nitride semiconductor layer from the other surface of the insulator substrate or semiconductor substrate, the other surface side of the insulator substrate or semiconductor substrate is polished to reduce the thickness. The method of manufacturing a gallium nitride semiconductor device according to claim 1, wherein a plurality of the trenches are formed. 5. The method of manufacturing a gallium nitride semiconductor device according to claim 4, wherein the conductive material embedded in the trench is aluminum. 5. The method of manufacturing a gallium nitride semiconductor device according to claim 4, wherein the conductive material embedded in the trench is polysilicon having a high impurity concentration.

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