JP2006156658A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2006156658A
JP2006156658A JP2004344338A JP2004344338A JP2006156658A JP 2006156658 A JP2006156658 A JP 2006156658A JP 2004344338 A JP2004344338 A JP 2004344338A JP 2004344338 A JP2004344338 A JP 2004344338A JP 2006156658 A JP2006156658 A JP 2006156658A
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substrate
electrode
layer
sic
type
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Makoto Mizukami
誠 水上
Takashi Shinohe
孝 四戸
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Toshiba Corp
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Toshiba Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which is capable of reducing the ON-state resistance, while keeping its substrate high in strength. <P>SOLUTION: The semiconductor device is equipped with a support 21, which has two or more recesses formed through reticulate projections provided on its rear side and is formed of semiconductor having first impurity concentration, a semiconductor layer 3 which is formed on the surface of the support 21 opposite to its rear side and has a second impurity concentration lower than the first impurity concentration, and a semiconductor element formed on the semiconductor layer 3. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は半導体装置に関し、特に基板抵抗を構造的に低減させ、低オン抵抗を実現可能とする半導体装置に関する。   The present invention relates to a semiconductor device, and more particularly to a semiconductor device that can reduce substrate resistance structurally and realize low on-resistance.

半導体装置において、素子内の電流経路が、素子の第一の主面から第二の主面に向かって流れる縦型の半導体装置が知られている。この種の半導体装置の性能は、主として基板表面に形成されたエピタキシャル層に形成された素子構造により決定され、基板は上記エピタキシャル層を保持し、強度を保つ役割を担っている。   As a semiconductor device, a vertical semiconductor device in which a current path in an element flows from a first main surface to a second main surface of the element is known. The performance of this type of semiconductor device is mainly determined by the element structure formed in the epitaxial layer formed on the substrate surface, and the substrate holds the epitaxial layer and plays the role of maintaining the strength.

縦型半導体装置の電流経路の抵抗は、大別してエピタキシャル面と電極とのコンタクト抵抗、エピタキシャル層抵抗、基板抵抗、基板面と電極とのコンタクト抵抗を合わせた直列抵抗で構成されるが、エピタキシャル層に強度を付与するための基板の抵抗が非常に大きく、全体の抵抗を下げるためには、基板抵抗を下げなければならない。   The resistance of the current path of the vertical semiconductor device is roughly divided into the contact resistance between the epitaxial surface and the electrode, the epitaxial layer resistance, the substrate resistance, and the series resistance that combines the contact resistance between the substrate surface and the electrode. The resistance of the substrate for imparting strength is very large, and in order to reduce the overall resistance, the substrate resistance must be lowered.

シリコンの縦型半導体装置では、基板抵抗を極力小さくするために、エピタキシャル層表面に素子構造を形成した後、基板を数１０〜１００μｍ程度に研削し、裏面電極とのコンタクト抵抗を下げるために、裏面にイオン注入をした後に、レーザーアニールにより注入したイオンを活性化させ、コンタクト抵抗を下げている。   In the vertical semiconductor device of silicon, in order to reduce the substrate resistance as much as possible, after forming the element structure on the surface of the epitaxial layer, the substrate is ground to about several tens to 100 μm to reduce the contact resistance with the back electrode. After ion implantation on the back surface, the ions implanted by laser annealing are activated to lower the contact resistance.

ここで、基板裏面研削の前にエピタキシャル層表面に素子構造を形成している理由は、基板を数１０〜１００μｍ程度に研削したあとに、素子構造形成プロセス(熱工程、金属膜形成、酸化膜形成)を通してしまうと、歪みや熱膨張係数の違いにより、基板が割れてしまうという問題があるからである。   Here, the reason why the element structure is formed on the surface of the epitaxial layer before grinding the back surface of the substrate is that after the substrate is ground to about several tens to 100 μm, the element structure forming process (thermal process, metal film formation, oxide film) This is because the substrate is cracked due to differences in strain and thermal expansion coefficient.

同一の手法を炭化珪素（ＳｉＣ）基板を用いた素子に適応させた場合、ＳｉＣの活性化アニール温度が１６００℃程度であることから、表面に形成した酸化膜、電極などが損傷してしまう問題があった。   When the same technique is applied to an element using a silicon carbide (SiC) substrate, the activation annealing temperature of SiC is about 1600 ° C., so that the oxide film, electrode, etc. formed on the surface are damaged. was there.

また、レーザーアニール、パルスアニールのように基板最表面のみを加熱する手段を用いても、ＳｉＣの熱伝導係数が４．９Ｗ／ｃｍＫで銅（Ｃｕ）と同程度であり、対向する面（アニール面を裏面とした場合は“表面”）への熱損傷は不可避な問題であった。また、ＳｉＣにおいても、エピタキシャル層表面に素子構造を形成する前に、基板裏面研削を行うと、基板が割れてしまう問題がある。   Further, even when a means for heating only the uppermost surface of the substrate, such as laser annealing or pulse annealing, is used, the thermal conductivity coefficient of SiC is 4.9 W / cmK, which is similar to copper (Cu), and the opposite surface (annealing) When the surface was the back surface, thermal damage to the “front surface”) was an inevitable problem. Also, in SiC, there is a problem that if the substrate back surface grinding is performed before the element structure is formed on the surface of the epitaxial layer, the substrate is cracked.

上記の問題を解決するために、特許文献１では、シリコン基板上に縦型ＭＯＳＦＥＴとバイポーラトランジスタを混在させた半導体装置において、縦型ＭＯＳＦＥＴ形成部分の半導体基板の裏面に凹部を設け、凹部底面にドレイン電極を設けてオン抵抗を下げている。この例では、縦型ＭＯＳＦＥＴとバイポーラトランジスタの混在基板の局所に凹部を設けるので、基板全体の強度は確保されると思われるが、縦型ＭＯＳＦＥＴ単独の半導体装置を形成する場合、基板強度が低下する虞があった。   In order to solve the above problem, in Patent Document 1, in a semiconductor device in which a vertical MOSFET and a bipolar transistor are mixed on a silicon substrate, a recess is provided on the back surface of the semiconductor substrate in the vertical MOSFET forming portion, and the bottom surface of the recess is formed. A drain electrode is provided to lower the on-resistance. In this example, since the concave portion is provided locally on the mixed substrate of the vertical MOSFET and the bipolar transistor, it seems that the strength of the entire substrate is ensured, but the substrate strength is lowered when forming the semiconductor device of the vertical MOSFET alone. There was a fear.

また、特許文献２においては、炭化珪素基板を用いた縦型ＭＯＳＦＥＴにおいて、素子形成部の下部の基板裏面に凹部を設け、凹部底面にドレイン電極を形成して、オン抵抗を下げている。この例では、縦型ＭＯＳＦＥＴ単独の半導体装置において、基板に凹部を設けているが、基板の厚さ４００μｍに対して２００μｍ程度の深さの凹部を設けて基板強度を確保している。オン抵抗を充分に下げるために凹部の深さをさらに深くすると、基板強度が低下するという問題が予想される。
特開平９−１０２６０４号公報 特開２００３−３０３９６６号公報 Further, in Patent Document 2, in a vertical MOSFET using a silicon carbide substrate, a concave portion is provided on the back surface of the substrate below the element forming portion, and a drain electrode is formed on the bottom surface of the concave portion to reduce the on-resistance. In this example, in the semiconductor device having a single vertical MOSFET, the substrate is provided with a recess, but the substrate strength is ensured by providing a recess having a depth of about 200 μm with respect to the thickness of the substrate of 400 μm. If the depth of the recess is further increased in order to sufficiently reduce the on-resistance, a problem that the strength of the substrate is lowered is expected.
JP-A-9-102604 JP 2003-303966 A

本発明は上記事情に鑑みて為されたもので、基板抵抗の高い基板を用いた場合でも、基板強度確保しながら、電極引出し部の抵抗を下げることができる半導体装置の構成を提供することを目的とする。   The present invention has been made in view of the above circumstances, and provides a configuration of a semiconductor device capable of reducing the resistance of an electrode lead portion while ensuring the substrate strength even when a substrate having a high substrate resistance is used. Objective.

上記課題を解決するために、本発明の半導体装置は、網目状の凸部により形成された複数の凹部を裏面に有し、第１の不純物濃度を有する半導体からなる支持体と、前記支持体の前記裏面に対向する表面に形成され、前記第１の不純物濃度よりも低い第２の不純物濃度を有する半導体層と、前記半導体層に形成された半導体素子とを具備することを特徴とする。   In order to solve the above-described problems, a semiconductor device according to the present invention includes a support made of a semiconductor having a plurality of recesses formed on a back surface and having a first impurity concentration, and the support. And a semiconductor layer having a second impurity concentration lower than the first impurity concentration, and a semiconductor element formed in the semiconductor layer.

本発明では、網目状の凸部により形成された複数の凹部を基板裏面に設けて連続ワッフル状に加工し、裏面電極の少なくとも一部をワッフル凹部に形成する。網目状の凸部の壁面はお互いが繋がっているので、熱工程を通しても、あるいは基板（エピタキシャル層）表面に酸化膜、金属膜を形成しても、基板の反りを大幅に抑制することができる。これと同時に、ワッフル凹部はワッフル間凸部に比べ、エピタキシャル層までの厚みが薄い、若しくはゼロにできるので、基板抵抗を大幅に低減させることが可能となる。   In the present invention, a plurality of concave portions formed by mesh-like convex portions are provided on the back surface of the substrate and processed into a continuous waffle shape, and at least a part of the back surface electrode is formed in the waffle concave portion. Since the wall surfaces of the mesh-shaped convex portions are connected to each other, even if an oxide film or a metal film is formed on the surface of the substrate (epitaxial layer) through a thermal process, the warpage of the substrate can be greatly suppressed. . At the same time, the waffle recess can be made thinner or zero in thickness up to the epitaxial layer than the inter-waffle protrusion, so that the substrate resistance can be greatly reduced.

以下、本発明の実施の形態を図面を参照しつつ説明する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings.

（第１の実施形態）
図１は、本発明の第１の実施形態に係る半導体装置（ショットキーバリアダイオード）の摸式的な断面図、図２はその底面図で、図２のＡ−Ａ線に沿った断面図が図１に相当する。即ち裏面に複数の（この場合４個の）凹部（ワッフル部）が設けられた連続ワッフル基板を用いている。なお、上面図は矩形の基板中央に矩形の電極が形成されるだけなので省略する。 (First embodiment)
1 is a schematic cross-sectional view of a semiconductor device (Schottky barrier diode) according to a first embodiment of the present invention, FIG. 2 is a bottom view thereof, and a cross-sectional view along the line AA in FIG. Corresponds to FIG. That is, a continuous waffle substrate having a plurality of (in this case, four) concave portions (waffle portions) on the back surface is used. Note that the top view is omitted because only a rectangular electrode is formed at the center of the rectangular substrate.

より詳細には、図１に示すように、バルクＳｉＣからなる支持体２１の上にＳｉＣエピタキシャル層（低濃度層）３がホモエピタキシャル成長で形成されている。このＳｉＣエピタキシャル層３には、ショットキーバリアダイオード（ＳＢＤ）素子構造が形成されている。本実施形態では、バルクＳｉＣとエピタキシャル層３はｎ型である。エピタキシャル層３の裏面は、複数の凹部を有するＳｉＣ支持体２１の平面部により支持されており、バルクＳｉＣ支持体とエピタキシャル層３からなる基板１は、全体として連続ワッフル状に形成されている。エピタキシャル層３の上面には、エピタキシャル層３とショットキー接触をする表面電極１９が形成されており、裏面にはオーミックコンタクト層１３を介して裏面電極１７が形成されている。本実施形態では、オーミックコンタクト層１３はｎ型であり、表面電極１９と裏面電極１７の間にショットキーバリアダイオードが形成されている。   More specifically, as shown in FIG. 1, a SiC epitaxial layer (low concentration layer) 3 is formed by homoepitaxial growth on a support 21 made of bulk SiC. In this SiC epitaxial layer 3, a Schottky barrier diode (SBD) element structure is formed. In this embodiment, the bulk SiC and the epitaxial layer 3 are n-type. The back surface of the epitaxial layer 3 is supported by a plane portion of the SiC support 21 having a plurality of recesses, and the substrate 1 composed of the bulk SiC support and the epitaxial layer 3 is formed in a continuous waffle shape as a whole. A surface electrode 19 that makes a Schottky contact with the epitaxial layer 3 is formed on the upper surface of the epitaxial layer 3, and a back electrode 17 is formed on the rear surface via an ohmic contact layer 13. In this embodiment, the ohmic contact layer 13 is n-type, and a Schottky barrier diode is formed between the front surface electrode 19 and the back surface electrode 17.

エピタキシャル層３の上面には、表面電極１９との接触部を囲んで、終端構造であるリサーフ領域１２、ガードリング１４が形成されており、本実施形態では夫々ｐ型で形成されている。エピタキシャル層３の上面はＳｉ酸化層１５で覆われており、表面電極１９形成領域は選択的に開口され、ここに表面電極（第１の電極）１９が形成されている。エピタキシャル層３の裏面では、オーミックコンタクト層１３の上に裏面電極（第２の電極）１７が形成されている。裏面電極１７は、ＳｉＣ支持体２１の脚部底面にも形成されている。   On the upper surface of the epitaxial layer 3, a resurf region 12 and a guard ring 14, which are termination structures, are formed so as to surround a contact portion with the surface electrode 19, and each of them is formed in a p-type in this embodiment. The upper surface of the epitaxial layer 3 is covered with the Si oxide layer 15, the surface electrode 19 formation region is selectively opened, and the surface electrode (first electrode) 19 is formed here. On the back surface of the epitaxial layer 3, a back electrode (second electrode) 17 is formed on the ohmic contact layer 13. The back surface electrode 17 is also formed on the bottom surface of the leg portion of the SiC support 21.

第１の実施形態のショットキーバリアダイオードは、裏面に田の字型突起を有するバルクＳｉＣの支持体２１により強度が付与されており、エピタキシャル層３に形成されたダイオード素子は、裏面電極との距離が短いので、低オン抵抗が実現されている。   The Schottky barrier diode of the first embodiment is given strength by a bulk SiC support 21 having a U-shaped projection on the back surface, and the diode element formed in the epitaxial layer 3 is connected to the back electrode. Since the distance is short, low on-resistance is realized.

次に、第１の実施形態に係る半導体装置の製造方法を説明する。まず、図３に示すように、基板抵抗０．０２ΩｃｍのＳｉＣ基板２（n型）上に、ｎ型不純物濃度３．５×１０１５ｃｍ−３のエピタキシャル層３を１０μｍ成長させた基板（以下基板１と称する）を用意する。この基板１を硫酸と過酸化水素水の混酸で基板１に付着した有機汚れを除去し、純水によりリンスする。ついで、希塩酸と過酸化水素水の混酸で基板１に付着した金属不純物を除去し、純水によりリンスする。そして、最後に希フッ酸により基板１表面の自然酸化膜を除去し、純水によりリンスする。 Next, a method for manufacturing the semiconductor device according to the first embodiment will be described. First, as shown in FIG. 3, a substrate obtained by growing 10 μm of an epitaxial layer 3 having an n-type impurity concentration of 3.5 × 10 15 cm −3 on an SiC substrate 2 (n-type) having a substrate resistance of 0.02 Ωcm (hereinafter referred to as “the substrate”). (Referred to as substrate 1). The substrate 1 is removed of organic stains adhering to the substrate 1 with a mixed acid of sulfuric acid and hydrogen peroxide solution, and rinsed with pure water. Next, metal impurities adhering to the substrate 1 are removed with a mixed acid of dilute hydrochloric acid and hydrogen peroxide, and rinsed with pure water. Finally, the natural oxide film on the surface of the substrate 1 is removed with dilute hydrofluoric acid and rinsed with pure water.

この基板１を酸素雰囲気で、１１００℃において２時間加熱し、基板１表面を酸化し犠牲酸化膜５を形成する。この基板１の裏面にＴｉ膜７を５０ｎｍ成膜した後、Ａｌ膜９を２μｍ成膜する。ここでＴｉ膜７はＳｉＣ基板２とＡｌ膜９を密着させる密着層の役割を果たし、Ａｌ膜９は後のＳｉＣエッチングのエッチングマスクの役割を果たす。   The substrate 1 is heated in an oxygen atmosphere at 1100 ° C. for 2 hours to oxidize the surface of the substrate 1 to form a sacrificial oxide film 5. After a Ti film 7 having a thickness of 50 nm is formed on the back surface of the substrate 1, an Al film 9 having a thickness of 2 μm is formed. Here, the Ti film 7 serves as an adhesion layer for bringing the SiC substrate 2 and the Al film 9 into close contact, and the Al film 9 serves as an etching mask for later SiC etching.

このＡｌ膜９の表面に、図４に示すように２μｍ程度のレジスト１１をスピンコートし、ワッフル凹部を形成するためのパターンを、露光・現像により形成した後に、高温でハードベークをしてレジスト１１を焼き固める。このレジスト１１がパターニングされた基板１を塩素系ガスを用いるＲＩＥチャンバーに導入し、図５に示すように、パターニングされたレジスト１１をエッチングマスクとしてＡｌ膜９、Ｔｉ膜７をドライエッチングする。   As shown in FIG. 4, a resist 11 having a thickness of about 2 μm is spin-coated on the surface of the Al film 9, and a pattern for forming a waffle recess is formed by exposure and development, followed by hard baking at a high temperature. 11 is baked and hardened. The substrate 1 on which the resist 11 is patterned is introduced into an RIE chamber using a chlorine-based gas, and the Al film 9 and the Ti film 7 are dry-etched using the patterned resist 11 as an etching mask as shown in FIG.

ついで、パターニングされたＡｌ膜９をエッチングマスクとしてＳｉＣ基板２をＣＦ4とＯ2の混合ガスによりドライエッチングする。このプロセスを繰り返すことにより、レジスト開口部がワッフル形状の凹部となり、ＳｉＣ基板２が全てエッチングされ、図６に示すように、エピタキシャル層３が裏面に現れる。 Next, the SiC substrate 2 is dry-etched with a mixed gas of CF 4 and O 2 using the patterned Al film 9 as an etching mask. By repeating this process, the resist opening becomes a waffle-shaped recess, and the SiC substrate 2 is entirely etched, and the epitaxial layer 3 appears on the back surface as shown in FIG.

上記Ａｌ膜９の成膜方法は、電子銃蒸着法や、スパッタ、溶融めっきなどがあり、溶融めっきは、電子銃蒸着法やスパッタなどの真空蒸着法に比べ、厚膜のＡｌを得ることができる。溶融めっきの場合は、犠牲酸化膜により保護されたＳｉＣ基板裏面に鉄などを成膜し、溶融アルミ槽に基板を漬け込むことにより、ＳｉＣ基板裏面にアルミニウムの溶融めっき被膜を得る。この工程で、熱酸化による犠牲酸化膜上にさらに化学蒸着による酸化膜を１μｍ程度成膜し、Ａｒ雰囲気で１０００℃、３０分の酸化膜シンターを行って、蒸着した酸化膜を高密度化させると、保護膜としての機能を向上させることができる。   The Al film 9 can be formed by electron gun vapor deposition, sputtering, hot dipping, or the like, and hot dipping can obtain thicker Al than vacuum evaporation such as electron gun vapor deposition or sputtering. it can. In the case of hot dip plating, iron or the like is formed on the back surface of the SiC substrate protected by the sacrificial oxide film, and the hot dip plating film of aluminum is obtained on the back surface of the SiC substrate by immersing the substrate in a molten aluminum bath. In this step, an oxide film by chemical vapor deposition is further formed on the sacrificial oxide film by thermal oxidation to about 1 μm, and oxide film sintering is performed at 1000 ° C. for 30 minutes in an Ar atmosphere to increase the density of the deposited oxide film. And the function as a protective film can be improved.

この基板１を硫酸と過酸化水素水の混酸で洗浄し、基板１に付着したレジスト、金属を除去した後、純水によりリンスし、ＳｉＣ支持体２１の裏面に形成されていたＡｌ層９、Ｔｉ層７も除去し、純水によりリンスする。   The substrate 1 is washed with a mixed acid of sulfuric acid and hydrogen peroxide solution, the resist and metal adhering to the substrate 1 are removed, rinsed with pure water, and the Al layer 9 formed on the back surface of the SiC support 21. The Ti layer 7 is also removed and rinsed with pure water.

次に、基板１裏面に総ドーズ量７×１０15ｃｍ-2、最大加速エネルギー２００ｋｅＶにより、Ｐ（リン）イオンの多段注入を行い、図７に示すように裏面電極用のオーミックコンタクト領域１３を形成する。 Next, multistage implantation of P (phosphorus) ions is performed on the back surface of the substrate 1 with a total dose of 7 × 10 15 cm −2 and a maximum acceleration energy of 200 keV, and an ohmic contact region 13 for the back electrode is formed as shown in FIG. Form.

ついで、エピタキシャル層３の上面に、犠牲酸化膜５を介してイオン注入用マスク層（不図示）を成膜し、その上にレジスト膜（不図示）を成膜し、終端構造となるリサーフ領域、ガードリング領域をパターニングする。このレジストパターンをもとに、イオン注入マスク層をパターニングする。このイオン注入マスクを用いて、総ドーズ量１．５×１０13ｃｍ-2、最大加速エネルギー３００ｋｅＶによりアルミイオンの多段注入を行い、図８に示すように、リサーフ領域１２、ガードリング１４を形成する。 Next, a mask layer for ion implantation (not shown) is formed on the upper surface of the epitaxial layer 3 via the sacrificial oxide film 5, and a resist film (not shown) is formed thereon, so that a RESURF region serving as a termination structure is formed. The guard ring region is patterned. Based on this resist pattern, the ion implantation mask layer is patterned. Using this ion implantation mask, aluminum ions are subjected to multi-stage implantation with a total dose of 1.5 × 10 13 cm −2 and a maximum acceleration energy of 300 keV to form a resurf region 12 and a guard ring 14 as shown in FIG. To do.

この基板１を 硫酸と過酸化水素水の混酸で洗浄し、基板１に付着したレジスト、金属を除去した後、純水によりリンスする。ついで、希塩酸と過酸化水素水の混酸で基板に付着した微量の金属不純物を除去し、純水によりリンスする。そして、最後に希フッ酸により基板１表面の犠牲酸化膜５を除去し、純水によりリンスする。   The substrate 1 is washed with a mixed acid of sulfuric acid and hydrogen peroxide solution to remove the resist and metal adhering to the substrate 1 and then rinsed with pure water. Next, a trace amount of metal impurities adhering to the substrate is removed with a mixed acid of dilute hydrochloric acid and hydrogen peroxide, and rinsed with pure water. Finally, the sacrificial oxide film 5 on the surface of the substrate 1 is removed with dilute hydrofluoric acid and rinsed with pure water.

洗浄が終了した基板１を誘導加熱型の活性化アニール炉に導入し、到達真空度１×１０-4Ｐａまで真空にした後、不活性ガスであるＡｒで満たし、１６００℃、５分間の活性化アニールを行い図９に示す構造体を得る。 The cleaned substrate 1 is introduced into an induction heating type activation annealing furnace, evacuated to an ultimate vacuum of 1 × 10 −4 Pa, filled with Ar as an inert gas, and activated at 1600 ° C. for 5 minutes. An annealing process is performed to obtain the structure shown in FIG.

ついで、再び基板１表面を熱酸化した後に、図１０に示すように、ＣＶＤにより基板１表面に１μｍのＳｉ酸化膜（ＳｉＯ2）膜１５を成膜し、Ａｒ雰囲気中１０００℃でＳｉ酸化膜をシンターする。さらに、図１１に示すように、基板１の裏面に裏面電極１７となるＮｉ膜を電子銃蒸着により成膜し、Ａｒ雰囲気中１０００℃、１分間のシンターを行い、オーミックコンタクト領域１３と裏面電極１７とをオーミックコンタクトさせる。 Next, after thermally oxidizing the surface of the substrate 1 again, as shown in FIG. 10, a 1 μm Si oxide film (SiO 2 ) film 15 is formed on the surface of the substrate 1 by CVD, and an Si oxide film is formed at 1000 ° C. in an Ar atmosphere. Sinter. Further, as shown in FIG. 11, a Ni film to be the back electrode 17 is formed on the back surface of the substrate 1 by electron gun vapor deposition, and sintering is performed in an Ar atmosphere at 1000 ° C. for 1 minute, so that the ohmic contact region 13 and the back electrode 17 is in ohmic contact.

ついで、基板１裏面をレジストにより保護した後、基板表面のＳｉ酸化膜１５表面にレジスト（不図示）を塗布し、表面電極形成領域上をパターニングにより開口させる。ついで、ＣＦ4とＯ2のＲＩＥによりＳｉ酸化膜１５をエッチングし、さらに希フッ酸により基板最表面の自然酸化膜を除去し、表面電極１９となるＴｉ膜を成膜し、不要部分をレジストパターニングとＲＩＥにより除去する。このプロセスにより、図１に示すような基板裏面が連続ワッフル状に加工されたＳｉＣのショットキーバリアダイオード（ＳＢＤ）が形成される。 Next, after protecting the back surface of the substrate 1 with a resist, a resist (not shown) is applied to the surface of the Si oxide film 15 on the surface of the substrate, and an opening is formed on the surface electrode formation region by patterning. Next, the Si oxide film 15 is etched by RIE of CF 4 and O 2 , the natural oxide film on the outermost surface of the substrate is removed by dilute hydrofluoric acid, a Ti film to be the surface electrode 19 is formed, and unnecessary portions are resisted. It is removed by patterning and RIE. Through this process, a SiC Schottky barrier diode (SBD) is formed in which the back surface of the substrate is processed into a continuous waffle shape as shown in FIG.

本実施形態のＳＢＤ素子のオン抵抗は１．２Ωｃｍ2であり、耐圧は１０００Ｖであった。裏面基板がワッフル状でない普通の基板の場合、耐圧は同様に１０００Ｖであるが、オン抵抗は２ｍΩｃｍ2であり、これに比べてワッフル状に加工した素子のオン抵抗は４０％低減していることがわかった。 The on-resistance of the SBD element of this embodiment was 1.2 Ωcm 2 and the withstand voltage was 1000V. When the back substrate is a normal substrate that is not waffle-shaped, the withstand voltage is similarly 1000 V, but the on-resistance is 2 mΩcm 2. Compared with this, the on-resistance of the element processed into a waffle is reduced by 40%. I understood.

さらに、図１２に示すように、1素子に対し、ワッフル凹部が1つである(つまり、ダイシングライン２３に沿ってワッフル凸部２１が形成されているのみ)であると、ダイシングの際に凸部２１が欠けてしまい、素子全体が壊れてしまう危険性がある。そこで、本実施例の如く、図１３に示すように1素子に対しワッフル凹部を２つ以上にすると、素子の破壊を防止することができる。本実施例では基板裏面凸部を田の字型としたが、本発明はこれに限らず、裏面凸部の形状を“日の字”、“田の字”、“囲の字”のようにし、ダイシングライン２３よりも内側にワッフル凸部２１を多数形成し、補強すると更によい。図１４にワッフル凸部２１を多数形成した場合の模式的な斜視図を示す。また、図１３に示すようにダイシングラインより内側の面積で規定される素子面積（Ａ）とワッフルの凹部面積の総計（Ｂ）の関係は、ワッフル凹部の総計平面積（Ｂ）≦素子面積（Ａ）である。これらの事項は、第２の実施形態以降についても適用される。なお、図１２，１３で凸部２１の形状をテーパー形状としたが、これについては第２の実施形態で説明する。   Furthermore, as shown in FIG. 12, if one element has one waffle concave portion (that is, only the waffle convex portion 21 is formed along the dicing line 23), the convex portion is formed during dicing. There is a risk that the part 21 is missing and the entire device is broken. Thus, as in this embodiment, if two or more waffle recesses are provided for one element as shown in FIG. 13, the element can be prevented from being destroyed. In the present embodiment, the convex portion on the back surface of the substrate has a square shape, but the present invention is not limited to this, and the shape of the convex portion on the back surface is such as “day letter”, “field letter”, “enclosed letter”. It is further preferable to form a large number of waffle projections 21 inside the dicing line 23 and reinforce them. FIG. 14 shows a schematic perspective view when a large number of waffle convex portions 21 are formed. Moreover, as shown in FIG. 13, the relationship between the element area (A) defined by the area inside the dicing line and the total of the concave area of the waffle (B) is as follows. A). These items are also applied to the second and subsequent embodiments. In addition, although the shape of the convex part 21 was made into the taper shape in FIG. 12, 13, this is demonstrated in 2nd Embodiment.

また、本実施形態ではワッフル凹部はＳｉＣ基板２の全てをエッチングにより取り除いたが、図１５に示すように、ＳｉＣ基板２部分が一部残っていても構わない。図１５（ａ）は、第１の実施形態の変形例であり、図１５（ｂ）は後述の第２の実施形態でＳｉＣ支持体２１の凹部にテーパを設けた場合の変形例である。凹部底面のコンタクト層１３がＳｉＣ基板２に設けられる他は、図１と基本的に同じである。この場合、基板の残り量と基板抵抗はリニアの関係にあり、残り量が多いほど基板抵抗が上がってしまうが、基板強度がその分上がる利点がある。素子の設計および、要求性能により、使用者が凹部の残し量を勘案することができる。これは、第２〜第６の実施形態についても適用されるものである。   Further, in this embodiment, the waffle concave portion is formed by removing all of the SiC substrate 2 by etching, but a part of the SiC substrate 2 may remain as shown in FIG. FIG. 15A is a modification of the first embodiment, and FIG. 15B is a modification in the case where a taper is provided in the concave portion of the SiC support 21 in the second embodiment described later. 1 is basically the same as that of FIG. 1 except that the contact layer 13 on the bottom surface of the recess is provided on the SiC substrate 2. In this case, the remaining amount of the substrate and the substrate resistance are in a linear relationship, and as the remaining amount increases, the substrate resistance increases, but there is an advantage that the substrate strength increases accordingly. Depending on the design of the element and the required performance, the user can consider the remaining amount of the recess. This is also applied to the second to sixth embodiments.

また、第１の実施形態では、ＳｉＣエッチングのマスク材としてアルミニウムの例を挙げたが、ＳｉＣとのエッチングレートに充分な差があればよく、材料、成膜方法には依存しない。アルミニウム以外では、例えば厚膜レジストでパターニングしたＳｉＣ基板裏面に、無電解めっき法でＮｉやＣｕを成膜し、アセトンによりレジスト部分とその上のＮｉ（Ｃｕ）をリフトオフすることで、ワッフルを形成するエッチングマスクを形成し、ＣＦ4 等のエッチングガスでＲＩＥしても構わない。 In the first embodiment, aluminum is used as an example of a mask material for SiC etching. However, it is sufficient that there is a sufficient difference in etching rate with SiC, and it does not depend on the material and the film forming method. Other than aluminum, for example, Ni or Cu is formed by electroless plating on the back side of a SiC substrate patterned with a thick film resist, and waffles are formed by lifting off the resist portion and Ni (Cu) thereon using acetone. An etching mask to be formed may be formed, and RIE may be performed with an etching gas such as CF 4 .

（第２の実施形態）
図１６は、本発明の第２の実施形態に係るショットキバリアダイオード（ＳＢＤ）の断面図である。第２の実施形態が第１の実施形態と異なる点は、ＳｉＣ支持体２１の凹部側面がテーパを持って形成されていることである。このように形成することにより、ＳｉＣ支持体２１の強度を増加させることができるとともに、裏面コンタクト面積を増やすことができる。 (Second Embodiment)
FIG. 16 is a cross-sectional view of a Schottky barrier diode (SBD) according to the second embodiment of the present invention. The second embodiment is different from the first embodiment in that the side surface of the concave portion of the SiC support 21 is formed with a taper. By forming in this way, the strength of the SiC support 21 can be increased and the back contact area can be increased.

次に、第２の実施形態のＳＢＤの製造方法を説明する。第１の実施形態と同一部分には同一番号を付し、重複する説明を省略する。まず、第１の実施形態の図３乃至図５までの工程を同一条件で実施する。ついで、図１７に示すように、パターニングされたＡｌ膜９をエッチングマスクとしてＳｉＣ基板２をＣＦ4とＯ2の混合ガスによりドライエッチングする。このプロセスにより、レジストパターニングで開口した部分がワッフル形状の凹部となり、ＳｉＣ基板２が全てエッチングされ、エピタキシャル層が表面に現れる。本実施形態ではテーパ形状のワッフル凹部を形成するが、エッチャントガスのガス圧を高くすると、横方向のエッチング量が増加する性質を利用して、ワッフル凹部にテーパ形状を形成することができる。この基板１を硫酸と過酸化水素水の混酸で洗浄し、基板１に付着したレジスト、金属を除去した後、純水によりリンスし、ＳｉＣ支持体２１の裏面に形成されていたＡｌ層９、Ｔｉ層７も除去し、純水によりリンスする。 Next, a method for manufacturing the SBD of the second embodiment will be described. The same parts as those in the first embodiment are denoted by the same reference numerals, and redundant description is omitted. First, the steps from FIG. 3 to FIG. 5 of the first embodiment are performed under the same conditions. Next, as shown in FIG. 17, the SiC substrate 2 is dry-etched with a mixed gas of CF 4 and O 2 using the patterned Al film 9 as an etching mask. By this process, a portion opened by resist patterning becomes a waffle-shaped recess, and the SiC substrate 2 is entirely etched, and an epitaxial layer appears on the surface. In the present embodiment, the tapered waffle recess is formed. However, when the gas pressure of the etchant gas is increased, the tapered shape can be formed in the waffle recess by utilizing the property that the etching amount in the lateral direction increases. The substrate 1 is washed with a mixed acid of sulfuric acid and hydrogen peroxide solution, the resist and metal adhering to the substrate 1 are removed, rinsed with pure water, and the Al layer 9 formed on the back surface of the SiC support 21. The Ti layer 7 is also removed and rinsed with pure water.

次に、図１８に示すように、基板１裏面に総ドーズ量７×１０15ｃｍ-2、最大加速エネルギー２００ｋｅＶにより、Ｐ（リン）イオンの多段注入を行い、裏面電極のオーミックコンタクト層１３を形成する。この時、ワッフル凹部がテーパー形状となっていることにより、オーミックコンタクト層１３がワッフルの側壁にも成膜され、基板最底部(裏面最表面)までオーミックコンタクト層１３が連続して成膜されることになる。 Next, as shown in FIG. 18, multistage implantation of P (phosphorus) ions is performed on the back surface of the substrate 1 with a total dose of 7 × 10 15 cm −2 and a maximum acceleration energy of 200 keV, and the ohmic contact layer 13 of the back electrode is formed. Form. At this time, since the waffle recess has a tapered shape, the ohmic contact layer 13 is also formed on the side wall of the waffle, and the ohmic contact layer 13 is continuously formed to the bottom of the substrate (back surface). It will be.

次に、第１の実施形態と同様に、エピタキシャル層３の上面に、図１９に示すように、リサーフ領域１２、ガードリング１４を形成する。ついで、この基板１を第１の実施形態と同様な表面処理・洗浄工程に供し、洗浄が終了した基板１を誘導加熱型の活性化アニール炉中で活性化アニールを行い、図２０に示す構造体を得る。   Next, as in the first embodiment, the RESURF region 12 and the guard ring 14 are formed on the upper surface of the epitaxial layer 3 as shown in FIG. Next, the substrate 1 is subjected to the same surface treatment / cleaning process as in the first embodiment, and the substrate 1 that has been cleaned is subjected to activation annealing in an induction heating type activation annealing furnace, and the structure shown in FIG. Get the body.

ついで、図２１に示すように、再び基板１表面にＳｉ酸化膜（ＳｉＯ2）膜１５を成膜し、このＳｉ酸化膜をシンターする。さらに、図２２に示すように、基板１の裏面に裏面電極１７となるＮｉ膜を電子銃蒸着により成膜し、シンターを行ってオーミックコンタクト領域１３と裏面電極１７とをオーミックコンタクトさせる。この時、ワッフル凹部がテーパ形状となっていることで、裏面オーミックコンタクト層１３にコンタクトしたＮｉ膜がワッフルの側壁にも成膜され、基板最底部(裏面最表面)まで裏面電極１７が連続して成膜されることになる。この形状を取ることにより、裏面電極１７との接続を基板最底部で行うことができる。 Next, as shown in FIG. 21, an Si oxide film (SiO 2 ) film 15 is again formed on the surface of the substrate 1, and this Si oxide film is sintered. Further, as shown in FIG. 22, a Ni film to be the back electrode 17 is formed on the back surface of the substrate 1 by electron gun vapor deposition, and the ohmic contact region 13 and the back electrode 17 are brought into ohmic contact by sintering. At this time, since the waffle recess has a tapered shape, the Ni film in contact with the back ohmic contact layer 13 is also formed on the side wall of the waffle, and the back electrode 17 continues to the bottom of the substrate (back surface top surface). The film is formed. By adopting this shape, connection to the back electrode 17 can be performed at the bottom of the substrate.

ついで、裏面をレジストにより保護した後、表面のＳｉ酸化膜１５表面を選択的に開口させ、基板最表面の自然酸化膜を除去し、ショットキー電極であるＴｉを成膜し、不要部分をパターニングとＲＩＥにより除去する。このプロセスにより、図１６に示すような基板裏面が連続ワッフル状に加工されたＳｉＣのショットキーバリアダイオードが形成される。   Next, after protecting the back surface with a resist, the surface of the Si oxide film 15 on the front surface is selectively opened, the natural oxide film on the outermost surface of the substrate is removed, Ti that is a Schottky electrode is formed, and unnecessary portions are patterned. And removed by RIE. By this process, a SiC Schottky barrier diode in which the back surface of the substrate is processed into a continuous waffle shape as shown in FIG. 16 is formed.

本素子のオン抵抗は１．２ｍΩｃｍ2であり、耐圧は１０００Ｖであった。参考として、裏面基板がワッフル状でない、普通の基板の場合、耐圧は同様に１０００Ｖであるが、オン抵抗は２ｍΩｃｍ2であり、これに対しワッフル状に加工した素子のオン抵抗が４０％低減していることがわかった。 The on-resistance of this element was 1.2 mΩcm 2 and the withstand voltage was 1000V. For reference, in the case of a normal substrate where the back substrate is not waffle, the withstand voltage is similarly 1000 V, but the on-resistance is 2 mΩcm 2. On the other hand, the on-resistance of the element processed into a waffle is reduced by 40%. I found out.

（第３の実施形態）
図２３は、本発明の第３の実施形態に係る静電誘導型トランジスタ（ＳＩＴ）の断面図で、図２４に示す上面図のＢ−Ｂ線に沿った断面図である。なお、底面図は、テーパ部分を除いて図２と同様となるので省略する。また、本実施例は接合型電界効果トランジスタ（ＪＦＥＴ）にも、略そのまま適用することができる。 (Third embodiment)
FIG. 23 is a cross-sectional view of the electrostatic induction transistor (SIT) according to the third embodiment of the present invention, and is a cross-sectional view taken along line BB of the top view shown in FIG. Note that the bottom view is the same as FIG. Further, the present embodiment can be applied almost directly to a junction field effect transistor (JFET).

より詳細には、図２３において、バルクＳｉＣからなる支持体２１の上に形成されたＳｉＣエピタキシャル層（低濃度層）３にＳＩＴ若しくはＪＦＥＴの複数のユニット素子が並列に形成されている。本実施形態では、バルクＳｉＣとエピタキシャル層３はｎ型である。エピタキシャル層３の裏面は、複数の凹部を有するＳｉＣ支持体２１により支持されており、バルクＳｉＣ支持体２１とエピタキシャル層３からなる基板１には、複数のワッフルが連続的に形成されている。エピタキシャル層３の上面には、ソース領域２５、ゲート領域２７が形成されており、裏面にはオーミックコンタクト層１３を介してドレイン電極となる裏面電極１７が形成されている。本実施形態では、ソース領域２５はｎ型であり、ゲート領域２７はｐ型である。   More specifically, in FIG. 23, a plurality of SIT or JFET unit elements are formed in parallel on a SiC epitaxial layer (low concentration layer) 3 formed on a support 21 made of bulk SiC. In this embodiment, the bulk SiC and the epitaxial layer 3 are n-type. The back surface of the epitaxial layer 3 is supported by a SiC support 21 having a plurality of recesses, and a plurality of waffles are continuously formed on the substrate 1 composed of the bulk SiC support 21 and the epitaxial layer 3. A source region 25 and a gate region 27 are formed on the upper surface of the epitaxial layer 3, and a back electrode 17 serving as a drain electrode is formed on the back surface via an ohmic contact layer 13. In the present embodiment, the source region 25 is n-type and the gate region 27 is p-type.

エピタキシャル層３の上面には、ゲート領域２７を囲んで、終端構造であるリサーフ層１２、ガードリング１４が形成されており、本実施形態では夫々ｐ型で形成されている。エピタキシャル層３の上面はＳｉ酸化層１５で覆われており、表面電極であるソース電極１９ｓ、ゲート電極１９ｇが、Ｓｉ酸化膜１５に選択的に形成された開口部に夫々設けられている。エピタキシャル層３の裏面には、オーミックコンタクト層１３の上に裏面電極（ドレイン電極）１７が形成されている。裏面電極１７は、ＳｉＣ支持体２１の内部側面傾斜部及び底面にも形成されている。   On the upper surface of the epitaxial layer 3, the RESURF layer 12 and the guard ring 14, which are termination structures, are formed so as to surround the gate region 27, and in this embodiment, each is formed of a p-type. The upper surface of the epitaxial layer 3 is covered with a Si oxide layer 15, and a source electrode 19 s and a gate electrode 19 g as surface electrodes are provided in openings selectively formed in the Si oxide film 15, respectively. A back electrode (drain electrode) 17 is formed on the ohmic contact layer 13 on the back surface of the epitaxial layer 3. The back electrode 17 is also formed on the inner side inclined portion and the bottom surface of the SiC support 21.

第３の実施形態のＳＩＴ若しくはＪＦＥＴは、バルクＳｉＣの支持体２１により強度が付与されており、アクティブ領域はエピタキシャル層３に形成され、裏面電極１７との距離が短いので、低オン抵抗が実現されている。   In the SIT or JFET of the third embodiment, the strength is given by the bulk SiC support 21, the active region is formed in the epitaxial layer 3, and the distance from the back electrode 17 is short, so low on-resistance is realized. Has been.

次に、第３の実施形態のＳＩＴ（ＪＦＥＴ）の製造方法を説明する。第１および第２の実施形態と同一部分には同一番号を付し、重複する説明を省略する。第２の実施形態の図１９の工程までを同様に実施する。ついで、図２５に示すように、表面のソース領域２５、をイオン注入により形成するために、イオン注入用マスク（不図示）を形成し、イオン注入を行なう。ソース領域２５には、総ドーズ量７×１０15ｃｍ-2、最大加速エネルギー２００ｋｅＶのＰ（リン）の多段注入によりボックスプロファイルを持たせる。同様にして、ゲート領域２７にはＡｌイオンを注入するが、ソース領域より高エネルギーでイオン注入し、ソース領域より深くゲート領域を形成する。ここでは、イオン注入用マスクに酸化膜を用い、この酸化膜をＲＩＥによりエッチングする。 Next, a method for manufacturing the SIT (JFET) of the third embodiment will be described. The same parts as those in the first and second embodiments are denoted by the same reference numerals, and redundant description is omitted. The process up to the process of FIG. 19 of the second embodiment is similarly performed. Next, as shown in FIG. 25, in order to form the source region 25 on the surface by ion implantation, an ion implantation mask (not shown) is formed and ion implantation is performed. The source region 25 is given a box profile by multistage implantation of P (phosphorus) with a total dose of 7 × 10 15 cm −2 and a maximum acceleration energy of 200 keV. Similarly, Al ions are implanted into the gate region 27, but ions are implanted with higher energy than the source region to form a gate region deeper than the source region. Here, an oxide film is used as an ion implantation mask, and this oxide film is etched by RIE.

表面の終端領域１２，１４、ソース領域２５、ゲート領域２７のイオン注入が終了した後、図２６に示すように、ＳｉＣ支持体２１裏面のＡｌ膜９、Ｔｉ膜７を除去し、硫酸と過酸化水素水の混酸により基板表面に付着したイオン注入用マスクを除去した後、希フッ酸により基板表面の犠牲酸化膜５等を除去し水洗する。   After the ion implantation of the termination regions 12 and 14 on the surface, the source region 25, and the gate region 27 is completed, as shown in FIG. 26, the Al film 9 and the Ti film 7 on the back surface of the SiC support 21 are removed, After removing the ion implantation mask attached to the substrate surface with a mixed acid of hydrogen oxide water, the sacrificial oxide film 5 and the like on the substrate surface are removed with diluted hydrofluoric acid and washed with water.

洗浄が終了した基板を誘導加熱型の活性化アニール炉に導入し、到達真空度１×１０-4Ｐａまで真空にした後、不活性ガスであるＡｒで満たし、１６００℃、５分間の活性化アニールを行う。 The substrate after cleaning is introduced into an induction heating type activation annealing furnace, evacuated to an ultimate vacuum of 1 × 10 −4 Pa, filled with Ar as an inert gas, and activated at 1600 ° C. for 5 minutes. Annealing is performed.

再び基板表面を熱酸化した後に、図２７に示すように、ＣＶＤにより基板表面に１μｍのＳｉ酸化膜１５を成膜し、Ａｒ雰囲気中で１０００℃でＳｉ酸化膜１５をシンターする。   After the substrate surface is thermally oxidized again, as shown in FIG. 27, a 1 μm Si oxide film 15 is formed on the substrate surface by CVD, and the Si oxide film 15 is sintered at 1000 ° C. in an Ar atmosphere.

この基板の表面のソースコンタクト部分およびゲートコンタクト部分にあたるＳｉ酸化膜１５を、図２８に示すようにエッチングにより除去し、電子銃蒸着によりソースコンタクト部分に選択的にＮｉ膜を成膜してソース電極１９ｓを形成し、ゲートコンタクト部分にはＮｉ膜を成膜してゲート電極１９ｇを形成する。さらに裏面にＮｉ膜を電子銃蒸着により成膜して裏面電極（ドレイン電極）１７を形成し、Ａｒ雰囲気中、１０００℃、１分間のシンターを行い、ソース電極１９ｓ、ゲート電極１９ｇ、裏面電極１７を夫々のコンタクト領域にオーミックコンタクトさせる。このプロセスにより、図２３に示すような基板裏面が連続ワッフル状に加工されたＳｉＣのＳＩＴ（あるいはＪＦＥＴ）が形成される。ここでは、ソース電極、ゲート電極、ドレイン電極ともにＮｉを成膜したが、ゲート電極にＡｌを用いると、ゲートコンタクト抵抗がさらに下がり、スイッチングスピードが向上する。   The Si oxide film 15 corresponding to the source contact portion and the gate contact portion on the surface of the substrate is removed by etching as shown in FIG. 28, and a Ni film is selectively formed on the source contact portion by electron gun evaporation to form a source electrode. 19s is formed, and a Ni film is formed on the gate contact portion to form a gate electrode 19g. Further, a Ni film is formed on the back surface by electron gun vapor deposition to form a back electrode (drain electrode) 17, and sintering is performed at 1000 ° C. for 1 minute in an Ar atmosphere. The source electrode 19s, the gate electrode 19g, and the back electrode 17 Are brought into ohmic contact with the respective contact regions. By this process, an SIT (or JFET) of SiC in which the back surface of the substrate is processed into a continuous waffle shape as shown in FIG. 23 is formed. Here, Ni is formed on the source electrode, the gate electrode, and the drain electrode. However, when Al is used for the gate electrode, the gate contact resistance is further lowered and the switching speed is improved.

本素子のオン抵抗は５ｍΩｃｍ2であり、耐圧は１０００Ｖであった。参考のため、裏面基板がワッフル状でない、普通の基板の場合、耐圧は同様に１０００Ｖであるものの、オン抵抗は５．８ｍΩｃｍ2であり、ワッフル状に加工した素子のオン抵抗が０．８ｍΩｃｍ2低減していることがわかる。 The on-resistance of this element was 5 mΩcm 2 and the withstand voltage was 1000V. For reference, in the case of a normal substrate in which the back substrate is not waffle, the withstand voltage is similarly 1000 V, but the on-resistance is 5.8 mΩcm 2 , and the on-resistance of the element processed into the waffle is 0.8 mΩcm 2. It can be seen that there is a reduction.

（第４の実施形態）
図２９は、本発明の第４の実施形態に係るＭＯＳＦＥＴの断面図で、図３０に示す上面図のＣ−Ｃ線に沿った断面図である。底面図は第１の実施形態の図２とテーパ部分を除いて同じになるので省略する。 (Fourth embodiment)
FIG. 29 is a cross-sectional view of the MOSFET according to the fourth embodiment of the present invention, and is a cross-sectional view taken along line CC in the top view shown in FIG. Since the bottom view is the same as FIG. 2 of the first embodiment except for the tapered portion, it is omitted.

本実施形態のＭＯＳＦＥＴは、バルクＳｉＣからなる支持体２１の上に形成されたＳｉＣエピタキシャル層（低濃度層）３にＭＯＳＦＥＴの複数のユニット素子が並列に形成されている。本実施形態では、バルクＳｉＣとエピタキシャル層３はｎ型である。エピタキシャル層３の裏面は、複数の凹部を備えたＳｉＣ支持体２１により支持されたており、バルクＳｉＣ支持体２１とエピタキシャル層３からなる基板１には複数のワッフルが連続的に形成されている。エピタキシャル層３の上面には、ｐ型ウェル２９に形成されたｎ型のソース領域２５、ゲート絶縁膜３１を介して形成されたゲート電極１９ｇが形成されており、裏面にはオーミックコンタクト層１３を介してドレイン電極となる裏面電極１７が形成されている。   In the MOSFET of this embodiment, a plurality of unit elements of the MOSFET are formed in parallel on a SiC epitaxial layer (low concentration layer) 3 formed on a support 21 made of bulk SiC. In this embodiment, the bulk SiC and the epitaxial layer 3 are n-type. The back surface of the epitaxial layer 3 is supported by a SiC support 21 having a plurality of recesses, and a plurality of waffles are continuously formed on the substrate 1 composed of the bulk SiC support 21 and the epitaxial layer 3. . An n-type source region 25 formed in a p-type well 29 and a gate electrode 19g formed through a gate insulating film 31 are formed on the upper surface of the epitaxial layer 3, and an ohmic contact layer 13 is formed on the rear surface. A back electrode 17 serving as a drain electrode is formed therebetween.

エピタキシャル層３の上面には、ｐ型ウェル２９を囲んで、終端構造であるリサーフ層１２、ガードリング１４が形成されており、本実施形態では夫々ｐ型で形成されている。エピタキシャル層３の上面はＳｉ酸化層１５で覆われており、表面電極であるソース電極１９ｓ、ゲート電極１９ｇ形成領域は選択的に開口され、ここに夫々の電極が形成されている。エピタキシャル層３の裏面では、オーミックコンタクト層１３の上に裏面電極（ドレイン電極）１７が形成されている。裏面電極１７は、ＳｉＣ支持体２１の内部側面及び底面にも形成されている。   On the upper surface of the epitaxial layer 3, the RESURF layer 12 and the guard ring 14, which are termination structures, are formed so as to surround the p-type well 29, and in this embodiment, each is formed of p-type. The upper surface of the epitaxial layer 3 is covered with a Si oxide layer 15, and the source electrode 19s and gate electrode 19g forming regions which are surface electrodes are selectively opened, and the respective electrodes are formed therein. On the back surface of the epitaxial layer 3, a back electrode (drain electrode) 17 is formed on the ohmic contact layer 13. The back electrode 17 is also formed on the inner side surface and the bottom surface of the SiC support 21.

第４の実施形態のＭＯＳＦＥＴは、バルクＳｉＣの支持体２１により強度が付与されており、アクティブ領域は低抵抗のエピタキシャル層３に形成され、裏面電極１７との距離が短いので、低オン抵抗が実現されている。   In the MOSFET of the fourth embodiment, the strength is given by the bulk SiC support 21, the active region is formed in the low-resistance epitaxial layer 3, and the distance from the back electrode 17 is short, so that the low on-resistance is low. It has been realized.

次に、第４の実施形態のＭＯＳＦＥＴの製造方法を説明する。第１および第２の実施形態と同一部分には同一番号を付し、重複する説明を省略する。第２の実施形態の図１９の工程までを同様に実施する。   Next, a method for manufacturing the MOSFET of the fourth embodiment will be described. The same parts as those in the first and second embodiments are denoted by the same reference numerals, and redundant description is omitted. The process up to the process of FIG. 19 of the second embodiment is similarly performed.

ついで、表面のp型ウェル領域２９をイオン注入により形成するために、イオン注入用マスク（不図示）を成膜し、その表面にレジストを塗布、パターニングする。このパターンが転写されたレジストをイオン注入用マスクのエッチングマスクとして用いてイオン注入用マスクをエッチングする。次に、図３１に示すように、ウェル領域２９にp型の導電性を持たせるために、Ａｌイオンを注入する。   Next, in order to form the p-type well region 29 on the surface by ion implantation, an ion implantation mask (not shown) is formed, and a resist is applied to the surface and patterned. The ion implantation mask is etched using the resist to which this pattern is transferred as an etching mask for the ion implantation mask. Next, as shown in FIG. 31, Al ions are implanted to make the well region 29 have p-type conductivity.

さらに、表面のｐ型コンタクト領域３０をイオン注入により形成するために、イオン注入用マスクを成膜し、その表面にレジストを塗布、パターニングする。このパターンが転写されたレジストを、イオン注入用マスクのエッチングマスクとして用いて、イオン注入用マスクをエッチングで作成する。このコンタクト領域３０はｐ型の導電性を持たせるためにＡｌイオンを注入し、ウェル領域よりも高濃度に形成される。   Further, in order to form the p-type contact region 30 on the surface by ion implantation, an ion implantation mask is formed, and a resist is applied to the surface and patterned. Using the resist to which this pattern is transferred as an etching mask for the ion implantation mask, an ion implantation mask is formed by etching. This contact region 30 is formed at a higher concentration than the well region by implanting Al ions to provide p-type conductivity.

同様に、ソース領域２５にはＰ（リン）イオンを注入する。ソース領域２５はp型ウェル領域２９よりも浅い領域に形成されている。ここでは、イオン注入用マスクに酸化膜を用い、この酸化膜をエッチングするためにＣＦ4とＯ2の混合ガスによるＲＩＥを用いる。 Similarly, P (phosphorus) ions are implanted into the source region 25. The source region 25 is formed in a region shallower than the p-type well region 29. Here, an oxide film is used as an ion implantation mask, and RIE using a mixed gas of CF 4 and O 2 is used to etch the oxide film.

表面の終端領域、p型ウェル領域２９、ソース領域２５のイオン注入が終了した後、ＳｉＣ支持体２１の裏面に形成されたＡｌ膜９、Ｔｉ膜７を除去し、硫酸と過酸化水素水の混酸により基板表面に付着したイオン注入用マスク(Ｍｏ)を除去した後、希フッ酸により犠牲酸化膜５等を除去し水洗する。   After ion implantation of the surface termination region, p-type well region 29, and source region 25 is completed, the Al film 9 and Ti film 7 formed on the back surface of the SiC support 21 are removed, and sulfuric acid and hydrogen peroxide solution are removed. After removing the ion implantation mask (Mo) adhering to the substrate surface by the mixed acid, the sacrificial oxide film 5 and the like are removed by dilute hydrofluoric acid and washed with water.

洗浄が終了した基板を誘導加熱型の活性化アニール炉に導入し、到達真空度１×１０-4Ｐａまで真空とした後、不活性ガスであるＡｒで満たし、１６００℃、５分間の活性化アニールを行い、図３２に示す構造体を得る。 The substrate after cleaning is introduced into an induction heating type activation annealing furnace, evacuated to an ultimate vacuum of 1 × 10 −4 Pa, filled with Ar as an inert gas, and activated at 1600 ° C. for 5 minutes. Annealing is performed to obtain the structure shown in FIG.

再び基板表面を熱酸化した後に、図３３に示すようにＣＶＤにより基板表面に１μｍのＳｉ酸化膜１５を成膜し、Ａｒ雰囲気中１０００℃でＳｉ酸化膜１５をシンターする。ついで図３４に示すように、この基板の表面のソースコンタクト部分および、ゲート領域にあたるＳｉ酸化膜１５をエッチングにより除去する。   After thermally oxidizing the substrate surface again, as shown in FIG. 33, a 1 μm Si oxide film 15 is formed on the substrate surface by CVD, and the Si oxide film 15 is sintered at 1000 ° C. in an Ar atmosphere. Next, as shown in FIG. 34, the source contact portion on the surface of the substrate and the Si oxide film 15 corresponding to the gate region are removed by etching.

ついで、図３５に示すように、この基板を再び熱酸化させたのち、ＣＶＤ酸化膜を成膜し、パターニングによりゲート絶縁膜３１を形成する。次に、ソース領域にあるＳｉ酸化膜１５を除去し、ソース領域および絶縁ゲート領域に選択的にＮｉ膜を成膜し、ソース電極１９ｓ、ゲート電極１９ｇを形成する。さらに裏面にＮｉ膜を電子銃蒸着により成膜して裏面電極（ドレイン電極）１７を形成し、Ａｒ雰囲気中１０００℃で１分間のシンターを行い、ソース電極１９ｓ、ゲート電極１９ｇ、裏面電極１７を夫々のコンタクト領域にオーミックコンタクトさせる。このプロセスにより、図２９に示したような、基板の裏面がワッフル状に加工されたＳｉＣのＭＯＳＦＥＴが完成する。   Next, as shown in FIG. 35, the substrate is thermally oxidized again, a CVD oxide film is formed, and a gate insulating film 31 is formed by patterning. Next, the Si oxide film 15 in the source region is removed, a Ni film is selectively formed in the source region and the insulated gate region, and a source electrode 19s and a gate electrode 19g are formed. Further, a Ni film is formed on the back surface by electron gun vapor deposition to form a back electrode (drain electrode) 17, and sintering is performed at 1000 ° C. for 1 minute in an Ar atmosphere so that the source electrode 19s, the gate electrode 19g, and the back electrode 17 are Make ohmic contact with each contact area. By this process, a SiC MOSFET in which the back surface of the substrate is processed into a waffle shape as shown in FIG. 29 is completed.

本素子のオン抵抗は１０ｍΩｃｍ2であり、耐圧は１０００Ｖであった。参考のため、基板の裏面がワッフル状でない、普通の基板の場合、耐圧は同様に１０００Ｖであるものの、オン抵抗は１０．８ｍΩｃｍ2であり、ワッフル状に加工した素子のオン抵抗がこれより０．８ｍΩｃｍ2低減していることがわかる。 The on-resistance of this device was 10 mΩcm 2 and the withstand voltage was 1000V. For reference, in the case of a normal substrate in which the back surface of the substrate is not waffle, the withstand voltage is similarly 1000 V, but the on-resistance is 10.8 mΩcm 2 , and the on-resistance of the element processed into a waffle is 0 It can be seen that it is reduced by .8 mΩcm 2 .

（第５の実施形態）
図３６は、本発明の第５の実施形態に係るｐｉｎダイオードの断面図である。上面図は矩形基板の中央に矩形電極が形成されているだけなので省略する。底面図はテーパが形成されている点を除き、図２と同様である。 (Fifth embodiment)
FIG. 36 is a cross-sectional view of a pin diode according to the fifth embodiment of the present invention. The top view is omitted because the rectangular electrode is only formed at the center of the rectangular substrate. The bottom view is the same as FIG. 2 except that a taper is formed.

バルクＳｉＣからなるＳｉＣ支持体２１の上に形成されたＳｉＣエピタキシャル層３にダイオード素子構造が形成されている。本実施形態では、バルクＳｉＣとエピタキシャル層３はｐ型である。エピタキシャル層３の裏面は、複数の凹部が形成されたＳｉＣ支持体２１により支持されており、基板１は連続ワッフル状に形成されている。エピタキシャル層３の上面と裏面には第１のコンタクト層３３と第２のコンタクト層１３が夫々形成されている。本実施形態では、第１のコンタクト層３３はｎ型、第２のコンタクト層１３がｐ型であり、低濃度ｐ型エピタキシャル層３をｉ型と考えると、これを挟んでｐｉｎダイオードが形成されている。   A diode element structure is formed in SiC epitaxial layer 3 formed on SiC support 21 made of bulk SiC. In this embodiment, the bulk SiC and the epitaxial layer 3 are p-type. The back surface of the epitaxial layer 3 is supported by a SiC support 21 having a plurality of recesses, and the substrate 1 is formed in a continuous waffle shape. A first contact layer 33 and a second contact layer 13 are formed on the upper surface and the back surface of the epitaxial layer 3, respectively. In the present embodiment, when the first contact layer 33 is n-type, the second contact layer 13 is p-type, and the low-concentration p-type epitaxial layer 3 is considered i-type, a pin diode is formed sandwiching this. ing.

エピタキシャル層３の上面には、第１のコンタクト層３３を囲んで、終端構造であるリサーフ層１２、ガードリング１４が形成されており、本実施形態では夫々ｎ型で形成されている。エピタキシャル層３の上面はＳｉ酸化層１５で覆われており、第１のコンタクト層３３の上部は選択的に開口され、ここに表面電極（第１の電極）１９が形成されている。エピタキシャル層３の裏面には、第２のコンタクト層１３の上に裏面電極（第２の電極）３５が形成されている。裏面電極（第２の電極）１７は、凹部底面からＳｉＣ支持体２１のテーパ状の側部内面、ＳｉＣ支持体２１の脚部底面にかけて延在して形成されている。   On the upper surface of the epitaxial layer 3, the RESURF layer 12 and the guard ring 14, which are termination structures, are formed so as to surround the first contact layer 33, and in this embodiment, each is formed in an n-type. The upper surface of the epitaxial layer 3 is covered with a Si oxide layer 15, and the upper portion of the first contact layer 33 is selectively opened, and a surface electrode (first electrode) 19 is formed there. On the back surface of the epitaxial layer 3, a back surface electrode (second electrode) 35 is formed on the second contact layer 13. The back electrode (second electrode) 17 is formed to extend from the bottom surface of the recess to the tapered inner side surface of the SiC support 21 and the bottom surface of the leg portion of the SiC support 21.

第５の実施形態のｐｉｎダイオードは、ＳｉＣ支持体２１により強度が付与されており、ダイオード素子はエピタキシャル層３に形成され、裏面電極１７との距離が短いので、低オン抵抗が実現されている。   The pin diode of the fifth embodiment is given strength by the SiC support 21, and the diode element is formed in the epitaxial layer 3, and since the distance from the back electrode 17 is short, a low on-resistance is realized. .

次に、第５の実施形態のｐｉｎダイオードの製造方法を説明する。第１および第２の実施形態と同一部分には同一番号を付し、重複する説明を省略する。また、同一形状を示す図面は、第１若しくは第２の実施形態の図を参照することにする。   Next, a manufacturing method of the pin diode of the fifth embodiment will be described. The same parts as those in the first and second embodiments are denoted by the same reference numerals, and redundant description is omitted. The drawings showing the same shape refer to the drawings of the first or second embodiment.

第５の実施形態が第１の実施形態と異なる点の１つは、基板比抵抗５ΩｃｍのＳｉＣ基板２（但しp型）上にｐ導電型の不純物濃度が３．５×１０15ｃｍ-3のエピタキシャル層３を１０μｍ成長させた基板１を用意することである。断面構造としては、第１の実施形態の図２と同様になる。この基板１を第１の実施形態と同様な条件の洗浄工程を通し、図３と同様に、基板上面に犠牲酸化膜５を形成し、基板裏面にＴｉ層７、Ａｌ層９、レジスト層１１を順次形成する。 One of the differences of the fifth embodiment from the first embodiment is that the p-conductivity type impurity concentration is 3.5 × 10 15 cm −3 on the SiC substrate 2 (p-type) having a substrate resistivity of 5 Ωcm. The substrate 1 is prepared by growing the epitaxial layer 3 of 10 μm. The cross-sectional structure is the same as that in FIG. 2 of the first embodiment. The substrate 1 is subjected to a cleaning process under the same conditions as in the first embodiment, a sacrificial oxide film 5 is formed on the upper surface of the substrate, and a Ti layer 7, an Al layer 9, and a resist layer 11 are formed on the rear surface of the substrate, as in FIG. Are sequentially formed.

続いて、レジスト層１１にワッフル凹部を形成するためのレジストパターンを形成し、塩素系ガスによるＲＩＥチャンバーに導入し、レジストパターンをエッチングマスクとして、図４と同様に、Ａｌ層９、Ｔｉ層７をドライエッチングする。   Subsequently, a resist pattern for forming a waffle recess is formed in the resist layer 11 and introduced into an RIE chamber using a chlorine-based gas. Using the resist pattern as an etching mask, an Al layer 9 and a Ti layer 7 are formed as in FIG. Is dry-etched.

ついで、パターニングされたＡｌ層９をエッチングマスクとして、第２の実施形態の図１７と同様に、ＳｉＣ基板２をＣＦ4とＯ2の混合ガスによりドライエッチングする。本実施形態においてもテーパ形状のワッフル凹部を形成する。この基板を硫酸と過酸化水素水の混酸で洗浄し、基板に付着したレジスト、金属を除去した後、純水によりリンスし、ＳｉＣ支持体２１の裏面に形成されたＡｌ層９、Ｔｉ層７も除去し、純水によりリンスする。 Next, using the patterned Al layer 9 as an etching mask, the SiC substrate 2 is dry-etched with a mixed gas of CF 4 and O 2 as in FIG. 17 of the second embodiment. Also in this embodiment, a tapered waffle recess is formed. This substrate is washed with a mixed acid of sulfuric acid and hydrogen peroxide solution, the resist and metal adhering to the substrate are removed, rinsed with pure water, and the Al layer 9 and Ti layer 7 formed on the back surface of the SiC support 21. Also rinse with pure water.

次に、第２の実施形態の図１８と同様に、基板裏面に総ドーズ量７×１０15ｃｍ-2、最大加速エネルギー２００ｋｅＶにより、Ａｌイオンの多段注入を行い、裏面電極用のオーミックコンタクト領域１３を形成する。 Next, similarly to FIG. 18 of the second embodiment, Al ion multi-stage implantation is performed on the back surface of the substrate with a total dose of 7 × 10 15 cm −2 and a maximum acceleration energy of 200 keV, and an ohmic contact region for the back electrode 13 is formed.

ついで、エピタキシャル層３の上面に、終端構造となるリサーフ領域１２、ガードリング領域１４を形成するためのイオン注入マスクを形成する。そのマスク形成面に、総ドーズ量１．５×１０13ｃｍ-2、最大加速エネルギー３００ｋｅＶによりＰ（リン）イオンの多段注入を行い、図１９に示すようなリサーフ領域１２、ガードリング１４を形成する。 Next, an ion implantation mask for forming the RESURF region 12 and the guard ring region 14 serving as termination structures is formed on the upper surface of the epitaxial layer 3. A multi-stage implantation of P (phosphorus) ions is performed on the mask formation surface with a total dose of 1.5 × 10 13 cm −2 and a maximum acceleration energy of 300 keV to form a resurf region 12 and a guard ring 14 as shown in FIG. To do.

続いて、図３７に示すように、リサーフ層１２の内側部分に選択的に表面電極用のオーミックコンタクト領域３３を形成するために、基板上面に総ドーズ量７×１０15ｃｍ-2、最大加速エネルギー２００ｋｅＶでＰ（リン）イオンの多段注入を行う。 Subsequently, as shown in FIG. 37, in order to selectively form the ohmic contact region 33 for the surface electrode in the inner portion of the RESURF layer 12, the total dose amount is 7 × 10 15 cm −2 and the maximum acceleration is formed on the upper surface of the substrate. Multistage implantation of P (phosphorus) ions is performed at an energy of 200 keV.

この基板を 硫酸と過酸化水素水の混酸で洗浄し、基板に付着したレジスト、金属を除去した後、純水によりリンスする。ついで、希塩酸と過酸化水素水の混酸で基板に付着した微量の金属不純物を除去し、純水によりリンスする。そして、最後に希フッ酸により基板表面の犠牲酸化膜５等を除去し、純水によりリンスする。   The substrate is washed with a mixed acid of sulfuric acid and hydrogen peroxide solution to remove the resist and metal adhering to the substrate, and then rinsed with pure water. Next, a trace amount of metal impurities adhering to the substrate is removed with a mixed acid of dilute hydrochloric acid and hydrogen peroxide, and rinsed with pure water. Finally, the sacrificial oxide film 5 and the like on the substrate surface are removed with dilute hydrofluoric acid, and rinsed with pure water.

洗浄が終了した基板を誘導加熱型の活性化アニール炉に導入し、到達真空度１×１０-4Ｐａまで真空にした後、不活性ガスであるＡｒで満たし、１６００℃、５分間の活性化アニールを行い、図３８に示した構造体を得る。 The substrate after cleaning is introduced into an induction heating type activation annealing furnace, evacuated to an ultimate vacuum of 1 × 10 −4 Pa, filled with Ar as an inert gas, and activated at 1600 ° C. for 5 minutes. Annealing is performed to obtain the structure shown in FIG.

ついで、再び基板の表面を熱酸化した後に、図３９に示すように、ＣＶＤにより基板表面１μｍのＳｉ酸化膜１５を成膜し、Ａｒ雰囲気中１０００℃でＳｉ酸化膜１５をシンターする。   Next, after the surface of the substrate is thermally oxidized again, as shown in FIG. 39, a Si oxide film 15 having a substrate surface of 1 μm is formed by CVD, and the Si oxide film 15 is sintered at 1000 ° C. in an Ar atmosphere.

この基板１の表面のＳｉ酸化膜１５上にレジストを塗布、パターニングして、オーミックコンタクト領域３３上の領域を選択的に開口させる。ついで、ＣＦ4とＯ2のＲＩＥによりＳｉ酸化膜１５をエッチングし、さらに希フッ酸により基板最表面の自然酸化膜を除去し、Ｎｉ層を電子銃蒸着により成膜する。ついで、図４０に示すように、開口部分に選択的にＮｉを残し、残りの部分を除去して表面電極１９を形成する。その後、Ａｒ雰囲気中、１０００℃、１分間のシンターを行い、表面電極１９とオーミックコンタクト領域３３の間のオーミックコンタクトを実現する。 A resist is applied and patterned on the Si oxide film 15 on the surface of the substrate 1 to selectively open a region on the ohmic contact region 33. Next, the Si oxide film 15 is etched by RIE of CF 4 and O 2 , the natural oxide film on the outermost surface of the substrate is removed by dilute hydrofluoric acid, and a Ni layer is formed by electron gun evaporation. Next, as shown in FIG. 40, Ni is selectively left in the opening portion, and the remaining portion is removed to form the surface electrode 19. Thereafter, sintering is performed in an Ar atmosphere at 1000 ° C. for 1 minute to realize ohmic contact between the surface electrode 19 and the ohmic contact region 33.

ついで、裏面のオーミック電極であるＡｌ膜１７を成膜し、Ａｒ雰囲気でシンターする。このプロセスにより、図３６に示すような、基板裏面が連続ワッフル状に加工されたＳｉＣのｐｉｎダイオードが完成する。   Next, an Al film 17 which is an ohmic electrode on the back surface is formed and sintered in an Ar atmosphere. This process completes a SiC pin diode as shown in FIG. 36 in which the back surface of the substrate is processed into a continuous waffle shape.

本実施形態ではp型ＳｉＣ基板上に低不純物濃度のｐ型エピタキシャル層を成長させて素子を形成したが、n型ＳｉＣ基板と同程度の低基板抵抗p型ＳｉＣ基板を得ることは困難であり、現状での基板比抵抗は概ね５Ωｃｍ以上である。この場合２Ωｃｍ2以上もの大きな基板抵抗がシリーズ抵抗として残ってしまうが、本実施形態を使用することで、この大きな基板抵抗を無くすことができる。 In this embodiment, a device is formed by growing a p-type epitaxial layer having a low impurity concentration on a p-type SiC substrate. However, it is difficult to obtain a p-type SiC substrate having a low substrate resistance comparable to that of an n-type SiC substrate. The current substrate resistivity is approximately 5 Ωcm or more. In this case, a large substrate resistance of 2 Ωcm 2 or more remains as a series resistance, but this large substrate resistance can be eliminated by using this embodiment.

（第６の実施形態）
第５の実施形態は、ｐ型ＳｉＣ基板にｐ型エピタキシャル層を成長させた基板を用いて形成されたｐｉｎダイオードであったが、第６の実施形態では、ｎ型ＳｉＣ基板にｎ型エピタキシャル層を成長させた基板を用いてｐｉｎダイオードを形成する実施形態を説明する。導電型や使用する材料は第５の実施形態と異なるが、構造としては第５の実施形態と同じになるので、第５の実施形態で参照した図３６乃至４０を援用して説明する。また、第１および第２の実施形態と同一部分には同一番号を付し、重複する説明を省略する。 (Sixth embodiment)
Although the fifth embodiment is a pin diode formed using a substrate obtained by growing a p-type epitaxial layer on a p-type SiC substrate, in the sixth embodiment, an n-type epitaxial layer is formed on an n-type SiC substrate. An embodiment will be described in which a pin diode is formed using a substrate on which is grown. Although the conductivity type and the material used are different from those of the fifth embodiment, the structure is the same as that of the fifth embodiment. Therefore, description will be made with reference to FIGS. 36 to 40 referred to in the fifth embodiment. Further, the same parts as those in the first and second embodiments are denoted by the same reference numerals, and redundant description is omitted.

第６の実施形態に係るｐｉｎダイオードの断面図も図３６のようになる。但し、本実施形態では、ＳｉＣ支持体２１とエピタキシャル層３はｎ型である。また、第１のオーミックコンタクト層３３はｐ型、第２のオーミックコンタクト層１３がｎ型であり、第１のオーミックコンタクト層３３と第２のオーミックコンタクト層１３の間にｎ型低不純物濃度エピタキシャル層３を挟んだｐｉｎダイオードが形成されている。   A cross-sectional view of the pin diode according to the sixth embodiment is as shown in FIG. However, in the present embodiment, the SiC support 21 and the epitaxial layer 3 are n-type. The first ohmic contact layer 33 is p-type, and the second ohmic contact layer 13 is n-type. An n-type low impurity concentration epitaxial layer is provided between the first ohmic contact layer 33 and the second ohmic contact layer 13. A pin diode sandwiching the layer 3 is formed.

エピタキシャル層３の上面には、第１のコンタクト層３３を囲んで、終端構造であるリサーフ層１２、ガードリング１４が形成されており、本実施形態では夫々ｐ型である。   On the upper surface of the epitaxial layer 3, the RESURF layer 12 and the guard ring 14, which are termination structures, are formed so as to surround the first contact layer 33, and each is p-type in this embodiment.

第６の実施形態のｐｉｎダイオードも、バルクＳｉＣの支持体２１により強度が付与されており、ダイオード素子はエピタキシャル層３に形成されているので、低オン抵抗が実現されている。   The pin diode of the sixth embodiment is also given strength by the bulk SiC support 21, and the diode element is formed in the epitaxial layer 3, so that a low on-resistance is realized.

次に、第６の実施形態に係るｐｉｎ型ダイオードの製造方法を説明する。同一形態を示す図面は、第１若しくは第２の実施形態の図を参照することにする。第２の実施形態の図１９の工程までを同様に実施する。   Next, a manufacturing method of the pin type diode according to the sixth embodiment will be described. For the drawings showing the same form, reference is made to the drawings of the first or second embodiment. The process up to the process of FIG. 19 of the second embodiment is similarly performed.

ついで、リサーフ領域１２の内側部分に選択的に表面電極のオーミックコンタクト領域３３を形成するために、図３７に示すように、基板表面に総ドーズ量７×１０15ｃｍ-2、最大加速エネルギー２００ｋｅＶのＡｌイオンの多段注入を行う。この基板を第１の実施形態と同様の条件で洗浄、活性化アニールを行い、図３８に示すような構造体を得る。 Next, in order to selectively form the ohmic contact region 33 of the surface electrode in the inner portion of the RESURF region 12, as shown in FIG. 37, the total dose amount is 7 × 10 15 cm −2 and the maximum acceleration energy is 200 keV on the substrate surface. Multi-stage implantation of Al ions is performed. This substrate is subjected to cleaning and activation annealing under the same conditions as in the first embodiment to obtain a structure as shown in FIG.

ついで、図３９に示すように、再び基板の上面を熱酸化した後に、ＣＶＤにより基板上面に１μmのＳｉ酸化膜１５を成膜し、Ａｒ雰囲気中、１０００℃でＳｉ酸化膜１５をシンターする。   Next, as shown in FIG. 39, after thermally oxidizing the upper surface of the substrate again, a 1 μm Si oxide film 15 is formed on the upper surface of the substrate by CVD, and the Si oxide film 15 is sintered at 1000 ° C. in an Ar atmosphere.

その後、第５の実施形態と同様にして、Ｓｉ酸化膜１５のオーミックコンタクト領域３３上の領域を選択的に開口させ、Ａｌを成膜した後、開口部分のＡｌを選択的に残し、残りの部分を選択的に除去して上部電極１９を形成する。その後、Ａｒ雰囲気中、１０００℃、１分間のシンターを行い、表面電極１９とオーミックコンタクト領域３３のオーミックコンタクトを実現させる。   Thereafter, in the same manner as in the fifth embodiment, a region on the ohmic contact region 33 of the Si oxide film 15 is selectively opened, and after Al is formed, Al in the opening is selectively left, and the remaining The portion is selectively removed to form the upper electrode 19. Thereafter, sintering is performed in an Ar atmosphere at 1000 ° C. for 1 minute to realize ohmic contact between the surface electrode 19 and the ohmic contact region 33.

ついで、第５の実施形態と同様にして裏面電極３５をＮｉで形成し、シンターしてオーミックコンタクトを形成して、図３６に示すような、基板裏面がワッフル状に加工されたＳｉＣのｐｉｎダイオードが完成する。   Next, as in the fifth embodiment, a back electrode 35 is formed of Ni and sintered to form an ohmic contact. As shown in FIG. 36, an SiC pin diode whose back surface is processed into a waffle shape is formed. Is completed.

一般的にはp型の導電性の基板上に、低不純物濃度のn型エピタキシャル層を成長させ、裏面にＡｌ、表面にＰ（リン）をイオン注入してｐｉｎダイオードを形成させるが、本実施形態では０．０２Ωｃｍのn型基板上に、低不純物濃度のｎ型エピタキシャル層を成長させ、裏面基板をワッフル状に加工した後、表面にｐ型の導電性の不純物イオン(Ａｌ)をイオン注入して表面のオーミック電極をコンタクトさせた後、裏面にｎ型の導電性となる不純物イオン(Ｐ)をイオン注入してｐｉｎダイオードを形成させた。   In general, an n-type epitaxial layer having a low impurity concentration is grown on a p-type conductive substrate, and a pin diode is formed by ion implantation of Al on the back surface and P (phosphorus) on the front surface. In this embodiment, an n-type epitaxial layer with a low impurity concentration is grown on an n-type substrate of 0.02 Ωcm, the back substrate is processed into a waffle shape, and then p-type conductive impurity ions (Al) are implanted into the surface. Then, after contacting the ohmic electrode on the surface, impurity ions (P) that become n-type conductivity are ion-implanted on the back surface to form a pin diode.

p型基板の基板比抵抗は概ね５Ωｃｍ以上であり、通常のｐｉｎダイオード製作方法を用いた場合２Ωｃｍ2以上もの大きな基板抵抗がシリーズ抵抗として残ってしまうが、本発明を使用することで、この大きな基板抵抗をなくすことができる。 The substrate specific resistance of the p-type substrate is approximately 5 Ωcm or more, and a large substrate resistance of 2 Ωcm 2 or more remains as a series resistance when a normal pin diode manufacturing method is used. Substrate resistance can be eliminated.

また、p型基板上のn型エピタキシャル成長は品質の良い膜を成長させるのが困難であり、結晶欠陥による素子性能の劣化が問題とされていたが、本実施形態によればn型エピタキシャル成長はn型基板上に作ることができるので、エピタキシャル膜の結晶欠陥を大幅に抑制することができる。   In addition, n-type epitaxial growth on a p-type substrate is difficult to grow a high-quality film, and degradation of device performance due to crystal defects has been a problem. According to this embodiment, n-type epitaxial growth is n Since it can be formed on a mold substrate, crystal defects in the epitaxial film can be greatly suppressed.

（第７の実施形態）
図４１は、本発明の第７の実施形態に係る絶縁ゲートバイポーラトランジスタ（ＩＧＢＴ）の断面図である。上面図は第４の実施形態のＭＯＳＦＥＴの図３０に同じになり、底面図は第１の実施形態とテーパ部分を除き同じになるので省略する。 (Seventh embodiment)
FIG. 41 is a cross-sectional view of an insulated gate bipolar transistor (IGBT) according to the seventh embodiment of the present invention. The top view is the same as that of the MOSFET of the fourth embodiment shown in FIG. 30, and the bottom view is the same as that of the first embodiment except for the taper portion, and is omitted.

本実施形態のＩＧＢＴは、バルクＳｉＣからなる支持体２１の上に形成されたＳｉＣエピタキシャル層（低濃度層）３にＩＧＢＴの複数のユニット素子が並列に形成されている。本実施形態では、バルクＳｉＣとエピタキシャル層３はｎ型である。エピタキシャル層３の裏面は、複数の凹部を備えたＳｉＣ支持体２１により支持されており、バルクＳｉＣ支持体２１とエピタキシャル層３からなる基板１には複数のワッフルが連続的に形成されている。エピタキシャル層３の上面には、ｐ型ウェル２９に形成されたｎ型のソース領域２５、ゲート絶縁膜３１を介して形成されたゲート電極１９ｇが形成されており、裏面にはｐ型オーミックコンタクト層１３を介してドレイン電極となる裏面電極１７が形成されている。なお、ＳｉＣ支持体２１はｎ型なので、これと裏面電極１７の間には絶縁膜３５が形成され、ｐ型オーミックコンタクト層１３に接続される裏面電極１７との間を絶縁している。   In the IGBT of this embodiment, a plurality of IGBT unit elements are formed in parallel on a SiC epitaxial layer (low concentration layer) 3 formed on a support 21 made of bulk SiC. In this embodiment, the bulk SiC and the epitaxial layer 3 are n-type. The back surface of the epitaxial layer 3 is supported by a SiC support 21 having a plurality of recesses, and a plurality of waffles are continuously formed on the substrate 1 composed of the bulk SiC support 21 and the epitaxial layer 3. An n-type source region 25 formed in a p-type well 29 and a gate electrode 19g formed through a gate insulating film 31 are formed on the upper surface of the epitaxial layer 3, and a p-type ohmic contact layer is formed on the rear surface. A back electrode 17 serving as a drain electrode is formed via 13. Since the SiC support 21 is n-type, an insulating film 35 is formed between the SiC support 21 and the back electrode 17 to insulate the back electrode 17 connected to the p-type ohmic contact layer 13.

エピタキシャル層３の上面には、ｐ型ウェル２９を囲んで、終端構造であるリサーフ層１２、ガードリング１４が形成されており、本実施形態では夫々ｐ型で形成されている。エピタキシャル層３の上面はＳｉ酸化層１５で覆われており、表面電極であるソース電極１９ｓ、ゲート電極１９ｇ形成領域は選択的に開口され、ここに夫々の電極が形成されている。   On the upper surface of the epitaxial layer 3, the RESURF layer 12 and the guard ring 14, which are termination structures, are formed so as to surround the p-type well 29, and in this embodiment, each is formed of p-type. The upper surface of the epitaxial layer 3 is covered with a Si oxide layer 15, and the source electrode 19s and gate electrode 19g forming regions which are surface electrodes are selectively opened, and the respective electrodes are formed therein.

第７の実施形態のＩＧＢＴは、バルクＳｉＣの支持体２１により強度が付与されており、アクティブ領域は低抵抗のエピタキシャル層３に形成され、裏面電極１７との距離が短いので、低オン抵抗が実現されている。   The strength of the IGBT according to the seventh embodiment is given by the bulk SiC support 21, the active region is formed in the low-resistance epitaxial layer 3, and the distance from the back electrode 17 is short. It has been realized.

次に、第７の実施形態のＩＧＢＴの製造方法を説明する。第１および第２の実施形態と同一部分には同一番号を付し、重複する説明を省略する。また、同一形態を示す図面は、第１若しくは第２の実施形態の図を参照することにする。第２の実施形態の図１７の工程までは同様に実施する。ついで、図１８に示すように、裏面コンタクト領域１３を形成するが、本実施例では基板裏面に総ドーズ量７×１０17ｃｍ-3、最大加速エネルギー２００ｋｅＶにて、Ａｌイオンの多段注入を行い、裏面電極のオーミックコンタクト領域１３ともなるｐ型領域を形成する。ついで、図１９の工程を第２の実施形態と同様に実施し、さらに第４の実施形態（ＭＯＳＦＥＴ）の図３１，３２の工程を同様に実施する。   Next, the manufacturing method of IGBT of 7th Embodiment is demonstrated. The same parts as those in the first and second embodiments are denoted by the same reference numerals, and redundant description is omitted. For the drawings showing the same form, refer to the drawings of the first or second embodiment. The steps up to the process of FIG. 17 of the second embodiment are similarly performed. Next, as shown in FIG. 18, a back contact region 13 is formed. In this embodiment, Al ions are multi-stage implanted into the back surface of the substrate at a total dose of 7 × 10 17 cm −3 and a maximum acceleration energy of 200 keV. A p-type region that also serves as an ohmic contact region 13 of the electrode is formed. Next, the process of FIG. 19 is performed similarly to the second embodiment, and the processes of FIGS. 31 and 32 of the fourth embodiment (MOSFET) are performed similarly.

ついで、再び基板表面を熱酸化した後に、図４２に示すように、ＣＶＤにより基板表面に１μｍのＳｉ酸化膜１５、基板裏面に１μｍのＳｉ酸化膜３５を成膜し、Ａｒ雰囲気中、１０００℃でＳｉＯ2膜をシンターする。   Next, after the substrate surface is thermally oxidized again, as shown in FIG. 42, a 1 μm Si oxide film 15 is formed on the substrate surface by CVD and a 1 μm Si oxide film 35 is formed on the back surface of the substrate, and is 1000 ° C. in Ar atmosphere. Then, the SiO2 film is sintered.

続いて、図４３に示すように、この基板の表面のソースコンタクト部分および、ゲート領域にあたる酸化膜をエッチングにより除去する。ついで、図４４に示すように、この基板を再び熱酸化させたのち、ＣＶＤ酸化膜を成膜し、パターニングによりゲート絶縁膜３１を形成する。   Subsequently, as shown in FIG. 43, the source contact portion on the surface of the substrate and the oxide film corresponding to the gate region are removed by etching. Next, as shown in FIG. 44, the substrate is thermally oxidized again, a CVD oxide film is formed, and a gate insulating film 31 is formed by patterning.

次に、ソース領域２５に形成された自然酸化膜を除去し、ソース領域２５およびゲート絶縁膜３１上に選択的にＮｉを成膜する。Ａｒ雰囲気中、１０００℃、１分間のシンターを行い、表面電極をオーミックコンタクトさせる。   Next, the natural oxide film formed in the source region 25 is removed, and Ni is selectively formed on the source region 25 and the gate insulating film 31. Sintering is performed at 1000 ° C. for 1 minute in an Ar atmosphere to make ohmic contact with the surface electrode.

ついで、表面をレジストにより保護した後、裏面のＳｉ酸化膜３５表面にレジストを塗布し、厚膜レジストによるパターニングで裏面電極部（ｐ型コンタクト領域１３の直下）をパターニングにより開口させる。ついで、ＣＦ4とＯ2のＲＩＥによりＳｉ酸化膜３５をエッチングし、さらに希フッ酸により基板最表面の酸化膜を除去し、裏面のオーミック電極であるＡｌ膜を成膜し、Ａｒ雰囲気でシンターする。このプロセスにより、図４１に示すような、基板裏面がワッフル状に加工されたＳｉＣのＩＧＢＴが形成される。 Next, after protecting the surface with a resist, a resist is applied to the surface of the Si oxide film 35 on the back surface, and the back electrode portion (directly under the p-type contact region 13) is opened by patterning by patterning with a thick film resist. Next, the Si oxide film 35 is etched by RIE of CF 4 and O 2 , the oxide film on the outermost surface of the substrate is removed by dilute hydrofluoric acid, and an Al film that is an ohmic electrode on the back surface is formed, and sintered in an Ar atmosphere. To do. By this process, as shown in FIG. 41, a SiC IGBT whose back surface is processed into a waffle shape is formed.

本実施形態では０．０２Ωｃｍのｎ型ＳｉＣ基板２上に、低不純物濃度のn型エピタキシャル層３を成長させ、基板裏面をワッフル状に加工した後、裏面にp型の導電性の不純物イオン(Ａｌ)をイオン注入して裏面のオーミック領域１３を形成した後、表面に終端構造１２，１４、p型ウェル領域２９、ソース領域２５、ｐ型コンタクト領域３０を形成し、ＩＧＢＴを作ったが、ｐ型基板上にn型のエピタキシャル層を成長させたのち、基板裏面をワッフル状に加工してＩＧＢＴを作ってもかまわない。   In this embodiment, an n-type epitaxial layer 3 having a low impurity concentration is grown on an n-type SiC substrate 2 of 0.02 Ωcm, the back surface of the substrate is processed into a waffle shape, and then p-type conductive impurity ions ( After forming the ohmic region 13 on the back surface by ion implantation of Al), the termination structures 12, 14, the p-type well region 29, the source region 25, and the p-type contact region 30 are formed on the front surface to make an IGBT. After growing an n-type epitaxial layer on a p-type substrate, the back surface of the substrate may be processed into a waffle to make an IGBT.

p型基板を用いた場合、現状での基板比抵抗は概ね５Ωｃｍ以上である。この場合２Ωｃｍ2以上もの大きな基板抵抗がシリーズ抵抗として残ってしまうが、本発明を使用することで、この大きな基板抵抗をなくすことができる。 When a p-type substrate is used, the current substrate specific resistance is approximately 5 Ωcm or more. In this case, a large substrate resistance of 2 Ωcm 2 or more remains as a series resistance, but this large substrate resistance can be eliminated by using the present invention.

また、本実施形態ではｎ型基板上にn型のエピタキシャル膜を成長させ、基板をワッフル状に加工する際、ワッフル凹部は基板全てをエッチングにより取り除き、裏面にp型の導電型となる不純物イオン(Ａｌ)をイオン注入したが、p型基板上にn型のエピタキシャル膜を成長させてＩＧＢＴを作る場合は、基板部分が一部残っていても構わない。この場合、基板の残り量と基板抵抗はリニアの関係にあり、残り量が多いほど基板抵抗が上がってしまうが、基板強度がその分上がる利点がある。素子の設計および、要求性能により、使用者が凹部の残し量を勘案することができる。   Further, in this embodiment, when an n-type epitaxial film is grown on an n-type substrate and the substrate is processed into a waffle shape, the waffle recess is removed by etching all the substrate, and impurity ions that become p-type conductivity are formed on the back surface. (Al) is ion-implanted, but when making an IGBT by growing an n-type epitaxial film on a p-type substrate, a part of the substrate may be left. In this case, the remaining amount of the substrate and the substrate resistance are in a linear relationship, and as the remaining amount increases, the substrate resistance increases, but there is an advantage that the substrate strength increases accordingly. Depending on the design of the element and the required performance, the user can consider the remaining amount of the recess.

一方、p型基板上のn型エピタキシャル成長は品質の良い膜を成長させるのが困難であり、結晶欠陥による素子性能の劣化が問題とされているが、本発明によればn型エピタキシャル成長をn型基板上に成長させた後に、n型基板裏面をワッフル状に加工した上でＩＧＢＴを作成することができるので、エピタキシャル膜の結晶欠陥を大幅に抑制することができる。   On the other hand, n-type epitaxial growth on a p-type substrate makes it difficult to grow a high-quality film, and degradation of device performance due to crystal defects is a problem. After growing on the substrate, the back surface of the n-type substrate is processed into a waffle shape, and thus an IGBT can be created, so that crystal defects in the epitaxial film can be greatly suppressed.

（第８の実施形態）
ＳｉＣと同様にワイドバンドギャップ半導体であるＧａＮのパワーデバイスへの応用が注目されている。ＧａＮの場合、ＡｌＧａＮと組み合わせてＡｌＧａＮ／ＧａＮヘテロ構造を形成すると二次元電子ガスチャネルが得られ、チャネル移動度が非常に高くなり、低オン抵抗が実現することが知られている。このＡｌＧａＮ／ＧａＮを応用したＨＥＭＴでは、最上層のＡｌＧａＮ層上にソース・ゲート・ドレインが横方向に形成される横型素子が一般的であるが、チップ面積縮小、回路配線の短縮などの目的で、ドレイン電極を基板の下面より取り出す構造が望ましい場合も有る。第８の実施形態では、本発明をこのような縦形ＧａＮＨＥＭＴに応用した例を説明する。 (Eighth embodiment)
Similar to SiC, attention is focused on the application of GaN, which is a wide bandgap semiconductor, to power devices. In the case of GaN, it is known that when an AlGaN / GaN heterostructure is formed in combination with AlGaN, a two-dimensional electron gas channel is obtained, the channel mobility is very high, and low on-resistance is realized. In this HEMT using AlGaN / GaN, a horizontal element in which a source, a gate, and a drain are formed laterally on the uppermost AlGaN layer is generally used. However, for the purpose of reducing the chip area and circuit wiring, etc. In some cases, a structure in which the drain electrode is taken out from the lower surface of the substrate is desirable. In the eighth embodiment, an example in which the present invention is applied to such a vertical GaN HEMT will be described.

図４５は、第８の実施形態に係るＧａＮスイッチング素子（ＭＥＭＴ）の断面図である。裏面がワッフル状に形成されたｎ型ＳｉＣ基板４１上にＡｌＮ緩衝層４３が１００ｎｍ形成されている。さらにその上にアンドープＧａＮ層４５（３μｍ）、アンドープＡｌＧａＮ層４７（３ｎｍ）、ｎ型ＡｌＧａＮ層４９（１０ｎｍ）、アンドープＡｌＧａＮ層５１（５ｎｍ）が順次形成されている。アンドープＡｌＧａＮ層５１を貫通し、ｎ型ＡｌＧａＮ層４９上には選択的にソース領域５３か形成されている。アンドープＡｌＧａＮ層５１上には選択的にゲート電極５５が形成されている。アンドープＡｌＧａＮ層５１からＳｉＣ基板４１に達するコンタクトホールが形成され、これを埋め込むようにドレイン領域５９が形成されている。この構造体の上面にはＳｉＮ膜５９を介してＳｉ酸化膜５１が形成され、その上にフィールドプレート６３が選択的に形成されている。ＳｉＣ基板４１の裏面には、裏面電極６５が形成されている。上記の構成により、ドレイン領域５９が裏面電極６５に取り出されたＧａＮスイッチング素子が実現されている。   FIG. 45 is a cross-sectional view of a GaN switching element (MEMT) according to the eighth embodiment. An AlN buffer layer 43 having a thickness of 100 nm is formed on an n-type SiC substrate 41 whose back surface is formed in a waffle shape. Further thereon, an undoped GaN layer 45 (3 μm), an undoped AlGaN layer 47 (3 nm), an n-type AlGaN layer 49 (10 nm), and an undoped AlGaN layer 51 (5 nm) are sequentially formed. A source region 53 is selectively formed on the n-type AlGaN layer 49 through the undoped AlGaN layer 51. A gate electrode 55 is selectively formed on the undoped AlGaN layer 51. A contact hole reaching the SiC substrate 41 from the undoped AlGaN layer 51 is formed, and a drain region 59 is formed so as to fill the contact hole. A Si oxide film 51 is formed on the upper surface of this structure via a SiN film 59, and a field plate 63 is selectively formed thereon. A back electrode 65 is formed on the back surface of the SiC substrate 41. With the above configuration, a GaN switching element in which the drain region 59 is extracted to the back electrode 65 is realized.

次に、本実施形態のスイッチング素子の形成方法を説明する。まず、基板抵抗０．０２Ωｃｍのn型ＳｉＣ基板（基板）を硫酸と過酸化水素水の混酸で基板に付着した有機汚れを除去し、純水によりリンスする。ついで、希塩酸と過酸化水素水の混酸で基板に付着した金属不純物を除去し、純水によりリンスする。そして、最後に希フッ酸により基板表面の自然酸化膜を除去し、純水によりリンスする。   Next, a method for forming the switching element of this embodiment will be described. First, an organic stain adhering to a substrate is removed from a n-type SiC substrate (substrate) having a substrate resistance of 0.02 Ωcm with a mixed acid of sulfuric acid and hydrogen peroxide, and rinsed with pure water. Next, metal impurities adhering to the substrate are removed with a mixed acid of dilute hydrochloric acid and hydrogen peroxide, and rinsed with pure water. Finally, the natural oxide film on the substrate surface is removed with dilute hydrofluoric acid and rinsed with pure water.

この基板を、図示は省略するが第１の実施形態と同様に、酸素雰囲気、１１００℃、２時間加熱し、基板表面を酸化し犠牲酸化膜を形成する。この基板裏面にＴｉを５０ｎｍ成膜した後、Ａｌを２μｍ成膜する。ここでＴｉはＳｉＣとＡｌを密着させる密着層の役割を果たし、Ａｌは後のＳｉＣエッチングのエッチングマスクの役割を果たす。このＡｌ表面に２μｍ程度のレジストをスピンコートし、ワッフル凹部を形成するためのパターンを露光・現像した後にハードベークをしてレジストを焼き固める。このレジストがパターニングされた基板を塩素系ガスによるＲＩＥチャンバーに導入し、パターニングされたレジストをエッチングマスクとしてＡｌをドライエッチングする。   Although not shown, this substrate is heated in an oxygen atmosphere at 1100 ° C. for 2 hours to oxidize the substrate surface and form a sacrificial oxide film, as in the first embodiment. After a Ti film having a thickness of 50 nm is formed on the back surface of the substrate, an Al film having a thickness of 2 μm is formed. Here, Ti serves as an adhesion layer for bringing SiC and Al into close contact, and Al serves as an etching mask for later SiC etching. A resist of about 2 μm is spin-coated on the Al surface, a pattern for forming a waffle recess is exposed and developed, and then hard-baked to harden the resist. The substrate on which the resist is patterned is introduced into an RIE chamber using a chlorine-based gas, and Al is dry etched using the patterned resist as an etching mask.

ついで、パターニングされたＡｌをエッチングマスクとしてＳｉＣをＣＦ4とＯ2の混合ガスによりドライエッチングする。このプロセスにより、ＳｉＣ基板４１の裏面が選択的にエッチングされ、ワッフル形状の凹部が形成される。 Then, SiC is dry-etched with a mixed gas of CF 4 and O 2 using the patterned Al as an etching mask. By this process, the back surface of the SiC substrate 41 is selectively etched to form a waffle-shaped recess.

次に、基板裏面に総ドーズ量７×１０15ｃｍ-2、最大加速エネルギー２００ｋｅＶにより、Ｐ（リン）イオンの多段注入を行い、裏面電極のオーミックコンタクト領域（不図示）を形成する。 Next, multistage implantation of P (phosphorus) ions is performed on the back surface of the substrate with a total dose of 7 × 10 15 cm −2 and a maximum acceleration energy of 200 keV, thereby forming an ohmic contact region (not shown) of the back electrode.

この基板を再び 硫酸と過酸化水素水の混酸で洗浄し、裏面のＴｉ／Ａｌおよび有機物を除去し、純水によりリンスする。ついで、希塩酸と過酸化水素水の混酸で基板に付着した金属不純物を更に除去し、純水によりリンスする。そして、最後に希フッ酸により基板表面の犠牲酸化膜を除去し、純水によりリンスし、ワッフル基板４１を形成する。   This substrate is again washed with a mixed acid of sulfuric acid and hydrogen peroxide solution to remove Ti / Al and organic substances on the back surface and rinse with pure water. Next, metal impurities adhering to the substrate are further removed with a mixed acid of dilute hydrochloric acid and hydrogen peroxide, and rinsed with pure water. Finally, the sacrificial oxide film on the substrate surface is removed with dilute hydrofluoric acid, and rinsed with pure water to form a waffle substrate 41.

この基板４１をＭＯ−ＣＶＤ(有機金属化学気相成長)装置に搬送し、図４６に示すように、ＡｌＮ緩衝層４３を１００ｎｍ、アンドープＧａＮ層４５を３μｍ、アンドープＡｌＧａＮ層４７を３ｎｍ、ｎ型ＡｌＧａＮ層４９を１０ｎｍ、アンドープＡｌＧａＮ層５１を５ｎｍ、順次ヘテロエピタキシャル成長させる。ここで、ＡｌＧａＮ層４９，５１のＡｌ含有量は３０％であり、ｎ型ＡｌＧａＮ層４９のドーピング濃度は５×１０18ｃｍ-3である。また、ＳｉＣ基板４１を用いているのは、上層のＧａＮ層の格子ミスマッチが少なく、エピタキシャル成長をさせ易いからである。 The substrate 41 is transferred to an MO-CVD (metal organic chemical vapor deposition) apparatus, and as shown in FIG. 46, the AlN buffer layer 43 is 100 nm, the undoped GaN layer 45 is 3 μm, the undoped AlGaN layer 47 is 3 nm, and the n-type. The AlGaN layer 49 is 10 nm and the undoped AlGaN layer 51 is sequentially heteroepitaxially grown. Here, the Al content of the AlGaN layers 49 and 51 is 30%, and the doping concentration of the n-type AlGaN layer 49 is 5 × 10 18 cm −3 . Also, the SiC substrate 41 is used because there is little lattice mismatch of the upper GaN layer and it is easy to perform epitaxial growth.

その後、図４７に示すように、リソグラフィ法及び異方性エッチング法等により基板表面からｎ型ＡｌＧａＮ層４９に到達するソースコンタクト領域６７を設ける。ついで、図４８に示すように、リソグラフィ法及び異方性エッチング法等により基板表面からＳｉＣ基板４１に到達する内部コンタクトホール６９を設ける。   Thereafter, as shown in FIG. 47, a source contact region 67 reaching the n-type AlGaN layer 49 from the substrate surface is provided by lithography or anisotropic etching. Next, as shown in FIG. 48, an internal contact hole 69 that reaches the SiC substrate 41 from the substrate surface is provided by lithography or anisotropic etching.

その後、パターニングマスクおよび、エッチングマスクを除去し、基板表面にレジストをスピンコートさせた後、再びパターニングでソースコンタクト領域および、コンタクトホール領域を開口させ、ＭＯ−ＣＶＤ、スパッタ、電子蒸着法などでＴｉ／Ａｌで表面電極を成膜し、裏面電極６５もＴｉ／Ａｌで成膜する。その後、表面の電極非成膜部分はレジスト除去と同時にリフトオフにより除去し、図４９に示すように、ソース領域（電極）５３、ドレイン領域５９を形成する。このあと、Ａｒ雰囲気でシンターを行い、電極部分をオーミックコンタクトさせる。   Thereafter, the patterning mask and the etching mask are removed, and a resist is spin-coated on the substrate surface. Then, the source contact region and the contact hole region are opened again by patterning, and Ti is formed by MO-CVD, sputtering, electron evaporation, or the like. The front electrode is formed with / Al, and the back electrode 65 is also formed with Ti / Al. Thereafter, the electrode non-film forming portion on the surface is removed by lift-off simultaneously with the resist removal, and a source region (electrode) 53 and a drain region 59 are formed as shown in FIG. Thereafter, sintering is performed in an Ar atmosphere to make ohmic contact between the electrode portions.

ついで、ゲート電極５５を形成するためにレジストパターニングを行い、電子銃蒸着などでＮｉ／Ａｕを成膜する。ここでも、図５０に示すように、表面の電極非成膜部分はレジスト除去と同時にリフトオフにより除去しシンターをする。   Next, resist patterning is performed to form the gate electrode 55, and Ni / Au is deposited by electron gun evaporation or the like. Also here, as shown in FIG. 50, the electrode non-film formation portion on the surface is removed by lift-off and sintered simultaneously with the resist removal.

次に、図５１に示すように、基板表面に絶縁膜のＳｉＮ膜５９を成膜、ついで図５２に示すように、その上にさらにＳｉ酸化膜６１を堆積する。最後に、フィールドプレート６３を形成し、図４５に示す高耐圧ＧａＮスイッチング素子を完成させる。   Next, as shown in FIG. 51, a SiN film 59 as an insulating film is formed on the substrate surface, and then a Si oxide film 61 is further deposited thereon as shown in FIG. Finally, a field plate 63 is formed to complete the high breakdown voltage GaN switching element shown in FIG.

以上により、裏面にワッフル部を有する基板上にヘテロエピタキシャル成長させた半導体層に半導体素子が形成された半導体装置を得ることができ、裏面から取り出したドレイン領域の抵抗を下げることが可能になる。   As described above, a semiconductor device in which a semiconductor element is formed in a semiconductor layer heteroepitaxially grown on a substrate having a waffle portion on the back surface can be obtained, and the resistance of the drain region taken out from the back surface can be reduced.

（第９の実施形態）
第１〜第８の実施形態で説明した半導体装置（パワーデバイス）を、ヒートシンクに取り付けて使用する場合、裏面のドレイン電極を表面に取り出し、電極への配線を全て上面で行いたい場合がある。このような要求にも、本発明のワッフル型の半導体装置を容易に適用させることができる。第９の実施形態では、このような例を説明する。 (Ninth embodiment)
When the semiconductor device (power device) described in the first to eighth embodiments is used by being attached to a heat sink, there is a case where the drain electrode on the back surface is taken out to the front surface and all wiring to the electrode is desired to be performed on the top surface. The waffle type semiconductor device of the present invention can be easily applied to such a demand. In the ninth embodiment, such an example will be described.

図５３は、第９の実施形態に係る半導体装置の実装形態を示す摸式的な斜視図である。半導体素子７１は、例えば第１あるいは第２の実施形態で説明したＳＢＤであるとする。参照番号１９は表面電極（第１の電極）である。半導体装置７１は、ヒートシンク７３に絶縁膜７５を介して接着されている。ＳＢＤ７１の裏面電極（１７）は、後に説明する方法で第２の電極７７に接続され、第１及び第２の電極への接続が半導体装置の上面で可能なように構成されている。   FIG. 53 is a schematic perspective view showing a mounting form of the semiconductor device according to the ninth embodiment. The semiconductor element 71 is assumed to be the SBD described in the first or second embodiment, for example. Reference numeral 19 is a surface electrode (first electrode). The semiconductor device 71 is bonded to the heat sink 73 via an insulating film 75. The back electrode (17) of the SBD 71 is connected to the second electrode 77 by a method described later, and is configured so that connection to the first and second electrodes is possible on the upper surface of the semiconductor device.

つぎに、この半導体構造の形成方法を説明する。まず、図５４に示すように、ＳＢＤ７１形成用の基板裏面の複数のワッフル形成部を連結するように複数のストライプ状の段差７９を設ける。基板上面には、図５５に示すように、既に第１あるいは第２の実施形態で説明したと同様の方法で表面素子領域８１を形成し、裏面にはコンタクトメタル１７までを形成する。次に、図５６に示すように、基板表面を厚膜レジスト（不図示）等で保護した後、基板裏面のワッフル凹部の段差７９をＡｌやＣｕの導体８３により埋め込む。   Next, a method for forming this semiconductor structure will be described. First, as shown in FIG. 54, a plurality of stripe-shaped steps 79 are provided so as to connect a plurality of waffle forming portions on the back surface of the substrate for forming the SBD 71. As shown in FIG. 55, the surface element region 81 is formed on the upper surface of the substrate by the same method as already described in the first or second embodiment, and the contact metal 17 is formed on the rear surface. Next, as shown in FIG. 56, after protecting the substrate surface with a thick film resist (not shown) or the like, the step 79 of the waffle recess on the back surface of the substrate is embedded with a conductor 83 of Al or Cu.

続いて、図５７に示すように、表面保護膜（不図示）を除去した後、再び表面にレジスト（不図示）を塗布し、パターニングにより、素子領域より外周部分を開口させ、ＲＩＥなどにより裏面の埋め込み電極１７が見えるまでエッチングをする。表面に現れた裏面埋め込み電極１７はＡｌストラップなどで接続し、第２の電極７９とする。   Subsequently, as shown in FIG. 57, after removing the surface protective film (not shown), a resist (not shown) is applied to the surface again, and the outer peripheral portion is opened from the element region by patterning, and the back surface is formed by RIE or the like. Etching is performed until the embedded electrode 17 is visible. The back-surface embedded electrode 17 that appears on the front surface is connected by an Al strap or the like to serve as the second electrode 79.

最後に、図５３に示すように、表面に絶縁膜７５の付いた冷却フィン７３上に上記ＳＢＤ７１をマウントし、第１の電極１９、第２の電極７９をボンディングワイヤ８５で所要の接続箇所とボンディングする。   Finally, as shown in FIG. 53, the SBD 71 is mounted on the cooling fin 73 with the insulating film 75 on the surface, and the first electrode 19 and the second electrode 79 are connected to the required connection locations by the bonding wires 85. Bond.

以上の工程で、ヒーシンクに取り付けられたワッフル型パワーデバイスが完成し、第１及び第２の電極の配線を、パワーデバイス（半導体装置）の上面で容易に行なうことができる。   Through the above steps, the waffle type power device attached to the heat sink is completed, and the wiring of the first and second electrodes can be easily performed on the upper surface of the power device (semiconductor device).

（変形例）
第１〜第８の実施形態では、裏面電極１７をワッフル凹部の底面、若しくは凸部から凹部底面にかけての面に沿って形成したが、図５８に示すように、凹部を導体８３で埋め込んでも良い。この場合、導体８３は第９の実施形態と同様にＡｌやＣｕを埋め込めばよい。 (Modification)
In the first to eighth embodiments, the back electrode 17 is formed along the bottom surface of the waffle recess or the surface from the projection to the bottom of the recess. However, the recess may be embedded with a conductor 83 as shown in FIG. . In this case, the conductor 83 may be embedded with Al or Cu as in the ninth embodiment.

また、第１〜第８の実施形態では、図５９に示すようにダイシングライン２３をワッフル凸部２１に一致させたが、図６０に示すように、ダイシングライン２３がワッフル凹部を通るようにしてもよい。即ち、即ち、素子形成領域の直下に、ワッフル凹部の少なくとも一部が配置されればよい。なお、図５９，６０では、理解を容易にするために、ダイシングライン２３を１素子分のみ模式的に表示している。   In the first to eighth embodiments, the dicing line 23 is made to coincide with the waffle convex portion 21 as shown in FIG. 59. However, as shown in FIG. 60, the dicing line 23 passes through the waffle concave portion. Also good. That is, at least a part of the waffle recess may be disposed immediately below the element formation region. In FIGS. 59 and 60, only one element of the dicing line 23 is schematically displayed for easy understanding.

さらに、本発明は上記実施形態、変形例に限らず、発明の要旨を逸脱しない範囲で、種々変更して実施することができる。   Furthermore, the present invention is not limited to the above-described embodiments and modifications, and various modifications can be made without departing from the spirit of the invention.

本発明の第１の実施形態に係る半導体装置（ＳＢＤ）の断面図。1 is a cross-sectional view of a semiconductor device (SBD) according to a first embodiment of the present invention. 第１の実施形態の半導体装置の底面図。The bottom view of the semiconductor device of a 1st embodiment. 第１の実施形態の製造工程を説明するための断面図。Sectional drawing for demonstrating the manufacturing process of 1st Embodiment. 第１の実施形態の製造工程を説明するための断面図。Sectional drawing for demonstrating the manufacturing process of 1st Embodiment. 第１の実施形態の製造工程を説明するための断面図。Sectional drawing for demonstrating the manufacturing process of 1st Embodiment. 第１の実施形態の製造工程を説明するための断面図。Sectional drawing for demonstrating the manufacturing process of 1st Embodiment. 第１の実施形態の製造工程を説明するための断面図。Sectional drawing for demonstrating the manufacturing process of 1st Embodiment. 第１の実施形態の製造工程を説明するための断面図。Sectional drawing for demonstrating the manufacturing process of 1st Embodiment. 第１の実施形態の製造工程を説明するための断面図。Sectional drawing for demonstrating the manufacturing process of 1st Embodiment. 第１の実施形態の製造工程を説明するための断面図。Sectional drawing for demonstrating the manufacturing process of 1st Embodiment. 第１の実施形態の製造工程を説明するための断面図。Sectional drawing for demonstrating the manufacturing process of 1st Embodiment. 凹部１個毎のダイシングを説明する断面図。Sectional drawing explaining the dicing for every recessed part. 凹部４個毎のダイシングを説明する断面図。Sectional drawing explaining the dicing for every four recessed parts. 本発明のワッフル基板を説明する模式的斜視図。The typical perspective view explaining the waffle board | substrate of this invention. 凹部形成の変形例を示す断面図。Sectional drawing which shows the modification of recessed part formation. 本発明の第２の実施形態に係る半導体装置（ＳＢＤ）の断面図。Sectional drawing of the semiconductor device (SBD) which concerns on the 2nd Embodiment of this invention. 第２の実施形態の製造工程を説明するための断面図。Sectional drawing for demonstrating the manufacturing process of 2nd Embodiment. 第２の実施形態の製造工程を説明するための断面図。Sectional drawing for demonstrating the manufacturing process of 2nd Embodiment. 第２の実施形態の製造工程を説明するための断面図。Sectional drawing for demonstrating the manufacturing process of 2nd Embodiment. 第２の実施形態の製造工程を説明するための断面図。Sectional drawing for demonstrating the manufacturing process of 2nd Embodiment. 第２の実施形態の製造工程を説明するための断面図。Sectional drawing for demonstrating the manufacturing process of 2nd Embodiment. 第２の実施形態の製造工程を説明するための断面図。Sectional drawing for demonstrating the manufacturing process of 2nd Embodiment. 本発明の第３の実施形態に係る半導体装置（ＳＩＴ／ＪＦＥＴ）の断面図。Sectional drawing of the semiconductor device (SIT / JFET) concerning the 3rd Embodiment of this invention. 第３の実施形態に係る半導体装置（ＳＩＴ／ＪＦＥＴ）の上面図。The top view of the semiconductor device (SIT / JFET) concerning a 3rd embodiment. 第３の実施形態の製造工程を説明するための断面図。Sectional drawing for demonstrating the manufacturing process of 3rd Embodiment. 第３の実施形態の製造工程を説明するための断面図。Sectional drawing for demonstrating the manufacturing process of 3rd Embodiment. 第３の実施形態の製造工程を説明するための断面図。Sectional drawing for demonstrating the manufacturing process of 3rd Embodiment. 第３の実施形態の製造工程を説明するための断面図。Sectional drawing for demonstrating the manufacturing process of 3rd Embodiment. 本発明の第４の実施形態に係る半導体装置（ＭＯＳＦＥＴ）の断面図。Sectional drawing of the semiconductor device (MOSFET) based on the 4th Embodiment of this invention. 第４の実施形態に係る半導体装置（ＭＯＳＦＥＴ）の上面図。The top view of the semiconductor device (MOSFET) concerning a 4th embodiment. 第４の実施形態の製造工程を説明するための断面図。Sectional drawing for demonstrating the manufacturing process of 4th Embodiment. 第４の実施形態の製造工程を説明するための断面図。Sectional drawing for demonstrating the manufacturing process of 4th Embodiment. 第４の実施形態の製造工程を説明するための断面図。Sectional drawing for demonstrating the manufacturing process of 4th Embodiment. 第４の実施形態の製造工程を説明するための断面図。Sectional drawing for demonstrating the manufacturing process of 4th Embodiment. 第４の実施形態の製造工程を説明するための断面図。Sectional drawing for demonstrating the manufacturing process of 4th Embodiment. 本発明の第５（第６）の実施形態に係る半導体装置（ｐｉｎダイオード）の断面図。Sectional drawing of the semiconductor device (pin diode) which concerns on 5th (6th) embodiment of this invention. 第５（第６）の実施形態の製造工程を説明するための断面図。Sectional drawing for demonstrating the manufacturing process of 5th (6th) embodiment. 第５（第６）の実施形態の製造工程を説明するための断面図。Sectional drawing for demonstrating the manufacturing process of 5th (6th) embodiment. 第５（第６）の実施形態の製造工程を説明するための断面図。Sectional drawing for demonstrating the manufacturing process of 5th (6th) embodiment. 第５（第６）の実施形態の製造工程を説明するための断面図。Sectional drawing for demonstrating the manufacturing process of 5th (6th) embodiment. 本発明の第７の実施形態に係る半導体装置（ＩＧＢＴ）の断面図。Sectional drawing of the semiconductor device (IGBT) which concerns on the 7th Embodiment of this invention. 第７の実施形態の製造工程を説明するための断面図。Sectional drawing for demonstrating the manufacturing process of 7th Embodiment. 第７の実施形態の製造工程を説明するための断面図。Sectional drawing for demonstrating the manufacturing process of 7th Embodiment. 第７の実施形態の製造工程を説明するための断面図。Sectional drawing for demonstrating the manufacturing process of 7th Embodiment. 本発明の第８の実施形態に係る半導体装置（ＨＥＭＴ）の断面図。Sectional drawing of the semiconductor device (HEMT) which concerns on the 8th Embodiment of this invention. 第８の実施形態の製造工程を説明するための断面図。Sectional drawing for demonstrating the manufacturing process of 8th Embodiment. 第８の実施形態の製造工程を説明するための断面図。Sectional drawing for demonstrating the manufacturing process of 8th Embodiment. 第８の実施形態の製造工程を説明するための断面図。Sectional drawing for demonstrating the manufacturing process of 8th Embodiment. 第８の実施形態の製造工程を説明するための断面図。Sectional drawing for demonstrating the manufacturing process of 8th Embodiment. 第８の実施形態の製造工程を説明するための断面図。Sectional drawing for demonstrating the manufacturing process of 8th Embodiment. 第８の実施形態の製造工程を説明するための断面図。Sectional drawing for demonstrating the manufacturing process of 8th Embodiment. 第８の実施形態の製造工程を説明するための断面図。Sectional drawing for demonstrating the manufacturing process of 8th Embodiment. 本発明の第９の実施形態に係る半導体装置の断面図。Sectional drawing of the semiconductor device which concerns on the 9th Embodiment of this invention. 第９の実施形態の製造工程を説明するための断面図。Sectional drawing for demonstrating the manufacturing process of 9th Embodiment. 第９の実施形態の製造工程を説明するための断面図。Sectional drawing for demonstrating the manufacturing process of 9th Embodiment. 第９の実施形態の製造工程を説明するための断面図。Sectional drawing for demonstrating the manufacturing process of 9th Embodiment. 第９の実施形態の製造工程を説明するための断面図。Sectional drawing for demonstrating the manufacturing process of 9th Embodiment. 本発明の変形例を説明する断面図。Sectional drawing explaining the modification of this invention. 本発明のワッフル基板の凸部とダンシングラインの関係の一例を説明する図。The figure explaining an example of the relationship between the convex part of the waffle board | substrate of this invention, and a dancing line. 本発明のワッフル基板の凸部とダンシングラインの関係の他の例を説明する図。The figure explaining the other example of the relationship between the convex part of the waffle board | substrate of this invention, and a dancing line.

符号の説明Explanation of symbols

１…基板
２…ＳｉＣ基板
３…エピタキシャル層
５…犠牲酸化膜
７…Ｔｉ層
９…Ａｌ層
１１…レジスト
１２…リサーフ領域
１３…裏面電極用（第２の）オーミックコンタクト領域
１４…ガードリング
１５…Ｓｉ酸化膜
１７…裏面（第２の）電極
１９…上面（第１の）電極
１９ｇ…ゲート電極
１９ｓ…ソース電極
２１…ＳｉＣ支持体
２３…ダイシングライン
２５…ソース領域
２７…ゲート領域
２９…ｐ型ウェル
３１…ゲート絶縁膜
３３…上部電極用（第１の）オーミックコンタクト領域
３５…絶縁膜
４１…ＳｉＣ基板
４３…ＡｌＮ緩衝層
４５…アンドープＧａＮ層
４７…アンドープＡｌＧａＮ層
４９…ｎ型ＡｌＧａＮ層
５１…アンドープＡｌＧａＮ層
５３…ソース領域
５５…ゲート電極
５７…ドレイン領域
５９…シリコン窒化膜
６１…シリコン酸化膜
６３…フィールドプレート
６５…裏面電極
７１…ＳＢＤ素子
７３…ヒートシンク
７５…絶縁膜
７７…第２の電極（ドレイン電極）
７９…段差
８１…ＳＢＤ素子領域
８３…導体
８５…ボンディングワイヤ DESCRIPTION OF SYMBOLS 1 ... Substrate 2 ... SiC substrate 3 ... Epitaxial layer 5 ... Sacrificial oxide film 7 ... Ti layer 9 ... Al layer 11 ... Resist 12 ... RESURF region 13 ... (second) ohmic contact region 14 for back electrode ... Guard ring 15 ... Si oxide film 17 ... back surface (second) electrode 19 ... top surface (first) electrode 19g ... gate electrode 19s ... source electrode 21 ... SiC support 23 ... dicing line 25 ... source region 27 ... gate region 29 ... p-type Well 31 ... Gate insulating film 33 ... (first) ohmic contact region 35 for upper electrode ... Insulating film 41 ... SiC substrate 43 ... AlN buffer layer 45 ... Undoped GaN layer 47 ... Undoped AlGaN layer 49 ... n-type AlGaN layer 51 ... Undoped AlGaN layer 53 ... source region 55 ... gate electrode 57 ... drain region 59 ... silicon nitride film 61 ... silico Oxide film 63 ... field plate 65 ... back electrode 71 ... SBD device 73 ... heat sink 75 ... insulating film 77 ... second electrode (drain electrode)
79 ... Step 81 ... SBD element region 83 ... Conductor 85 ... Bonding wire

Claims (6)

網目状の凸部により形成された複数の凹部を裏面に有し、第１の不純物濃度を有する半導体からなる支持体と、
前記支持体の前記裏面に対向する表面に形成され、前記第１の不純物濃度よりも低い第２の不純物濃度を有する半導体層と、
前記半導体層に形成された半導体素子と、
を具備することを特徴とする半導体装置。 A support made of a semiconductor having a plurality of recesses formed by mesh-like protrusions on the back surface and having a first impurity concentration;
A semiconductor layer formed on a surface facing the back surface of the support and having a second impurity concentration lower than the first impurity concentration;
A semiconductor element formed in the semiconductor layer;
A semiconductor device comprising: 前記支持体の前記表面の面積は、前記複数の凹部の占有平面積の合計より大きいことを特徴とする請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein an area of the surface of the support is larger than a total area occupied by the plurality of recesses. 前記表面に第１の電極が形成され、前記裏面の少なくとも前記複数の凹部の底面に第２の電極が形成され、前記第１の電極の直下に前記第２の電極の少なくとも一部が配置されることを特徴とする請求項１または２に記載の半導体装置。   A first electrode is formed on the front surface, a second electrode is formed on at least the bottom surfaces of the plurality of recesses on the back surface, and at least a part of the second electrode is disposed directly below the first electrode. The semiconductor device according to claim 1, wherein: 前記半導体層は、前記支持体と同一元素で構成され、同一結晶方位を有することを特徴とする請求項１乃至３のいずれかに記載の半導体装置。   4. The semiconductor device according to claim 1, wherein the semiconductor layer is made of the same element as the support and has the same crystal orientation. 前記同一元素はＳｉ，Ｃを含むことを特徴とする請求項４に記載の半導体装置。   The semiconductor device according to claim 4, wherein the same element includes Si and C. 前記半導体層は、前記支持体と異種の元素を含んで構成され、同一結晶方位を有することを特徴とする請求項１乃至３のいずれかに記載の半導体装置。   The semiconductor device according to claim 1, wherein the semiconductor layer includes an element different from the support and has the same crystal orientation.
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