JP2011023478A - Semiconductor device, and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device of which the breakage due to an overvoltage can be suppressed, and to provide a method of manufacturing the same. <P>SOLUTION: As one embodiment of the semiconductor device, a semiconductor device includes: a plurality of vertical transistors 32 which are connected to one another in parallel and each of which includes a gate electrode 10, a source electrode 9 and a drain electrode 15; and a diode 31 individually surrounding the plurality of vertical transistors 32. An anode 11 of the diode 31 is connected to the source electrode 9 and a cathode 1 of the diode is connected to the drain electrode 15. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  Power device structures include a horizontal structure in which a source and a drain are arranged in parallel to the surface of the substrate, and a vertical structure in which the source and the drain are arranged perpendicular to the surface of the substrate. In the vertical structure, the current path is three-dimensional, so that the amount of current per chip is larger than that in the horizontal structure. In the vertical structure, since the source electrode and the drain electrode are formed on the front surface and the back surface of the substrate, they are used for the source electrode and the drain electrode as compared with the horizontal structure formed only on the surface of the substrate. Small chip area is required. Furthermore, in the vertical structure, the ratio of the electrodes per chip is larger than that in the horizontal structure, so that heat dissipation is high.

  Si type vertical transistors and GaN high electron mobility transistors (HEMTs) are known as vertical structure power devices. FIG. 1 is a diagram showing the configuration of a Si-based vertical transistor and a GaN-based HEMT. As shown in FIG. 1A, a diode 102 and a capacitor 103 are parasitic in the Si-based vertical transistor 101. The diode 102 functions as a current path when a voltage is applied in the reverse direction between the source and the drain. The diode 102 also functions as a protective diode that prevents breakdown of the transistor by flowing a breakdown current when an overvoltage is applied between the source and the drain. On the other hand, in the GaN-based HEMT 111, as shown in FIG. 1B, the capacitor 113 is parasitic, but the diode is not parasitic. Therefore, integration of GaN-based HEMTs and diodes has been attempted.

  However, in the conventional technology, in both the GaN HEMT integrated with the diode and the Si vertical transistor, the breakdown due to the application of the overvoltage, particularly the breakdown due to the surge flowing in through the bonded wire. It cannot be adequately protected.

JP 2007-59882 A JP 2000-40818 International Publication No. 2005/096365 JP 2000-294778 A JP 2007-35736 A

Proceedings of the 19th International Symposium on Power Semiconductor Devices & ICs, p.117-120

  An object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can suppress the breakdown due to overvoltage.

  One embodiment of a semiconductor device includes a plurality of vertical transistors that are connected in parallel to each other and that include a gate electrode, a source electrode, and a drain electrode, and diodes that individually surround the plurality of vertical transistors. . The anode of the diode is connected to the source electrode, and the cathode of the diode is connected to the drain electrode.

  According to the above semiconductor device or the like, since an appropriate diode is provided, it is possible to suppress the breakdown of the vertical transistor even when an overvoltage is applied.

It is a figure which shows the structure of Si type vertical transistor and GaN type HEMT. 1 is a plan view showing a structure of a semiconductor device according to a first embodiment. It is sectional drawing which shows the structure of the semiconductor device which concerns on 1st Embodiment. It is a figure which shows the mounting state of the semiconductor device which concerns on 1st Embodiment. FIG. 6 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment in the order of steps. FIG. 5B is a cross-sectional view illustrating the manufacturing method of the semiconductor device according to the first embodiment in order of processes following FIG. FIG. 5B is a cross-sectional view illustrating the manufacturing method of the semiconductor device according to the first embodiment in order of processes, following FIG. 5B. FIG. 5D is a cross-sectional view illustrating the manufacturing method of the semiconductor device according to the first embodiment in order of processes following FIG. 5C. It is a figure which shows the structure of a HVPE apparatus and a MOCVD apparatus. It is sectional drawing which shows the structure of the semiconductor device which concerns on 2nd Embodiment. It is sectional drawing which shows the structure of the semiconductor device which concerns on 3rd Embodiment. It is a figure which shows the sample in experiment.

  Hereinafter, embodiments of the present invention will be specifically described with reference to the accompanying drawings.

(First embodiment)
First, the semiconductor device according to the first embodiment will be described. FIG. 2 is a plan view showing the structure of the semiconductor device according to the first embodiment, and FIG. 3 is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

  As shown in FIGS. 2 and 3, in the first embodiment, a plurality of GaN-based HEMTs 32 are connected in parallel to each other. That is, the gate electrode 10 of each GaN-based HEMT 32 is commonly connected to the gate pad 21 via the gate wiring 23, the source electrode 9 is commonly connected to the source wiring 13, and the drain electrode 15 is shared by all the GaN-based HEMTs 32. Yes. In each GaN-based HEMT 32, the gate electrode 10 and the source electrode 9 are located on the front surface side of the substrate 1, and the drain electrode 15 is located on the back surface side. The source electrode 9 is formed so as to surround the gate electrode 10 in plan view. An insulating film 22 is formed between the gate pad 21 and the source wiring 13, and the gate pad 21 and the source wiring 13 are insulated and separated from each other by the insulating film 22.

  Further, a diode 31 surrounding the GaN-based HEMT 32 in plan view is formed. The diode 31 is formed in a lattice shape, and the GaN-based HEMT 32 is located inside the lattice formed by the diode 31.

Here, the cross-sectional structures of the GaN-based HEMT 32 and the diode 31 will be described in detail. As shown in FIG. 3, the insulating layer 2, the electron transit layer 3, and the electron supply layer 4 are formed on the substrate 1. The substrate 1 is a single crystal substrate of a compound semiconductor such as gallium nitride (GaN). The insulating layer 2 is, for example, an aluminum nitride (AlN) film and has a thickness of about 0.01 μm to 10 μm. The electron transit layer 3 is a gallium nitride layer doped with, for example, about 1 × 10 ¹⁷ cm ⁻³ to 1 × 10 ²⁰ cm ^{−3 of} Si, and has a thickness of about 0.05 μm to 5 μm. The electron supply layer 4 is an AlGaN layer doped with, for example, about 1 × 10 ¹⁷ cm ⁻³ to 1 × 10 ¹⁹ cm ^{−3 of} Si, and has a thickness of about 1 nm to 20 nm. Since the electron supply layer 4 has a wide band gap, a deep potential well is formed in the vicinity of the interface between the electron transit layer 3 and the electron supply layer 4, and a two-dimensional electron gas 2DEG is generated there.

  A recess 5 for gate is formed in the electron supply layer 4 and the electron transit layer 3. A gate insulating film 7 is formed on the side and bottom surfaces of the recess 5 and the upper surface of the electron transit layer 3, and a gate electrode 10 is formed on the gate insulating film 7. A source electrode 9 is formed on the electron transit layer 3 so as to surround the gate electrode 10 and the gate insulating film 7 in plan view.

  Further, a recess 14 is formed that penetrates the substrate 1 and the insulating layer 2 and reaches the middle of the electron transit layer 3. The recess 14 is formed wider than the recess 5 immediately below the recess 5. A drain electrode 15 is formed on the side and bottom surfaces of the recess 5 and the back surface of the substrate 1. In this way, individual GaN-based HEMTs 32 are configured.

  Furthermore, a recess 6 for the diode that penetrates the electron supply layer 4, the electron transit layer 3, and the insulating layer 2 and reaches the middle of the substrate 1 is formed. The recess 6 is formed so as to surround each GaN-based HEMT 32 in plan view. A Schottky electrode 11 that is in Schottky contact with the substrate 1 is formed at the bottom of the recess 6. As the Schottky electrode 11, for example, a stacked body of a Ni film and an Au film formed thereon is used. In this way, the Schottky diode 31 is configured. In this diode 31, the Schottky electrode 11 functions as an anode, and the substrate 1 including a compound semiconductor functions as a cathode.

  Furthermore, the insulating film 12 covering the gate electrode 10, the gate wiring 23 commonly connecting each gate electrode 10 to the gate pad 21, the source wiring 13 commonly connecting each source electrode 9, and the source wiring 13 covering the gate wiring 23. An insulating film 22 for insulating and isolating the gate pad 21 is formed. Each Schottky electrode 11 is also connected to the source wiring 13.

  The semiconductor device according to the first embodiment is mounted on a mounting substrate 28, for example, as shown in FIG. The gate terminal G provided on the mounting substrate 28 and the gate pad 21 are connected by the gate wire 26, the source terminal S and the source wiring 13 are connected by the source wire 27, and the drain electrode 15 is connected to the drain terminal D. Is connected. In such a configuration, a surge may flow into the source wiring 13 through the source terminal S and the source wire 27. In this case, in the first embodiment, since the Schottky diode 31 connected to the source wiring 13 is located around each GaN-based HEMT 32, the surge does not flow through the GaN-based HEMT 32, and the diode 31 is not connected. Flowing. For this reason, destruction of the GaN-based HEMT 32 can be sufficiently suppressed. Even if there are protective diodes surrounding the GaN HEMTs 32 so as to surround all the GaN HEMTs 32, if there are no diodes 31 surrounding each GaN HEMT 32 individually, a large current due to a surge is generated in the protective diodes. Before flowing, a large current flows through the GaN-based HEMT 32 in the vicinity of the source wire 27. For this reason, it cannot be said that the protection of the GaN-based HEMT 32 is sufficient.

  Next, a method for manufacturing the semiconductor device according to the first embodiment will be described. 5A to 5D are cross-sectional views illustrating the method of manufacturing the semiconductor device according to the first embodiment in the order of steps.

  First, as shown in FIG. 5A (a), an insulating layer 2 is formed on a substrate 1 by a halogen vapor phase epitaxy (HVPE) method. For example, an AlN film is formed as the insulating layer 2.

Here, the HVPE apparatus will be described. FIG. 6A is a diagram illustrating a configuration of the HVPE apparatus. A high frequency coil 131 for induction heating is wound around a quartz reaction tube 130, and a carbon susceptor 132 for placing the substrate 120 is disposed therein. Two gas introduction pipes 134 and 135 are connected to the upstream end of the reaction tube 130 (the left end in FIG. 6A), and the downstream end of the reaction tube 130 (the right side in FIG. 6A). One gas discharge pipe 136 is connected to the end). A boat 138 is disposed on the upstream side of the susceptor 132 in the reaction tube 130, and a group III element source 139 of the compound to be grown is accommodated therein. The source 139 is Al when, for example, an AlN film is crystal-grown. Ammonia (NH ₃ ) gas is introduced from the gas introduction pipe 134 as an N source gas, and hydrogen chloride (HCl) gas is introduced from the gas introduction pipe 135. The HCl gas reacts with the group III source 139 in the boat 138 to generate a group III element chloride (such as AlCl) as the source gas. Source gas (AlCl gas or the like) and NH ₃ gas are conveyed onto the substrate 120 and react on the surface of the substrate 120 to grow an AlN film or the like. Excess gas is discharged from the gas discharge pipe 136 to the detoxification tower. Note that the source 139 for crystal growth of the GaN layer is Ga, and the source gas of the group III element chloride is GaCl.

Conditions for forming an AlN film as the insulating layer 2 are set as follows, for example.
Pressure: normal pressure
HCl gas flow rate: 100 ccm (100 cm ³ / min),
NH ₃ gas flow rate: 10 lm (10 liters / min),
Temperature: 1100 ° C.

  After the insulating layer 2 is formed, the electron transit layer 3 is formed on the insulating layer 2 by an organic chemical vapor deposition (MOCVD) method. For example, an n-type GaN layer is formed as the electron transit layer 3.

Here, the MOCVD apparatus will be described. FIG. 6B is a diagram showing the configuration of the MOCVD apparatus. A high frequency coil 141 is disposed around the quartz reaction tube 140, and a carbon susceptor 142 for placing the substrate 120 is disposed inside the reaction tube 140. Two gas introduction pipes 144 and 145 are connected to the upstream end of the reaction tube 140 (the left end in FIG. 6B), and a compound source gas is supplied. For example, NH ₃ gas is introduced from the gas introduction pipe 144 as an N source gas, and organic substances such as trimethylaluminum (TMA), trimethylgallium (TMA), and trimethylindium (TMI) are used as a group III element source gas from the gas introduction pipe 145. Group III compound raw material is introduced. Crystal growth is performed on the substrate 120, and excess gas is discharged from the gas discharge pipe 146 to the detoxification tower. When crystal growth by MOCVD is performed in a reduced pressure atmosphere, the gas exhaust pipe 146 is connected to a vacuum pump, and the exhaust port of the vacuum pump is connected to a detoxification tower. The MOCVD apparatus is used not only for forming an n-type GaN layer but also for forming an n-type AlGaN layer or the like as an electron supply layer 4 described later.

Conditions for forming an n-type GaN layer as the electron transit layer 3 are set as follows, for example.
Trimethylgallium (TMG) flow rate: 0-50 sccm,
Trimethylaluminum (TMA) flow rate: 0-50 sccm,
Trimethylindium (TMI) flow rate: 0-50 sccm,
Ammonia (NH ₃ ) flow rate: 20 slm,
n-type impurity: silane (SiH ₄ ),
Pressure: 100 Torr,
Temperature: 1100 ° C.

  When a silicon substrate is used as the substrate 1, even if an AlN film is formed as the insulating layer 2, the GaN layer is difficult to grow on the AlN film. For this reason, it is preferable to form an AlGaN layer (not shown) containing 10 atomic% (at%) of Al in the initial stage of forming the n-type GaN layer as the electron transit layer 3.

  After the electron transit layer 3 is formed, the electron supply layer 4 is formed on the electron transit layer 3 by MOCVD. For example, an n-type AlGaN layer is formed as the electron supply layer 4.

  Next, as shown in FIG. 5A (b), a recess 5 for gate and a recess 6 for diode are formed. The recesses 5 and 6 are preferably formed separately from each other, for example. This is because the depth is different. In forming the recess 5, for example, a resist pattern that exposes a region where the recess 5 is to be formed is formed, and the electron supply layer 4 and the electron transit layer 3 may be etched using the resist pattern as a mask. Thereafter, the resist pattern is removed. In forming the recess 6, for example, a resist pattern that exposes a region where the recess 6 is to be formed is formed, and the electron supply layer 4, the electron transit layer 3, the insulating layer 2, and the substrate 1 are etched using this resist pattern as a mask. do it. Thereafter, the resist pattern is removed.

  Thereafter, as shown in FIG. 5A (c), an insulating film 7a is formed on the entire surface by plasma CVD.

Subsequently, a resist pattern is formed on the insulating film 7a so as to cover a region where the gate insulating film 7 is to be formed, and the insulating film 7a is selectively etched using the resist pattern as a mask. As shown, a gate insulating film 7 is formed. At the time of selective etching of the insulating film 7a, for example, SF ₆ gas is used as an etching gas.

  Next, as shown in FIG. 5B (e), a source electrode 9 is formed around each gate insulating film 7 by, for example, a lift-off method. When forming the source electrode 9, for example, a Ta film is formed, and an Al film is formed thereon.

  Thereafter, as shown in FIG. 5B (f), the gate electrode 10 is formed on the gate insulating film 7 and the Schottky electrode 11 is formed on the bottom of the recess 6 by, for example, a lift-off method. When forming the gate electrode 10 and the Schottky electrode 11, for example, a Ni film is formed, and an Au film is formed thereon.

  Subsequently, as shown in FIG. 5C (g), the insulating film 12 is formed on the entire surface by plasma CVD.

Next, as shown in FIG. 5C (h), an opening exposing at least a part of the source electrode 9 and an opening exposing at least a part of the Schottky electrode 11 are formed in the insulating film 12. An opening exposing at least a part of the gate electrode 10 is also formed in the insulating film 12. In forming these openings, selective etching using SF ₆ gas is performed using the resist pattern as a mask.

  Thereafter, the gate wirings 23 and the gate pads 21 that are in contact with the gate electrodes 10 through the openings formed in the insulating film 12 are formed, for example, for lift-off (see FIG. 2). Subsequently, an insulating film 22 that covers the gate wiring 23 and exposes the source electrode 9 and the gate pad 21 is formed. At this time, the insulating film 22 is also provided with a portion surrounding the gate pad 21 (see FIG. 2).

  Next, as shown in FIG. 5C (i), the source wiring 13 that is insulated and separated from the gate pad 21 by the insulating film 22 and is in contact with each source electrode 9 and each Schottky electrode 11 is formed on the insulating film 12 or the like. That is, the source wiring 13 is formed on almost the entire surface of the substrate 1. When forming the source wiring 13, for example, an Au film is formed by a plating method.

  Thereafter, as shown in FIG. 5D (j), the substrate 1 is thinned to a predetermined thickness. In this case, for example, after the surface protective film 16 is formed on the front surface side of the substrate 1, the back surface is polished. Subsequently, a recess 14 reaching the middle of the electron transit layer 3 for each GaN-based HEMT 32 is formed from the back surface of the substrate 1. In forming the recess 14, for example, a resist pattern that exposes a region where the recess 14 is to be formed is formed, and the substrate 1, the insulating layer 2, and the electron transit layer 3 may be etched using this resist pattern as a mask. Thereafter, the resist pattern is removed.

  Next, the drain electrode 15 is formed on the entire back surface of the substrate 1. Thereafter, the surface protective film 16 is removed.

  In this way, the semiconductor device can be completed.

(Second Embodiment)
Next, a second embodiment will be described. In the first embodiment, a Schottky diode is provided as the diode 31. However, in the second embodiment, a pn junction type diode is provided as the diode 31. FIG. 7 is a cross-sectional view showing the structure of the semiconductor device according to the second embodiment.

  In the second embodiment, an n-type substrate is used as the substrate 1. A p-well 17 is formed around the recess 6 of the substrate 1. That is, a pn junction exists between the n-type substrate 1 and the p well 17. In this embodiment, an ohmic electrode 18 that is in ohmic contact with the p-well 17 is formed in place of the Schottky electrode 11. The p-well 17 functions as an anode, and the substrate 1 functions as a cathode. Other structures are the same as those of the first embodiment.

  Even in the second embodiment configured as described above, when a surge flows into the source wiring 13, the surge flows through the diode 31 without flowing through the GaN-based HEMT 32. For this reason, destruction of the GaN-based HEMT 32 can be sufficiently suppressed.

  The material, thickness, impurity concentration, etc. of the substrate 1 and each layer in the first and second embodiments are not particularly limited. For example, as the substrate 1, a conductive silicon substrate, a conductive sapphire substrate, a conductive SiC substrate, a conductive GaN substrate, or the like may be used. Moreover, as the electron transit layer 3 and the electron supply layer 4, those containing a group 3 nitride can be used.

  When the operating speed of the diode 31 is compared, the Schottky type can operate faster than the pn junction type.

(Third embodiment)
Next, a third embodiment will be described. In the first and second embodiments, a GaN-based HEMT is provided. In the third embodiment, a Si-based vertical transistor is provided. FIG. 8 is a cross-sectional view showing the structure of the semiconductor device according to the third embodiment.

  In the third embodiment, a plurality of Si-based vertical transistors 82 are connected in parallel to each other. That is, the gate electrode 60 of each Si-based vertical transistor 82 is commonly connected to the gate pad via the gate wiring, the source electrode 59 is commonly connected to the source wiring 63, and the drain electrode 65 is all Si-based vertical transistors 82. Shared by. The planar arrangement of the gate electrode 60, the source electrode 59, and the drain electrode 65 is the same as the planar arrangement of the gate electrode 10, the source electrode 9, and the drain electrode 15 of the first embodiment.

  Also, a diode 81 is formed surrounding the Si-based vertical transistor 82 in plan view. The diode 81 is formed in a lattice shape, and the Si-based vertical transistor 82 is located inside the lattice formed by the diode 81.

  Here, the cross-sectional structures of the Si-based vertical transistor 82 and the diode 81 will be described in detail. As shown in FIG. 8, an n-well 52 is formed on the surface of the n-type substrate 1. The impurity concentration of the substrate 1 is higher than the impurity concentration of the n-well 52. A gate insulating film 57 is formed on the n-well 52, and a gate electrode 60 is formed on the gate insulating film 57. A source electrode 59 is formed on the n-well 52 so as to surround the gate electrode 60 and the gate insulating film 57 in plan view.

  An n-type impurity diffusion layer 54 is formed in a region immediately below the source electrode 59 of the n-well 52, and a p-type impurity diffusion layer 53 is formed in the region around and immediately below the n-type impurity diffusion layer 54. The p-type impurity diffusion layer 53 extends to below the gate electrode 60, and the potential of the p-type impurity diffusion layer 53 is controlled by the gate electrode 60. On the other hand, the potential of the n-type impurity diffusion layer 54 is controlled by the source electrode 59.

  Further, a drain electrode 65 is formed on the back surface of the substrate 1. The potentials of the n-type substrate 51 and the n-well 52 are controlled by the drain electrode 65. In this manner, individual Si-based vertical transistors 82 are configured.

  Further, a recess 56 for the diode that penetrates the n-well 52 and reaches the middle of the substrate 51 is formed. The recess 56 is formed so as to surround each Si-type vertical transistor 82 in plan view. A Schottky electrode 61 that is in Schottky contact with the substrate 51 is formed at the bottom of the recess 56. As the Schottky electrode 61, for example, a stacked body of a Ni film and an Au film formed thereon is used. In this way, a Schottky diode 81 is configured. In the diode 81, a forward current flows from the Schottky electrode 61 toward the substrate 51.

  Further, an insulating film 62 covering the gate electrode 60, a gate wiring commonly connecting each gate electrode 60 to the gate pad, a source wiring 63 commonly connecting each source electrode 59, and a gate pad from the source wiring 63 while covering the gate wiring. An insulating film for insulating isolation is formed. Each Schottky electrode 61 is also connected to the source wiring 63.

  The semiconductor device according to the third embodiment is also mounted on the mounting substrate 28 as shown in FIG. 4, for example, as in the first embodiment. Therefore, a surge may flow into the source wiring 63. In this case, the surge flows through the diode 81 without flowing through the Si-based vertical transistor 82. For this reason, the destruction of the Si-based vertical transistor 82 can be sufficiently suppressed.

  Next, an experiment conducted by the present inventor will be described. In this experiment, as shown in FIG. 9A, a semiconductor device (example) according to the first embodiment was manufactured. That is, a lattice-shaped diode 92, a GaN-based HEMT 91 located in a lattice formed by the diode 92, a gate pad 93 to which the gate electrodes of the HEMT 91 are commonly connected, a source wiring 95 to which the source electrodes of the HEMT 91 are commonly connected, and A semiconductor device provided with an insulating film 94 for insulating and separating the gate pad 93 and the source wiring 95 was manufactured. The drain electrode was shared between the HEMTs 91. For comparison, as shown in FIG. 9B, a semiconductor device (comparative example) was also manufactured by removing a portion of the diode 92 located between the HEMTs 91 from the example. Next, these semiconductor devices were mounted on a mounting substrate by wire bonding as shown in FIG. Each sample was normally on.

  Thereafter, for each sample, a pulse of 1 μs was applied between the source and the drain in a state where the voltage Vds between the drain and the source was 0 V and the voltage Vgs between the gate and the source was −5 V. At this time, the magnitude of the pulse was 1A, 3A, 10A, 30A, and 100A, and the pulse was applied in the direction in which current flows from the drain to the source. Then, the number of samples in which destruction occurred was counted. The results are shown in Table 1. In addition, 25 samples of Examples and Comparative Examples were prepared for each pulse size.

  As shown in Table 1, in the example, the number of samples in which destruction occurred was extremely small as compared with the comparative example.

  In any of the embodiments, the gate electrode need not be completely surrounded by the source electrode. In addition, the entire vertical transistor such as the GaN-based HEMT and the Si-based vertical transistor does not have to be completely surrounded by the diode in plan view. However, from the viewpoint of the certainty of protection, it is desirable that 80% or more around the vertical transistor is surrounded.

  The application of these semiconductor devices is not particularly limited, and can be used as a power source for servers and personal computers, and as parts for automobiles and the like.

  Hereinafter, various aspects of the present invention will be collectively described as supplementary notes.

(Appendix 1)
A plurality of vertical transistors connected in parallel to each other and having a gate electrode, a source electrode, and a drain electrode;
Diodes individually surrounding the plurality of vertical transistors;
Have
The anode of the diode is connected to the source electrode;
A semiconductor device, wherein a cathode of the diode is connected to the drain electrode.

(Appendix 2)
The vertical transistor is
An electron transit layer formed on the drain electrode;
An electron supply layer formed on the electron transit layer;
Have
The semiconductor device according to appendix 1, wherein the gate electrode and the source electrode are located above the electron supply layer.

(Appendix 3)
A recess is formed in the electron transit layer and the electron supply layer,
The semiconductor device according to appendix 2, wherein the gate electrode is formed inside the recess through a gate insulating film.

(Appendix 4)
The semiconductor device according to appendix 2 or 3, wherein the electron transit layer and the electron supply layer contain a group III nitride.

(Appendix 5)
The diode is
A Schottky electrode connected to the source electrode;
The Schottky electrode is Schottky connected, and the compound semiconductor layer connected to the drain electrode,
5. The semiconductor device according to any one of appendices 2 to 4, wherein the semiconductor device includes:

(Appendix 6)
6. The semiconductor device according to appendix 5, wherein an insulating layer is formed between the compound semiconductor layer and the electron transit layer.

(Appendix 7)
Forming a plurality of vertical transistors connected in parallel to each other and having a gate electrode, a source electrode, and a drain electrode;
Forming diodes individually surrounding the plurality of vertical transistors;
Have
Connecting the anode of the diode to the source electrode;
A method of manufacturing a semiconductor device, comprising connecting the cathode of the diode to the drain electrode.

(Appendix 8)
The step of forming the vertical transistor includes:
Forming an electron transit layer above the compound semiconductor layer;
Forming an electron supply layer on the electron transit layer;
Forming the gate electrode and the source electrode above the electron supply layer;
Forming a recess reaching the electron transit layer in the compound semiconductor layer;
Forming the drain electrode under the electron transit layer through the recess;
Item 8. The method for manufacturing a semiconductor device according to appendix 7, wherein:

(Appendix 9)
Before the step of forming the gate electrode, the step of forming a recess for the gate in the electron transit layer and the electron supply layer,
9. The method of manufacturing a semiconductor device according to appendix 8, wherein the gate electrode is formed inside a recess for the gate through a gate insulating film.

(Appendix 10)
The step of forming the diode comprises:
Forming a recess for a diode reaching the compound semiconductor layer in the electron supply layer and the electron transit layer;
Forming a Schottky electrode for Schottky connection to the compound semiconductor layer in the recess for the diode;
Have
The method for manufacturing a semiconductor device according to appendix 8 or 9, wherein in the step of forming the drain electrode, the drain electrode is also brought into contact with the compound semiconductor layer.

1: substrate 2: insulating layer 3: electron transit layer 4: electron supply layer 9: source electrode 10: gate electrode 11: Schottky electrode 13: source wiring 15: drain electrode 17: p-well 18: ohmic electrode 21: gate pad 22: Insulating film 23: Gate wiring 31: Diode 32: HEMT
59: Source electrode 60: Gate electrode 61: Schottky electrode 63: Source wiring 65: Drain electrode 81: Diode 82: Si-based vertical transistor

Claims (6)

A plurality of vertical transistors connected in parallel to each other and having a gate electrode, a source electrode, and a drain electrode;
Diodes individually surrounding the plurality of vertical transistors;
Have
The anode of the diode is connected to the source electrode;
A semiconductor device, wherein a cathode of the diode is connected to the drain electrode. The vertical transistor is
An electron transit layer formed on the drain electrode;
An electron supply layer formed on the electron transit layer;
Have
The semiconductor device according to claim 1, wherein the gate electrode and the source electrode are located above the electron supply layer. The diode is
A Schottky electrode connected to the source electrode;
The Schottky electrode is Schottky connected, and the compound semiconductor layer connected to the drain electrode,
The semiconductor device according to claim 2, further comprising: Forming a plurality of vertical transistors connected in parallel to each other and having a gate electrode, a source electrode, and a drain electrode;
Forming diodes individually surrounding the plurality of vertical transistors;
Have
Connecting the anode of the diode to the source electrode;
A method of manufacturing a semiconductor device, comprising connecting the cathode of the diode to the drain electrode. The step of forming the vertical transistor includes:
Forming an electron transit layer above the compound semiconductor layer;
Forming an electron supply layer on the electron transit layer;
Forming the gate electrode and the source electrode above the electron supply layer;
Forming a recess reaching the electron transit layer in the compound semiconductor layer;
Forming the drain electrode under the electron transit layer through the recess;
The method of manufacturing a semiconductor device according to claim 4, wherein: The step of forming the diode comprises:
Forming a recess for a diode reaching the compound semiconductor layer in the electron supply layer and the electron transit layer;
Forming a Schottky electrode for Schottky connection to the compound semiconductor layer in the recess for the diode;
Have
6. The method of manufacturing a semiconductor device according to claim 5, wherein in the step of forming the drain electrode, the drain electrode is also brought into contact with the compound semiconductor layer.

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