JP5170885B2 - Field effect transistor and manufacturing method thereof - Google Patents

Description

  The present invention relates to a field effect transistor using a nitride (GaN) -based compound semiconductor and a method for manufacturing the same, and more particularly, to a field effect transistor having a protective diode built in between a gate electrode and a source electrode and / or between a gate electrode and a drain electrode. And its manufacturing method.

  GaN-based compound semiconductors such as GaN, InGaN, AlGaN, and AlInGaN have a larger band gap energy than Si and GaAs-based semiconductor materials, and electronic devices using these semiconductor materials have high heat resistance and excellent high-temperature operation. Therefore, in recent years, electronic devices such as FETs using GaN-based semiconductors have come to be used as power devices for controlling high voltage and large current.

An FET (Field Effect Transistor) using a nitride (GaN) compound semiconductor has a lower semiconductor layer including a buffer layer made of GaN formed on a substrate such as silicon or sapphire, and is made of undoped GaN thereon. It has a heterojunction structure in which a semiconductor operation layer including an electron transit layer and an electron supply layer made of undoped Al _a Ga _1-a N (0 <a <1) which is thinner than the electron transit layer is formed. A transistor formation region is defined on the semiconductor operation layer of the heterojunction structure, and a source electrode, a gate electrode, and a drain electrode are disposed in the region.

  Since a power transistor (power transistor) generally drives an inductance load such as a transformer or a transformer (coil), a large kickback voltage (back electromotive force) is generated from the load side particularly when the power transistor is turned on. Power) is applied between the electrodes, or a large voltage exceeding the rated value is applied between the electrodes due to static electricity or the like. When a voltage higher than the rated voltage is applied between the electrodes, so-called avalanche collapse occurs inside the transistor and the element is destroyed. To prevent this situation, many silicon-based semiconductor bipolar and MOS power transistors are protected to protect them from breakdown when a voltage higher than the breakdown voltage of the device is applied between the electrodes. It has been practiced to protect the diode by connecting it in parallel between the electrodes.

  In silicon-based semiconductors, since a PN junction can be formed relatively easily in a semiconductor, it has been conventionally performed that a protective diode is not provided externally but is incorporated in a semiconductor element when a transistor is formed. It was.

On the other hand, in the silicon carbide junction type power transistor, as shown in FIG. 14, in order to protect the transistor from static electricity, surge energy, etc., a SiC-JFET 2 and this SiC -Protective diodes 4, 6 and 8 for protecting JFET 2 are formed on the same chip, and the first and second Zener diode groups 4 and 6 clamp the surge voltage applied to SiC-JFET 2, It is known to discharge surge energy (see, for example, Patent Document 1).
JP 2003-68759 A

  However, in the carbon-silicon junction type power transistor described in Patent Document 1, a diode formation region that requires almost the same region as the transistor formation region is provided on the outer periphery of the cell forming the transistor, and the diode is formed after the transistor is formed. A process of forming and then wiring-connecting the electrode of the transistor and the electrode of the diode on the element is required.

  On the other hand, in a field effect transistor using a gallium nitride (GaN) compound semiconductor, it has been difficult to form a diode on the semiconductor operation layer. In comparison with conventional silicon-based semiconductor bipolar or MOS type power transistors with built-in protective diodes, they are not easy to use.

  The present invention has been made to solve the above-described problems. In a field effect transistor using a GaN-based compound semiconductor, a back electromotive force from an external load is generated between a gate electrode and a source electrode and / or between a gate electrode and a drain electrode. It is an object of the present invention to provide a power control field effect transistor having a built-in diode for effectively protecting the transistor from surge voltage such as electric power or static electricity, and a manufacturing method thereof.

  For this reason, the present invention provides a lower semiconductor layer including at least a buffer layer on a substrate, a semiconductor operation layer formed on the lower semiconductor layer, a source electrode, a drain electrode formed on the semiconductor operation layer, In a field effect transistor comprising a gallium nitride compound semiconductor having a gate electrode, a diode connected in parallel between one or both of the gate electrode and the source electrode, and between the gate electrode and the drain electrode, The present invention provides a field effect transistor formed by a groove between the electrodes and extending from the surface of the semiconductor operation layer to the vicinity of the interface between the semiconductor operation layer and the lower semiconductor layer.

  Here, the semiconductor operation layer includes an electron transit layer and an electron supply layer made of a material having a larger band gap energy than the electron transit layer. Specifically, the electron transit layer is made of undoped GaN. And the electron supply layer is n-type AlGaN.

  The breakdown voltage of the bidirectional diode is adjusted according to the width of the groove, and the breakdown voltage of the bidirectional diode is lower than the breakdown voltage of the field effect transistor by setting the width of the groove to a predetermined value. Set it. As a result, the protection diode has a breakdown voltage corresponding to the rated voltage of the transistor.

  The present invention further provides a source electrode formed on a gallium nitride compound semiconductor having a lower semiconductor layer including at least a buffer layer on a substrate, and a semiconductor operation layer formed of an electron transit layer and an electron supply layer. A method of manufacturing a field effect transistor having a drain electrode and a gate electrode, comprising: (a) forming the lower semiconductor layer on the substrate; (b) forming the semiconductor operating layer; ) Forming a source electrode, a gate electrode, and a drain electrode on the semiconductor operation layer; and (d) providing a diode formation region, and a groove extending from the semiconductor operation layer to the lower semiconductor layer in the diode formation region. Forming between the gate electrode and the source electrode and / or between the gate electrode and the drain electrode. Therefore, a diode is formed between any one or both of the gate electrode and the source electrode and between the gate electrode and the drain electrode. It is to provide.

  Here, the step (a) includes (a-1) a step of forming an AlN layer on the Si substrate, and (a-2) a buffer layer in which a GaN / AlN composite layer is laminated on the AlN layer. And (a-3) forming a lower semiconductor layer of p-type GaN on the buffer layer. The step (d) includes (d-1) a step of forming a mask layer on the electron transit layer, and (d-2) between the gate electrode and the source electrode and / or the gate electrode and The step includes removing the mask layer corresponding to the groove forming region formed between the drain electrodes, and (d-3) removing the groove forming region by etching.

  As described above, in the field effect transistor (hereinafter referred to as “the present FET” as appropriate) made of a gallium nitride compound semiconductor according to the present invention, any one of the gate electrode and the source electrode and the gate electrode and the drain electrode is selected. A diode connected in parallel to one or both is formed by a groove between the electrodes and extending from the semiconductor operation layer to the lower semiconductor layer, and this diode utilizes a leakage current that can be adjusted according to the width of the groove. ing. As a result, in this FET, by setting the leak current to flow between the grooves below the rated voltage value of the field effect transistor, the transistor is effectively prevented from surge voltage such as counter electromotive force from an external load or static electricity. A diode for protection could be incorporated in a field effect transistor device made of a GaN compound semiconductor.

  Hereinafter, an FET incorporating a protection diode according to the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a diagram for explaining the configuration of the FET 11, FIG. 1A is a diagram for explaining the configuration of the FET viewed from the upper surface side, and FIG. An equivalent circuit is shown.

As shown in FIG. 1A, the FET 11 incorporating the protection diode according to the present invention includes a transistor region (1) in which a drain electrode 12, a source electrode 13, and a gate electrode are formed on a GaN-based semiconductor operation layer 105. And a diode region (2) adjacent thereto. At least in the diode region (2), the grooves 15 extending from the semiconductor operation layer 105 to the lower semiconductor layer 104 (see FIGS. 2 and 3) therebelow are formed between the gate electrode 14 and the source electrode 13 and between the gate electrode 14 and the drain electrode 12. This creates diodes D1, D2, D3 and D4 that are formed in either or both of them, and connected in parallel between the electrodes (between 14-13 and / or 14-12). . The semiconductor operation layer 105 includes an electron transit layer and an electron supply layer formed on the electron transit layer, and the lower semiconductor layer 104 includes at least a buffer layer. The groove 15 only needs to reach at least the surface of the semiconductor operation layer 105 to the interface where the electron transit layer and the lower semiconductor layer 104 are in contact with each other, and to the region entering the lower semiconductor layer 104 side from the interface. It may be reached.

As shown in FIG. 1B, the diodes D1 and D2 connected in parallel between the gate electrode 14 and the source electrode 13 and the diodes D3 and D4 connected in parallel between the gate electrode 14 and the drain electrode 12 are A bidirectional diode generated by a leak current flowing between the buffer layers of the semiconductor operation layer 105 and the lower semiconductor layer 104 is formed.

  As shown in FIGS. 4 and 5, the trench 15 that isolates the electrodes 12, 13, and 14 can adjust the breakdown voltage of the bidirectional diodes D1, D2, D3, and D4 according to the width in the current direction. Therefore, by adjusting the width of the groove 15, it is set lower than the breakdown voltage corresponding to the rated voltage of the FET 11.

FIG. 2 shows a BB ′ cross section of the diode region (region ( 2 ) shown in FIG. 1A) in FIG. 1A of this FET, and shows examples of various groove formations. It is.

  In the first embodiment shown in FIG. 2A, the groove 15 is provided only between the gate electrode 14 and the drain electrode 12, and the diodes D3 and D4 are formed in the equivalent circuit shown in FIG. It becomes. In FIG. 2A, a groove 15 is formed between the gate electrode 14 and the drain electrode 12 from the semiconductor operation layer 105 to the lower semiconductor layer 104 (see FIGS. 2 and 3) therebelow. Thus, diodes D3 and D4 connected in parallel between the drain electrodes 12 are formed.

  In the second embodiment shown in FIG. 2B, the groove 15 is provided only between the gate electrode 14 and the source electrode 13, and the diodes D1 and D2 are formed in the equivalent circuit shown in FIG. It becomes. In FIG. 2B, a groove 15 is formed between the gate electrode 14 and the source electrode 13 from the semiconductor operation layer 105 to the lower semiconductor layer 104 (see FIGS. 2 and 3) therebelow. Diodes D1 and D2 connected in parallel between the source electrodes 13 are formed.

  In the third embodiment shown in FIG. 2C, grooves 15 are provided between the gate electrode 14 and the drain electrode 12, and between both the gate electrode 14 and the source electrode 13, and FIG. The same equivalent circuit. In FIG. 2C, a groove extending from the semiconductor operation layer 105 to the lower semiconductor layer 104 (see FIGS. 2 and 3) below the gate electrode 14 and the source electrode 13 and between the gate electrode 14 and the drain electrode 12. 15 is formed, thereby forming diodes D1, D2, D3 and D4 connected in parallel between the gate electrode 14 and the drain electrode 12 and between the gate electrode 14 and the source electrode 13, respectively.

FIG. 3 shows a BB ′ cross section in the diode region (2) of FIG. 1A of this FET, and shows another example of forming various grooves. 3A shows an example of a form in which a groove is dug in the region of the gate electrode part, and FIG. 3B shows an example of a form in which a groove is dug in the region of the source electrode part and the drain electrode part. FIG. 3C shows an example in which grooves are dug in all the electrode region portions of the source electrode portion, the drain electrode portion, and the gate electrode portion.

  In the example of forming the first groove in the diode region shown in FIG. 3A (the region (2) shown in FIG. 1A), the entire region where the gate electrode 14 is formed extends from the semiconductor operation layer 105 to the bottom. A trench 15 reaching the lower semiconductor layer 104 (see FIGS. 2 and 3) is formed, and a gate electrode 14 is formed on the trench 15.

  In the example of the second groove formation in the diode region shown in FIG. 3B (region (2) shown in FIG. 1A), the semiconductor operation is performed in the formation region of the drain electrode 12 and the formation region of the source electrode 13. A trench 15 is formed from the layer 105 to the lower semiconductor layer 104 (see FIGS. 2 and 3) below the layer 105, and the drain electrode 12 and the source electrode 13 are formed on the trench 15.

  In the example of the third groove formation in the diode region shown in FIG. 3C (region (2) shown in FIG. 1A), the formation region of all electrodes of the drain electrode 12, the source electrode 13 and the gate electrode 12 is formed. 2, a groove 15 is formed from the semiconductor operation layer 105 to the lower semiconductor layer 104 (see FIGS. 2 and 3) thereunder, and a drain electrode 12, a source electrode 13, and a gate electrode 14 are formed on the groove 15. .

  FIG. 4 shows the relationship between the interelectrode distance (groove width) provided in the diode region and the breakdown voltage.

  In the present FET incorporating the protection diode, as described above, the semiconductor operation layer and the lower semiconductor layer therebelow are configured in the diode region adjacent to the transistor region (1) (the region shown in (2) of FIG. 1). The groove 15 between the electrodes forms a substantially bidirectional diode (D1, D2, D3 and D4 in FIG. 1B) depending on the width of the groove between the electrodes generated by the leak current flowing between the buffer layers. The fact that the leakage current can be controlled by adjusting the width is used. That is, the breakdown voltage of the bidirectional diode formed between the electrodes is used. Thus, since the breakdown voltage of the bidirectional diode can be adjusted by setting the width of the groove 15 to a predetermined value, this corresponds to the breakdown voltage of this FET.

  As shown in the graph of FIG. 4B, the distance between the electrodes is defined as the distance shown in FIG. 4A, and the withstand voltage characteristics of the bidirectional diode corresponding to the distance between the electrodes can be obtained by experiment. Corresponding to the rated voltage of the FET, the interelectrode distance (groove width) in the diode region is selected.

  FIG. 5 shows, as an example, experimental data when the distance between the electrodes is set to a predetermined value. The horizontal axis indicates the voltage applied between the electrodes, and the actual value with the leakage current value on the vertical axis. Experimental data is shown. In this experimental example, as shown in FIG. 5, when a voltage of about 400 V or more is applied between the electrodes, a leakage current starts to flow. As described above, in the FET of the present invention, the protection diodes (D1, D2, D3, and D4 in FIG. 1B) are formed by using the leakage current flowing between the grooves provided between the electrodes.

  Next, a method for manufacturing an FET incorporating a protection diode according to the present invention will be described including a process for forming a semiconductor substrate.

  FIG. 6 shows an example of the structure of a MOS FET (completed) incorporating a protection diode according to the present invention.

7 to 11, first, a substrate (101) made of Si is set in a MOCVD apparatus to perform, for example, metal organic chemical vapor deposition (MOCVD), and hydrogen gas with a concentration of 100% is used as a carrier gas. And trimethylgallium (TMGa), trimethylaluminum (TMAl), and NH ₃ are introduced at flow rates of 58 μmol / min, 100 μmol / min, and 12 l / min, respectively, and the growth temperature is 1050 ° C. on the substrate 101. Then, the AlN layer 102, the buffer layer 103, and the lower semiconductor layer 104 made of p-GaN are epitaxially grown sequentially. Note that biscyclopentadienylmagnesium (Cp2Mg) is used as a p-type doping source for the lower semiconductor layer 104, and the flow rate of Cp2Mg is adjusted so that the Mg concentration is about 1 × 10 ¹⁷ cm ⁻³ .

Next, TMGa and NH ₃ are introduced at flow rates of 19 μmol / min and 12 l / min, respectively, and an electron transit layer 105a made of undoped GaN is epitaxially grown on the lower semiconductor layer 104 at a growth temperature of 1050 ° C., and TMAl, TMGa, and NH ₃ are introduced at flow rates of 125 μmol / min, 19 μmol / min, and 12 l / min, respectively, and an electron supply layer 105b made of undoped-AlGaN having an Al composition of 25% is epitaxially grown on the electron transit layer 105a. The semiconductor operation layer 105 is formed. The semiconductor operation layer 105 may be a single layer made of an n ^- GaN layer having a thickness of 25 nm and a carrier concentration of 5 × 10 ¹⁷ cm ⁻³ . Si (source gas is silane SiH ₄ ) can be used as the dopant.

  In the above description, the buffer layer 103 is formed by stacking only eight GaN / AlN composite layers having a thickness of 200 nm / 20 nm. The thicknesses of the AlN layer 102, the lower semiconductor layer 104, the electron transit layer 105a, and the electron supply layer 105b are 100 nm, 500 nm, 100 nm, and 20 nm, respectively.

Next, as shown in FIG. 8, a mask layer 110 made of SiO 2 is formed with a thickness of 500 nm on the electron supply layer 105b by using plasma enhanced chemical vapor deposition (PCVD), and photolithography and CHF ₃ gas are formed. Then, patterning is performed to form an opening 110a for forming the gate electrode 14 and the trench 15 (see FIG. 1A). In the opening for forming the groove 15, a protection diode in the FET incorporating the protection diode according to the present invention is formed.

Next, as shown in FIGS. 9 to 11, the mask layer 110 is removed, and a recess is formed on the semiconductor operation layer 105 by plasma enhanced chemical vapor deposition (PCVD) using SiH ₄ and N ₂ O as source gases. A gate insulating film 108 made of SiO ₂ and having a thickness of 60 nm is formed across the surface 104a of the lower semiconductor layer 104 in the portion 105c.

  Then, a part of the gate insulating film 103 is removed with hydrofluoric acid, and the source electrode 13 and the drain electrode 12 are formed on the semiconductor operation layer 105 by using a lift-off method. The source electrode 13 and the drain electrode 12 both have a Ti / Al structure with a thickness of 25 nm / 300 nm. The metal film can be formed using a sputtering method or a vacuum evaporation method. Then, after forming the source electrode 13 and the drain electrode 12, annealing is performed at 600 ° C. for 10 minutes, and then a Ti / Al / Ti structure gate electrode 14 is formed in the recess portion 105c by using a lift-off method. The MOS type FET 100 shown in FIG. 6 is completed.

  FIG. 12 shows an example of the structure of a HEMT type FET incorporating a protection diode according to the present invention. FIG. 13 shows an example of a manufacturing process of the HEMT type FET according to the present invention shown in FIG.

As shown in FIG. 13, first, a substrate (101) made of Si is set in, for example, an MOCVD apparatus to grow a metal-organic gas layer, and hydrogen gas having a concentration of 100% is used as a carrier gas, and trimethylgallium (TMGa) is used. And trimethylaluminum (TMAl) and NH ₃ are introduced at flow rates of 58 μmol / min, 100 μmol / min, and 12 l / min, respectively, and the growth temperature is 1050 ° C., the AlN layer 102 and the buffer layer are formed on the substrate 101. 103, the lower semiconductor layer 104 made of p-GaN is sequentially epitaxially grown.

Next, TMGa and NH ₃ are introduced at flow rates of 19 μmol / min and 12 l / min, respectively, and an electron transit layer 105a made of undoped GaN is epitaxially grown on the lower semiconductor layer 104 at a growth temperature of 1050 ° C., and TMAl, TMGa, and NH ₃ are introduced at flow rates of 125 μmol / min, 19 μmol / min, and 12 l / min, respectively, and an electron supply layer 105b made of undoped-AlGaN having an Al composition of 25% is epitaxially grown on the electron transit layer 105a. The semiconductor operation layer 105 is formed. Note that the buffer layer 103 is formed by stacking only eight GaN / AlN composite layers having a thickness of 200 nm / 20 nm. The thicknesses of the AlN layer 102, the lower semiconductor layer 104, the electron transit layer 105a, and the electron supply layer 105b are 100 nm, 500 nm, 100 nm, and 20 nm, respectively.

Next, a plasma chemical vapor deposition (PCVD) method is used to form a mask layer 110 made of SiO 2 with a thickness of 500 nm on the electron supply layer 105b, and patterning is performed using photolithography and CHF ₃ gas. An opening 110a for forming the gate electrode 14 and the trench 15 (see FIG. 1A) is formed. In the opening for forming the groove 15, a protection diode in the FET incorporating the protection diode according to the present invention is formed.

  Thereafter, the source electrode 13 and the drain electrode 12 are formed on the semiconductor operation layer 105 by using a lift-off method. The source electrode 13 and the drain electrode 12 both have a Ti / Al structure with a thickness of 25 nm / 300 nm. The metal film can be formed using a sputtering method or a vacuum evaporation method. Then, after forming the source electrode 13 and the drain electrode 12, annealing is performed at 600 ° C. for 10 minutes, and a gate electrode 14 having a Ni / Au structure is formed in the gate portion 105c by using a lift-off method. This completes the HEMT type FET 100 shown in FIG.

  As described above in detail, in the present invention, a gallium nitride compound having a lower semiconductor layer 104 including at least a buffer layer on a semiconductor substrate, and a semiconductor operation layer 105 formed of an electron transit layer and an electron supply layer. In a field effect transistor 11 having a source electrode 13, a drain electrode 12, and a gate electrode 14 formed on a semiconductor, a diode formation region (2) is provided next to a transistor region (1) for forming the field effect transistor 11, In this diode formation region (2), a groove 15 extending from the semiconductor operation layer 105 to the lower semiconductor layer 104 is formed between the gate electrode 14 and the source electrode 13 and / or between the gate electrode 14 and the drain electrode 12, and this groove The current flowing in the buffer layer of the lower semiconductor layer 104 generated by the breakdown voltage corresponding to the width. The leakage current is produce a diode connected in parallel between the electrodes.

  Thus, the present invention makes it possible to incorporate a diode for effectively protecting the transistor from a surge voltage such as a counter electromotive force from an external load or static electricity in an FET made of a GaN-based compound semiconductor.

  The present invention relates to a field effect transistor using a nitride (GaN) -based compound semiconductor and a method for manufacturing the same, and a field effect transistor including a protective diode built in between a gate electrode and a source electrode and / or between a gate electrode and a drain electrode, and the method It relates to a manufacturing method and has industrial applicability.

FIG. 1A is a diagram for explaining the configuration of the FET as viewed from the upper surface side, and FIG. 1B shows an equivalent circuit of the FET 11. . An example of the form of the A-A ′ cross section of the transistor region (1) in FIG. 1A of this FET is shown. The B-B 'cross section in the diode region (2) of FIG. 1A of this FET is shown, and various examples of groove formation are shown. This shows the relationship between the distance between electrodes (width of groove) provided in the diode region and the breakdown voltage. Actual experimental data is shown with the voltage applied between the electrodes on the horizontal axis and the leakage current value on the vertical axis. An example of the structure of a MOS type FET (completed) incorporating a protection diode according to the present invention is shown. FIG. 7 is a view (No. 1) for describing a manufacturing step of the MOS FET shown in FIG. 6; FIG. 7 is a diagram (No. 2) for describing a manufacturing step of the MOS FET illustrated in FIG. 6; FIG. 7 is a view (No. 3) for describing a manufacturing step of the MOS FET shown in FIG. 6; FIG. 7 is a diagram (No. 4) for explaining a step of manufacturing the MOS FET shown in FIG. 6; FIG. 7 is a view (No. 5) for explaining a manufacturing step of the MOS FET shown in FIG. 6; 1 shows an example of a structure of a HEMT type FET (completed) incorporating a protection diode according to the present invention. It is a figure explaining the manufacturing process of HEMT type FET shown in FIG. The example of the prior art which incorporated the protective diode in the silicon carbide junction type power transistor is shown.

Explanation of symbols

11: Field effect transistor (FET) according to the present invention
12: Drain electrode 13: Source electrode 14: Gate electrode 15: Groove 104: Lower semiconductor layer (including buffer layer)
105: Semiconductor operating layer

Claims (12)

A lower semiconductor layer including a buffer layer formed on the substrate;
A semiconductor operation layer including an electron transit layer formed on the lower semiconductor layer;
In a field effect transistor made of a gallium nitride compound semiconductor having a source electrode, a drain electrode, and a gate electrode formed on the semiconductor operation layer,
A transistor region having a transistor function and a diode region adjacent to the transistor region;
In the diode region, and between the gate electrode and the source electrode, the gate electrode and the between the drain electrode, either or Oite both of, before Symbol semiconductor operating layer surface, wherein said electron transit layer A groove extending to the interface with the lower semiconductor layer or the lower semiconductor layer is formed, and the groove functions as a bidirectional diode connected in parallel between the electrodes due to a leakage current flowing through the lower semiconductor layer between the electrodes. A field effect transistor characterized by comprising: The semiconductor active layer, the electric field effect transistor according to claim 1, wherein said electron transit layer, and the electron supply layer made of a material having a large band gap energy than the electron transit layer, in that it consists of.   3. The field effect transistor according to claim 1, wherein a breakdown voltage of the bidirectional diode is adjusted according to a width of the groove.   4. The field effect transistor according to claim 3, wherein the breakdown voltage of the bidirectional diode is set lower than the breakdown voltage of the field effect transistor by setting the width of the groove to a predetermined value. . 5. The field effect transistor according to claim 2 , wherein the electron transit layer is undoped GaN, and the electron supply layer is n-type AlGaN. A lower semiconductor layer including a buffer layer formed on the substrate;
A semiconductor operation layer including an electron transit layer formed on the lower semiconductor layer ;
A manufacturing method of the semiconductor source electrode formed on the operation layer, the electric field effect transistor from the gallium nitride-based compound semiconductor having a drain electrode and a gate electrode,
(A) forming the lower semiconductor layer on the substrate;
(B) forming the semiconductor operating layer on the lower semiconductor layer;
(C) forming a source electrode, a gate electrode and a drain electrode on the semiconductor operation layer;
(D) forming a transistor region having a transistor function and a diode region adjacent to the transistor region , wherein an interface between the electron transit layer and the lower semiconductor layer from the surface of the semiconductor operation layer or the lower semiconductor in the diode region; Forming a trench leading to a layer between the gate electrode and the source electrode and / or between the gate electrode and the drain electrode;
The groove formed in the step (d) functions as a bidirectional diode connected in parallel between the electrodes by a leakage current flowing through the lower semiconductor layer between the electrodes. A method for producing a field effect transistor, characterized in that: The step (a)
(A-1) forming an AlN layer on the Si substrate;
(A-2) forming a buffer layer in which a GaN / AlN composite layer is laminated on the AlN layer;
(A-3) forming a p-type GaN layer on the buffer layer;
The method of manufacturing a field effect transistor according to claim 6, comprising the steps of: The step (d)
(D-1) forming a mask layer on the electron transit layer;
(D-2) removing the mask layer corresponding to a groove forming region formed between the gate electrode and the source electrode and / or between the gate electrode and the drain electrode;
(D-3) removing the groove formation region by etching;
The method of manufacturing a field effect transistor according to claim 6 or 7, comprising the steps of: The semiconductor operation layer includes the electron transit layer and an electron supply layer made of a material having a larger band gap energy than the electron transit layer,
The electron transit layer is an undoped GaN, a method of manufacturing a field effect transistor according to any one of claims 6-8 wherein the electron supply layer is characterized by an n-type AlGaN. 10. The method of manufacturing a field effect transistor according to claim 6 , wherein a breakdown voltage of the bidirectional diode is adjusted according to a width of the groove for isolating the electrodes . 11. The field effect transistor according to claim 10 , wherein the breakdown voltage of the bidirectional diode is set lower than the breakdown voltage of the field effect transistor by setting the width of the groove to a predetermined value. Manufacturing method.   A lower semiconductor layer including a buffer layer formed on the substrate;
  A semiconductor operation layer including an electron transit layer formed on the lower semiconductor layer;
  In a field effect transistor made of a gallium nitride compound semiconductor having a source electrode, a drain electrode, and a gate electrode formed on the semiconductor operation layer,
  A transistor region having a transistor function and a diode region adjacent to the transistor region;
  In the diode region, at least one of the source electrode, the drain electrode, and the gate electrode is on the groove between the surface of the semiconductor operation layer and the interface between the electron transit layer and the lower semiconductor layer or the lower semiconductor layer. The trench is formed in parallel between the electrodes due to a leakage current flowing through the lower semiconductor layer in one or both of the gate electrode and the source electrode and between the gate electrode and the drain electrode. A field effect transistor which functions as a bidirectional diode to be connected.

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