CN116417512A - Semiconductor structure and manufacturing method thereof - Google Patents

Semiconductor structure and manufacturing method thereof Download PDF

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Publication number
CN116417512A
CN116417512A CN202210672429.XA CN202210672429A CN116417512A CN 116417512 A CN116417512 A CN 116417512A CN 202210672429 A CN202210672429 A CN 202210672429A CN 116417512 A CN116417512 A CN 116417512A
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doped region
layer
semiconductor structure
barrier layer
channel layer
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温文莹
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Nuvoton Technology Corp
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Nuvoton Technology Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material

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  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

The application discloses a semiconductor structure and a manufacturing method thereof, wherein the semiconductor structure comprises a substrate and a channel layer, and the channel layer is arranged on the substrate. The channel layer has a first doped region and a second doped region. A portion of the second doped region is embedded in the first doped region, and the doping type of the first doped region is opposite to the doping type of the second doped region. The semiconductor structure also includes a barrier layer disposed over the channel layer. The semiconductor structure further comprises a gate, a source and a drain, which are arranged above the barrier layer and penetrate through the barrier layer. The grid electrode is arranged on the second doped region, and the source electrode and the drain electrode are respectively arranged on two sides of the grid electrode. The invention can improve the overall electrical performance of the semiconductor structure.

Description

Semiconductor structure and manufacturing method thereof
Technical Field
The present invention relates to a semiconductor structure, and more particularly, to a semiconductor structure for a high electron mobility transistor (high electron mobility transistors, HEMT) and a method of fabricating the same.
Background
Gallium nitride (GaN) has many excellent material properties, such as: high heat resistance, wide gap (band-gap), high electron saturation rate, etc., and thus are widely used in the semiconductor industry.
However, in general, when a normally-off gallium nitride semiconductor is created for use in a high-power device, the breakdown voltage (breakdown voltage) is often insufficient, the on-resistance (on-resistance) is too high, and/or the electric field distribution (electric field distribution) is not uniform, which results in a decrease in the electrical performance of the entire high electron mobility transistor.
Disclosure of Invention
In the semiconductor structure of the embodiment of the application, the channel layer has two first doped regions (for example, N-type doped regions) and a second doped region (for example, P-type doped regions), a portion of the second doped region is embedded in the first doped region, the doping type of the first doped region is opposite to the doping type of the second doped region, and the gate is disposed on the second doped region. The second doped region may be used to improve electrical characteristics of the semiconductor structure (e.g., adjust the threshold voltage (threshold voltage)), and the first doped region may be used to reduce the on-resistance of the semiconductor structure and/or to make the electric field distribution more uniform, thereby improving the electrical performance of the semiconductor structure as a whole.
Embodiments of the present application include a semiconductor structure. The semiconductor structure comprises a substrate and a channel layer, wherein the channel layer is arranged on the substrate. The channel layer has a first doped region and a second doped region. A portion of the second doped region is embedded in the first doped region, and the doping type of the first doped region is opposite to the doping type of the second doped region. The semiconductor structure also includes a barrier layer disposed over the channel layer. The semiconductor structure further comprises a gate, a source and a drain, which are disposed over and pass through the barrier layer. The grid electrode is arranged on the second doped region, and the source electrode and the drain electrode are respectively arranged on two sides of the grid electrode.
Embodiments of the present application include a method of fabricating a semiconductor structure. The method for manufacturing the semiconductor structure comprises forming a channel layer on a substrate, forming a barrier layer on the channel layer, and forming a first dielectric layer on the barrier layer. The method also includes performing a first ion implantation on the channel layer using the first dielectric layer as a mask to form a first doped region. The method further includes forming a second dielectric layer over the barrier layer and patterning the channel layer to form a trench. The trench exposes a portion of the first doped region. In addition, the manufacturing method of the semiconductor structure comprises the steps of using the second dielectric layer as a mask, carrying out second ion implantation on the first doped region and the channel layer to divide the first doped region into two doped regions and forming a second doped region by a part of the first doped region and a part of the channel layer. A portion of the second doped region is embedded in the first doped region. The method for manufacturing the semiconductor structure also comprises the step of forming a source electrode and a drain electrode on two sides of the groove respectively. The source electrode and the drain electrode are arranged on the second dielectric layer and penetrate through the second dielectric layer and the barrier layer. The method further includes forming a gate in the trench, and the gate is disposed over the second doped region.
Drawings
Embodiments of the present application will be described in detail below with reference to the attached drawings. It should be noted that the various features are not drawn to scale and are merely illustrative. Indeed, the dimensions of the elements may be exaggerated or reduced to clearly illustrate the technical features of the embodiments of the present application.
Fig. 1-9 are partial cross-sectional views illustrating various stages in the manufacture of a semiconductor structure in accordance with some embodiments of the present application.
Fig. 10 is a partial cross-sectional view of a semiconductor structure according to some other embodiments of the present application.
Reference numerals
100,102 semiconductor structure
10 substrate
20 channel layer
30 barrier layer
40 protective layer
2DEG two-dimensional electron gas
C1 groove
D drain electrode
D1, D2, D3 dielectric layer
G: grid electrode
GP gate field plate
I1 first ion implantation
I2 second ion implantation
R1:first doped region
R11, R12 doped region
R2:second doped region
R21:channel region
R3 drift region
P1, P2 mask layer
S: source electrode
Thickness of the first doped region T1
Thickness of the second doped region T2
X, Y coordinate axes
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. The following disclosure describes specific examples of various features and arrangements thereof to simplify the description. Of course, these specific examples are not intended to be limiting. For example, if the embodiments herein describe a first feature formed on or over a second feature, it may include embodiments in which the first feature is in direct contact with the second feature, or may include embodiments in which other features are formed between the first feature and the second feature, such that the first feature and the second feature may not be in direct contact.
It is to be understood that additional operational steps may be performed before, during, or after the methods, and that in other embodiments of the methods, some of the operational steps may be replaced or omitted.
Furthermore, spatially relative terms, such as "under …," "under …," "lower," "above …," "over …," "upper," and the like, may be used herein to facilitate description of a relationship between one element(s) or feature(s) and another element(s) or feature(s) in the drawings, including different orientations of the device in use or operation, and orientations depicted in the drawings. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatially relative descriptors used herein interpreted in terms of the turned orientation.
In the specification, the terms "about", "substantially" generally mean within 20%, or within 10%, or within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. The amounts given herein are about amounts, i.e., where "about", "substantially" are not specifically recited, the meaning of "about", "substantially" may still be implied.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will be appreciated that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present application and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
The various embodiments disclosed below may repeat use of the same reference numerals and/or indicia. These repetition are for the purpose of simplicity and clarity and do not in itself dictate a particular relationship between the various embodiments and/or configurations discussed.
The hemts can be generally classified into enhancement (E-mode) hemts and depletion (D-mode) hemts. In fabricating enhanced (E-mode) high electron mobility transistors, it is often necessary to do so by a complex, difficult to control epitaxial (epi) process or a highly difficult etching process.
In accordance with some embodiments of the present invention, a semiconductor structure and a method of manufacturing the same are provided. By the manufacturing method of the embodiment of the application, the normally-closed enhanced (E-mode) high electron mobility transistor can be simply manufactured and used for a high-power element. The semiconductor structure of the embodiment also has the advantages of high breakdown voltage, low on-resistance, more uniform electric field distribution and the like, thereby improving the overall electrical performance of the semiconductor structure.
Fig. 1-9 are partial cross-sectional views illustrating various stages in the manufacture of a semiconductor structure 100 in accordance with some embodiments of the present application. It should be noted that for simplicity, some elements of the semiconductor structure 100 have been omitted from fig. 1-9.
Referring to fig. 1, in some embodiments, a channel layer 20 is formed over a substrate 10. The substrate 10 may be a bulk semiconductor substrate or comprise a composite substrate formed of different materials, and the substrate 10 may be doped (e.g., using p-type or n-type dopants) or undoped. For example, the substrate 10 may be a semiconductor substrate, a glass substrate, or a ceramic substrate, which may include, for example, silicon germanium, silicon carbide, aluminum nitride, sapphire (Sapphire), combinations thereof, or the like, but the embodiments of the present application are not limited thereto. In addition, the substrate 10 may also be a semiconductor-on-insulator (SOI) substrate formed by disposing a semiconductor material on an insulating layer.
The channel layer 20 may comprise one or more III-V compound semiconductor materials, such as: group III nitrides. For example, the channel layer 20 may include gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (indium gallium nitride, inGaN), indium gallium aluminum nitride (indium gallium aluminium nitride, inGaAlN), similar materials, or combinations thereof, but the embodiments are not limited thereto. The channel layer 20 may have dopants, such as n-type dopants or p-type dopants. In addition, the channel layer 20 may be formed by a deposition process, for example: metal organic chemical vapor deposition (metalorganic chemical vapor deposition, MOCVD), hydride vapor phase epitaxy (hydride vapor phase epitaxy, HVPE), molecular beam epitaxy (molecular beam epitaxy, MBE), other suitable methods, or combinations of the foregoing.
For example, the channel layer 20 may be epitaxially grown by Metal Organic Chemical Vapor Deposition (MOCVD) using a gallium-containing precursor and a nitrogen-containing precursor. The gallium-containing precursor may include Trimethylgallium (TMG), triethylgallium (TEG), or other suitable chemicals; nitrogen-containing precursors include ammonia (NH 3), tert-butylamine (TBAm), phenylhydrazine (phenylhydro), or other suitable chemicals. However, the embodiments of the present application are not limited thereto.
Although not shown in fig. 1, a buffer layer and/or a growth layer may be included between the substrate 10 and the channel layer 20. The buffer layer can relieve the lattice difference between the substrate 10 and a film layer subsequently formed on the buffer layer, and improve the crystallization quality. The buffer layer may comprise a III-V compound semiconductor material, such as: group III nitrides. For example, the buffer layer may include gallium nitride (GaN), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), aluminum indium nitride (aluminium indium nitride, alInN), similar materials, or combinations thereof, but the embodiments are not limited thereto. In addition, the buffer layer may be formed by a deposition process, such as chemical vapor deposition (chemical vapor deposition, CVD), atomic layer deposition (atomic layer deposition, ALD), molecular Beam Epitaxy (MBE), liquid phase epitaxy (liquid phase epitaxy, LPE), the like, or a combination thereof, but the embodiment is not limited thereto. In some embodiments, the buffer layer may include doped carbon.
The growth layer may be interposed between the substrate 10 and the buffer layer. The grown layer may further alleviate the lattice difference between the buffer layer and the substrate 10, improving the crystalline quality. The material of the growth layer may comprise aluminum nitride (AlN), aluminum oxide (Al 2 O 3 ) Aluminum gallium nitride (AlGaN), silicon carbide (SiC), aluminum (Al), other suitable materials, or combinations thereof, but the embodiments of the present application are not limited thereto. The growth layer may be a single layer or a multi-layer structure. In addition, the growth layer may be formed by an epitaxial growth process, for example: metal Organic Chemical Vapor Deposition (MOCVD), hydride Vapor Phase Epitaxy (HVPE), molecular Beam Epitaxy (MBE), other suitable methods, or combinations thereof, but the embodiments of the present application are not limited thereto.
Referring to fig. 1, in some embodiments, a barrier layer 30 is formed over the channel layer 20. The barrier layer 30 may comprise one or more III-V compound semiconductors, such as: group III nitrides. For example, the barrier layer 30 may include aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium aluminum nitride (InGaAlN), similar materials, or combinations thereof, but the embodiments are not limited thereto. In addition, the barrier layer 30 may be formed by a deposition process, such as: metal Organic Chemical Vapor Deposition (MOCVD), hydride Vapor Phase Epitaxy (HVPE), molecular Beam Epitaxy (MBE), other suitable methods, or combinations of the foregoing.
For example, the barrier layer 30 may be epitaxially grown by metal organic vapor phase epitaxy (MOCVD) using aluminum-containing precursors, gallium-containing precursors, and nitrogen-containing precursors. Aluminum-containing precursors include Trimethylaluminum (TMA), triethylaluminum (TEA), or other suitable chemicals; gallium-containing precursors include Trimethylgallium (TMG), triethylgallium (TEG), or other suitable chemicals; the nitrogen-containing precursor comprises ammonia (NH 3 ) Tertiary butylamine (TBAm), phenylhydrazine, or other suitable chemicals. However, the embodiments of the present application are not limited thereto.
By spontaneous polarization and piezoelectric polarization effects induced by different energy bands between the channel layer 20 and the barrier layer 30, a two-dimensional electron gas (two-dimensional electron gas) 2DEG is formed on a hetero interface (e.g., near the upper surface of the channel layer 20) between the channel layer 20 and the barrier layer 30, as shown by the dotted line depicted in fig. 1. The aforementioned two-dimensional electron gas 2DEG channel can provide conductive carriers of a High Electron Mobility Transistor (HEMT) to be formed later, and thus can act as a current path.
As shown in fig. 1, in some embodiments, a protective layer 40 is formed over the barrier layer 30. The material and formation of the protective layer 40 is the same or similar to that of the channel layer 20 and will not be repeated here. The passivation layer 40 may be used as a cap layer to protect the barrier layer 30, but the embodiment of the present application is not limited thereto. In some other embodiments, protective layer 40 may not be present.
Referring to fig. 1, in some embodiments, a dielectric layer D1 is formed over the barrier layer 30 (or the protective layer 40). The dielectric layer D1 may comprise an insulating material or a dielectric material, such as: silicon oxide (SiO) 2 ) Silicon nitride (SiN), silicon oxynitride (SiON), aluminum oxide (Al) 2 O 3 ) Aluminum nitride (AlN), magnesium oxide (MgO), magnesium nitride (Mg) 3 N 2 ) Zinc oxide (ZnO), titanium oxide (TiO) 2 ) Other suitable materials, or combinations thereof, but the embodiments of the present application are not limited thereto. In addition, the dielectric layer D1 may be a patterned dielectric layer, which may be formed through a deposition process and a photolithography process.
Deposition processes include Chemical Vapor Deposition (CVD), physical vapor deposition (physical vapor deposition, PVD), and the like. Chemical vapor deposition includes, for example, plasma Enhanced CVD (PECVD) and Atomic Layer Deposition (ALD), and physical vapor deposition includes, for example, sputtering (sputtering), but the embodiments of the present invention are not limited thereto. The photolithography process may include, but is not limited to, photoresist coating (e.g., spin-on coating), soft baking (soft baking), mask alignment (mask alignment), exposure (exposure), post-exposure baking (PEB), development (development), cleaning (ring), drying (e.g., hard baking), other suitable processes, or combinations thereof.
For example, as shown in fig. 1, the dielectric material (or insulating material) may be formed over the barrier layer 30 (or the protective layer 40) by a deposition process; next, forming a mask layer P1 over the dielectric material; finally, a portion of the dielectric material is exposed by the mask layer P1, and the exposed dielectric material is etched to form the dielectric layer D1, but the embodiment of the present application is not limited thereto. For example, the mask layer P1 may include a photoresist, such as a positive photoresist (positive photoresist) or a negative photoresist (negative photoresist). The mask layer P1 may have a single-layer or multi-layer structure.
Next, the mask layer P1 is removed. Referring to fig. 2, in some embodiments, a first ion implantation I1 is performed on the channel layer 20 using the dielectric layer D1 as a mask. Next, referring to fig. 3, in some embodiments, a rapid thermal processing (rapid thermal processing, RTP) annealing (annealing) process is performed (to remove the dielectric layer D1) to form the first doped region R1. The dopant of the first ion implantation I1 may be an N-type dopant, for example, including silicon (Si). Thus, in some embodiments, the first doped region R1 is an N-type doped region.
Referring to fig. 4, in some embodiments, a dielectric layer D2 is formed over the barrier layer 30 (or the protective layer 40). The material and formation of dielectric layer D2 may be the same as or similar to that of dielectric layer D1 and will not be repeated here.
Next, referring to fig. 4, in some embodiments, the barrier layer 30 (and the protective layer 40) is patterned to form a trench C1, and the trench C1 exposes a portion of the first doped region R1. For example, a masking layer P2 may be formed over the dielectric material; next, a portion of the dielectric material is exposed by the mask layer P2, and the exposed dielectric material and the barrier layer 30 (and the protection layer 40) disposed thereunder are etched to form the dielectric layer D2 and the trench C1, but the embodiment of the present application is not limited thereto.
Next, the mask layer P2 is removed. Referring to fig. 5, in some embodiments, a second ion implantation I2 is performed on the channel layer 20 using the dielectric layer D2 as a mask. Next, referring to fig. 6, in some embodiments, a Rapid Thermal Processing (RTP) annealing process is performed to divide the first doped region R1 into two doped regions R11, R12 and form a second doped region R2 from a portion of the first doped region R1 and a portion of the channel layer 20. In other words, as shown in fig. 6, in some embodiments, a portion of the second doped region R2 is embedded in the first doped region R1 (i.e., between the doped regions R11, R12). The dopant of the first ion implantation I2 may be a P-type dopant, for example, including magnesium (Mg). Thus, in some embodiments, the first doped region R1 (including the doped regions R11, R12) is an N-type doped region, and the second doped region R2 is a P-type doped region.
As shown in fig. 6, in some embodiments, the second doped region R2 is in direct contact with the first doped region R1 (including the doped regions R11, R12). In addition, the thickness T2 of the second doped region R2 may be greater than the thickness T1 of the first doped region R1 (including the doped regions R11 and R12), but the embodiment is not limited thereto.
Referring to fig. 7, in some embodiments, a dielectric layer D3 is formed in the trench C1 and over the dielectric layer D2. Specifically, the dielectric layer D3 may be formed on the bottom, the sidewall and the dielectric layer D2 of the trench C1 by a deposition process, and the dielectric layer D3 is in direct contact with the dielectric layer D2, but the embodiment of the present application is not limited thereto. The material of dielectric layer D3 is the same as or similar to the material of dielectric layer D1 and/or dielectric layer D2 and will not be repeated here. In addition, examples of deposition processes are as previously described and are not repeated here.
Referring to fig. 8, in some embodiments, a source S and a drain D are formed on both sides of the trench C1 in the X direction, respectively. Specifically, as shown in fig. 8, in some embodiments, the source S and the drain D are disposed on the dielectric layer D3 and pass through the dielectric layer D3, the dielectric layer D2 and the barrier layer 30 (and the protection layer 40). Further, as shown in fig. 8, in some embodiments, the source S forms an ohmic contact with the first doped region R1 (e.g., doped region R11), and the drain D forms an ohmic contact with the channel layer 20. As shown in fig. 8, in some embodiments, the front projection of the source S on the substrate 10 at least partially overlaps with the front projection of the doped region R11 on the substrate 10. In other words, the source S may be in direct contact with a portion of the first doped region R1 (i.e. the doped region R11), but the embodiment of the present application is not limited thereto.
The source S and drain D may comprise conductive materials such as metals, metal nitrides, metal silicides, semiconductor materials, other suitable materials, or combinations thereof. The metal may comprise gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), combinations of the foregoing, alloys of the foregoing, or multilayers of the foregoing. The semiconductor material may comprise polysilicon, or poly-germanium. In addition, the source S and the drain D may be formed by a deposition process and a photolithography process, and a Rapid Thermal Process (RTP) annealing process may be performed to complete ohmic contact (ohmic contact) between the source S and the drain D and the channel layer 20, but the embodiment of the present application is not limited thereto. Examples of deposition processes and lithographic processes are as described above and are not repeated here.
Referring to fig. 9, in some embodiments, a gate G is formed in the trench C1 to form a semiconductor structure 100. Specifically, the gate G is disposed over the second doped region R2. The material and formation of the gate electrode G may be the same as or similar to those of the source electrode S and the drain electrode D, and will not be repeated here. Further, passivation processing may be performed on the gate G, the source S, and the drain D (passivation process). Furthermore, the dielectric layer D3 may be used as a gate dielectric layer of the gate G.
As shown in fig. 9, in some embodiments, the gate G is further extendable to form a gate field plate GP extending toward the drain D in the X direction. Specifically, the gate field plate GP may be disposed on the dielectric layer D3 and extend toward the drain D. In some embodiments, a dielectric layer D3 is disposed between the gate G and the second doped region R2, and the dielectric layer D3 is disposed between (the gate field plate GP of) the gate G and the barrier layer 30.
As shown in fig. 9, in some embodiments, the orthographic projection of the doped region R12 on the substrate 10 is located within the orthographic projection of the gate field plate GP on the substrate 10. In other words, the gate field plate GP may cover a portion of the first doped region R1 (i.e., the doped region R12). As shown in fig. 9, the doped region R12 and a portion of the two-dimensional electron gas 2DEG in the channel layer 20 can be regarded as a drift region (drift region) R3. In other words, in some embodiments, a portion of the first doped region R1 (i.e., the doped region R12) and a portion of the two-dimensional electron gas 2DEG in the channel layer 20 define a drift region.
In embodiments of the present application, the semiconductor structure 100 may be a normally-off gallium nitride device. The drift region near the drain D end is divided into a two-dimensional electron gas 2DEG region and a doped region R12 (e.g., an N-type doped region) containing the two-dimensional electron gas 2DEG, which can improve (raise) the breakdown voltage and reduce the on-resistance. A doped region R11 (e.g., an N-type doped region) near the source S terminal may be used to electrically connect to the source S.
When a specific voltage (e.g., higher than the threshold voltage of the semiconductor structure 100) is applied to the gate G, a portion (e.g., the top) of the second doped region R2 near the gate G may form a channel region R21 (e.g., an N-type channel region). Since the second doped region R2 is in direct contact with the first doped region R1 (including the doped regions R11 and R12) (e.g., the N-type doped region), the first doped region R1 (including the doped regions R11 and R12) can ensure an interconnection with the channel region R21, so that the conductive path is not cut off and the on-resistance is effectively reduced.
In addition, since the second doped region R2 is formed by performing the second ion implantation I2 on the channel layer 20 and performing a Rapid Thermal Processing (RTP) annealing process, not by epitaxial growth, the threshold voltage of the semiconductor structure can be adjusted simply by the ion implantation process.
In some embodiments, the gate G has an extended gate field plate GP extending toward the drain D and may cover a doped region R12 containing the two-dimensional electron gas 2DEG, which may redistribute (redistribute) the electric field to improve the breakdown voltage of the semiconductor structure.
Fig. 10 is a partial cross-sectional view of a semiconductor structure 102 according to some other embodiments of the present application. Similarly, for simplicity, some elements of semiconductor structure 102 have been omitted from fig. 10.
The semiconductor structure 102 shown in fig. 10 has a similar structure to the semiconductor structure 100 shown in fig. 9, except that the semiconductor structure 102 does not have the protective layer 40.
In other words, in some embodiments, the semiconductor structure 102 includes the substrate 10 and the channel layer 20, and the channel layer 20 is disposed on the substrate 10. The channel layer 20 has a first doped region R1 (including doped regions R11, R12) and a second doped region R2, a portion of the second doped region R2 is embedded in the first doped region R1 (i.e., between the doped regions R11, R12), and a doping type (e.g., N-type) of the first doped region R1 (including the doped regions R11, R12) is opposite to a doping type (e.g., P-type) of the second doped region R2. The semiconductor structure 102 also includes a barrier layer 30, the barrier layer 30 being disposed over the channel layer 20. The semiconductor structure 102 further includes a gate G, a source S, and a drain D disposed over the barrier layer 30 and penetrating the barrier layer 30. The gate G is disposed on the second doped region R2, and the source S and the drain D are disposed on two sides of the gate G in the X direction.
As shown in fig. 10, in some embodiments, the second doped region R2 is in direct contact with the first doped region R1 (including the doped regions R11 and R12), and the front projection of the source S on the substrate 10 at least partially overlaps with the front projection of the doped region R11 on the substrate 10. In some embodiments, the first doped region R1 (including the doped regions R11, R12) is an N-type doped region, and the second doped region R2 is a P-type doped region.
Furthermore, as shown in fig. 10, in some embodiments, the gate G may be further extended to form a gate field plate GP extending toward the drain D in the X direction. Specifically, the gate field plate GP may be disposed on the dielectric layer D3 and extend toward the drain D. In some embodiments, the orthographic projection of the doped region R12 on the substrate 10 is located within the orthographic projection of the gate field plate GP on the substrate 10. In other words, the gate field plate GP may cover the doped region R12.
In the above description, in the semiconductor structure according to the embodiment of the present application, the drift region near the drain terminal is divided into the two-dimensional electron gas region and the first doped region (e.g., N-type doped region) containing the two-dimensional electron gas, which can improve (increase) the breakdown voltage and reduce the on-resistance. A first doped region (e.g., an N-type doped region) near the source terminal may be used to electrically connect to the source. When a specific voltage is applied to the gate, a portion (e.g., top) of the second doped region near the gate may form a channel region (e.g., an N-type channel region). Since the second doped region is in direct contact with the first doped region (e.g., N-type doped region), the first doped region can ensure that an internal connection is formed with the channel region, so that the conductive path is not interrupted, and the on-resistance is effectively reduced.
In addition, in some embodiments, the gate is further extendable to form a gate field plate extending toward the drain and covering the first doped region comprising two-dimensional electron gas, which redistributes the electric field to improve the breakdown voltage of the semiconductor structure.
The foregoing outlines components of several embodiments so that those skilled in the art may better understand the aspects of the embodiments of the present application. Those skilled in the art will appreciate that they may be able to devise and modify other arrangements and processes based on the embodiments herein to achieve the same purpose and/or advantage as the embodiments described herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. Accordingly, the scope of the application is to be defined by reference to the claims appended hereto. In addition, while the present application has been described with reference to a number of preferred embodiments, it is not intended to be limiting.
Reference throughout this specification to features, advantages, or similar language does not imply that all of the features and advantages that may be realized with the present application should be or are in any single embodiment of the application. Rather, language referring to the features and advantages is understood to mean that a specific feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment of the present application. Thus, discussion of the features and advantages, and similar language, throughout this specification may, but do not necessarily, refer to the same embodiment.
Furthermore, the described features, advantages, and characteristics of the application may be combined in any suitable manner in one or more embodiments. One skilled in the relevant art will recognize, in view of the description herein, that the application may be practiced without one or more of the specific features or advantages of a particular embodiment. In other instances, additional features and advantages may be recognized in certain embodiments that may not be present in all embodiments of the application.

Claims (13)

1. A semiconductor structure, comprising:
a substrate;
the channel layer is arranged on the substrate, wherein the channel layer is provided with a first doped region and a second doped region, a part of the second doped region is embedded into the first doped region, and the doping type of the first doped region is opposite to the doping type of the second doped region;
a barrier layer disposed over the channel layer;
the grid electrode, the source electrode and the drain electrode are arranged on the barrier layer and penetrate through the barrier layer, wherein the grid electrode is arranged on the second doped region, and the source electrode and the drain electrode are respectively arranged on two sides of the grid electrode.
2. The semiconductor structure of claim 1, wherein the second doped region is in direct contact with the first doped region.
3. The semiconductor structure of claim 1, wherein an orthographic projection of the source onto the substrate at least partially overlaps an orthographic projection of the first doped region onto the substrate.
4. The semiconductor structure of claim 1, wherein the gate has a gate field plate extending toward the drain.
5. The semiconductor structure of claim 4, wherein the gate field plate covers a portion of the first doped region.
6. The semiconductor structure of claim 1, further comprising:
and a dielectric layer arranged between the grid electrode and the second doped region and between the grid electrode and the barrier layer.
7. The semiconductor structure of claim 6, further comprising:
and a protective layer disposed over the barrier layer, wherein the protective layer is located between a portion of the dielectric layer and the barrier layer.
8. The semiconductor structure of claim 1, wherein a two-dimensional electron gas is formed between the channel layer and the barrier layer, and a portion of the first doped region and a portion of the two-dimensional electron gas in the channel layer define a drift region.
9. The semiconductor structure of claim 1, wherein the source forms an ohmic contact with the first doped region and the drain forms an ohmic contact with the channel layer.
10. A method of fabricating a semiconductor structure, comprising:
forming a channel layer over a substrate;
forming a barrier layer over the channel layer;
forming a first dielectric layer over the barrier layer;
using the first dielectric layer as a mask, and performing first ion implantation on the channel layer to form a first doped region;
forming a second dielectric layer over the barrier layer;
patterning the channel layer to form a trench, wherein the trench exposes a portion of the first doped region;
performing a second ion implantation on the first doped region and the channel layer by using the second dielectric layer as a mask to divide the first doped region into two doped regions and form a second doped region from a part of the first doped region and a part of the channel layer, wherein a part of the second doped region is embedded in the first doped region;
forming a source electrode and a drain electrode on two sides of the groove respectively, wherein the source electrode and the drain electrode are arranged on the second dielectric layer and penetrate through the second dielectric layer and the barrier layer; and
a gate is formed in the trench, wherein the gate is disposed over the second doped region.
11. The method of manufacturing a semiconductor structure of claim 10, wherein the gate extends to form a gate field plate, and the gate field plate extends toward the drain.
12. The method of manufacturing a semiconductor structure of claim 10, further comprising:
a third dielectric layer is formed in the trench and over the second dielectric layer.
13. The method of manufacturing a semiconductor structure of claim 10, further comprising:
a protective layer is formed over the barrier layer, wherein the protective layer is between the barrier layer and the second dielectric layer.
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