WO2009031001A2 - Vertical igbt and method of manufacturing the same - Google Patents

Vertical igbt and method of manufacturing the same Download PDF

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Publication number
WO2009031001A2
WO2009031001A2 PCT/IB2008/002268 IB2008002268W WO2009031001A2 WO 2009031001 A2 WO2009031001 A2 WO 2009031001A2 IB 2008002268 W IB2008002268 W IB 2008002268W WO 2009031001 A2 WO2009031001 A2 WO 2009031001A2
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor substrate
back surface
semiconductor device
portions
dopant
Prior art date
Application number
PCT/IB2008/002268
Other languages
French (fr)
Other versions
WO2009031001A3 (en
Inventor
Takeshi Fukami
Original Assignee
Toyota Jidosha Kabushiki Kaisha
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Filing date
Publication date
Application filed by Toyota Jidosha Kabushiki Kaisha filed Critical Toyota Jidosha Kabushiki Kaisha
Publication of WO2009031001A2 publication Critical patent/WO2009031001A2/en
Publication of WO2009031001A3 publication Critical patent/WO2009031001A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors

Definitions

  • the invention relates to a semiconductor device and a method of manufacturing the semiconductor device.
  • the invention relates to a vertical semiconductor device in which a surface electrode is formed in a surface of a semiconductor substrate and a back surface electrode is formed in a back surface of the semiconductor substrate.
  • the invention also relates to a method of manufacturing the vertical semiconductor thus configured.
  • the dopant diffusion region is formed in the back surface of the semiconductor substrate in the final stage of the manufacturing process.
  • the dopant diffusion region covers a fracture that occurs in the back surface prior to the formation of the dopant diffusion region. Furthermore, the possibility that a fracture occurs in the back surface of the semiconductor substrate is reduced, because the semiconductor substrate contacts manufacturing equipment less frequently after the dopant diffusion region is formed in the back surface. As a result, it is possible to suppress occurrence of a punch-through due to a fracture that occurs in the back surface.
  • a semiconductor device that is manufactured according to the above-described method is described in, for example, Japanese Patent Application Publication No. 2003-51597 (JP-A-2003-51597).
  • the invention provides a technology for suppressing occurrence of a fracture with which a dopant diffusion region is perforated after the dopant diffusion region is formed in a back surface of a semiconductor substrate. Further, the invention provides a semiconductor device in which occurrence of a punch-through due to, for example, a fracture caused during manufacture is suppressed, and a method of manufacturing such semiconductor device.
  • a first aspect of the invention relates to a vertical semiconductor device in which a surface electrode is formed in a surface of a semiconductor substrate and a back surface electrode is formed in a back surface of the semiconductor substrate.
  • a plurality of uneven portions is formed in the back surface of the semiconductor substrate, and each of the uneven portions includes a recessed portion having a flat bottom face.
  • a dopant diffusion region is formed in the semiconductor substrate, at a certain depth from the bottom faces of the recessed portions.
  • the length of a gap between the bottom faces of the adjacent recessed portions is a value that is equal to or smaller than 70% of the thickness of the dopant diffusion region.
  • the dopant is diffused in the semiconductor substrate in the thickness direction and the planar direction of the semiconductor substrate so that the dopant diffusion region is formed at the certain depth from the bottom faces of the recessed portions. If the length of a gap between the bottom faces of the adjacent recessed portions is a value larger than 70% of the thickness of the dopant diffusion region, gaps may be formed, at the certain depth from the bottom faces of the recessed portions, in the dopant diffusion region at portions corresponding to the protrusion portions formed in the back face of the semiconductor substrate.
  • the dopant diffusion region is formed at the certain depth from the bottom faces of the recessed portions even in the portions of the semiconductor substrate, which correspond to the protrusion portions.
  • the dopant diffusion region is formed at a depth of A + B from the surface of the protrusion portion.
  • the dopant diffusion region may be formed as a continuously extending region that includes a portion which corresponds to the gap between the recessed portions, and that is at the certain depth from the bottom faces of the recessed portions. Further, the dopant diffusion region may extend continuously in the planar direction of the semiconductor substrate.
  • the back surface of the semiconductor substrate means the surface from which the dopant is doped into the semiconductor substrate, and the surface of the semiconductor substrate means the surface opposite to the back surface.
  • the dopant diffusion region is formed in the semiconductor substrate, at the depth B from the back surface of the semiconductor substrate. If a fracture that occurs in the back surface develops and reaches the depth B, a punch-through may occur. In contrast, according to first aspect of the invention, even if a fracture occurs in the surface of the protrusion portion, a punch-through does not occur unless the fracture develops and reaches the depth of A + B.
  • the dopant diffusion region is formed in the semiconductor substrate at the depth B from the bottom faces of the recessed portions. If a fracture caused in the bottom face of the recessed portion develops and reaches the depth B, a punch-through may occur.
  • the bottom face of each of the recessed portions is recessed with respect to the surface of the protrusion portion, and therefore, the recessed portion is less prone to directly contact, for example, manufacturing equipment. Therefore, a fracture does not occur easily in the recessed portion.
  • the dopant diffusion region is formed at a position deep away from to the surface of the protrusion portion in which a fracture is more prone to occur, the possibility of occurrence of a punch-through due to a fracture is reduced.
  • a fracture does not occur easily in the bottom face of the recessed portion which is close to the dopant diffusion region. Accordingly, in the semiconductor device according to the first aspect of the invention, it is possible to reduce the possibility of occurrence of a punch-through due to a fracture that occurs in the back surface of the semiconductor device.
  • the plurality of uneven portions may extend linearly in the planar direction of the semiconductor substrate, or may be formed in a reticular pattern and extend in the planar direction of the semiconductor substrate.
  • the bottom face of the recessed portion and a side face of a projection portion of each of the uneven portions may form an obtuse angle
  • the back surface electrode may be formed in the entire area of the back surface of the semiconductor substrate.
  • the semiconductor device according to the first aspect of the invention may be an insulated gate bipolar transistor (IGBT).
  • IGBT insulated gate bipolar transistor
  • the dopant diffusion region may form a buffer layer that separates a collector layer and a drift layer from each other.
  • the buffer layer may be formed at the certain depth from the bottom faces of the recessed portions and extend continuously in the planar direction of the semiconductor substrate, regardless of configuration of the uneven portions formed in the back surface of the semiconductor substrate.
  • the collector layer may be formed at the certain depth from the bottom faces of the recessed portions, and extend discontinuously in the planar direction of the semiconductor substrate. If the collector layer is discontinuously formed, it is possible to suppress excessive supply of carriers from the collector electrode. As a result, it is possible to prevent the carriers from remaining when the semiconductor device is turned-off, thereby reducing the time required until the semiconductor device is turned off.
  • the dopant diffusion region in this specification means the region in which the dopant of the same type as that in the drift layer is diffused at a concentration higher than that is the drift layer. In particular, if the semiconductor device is formed of an IGBT, the dopant diffusion layer is used as a buffer layer.
  • a second aspect of the invention relates to a method of manufacturing a vertical semiconductor device in which a surface electrode is formed in a surface of a semiconductor substrate and a back surface electrode is formed in a back surface of the semiconductor substrate.
  • the method includes: forming a plurality of uneven portions in the back surface of the semiconductor substrate, each of the uneven portions including a recessed portion having a flat bottom face; doping a dopant into the semiconductor substrate from at least the bottom faces of the recessed portions at an energy level at which the dopant is allowed to reach a certain depth from the bottom faces of the recessed portions; and diffusing the dopant into the semiconductor substrate by thermally treating the semiconductor substrate, hi the method, the length of a gap between the bottom faces of the adjacent recessed portions is a value equal to or smaller than 70% of the thickness of the dopant diffusion region in which the dopant is diffused.
  • the length of the gap between the bottom faces of the adjacent recessed portions is a value equal to or smaller than 70% of the thickness of the dopant diffusion region. Therefore, the dopant diffusion region is continuously formed in the semiconductor substrate at a certain depth from the bottom faces of the recessed portions.
  • forming the uneven portions in the back surface of the semiconductor substrate may include forming a film made of a photo resist on part of the back surface of the semiconductor substrate, and etching the back surface of the semiconductor substrate.
  • a vertical semiconductor device in a vertical semiconductor device, it is possible to suppress occurrence of a punch-through due to, for example, a fracture that is caused during or after manufacture. Further, it is possible to manufacture such a vertical semiconductor device.
  • FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the invention
  • FIG. 2 is an enlarged sectional view showing a back surface of the semiconductor device according to the first embodiment of the invention
  • FIG. 3 shows a process of a method of manufacturing the semiconductor device according to the first embodiment of the invention
  • FIG. 4 shows a process of the method of manufacturing the semiconductor device according to the first embodiment of the invention
  • FIG. 5 shows a process of the method of manufacturing the semiconductor device according to the first embodiment of the invention
  • FIG. 6 shows a process of the method of manufacturing the semiconductor device according to the first embodiment of the invention
  • FIG. 7 shows a process of the method of manufacturing the semiconductor device according to the first embodiment of the invention.
  • FIG. 8 shows a process of the method of manufacturing the semiconductor device according to the first embodiment of the invention.
  • FIG. 9 is a sectional view showing the semiconductor device according to the first embodiment that is joined with a mounting substrate
  • FIG. 10 is a plan view showing a back surface of the semiconductor device according to the first embodiment of the invention
  • FIG. 11 is a plan view showing a back surface of a semiconductor device according to a second embodiment of the invention.
  • FIG. 12 is a plan view showing a back surface of a semiconductor device according to a third embodiment of the invention.
  • FIG. 13 is an enlarged view showing a back surface of a semiconductor device according to a fourth embodiment of the invention.
  • FIG. 1 is a sectional view showing a semiconductor device 100 according to a first embodiment of the invention.
  • the semiconductor device 100 is a vertical insulated gate bipolar transistor (IGBT).
  • the semiconductor device 100 includes: a metal collector electrode 2; a p + -type collector layer 4 that contacts an upper face of the collector electrode 2; an n + -type buffer layer 6 that contacts an upper face of the collector layer 4; an n ⁇ -type drift layer 8 that contacts an upper face of the buffer layer 6; a p ⁇ -type body region 10 that is formed on a portion of a surface of the drift layer 8; an n + -type emitter region 12 that is formed on a portion of a surface of the body region 10; a gate electrode 18 that faces, via a trench gate insulation film 20, a portion of the body region 10, which separates the emitter region 12 and the drift layer 8 from each other; and an emitter electrode 14 that contacts the emitter region 12 and that is insulated from the gate electrode 18 by a gate insulation film 16.
  • the semiconductor device 100 includes p + -type guard rings 22a, 22b, and 22c, an n + -type channel stopper region 26, and an interlayer insulating film 24, which are all formed in a terminal region of the semiconductor device 100.
  • the guard rings 22a, 22b, and 22c are formed around the periphery of the body region 10, and the n + -type channel stopper region 26 is formed on the outer side of the guard ring 22c that is at the outermost position from among the guard rings 22a, 22b and 22c.
  • the interlayer insulating film 24 is formed on the surface of the drift layer 8 at the terminal region.
  • FIG. 1 shows only three guard rings 22a, 22b and 22c. However, the number of the guard rings may be more than three.
  • the semiconductor device 100 further includes uneven portions 32, each of which includes a recessed portion 28 and a protrusion portion 30.
  • a reference character Ll indicates the thickness of a dopant diffusion region (i.e. buffer layer 6)
  • a reference character L2 indicates the length of a gap between bottom faces of the adjacent recessed portions 28 (hereinafter, the length of the gap will be simply referred to as "gap L2").
  • the gap L2 between the bottom faces of the adjacent recessed portions 28 signifies the shortest distance between the bottom faces of the two adjacent recessed portions 28 that face each other via the protrusion portion 30.
  • the protrusion portion 30 is formed of a semiconductor substrate that has a crystal structure which is connected to a crystal structure of the collector layer 4.
  • FIG. 2 is an enlarged sectional view showing a back surface of the semiconductor device 100.
  • the gap L2 is set to a value that is equal to or smaller than 70% of the thickness Ll of the dopant diffusion region (i.e. the buffer layer 6). Therefore, the buffer layer 6 is formed continuously without any gap.
  • the buffer layer 6 is formed at a certain depth L3 from the bottom face of the recessed portion 28. In the semiconductor device 100, because a gap is not formed in the buffer layer 6, a punch-through due to a gap does not occur.
  • a reference character L4 indicates the depth of the bottom face of the recessed portion 28 from the surface of the protrusion portion 30.
  • the dopant diffusion region i.e. the buffer layer 6
  • the dopant diffusion region is formed at a position sufficiently deep from an outer contact face of the semiconductor device 100 (i.e. the surface of the protrusion portion 30).
  • a fracture hardly develops until it reaches a depth of L3 + L4. Therefore, even if a fracture occurs in the protrusion portion 30, the possibility that the buffer layer 6 is perforated with the fracture is low.
  • the recessed portion 28 is recessed with respect to the protrusion portion 30, a fracture does not occur easily in the recessed portion 28.
  • FIGs. 3 to 8 show a method of manufacturing the semiconductor device 100.
  • a film, which is made from photo resist 34 and which has a predetermined pattern is formed on a back surface of an n ⁇ -type semiconductor substrate 70.
  • the pattern on the film that is made from the photo resist 34 is set in such a manner that the film are open at portions that correspond to the recessed portions 28 of the uneven portions 32.
  • the pattern on the film that is made from the photo resist 34 is adjusted so that the gap L2 is a value that is equal to or smaller than 70% of the thickness Ll of the dopant diffusion region (i.e. the buffer layer 6), which will be formed in a process described later.
  • the gap L2 is a value that is equal to or smaller than 70% of the thickness Ll of the dopant diffusion region (i.e. the buffer layer 6), which will be formed in a process described later.
  • the back surface of the semiconductor substrate 70, on which the patterned film that is made from the photo resist 34 is formed, is etched in the etching process, hi this etching process, the uneven portions 32 are formed in a manner such that the bottom faces of the recessed portions 28 are flat.
  • the depth, by which the back surface of the semiconductor substrate 70 is etched, is a value appropriately set based on a desired depth of the buffer layer 6 from the outer contact face of the semiconductor device 100.
  • the film made from the photo resist 34 is removed so that the uneven portions 32 are formed in the back surface of the semiconductor substrate 70.
  • dopants 38 and 36 are doped into the semiconductor substrate 70 from the bottom faces of the recessed portions 28.
  • the n-type dopant 38 (for example, phosphorus) is doped into the semiconductor substrate 70 as a dopant used to form the buffer layer 6.
  • the p-type dopant 36 (for example, boron) is doped into the semiconductor substrate 70 as a dopant used to form the collector layer 4.
  • the dopants 38 and 36 may be doped into the projection portions 30 from the surfaces thereof. However, the projection portions 30 need not be doped with the dopants 38 and 36.
  • the semiconductor substrate 70 is subjected to a thermal treatment so that the dopants 38 and 36 are thermally diffused.
  • the gap L2 is a value equal to or smaller than 70% of the thickness Ll of the dopant diffusion region (i.e. the buffer layer 6). Therefore, even in the portions within the semiconductor substrate 70, which correspond to the protrusion portions 30 formed in the back surface, the buffer layer 6 is reliably formed because the dopant 38 are sufficiently diffused in the planar direction of the semiconductor substrate 70 (in the lateral direction in FIG. 6) during the thermal diffusion.
  • the buffer layer 6, which extends continuously in the planar direction of the semiconductor substrate 70 (in the lateral direction in FIG.
  • the collector layer 4 is formed by thermally treating the semiconductor substrate 70. Unlike the buffer layer 6, the collector layer 4 may extend discontinuously in the planer direction of the semiconductor substrate 70. If the dopants 38 and 36 are doped into the protrusion portions 30, in addition to the recessed portions 28, from the surfaces thereof, a buffer layer 6a and a collector layer 4a are formed in each of the protrusion portions 30 as shown in FIG. 6. As described herein, the buffer layer 6a and the collector layer 4a may be formed in each of the protrusion portions 30.
  • the pattern on the film that is made from the photo resist 54 is set in such a manner that the film are open at portions that correspond to the recessed portions 28 of the uneven portions 32.
  • the buffer layer 6a and the collector layer 4a are not formed in each of the protrusion portions 30 (that is, the protrusion portions 30 are not doped with the dopants 38 and 36), and therefore, the buffer layer 6a and the collector layer 4a are not illustrated in FIG. 7 and the drawings subsequent to FIG. 7.
  • the collector electrode 2 is formed on the back surface of the semiconductor substrate 70. After formation of the collector electrode 2, the film made of the photo resist 54 is removed. The collector electrode 2 is formed on the bottom face of each recessed portion 28. Next, the semiconductor substrate 70 is diced into multiple pieces, each of which is used as the semiconductor device 100.
  • the semiconductor device 100 is manufactured according to the method described above.
  • FIG. 9 is a sectional view showing the semiconductor device 100 that is joined with a mounting substrate 42.
  • a solder 40 is filled in the recessed portions 28 formed in the back surface of the semiconductor device 100 so that the mounting substrate 42 contacts, via the solder 40, the collector electrode 2 formed on the bottom faces of the recessed portions 28.
  • FIG. 10 is a plan view of the back surface of the semiconductor device 100. As shown in FIG. 10, the recessed portions 28 and the protrusion portions 30 are formed in the back surface of the semiconductor device 100, and extend linearly in the planar direction of the semiconductor substrate 70.
  • FIG. 11 is a plan view of a back surface of a semiconductor device 200 according to a second embodiment of the invention. As shown in FIG. 11, recessed portions 48 and protrusion portions 50 are formed in the back surface of the semiconductor device 200 in a manner such that the recessed portions 48 and the protrusion portions 50 are formed in a reticular pattern in the planar direction of the semiconductor substrate 70.
  • FIG. 12 is a plan view of a back surface of a semiconductor device 300 according to a third embodiment of the invention.
  • recessed potions 58, recessed portions 68, and protrusion portions 60 are formed in the back surface of the semiconductor device 300, and extend linearly in the planer direction of the semiconductor substrate 70.
  • the protrusion portions 60 are indicated as the hutched regions for the sake of clarity.
  • the recessed portion 58 differs from the recessed portion 68 in the width of the bottom face. As exemplified herein, uneven portions may be linearly formed and disposed with uneven pitches.
  • FIG. 13 is an enlarged view showing the structure of a back surface of a semiconductor device 400 according to a fourth embodiment of the invention.
  • Uneven portions formed in the back surface of the semiconductor device 400 each include a recessed portion and a protrusion portion.
  • a bottom face 46 of the recessed portion and a side face 44 of the protrusion portion form an obtuse angle therebetween.
  • the length of a gap L5 between the bottom faces 46 of the adjacent recessed portions is set to a value that is equal to or smaller than 70% of the thickness Ll of the dopant diffusion region.
  • a collector electrode 52 is formed on the entire area of the back surface of the semiconductor device 400. Therefore, contact resistance of the collector electrode 52 is small in the semiconductor device 400.
  • the semiconductor device is a vertical IGBT.
  • the invention may be applied to other types of vertical semiconductor devices.
  • the technical elements described in the specification or the drawings achieve technical effectiveness independently of each other or in various combinations, and the invention is not limited to the combinations described in this specification.
  • the invention may be implemented regardless of whether the surface of the protrusion portion is flat.
  • the collector electrode may be formed only on the bottom face of each recessed portion.
  • the collector electrode may be formed on both the bottom face of each recessed portion and the surface of each protrusion portion.
  • the collector electrode may be additionally formed on the side face of each protrusion portion if necessary.

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Abstract

A semiconductor device 100, a vertical IGBT, includes a collector electrode 2, a p+-type collector layer 4, an n+-type buffer layer 6, an n--type drift layer 8, a p--type body region 10, an n+-type emitter region 12, a gate electrode 18, and an emitter electrode 14. The semiconductor device 100 includes uneven portions 32 in a back surface, each of which includes a recessed portion 28 and a protrusion portion 30. A gap L2 between bottom faces of the adjacent recessed portions 28 is 70% of or smaller than a thickness L1 of the buffer layer 6. Therefore, the buffer layer 6 is continuously formed, at a certain depth from the bottom faces of the recessed portions.

Description

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
BACKGROUND OF THE INVENTION 1. Field of the Invention
[0001] The invention relates to a semiconductor device and a method of manufacturing the semiconductor device. In particular, the invention relates to a vertical semiconductor device in which a surface electrode is formed in a surface of a semiconductor substrate and a back surface electrode is formed in a back surface of the semiconductor substrate. The invention also relates to a method of manufacturing the vertical semiconductor thus configured. 2. Description of the Related Art
[0002] Recently, development of vertical semiconductor devices has been promoted. During the process of manufacturing a semiconductor device, a fracture sometimes occurs in a back surface of a semiconductor substrate due to, for example, contact with manufacturing equipment. If the fracture develops and a dopant diffusion region, which is formed in the back surface of the vertical semiconductor device, is perforated with the fracture, a punch-through occurs. Occurrence of the punch-through deteriorates pressure resistance of the vertical semiconductor device. [0003] There has been proposed a method of manufacturing a vertical semiconductor device in which a punch-through is less prone to occur. A punch-through occurs if a dopant diffusion region, which is formed in a back surface of a semiconductor substrate, is perforated with a fracture. According to this manufacturing method, after a surface electrode is formed, the dopant diffusion region is formed in the back surface of the semiconductor substrate in the final stage of the manufacturing process. The dopant diffusion region covers a fracture that occurs in the back surface prior to the formation of the dopant diffusion region. Furthermore, the possibility that a fracture occurs in the back surface of the semiconductor substrate is reduced, because the semiconductor substrate contacts manufacturing equipment less frequently after the dopant diffusion region is formed in the back surface. As a result, it is possible to suppress occurrence of a punch-through due to a fracture that occurs in the back surface. A semiconductor device that is manufactured according to the above-described method is described in, for example, Japanese Patent Application Publication No. 2003-51597 (JP-A-2003-51597). [0004] However, even if a semiconductor device is manufactured according to the method described above, it is not possible to suppress occurrence of a fracture at a sufficient level after a dopant diffusion region is formed in the back surface of the semiconductor substrate. Once the dopant diffusion region is perforated with a fracture, it is not possible to suppress occurrence of a punch-through.
SUMMARY OF THE INVENTION
[0005] The invention provides a technology for suppressing occurrence of a fracture with which a dopant diffusion region is perforated after the dopant diffusion region is formed in a back surface of a semiconductor substrate. Further, the invention provides a semiconductor device in which occurrence of a punch-through due to, for example, a fracture caused during manufacture is suppressed, and a method of manufacturing such semiconductor device.
[0006] A first aspect of the invention relates to a vertical semiconductor device in which a surface electrode is formed in a surface of a semiconductor substrate and a back surface electrode is formed in a back surface of the semiconductor substrate. In the semiconductor device, a plurality of uneven portions is formed in the back surface of the semiconductor substrate, and each of the uneven portions includes a recessed portion having a flat bottom face. A dopant diffusion region is formed in the semiconductor substrate, at a certain depth from the bottom faces of the recessed portions. The length of a gap between the bottom faces of the adjacent recessed portions is a value that is equal to or smaller than 70% of the thickness of the dopant diffusion region.
[0007] With the aforementioned configuration, the dopant is diffused in the semiconductor substrate in the thickness direction and the planar direction of the semiconductor substrate so that the dopant diffusion region is formed at the certain depth from the bottom faces of the recessed portions. If the length of a gap between the bottom faces of the adjacent recessed portions is a value larger than 70% of the thickness of the dopant diffusion region, gaps may be formed, at the certain depth from the bottom faces of the recessed portions, in the dopant diffusion region at portions corresponding to the protrusion portions formed in the back face of the semiconductor substrate. In contrast, if the length of a gap between the bottom faces of the adjacent recessed portions is a value equal to or smaller than 70% of the thickness of the dopant diffusion region, the dopant diffusion region is formed at the certain depth from the bottom faces of the recessed portions even in the portions of the semiconductor substrate, which correspond to the protrusion portions. In the latter case, when the depth of the bottom face of the recessed portion from a surface of the protrusion portion is denoted by A, and the depth of the dopant diffusion region from the bottom face of the recessed portion is denoted by B, the dopant diffusion region is formed at a depth of A + B from the surface of the protrusion portion. [0008] In the semiconductor device according to the first aspect of the invention, the dopant diffusion region may be formed as a continuously extending region that includes a portion which corresponds to the gap between the recessed portions, and that is at the certain depth from the bottom faces of the recessed portions. Further, the dopant diffusion region may extend continuously in the planar direction of the semiconductor substrate.
[0009] In this specification, the back surface of the semiconductor substrate means the surface from which the dopant is doped into the semiconductor substrate, and the surface of the semiconductor substrate means the surface opposite to the back surface. [0010] If the uneven portions are not formed in the back surface of the semiconductor substrate, the dopant diffusion region is formed in the semiconductor substrate, at the depth B from the back surface of the semiconductor substrate. If a fracture that occurs in the back surface develops and reaches the depth B, a punch-through may occur. In contrast, according to first aspect of the invention, even if a fracture occurs in the surface of the protrusion portion, a punch-through does not occur unless the fracture develops and reaches the depth of A + B. Therefore, it is possible to suppress occurrence of a punch-through due to a fracture by ensuring the sufficient depth A. The dopant diffusion region is formed in the semiconductor substrate at the depth B from the bottom faces of the recessed portions. If a fracture caused in the bottom face of the recessed portion develops and reaches the depth B, a punch-through may occur. However, because the bottom face of each of the recessed portions is recessed with respect to the surface of the protrusion portion, and therefore, the recessed portion is less prone to directly contact, for example, manufacturing equipment. Therefore, a fracture does not occur easily in the recessed portion. Further, because the dopant diffusion region is formed at a position deep away from to the surface of the protrusion portion in which a fracture is more prone to occur, the possibility of occurrence of a punch-through due to a fracture is reduced. In addition, a fracture does not occur easily in the bottom face of the recessed portion which is close to the dopant diffusion region. Accordingly, in the semiconductor device according to the first aspect of the invention, it is possible to reduce the possibility of occurrence of a punch-through due to a fracture that occurs in the back surface of the semiconductor device.
[0011] In the semiconductor device according to the first aspect of the invention, the plurality of uneven portions may extend linearly in the planar direction of the semiconductor substrate, or may be formed in a reticular pattern and extend in the planar direction of the semiconductor substrate.
[0012] In the semiconductor device according to the first aspect of the invention, the bottom face of the recessed portion and a side face of a projection portion of each of the uneven portions may form an obtuse angle, and the back surface electrode may be formed in the entire area of the back surface of the semiconductor substrate. With the aforementioned configuration, it is possible to form the back surface electrode on the side surface of each protrusion portion, and thus, it is possible to form the back surface electrode in the entire area of the back surface of the semiconductor substrate. As a result, the electrode area of the back surface electrode is increased, whereby the contact resistance is reduced. Accordingly, it is possible to reduce the contact resistance as well as to suppress occurrence of a punch-through.
[0013] The semiconductor device according to the first aspect of the invention may be an insulated gate bipolar transistor (IGBT). hi this case, the dopant diffusion region may form a buffer layer that separates a collector layer and a drift layer from each other. In addition, the buffer layer may be formed at the certain depth from the bottom faces of the recessed portions and extend continuously in the planar direction of the semiconductor substrate, regardless of configuration of the uneven portions formed in the back surface of the semiconductor substrate.
[0014] In the semiconductor device according to the first aspect of the invention, the collector layer may be formed at the certain depth from the bottom faces of the recessed portions, and extend discontinuously in the planar direction of the semiconductor substrate. If the collector layer is discontinuously formed, it is possible to suppress excessive supply of carriers from the collector electrode. As a result, it is possible to prevent the carriers from remaining when the semiconductor device is turned-off, thereby reducing the time required until the semiconductor device is turned off. It should be noted that the dopant diffusion region in this specification means the region in which the dopant of the same type as that in the drift layer is diffused at a concentration higher than that is the drift layer. In particular, if the semiconductor device is formed of an IGBT, the dopant diffusion layer is used as a buffer layer. [0015] A second aspect of the invention relates to a method of manufacturing a vertical semiconductor device in which a surface electrode is formed in a surface of a semiconductor substrate and a back surface electrode is formed in a back surface of the semiconductor substrate. The method includes: forming a plurality of uneven portions in the back surface of the semiconductor substrate, each of the uneven portions including a recessed portion having a flat bottom face; doping a dopant into the semiconductor substrate from at least the bottom faces of the recessed portions at an energy level at which the dopant is allowed to reach a certain depth from the bottom faces of the recessed portions; and diffusing the dopant into the semiconductor substrate by thermally treating the semiconductor substrate, hi the method, the length of a gap between the bottom faces of the adjacent recessed portions is a value equal to or smaller than 70% of the thickness of the dopant diffusion region in which the dopant is diffused.
[0016] With the aforementioned configuration, the length of the gap between the bottom faces of the adjacent recessed portions is a value equal to or smaller than 70% of the thickness of the dopant diffusion region. Therefore, the dopant diffusion region is continuously formed in the semiconductor substrate at a certain depth from the bottom faces of the recessed portions.
[0017] With the aforementioned configuration, it is possible to form the bottom face of each recessed portion at a position deep away from an outer contact face of the semiconductor device, and therefore, it is possible to form the dopant diffusion region at a position deeper away from the outer contact face of the semiconductor device. Accordingly, the dopant diffusion region is not perforated with a fracture easily. Therefore, it is possible to suppress occurrence of a punch-through due to a fracture that occurs in the semiconductor device during manufacture. [0018] In the method according to the second aspect of the invention, forming the uneven portions in the back surface of the semiconductor substrate may include forming a film made of a photo resist on part of the back surface of the semiconductor substrate, and etching the back surface of the semiconductor substrate.
[0019] According to the aspects of the invention described above, in a vertical semiconductor device, it is possible to suppress occurrence of a punch-through due to, for example, a fracture that is caused during or after manufacture. Further, it is possible to manufacture such a vertical semiconductor device.
BRIEF DESCRIPTION OF THE DRAWINGS [0020] The foregoing and further features and advantages of the invention will become apparent from the following description of example embodiments with reference to the accompanying drawings, wherein like numerals are used to represent like elements and wherein:
FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the invention;
FIG. 2 is an enlarged sectional view showing a back surface of the semiconductor device according to the first embodiment of the invention;
FIG. 3 shows a process of a method of manufacturing the semiconductor device according to the first embodiment of the invention;
FIG. 4 shows a process of the method of manufacturing the semiconductor device according to the first embodiment of the invention;
FIG. 5 shows a process of the method of manufacturing the semiconductor device according to the first embodiment of the invention; FIG. 6 shows a process of the method of manufacturing the semiconductor device according to the first embodiment of the invention;
FIG. 7 shows a process of the method of manufacturing the semiconductor device according to the first embodiment of the invention;
FIG. 8 shows a process of the method of manufacturing the semiconductor device according to the first embodiment of the invention;
FIG. 9 is a sectional view showing the semiconductor device according to the first embodiment that is joined with a mounting substrate;
FIG. 10 is a plan view showing a back surface of the semiconductor device according to the first embodiment of the invention; FIG. 11 is a plan view showing a back surface of a semiconductor device according to a second embodiment of the invention;
FIG. 12 is a plan view showing a back surface of a semiconductor device according to a third embodiment of the invention; and
FIG. 13 is an enlarged view showing a back surface of a semiconductor device according to a fourth embodiment of the invention.
DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS [0021] FIG. 1 is a sectional view showing a semiconductor device 100 according to a first embodiment of the invention. The semiconductor device 100 is a vertical insulated gate bipolar transistor (IGBT). The semiconductor device 100 includes: a metal collector electrode 2; a p+-type collector layer 4 that contacts an upper face of the collector electrode 2; an n+-type buffer layer 6 that contacts an upper face of the collector layer 4; an n~-type drift layer 8 that contacts an upper face of the buffer layer 6; a p~-type body region 10 that is formed on a portion of a surface of the drift layer 8; an n+-type emitter region 12 that is formed on a portion of a surface of the body region 10; a gate electrode 18 that faces, via a trench gate insulation film 20, a portion of the body region 10, which separates the emitter region 12 and the drift layer 8 from each other; and an emitter electrode 14 that contacts the emitter region 12 and that is insulated from the gate electrode 18 by a gate insulation film 16.
[0022] The semiconductor device 100 includes p+-type guard rings 22a, 22b, and 22c, an n+-type channel stopper region 26, and an interlayer insulating film 24, which are all formed in a terminal region of the semiconductor device 100. The guard rings 22a, 22b, and 22c are formed around the periphery of the body region 10, and the n+-type channel stopper region 26 is formed on the outer side of the guard ring 22c that is at the outermost position from among the guard rings 22a, 22b and 22c. The interlayer insulating film 24 is formed on the surface of the drift layer 8 at the terminal region. FIG. 1 shows only three guard rings 22a, 22b and 22c. However, the number of the guard rings may be more than three. The semiconductor device 100 further includes uneven portions 32, each of which includes a recessed portion 28 and a protrusion portion 30. It should be noted that a reference character Ll indicates the thickness of a dopant diffusion region (i.e. buffer layer 6), and a reference character L2 indicates the length of a gap between bottom faces of the adjacent recessed portions 28 (hereinafter, the length of the gap will be simply referred to as "gap L2"). The gap L2 between the bottom faces of the adjacent recessed portions 28 signifies the shortest distance between the bottom faces of the two adjacent recessed portions 28 that face each other via the protrusion portion 30. The protrusion portion 30 is formed of a semiconductor substrate that has a crystal structure which is connected to a crystal structure of the collector layer 4.
[0023] FIG. 2 is an enlarged sectional view showing a back surface of the semiconductor device 100. The gap L2 is set to a value that is equal to or smaller than 70% of the thickness Ll of the dopant diffusion region (i.e. the buffer layer 6). Therefore, the buffer layer 6 is formed continuously without any gap. The buffer layer 6 is formed at a certain depth L3 from the bottom face of the recessed portion 28. In the semiconductor device 100, because a gap is not formed in the buffer layer 6, a punch-through due to a gap does not occur. It should be noted that a reference character L4 indicates the depth of the bottom face of the recessed portion 28 from the surface of the protrusion portion 30.
[0024] As shown in FIGs. 1 and 2, the dopant diffusion region (i.e. the buffer layer 6) is formed at a position sufficiently deep from an outer contact face of the semiconductor device 100 (i.e. the surface of the protrusion portion 30). A fracture hardly develops until it reaches a depth of L3 + L4. Therefore, even if a fracture occurs in the protrusion portion 30, the possibility that the buffer layer 6 is perforated with the fracture is low. Moreover, because the recessed portion 28 is recessed with respect to the protrusion portion 30, a fracture does not occur easily in the recessed portion 28. Therefore, even if a fracture occurs in the back surface of the semiconductor substrate during the process of manufacturing the semiconductor device 100, the possibility that the buffer layer 6 is perforated with the fracture is low. As a result, it is possible to suppress occurrence of a punch-through due to, for example, a fracture that occurs during the process of manufacturing the semiconductor device 100.
[0025] FIGs. 3 to 8 show a method of manufacturing the semiconductor device 100. As shown in FIG. 3, a film, which is made from photo resist 34 and which has a predetermined pattern, is formed on a back surface of an n~-type semiconductor substrate 70. The pattern on the film that is made from the photo resist 34 is set in such a manner that the film are open at portions that correspond to the recessed portions 28 of the uneven portions 32. In this process, the pattern on the film that is made from the photo resist 34 is adjusted so that the gap L2 is a value that is equal to or smaller than 70% of the thickness Ll of the dopant diffusion region (i.e. the buffer layer 6), which will be formed in a process described later. Then, as shown in FIG. 4, the back surface of the semiconductor substrate 70, on which the patterned film that is made from the photo resist 34 is formed, is etched in the etching process, hi this etching process, the uneven portions 32 are formed in a manner such that the bottom faces of the recessed portions 28 are flat. The depth, by which the back surface of the semiconductor substrate 70 is etched, is a value appropriately set based on a desired depth of the buffer layer 6 from the outer contact face of the semiconductor device 100. After the etching process is completed, the film made from the photo resist 34 is removed so that the uneven portions 32 are formed in the back surface of the semiconductor substrate 70. Next, as shown in FIG. 5, dopants 38 and 36 are doped into the semiconductor substrate 70 from the bottom faces of the recessed portions 28. More specifically, the n-type dopant 38 (for example, phosphorus) is doped into the semiconductor substrate 70 as a dopant used to form the buffer layer 6. Further, the p-type dopant 36 (for example, boron) is doped into the semiconductor substrate 70 as a dopant used to form the collector layer 4. As shown in FIG. 5, the dopants 38 and 36 may be doped into the projection portions 30 from the surfaces thereof. However, the projection portions 30 need not be doped with the dopants 38 and 36.
[0026] Next, as shown in FIG. 6, the semiconductor substrate 70 is subjected to a thermal treatment so that the dopants 38 and 36 are thermally diffused. The gap L2 is a value equal to or smaller than 70% of the thickness Ll of the dopant diffusion region (i.e. the buffer layer 6). Therefore, even in the portions within the semiconductor substrate 70, which correspond to the protrusion portions 30 formed in the back surface, the buffer layer 6 is reliably formed because the dopant 38 are sufficiently diffused in the planar direction of the semiconductor substrate 70 (in the lateral direction in FIG. 6) during the thermal diffusion. After the thermal diffusion, the buffer layer 6, which extends continuously in the planar direction of the semiconductor substrate 70 (in the lateral direction in FIG. 6), is formed at a position at the depth L3 from the bottom faces of the recessed portions 28. In addition to the buffer layer 6, the collector layer 4 is formed by thermally treating the semiconductor substrate 70. Unlike the buffer layer 6, the collector layer 4 may extend discontinuously in the planer direction of the semiconductor substrate 70. If the dopants 38 and 36 are doped into the protrusion portions 30, in addition to the recessed portions 28, from the surfaces thereof, a buffer layer 6a and a collector layer 4a are formed in each of the protrusion portions 30 as shown in FIG. 6. As described herein, the buffer layer 6a and the collector layer 4a may be formed in each of the protrusion portions 30. Even if the buffer layer 6a and the collector layer 4a of the protrusion portion 30 are perforated with a fracture, no problem will occur. Then, as shown in FIG. 7, a film, which is made from photo resist 54 and which has a predetermined pattern, is formed on the back surface of the semiconductor substrate 70. The pattern on the film that is made from the photo resist 54 is set in such a manner that the film are open at portions that correspond to the recessed portions 28 of the uneven portions 32. It should be noted that, in the semiconductor device 100, the buffer layer 6a and the collector layer 4a are not formed in each of the protrusion portions 30 (that is, the protrusion portions 30 are not doped with the dopants 38 and 36), and therefore, the buffer layer 6a and the collector layer 4a are not illustrated in FIG. 7 and the drawings subsequent to FIG. 7. Next, as shown in FIG. 8, the collector electrode 2 is formed on the back surface of the semiconductor substrate 70. After formation of the collector electrode 2, the film made of the photo resist 54 is removed. The collector electrode 2 is formed on the bottom face of each recessed portion 28. Next, the semiconductor substrate 70 is diced into multiple pieces, each of which is used as the semiconductor device 100. The semiconductor device 100 is manufactured according to the method described above.
[0027] FIG. 9 is a sectional view showing the semiconductor device 100 that is joined with a mounting substrate 42. As shown in FIG. 9, when the semiconductor device 100 is joined with the mounting substrate 42, a solder 40 is filled in the recessed portions 28 formed in the back surface of the semiconductor device 100 so that the mounting substrate 42 contacts, via the solder 40, the collector electrode 2 formed on the bottom faces of the recessed portions 28.
[0028] FIG. 10 is a plan view of the back surface of the semiconductor device 100. As shown in FIG. 10, the recessed portions 28 and the protrusion portions 30 are formed in the back surface of the semiconductor device 100, and extend linearly in the planar direction of the semiconductor substrate 70.
[0029] FIG. 11 is a plan view of a back surface of a semiconductor device 200 according to a second embodiment of the invention. As shown in FIG. 11, recessed portions 48 and protrusion portions 50 are formed in the back surface of the semiconductor device 200 in a manner such that the recessed portions 48 and the protrusion portions 50 are formed in a reticular pattern in the planar direction of the semiconductor substrate 70.
[0030] FIG. 12 is a plan view of a back surface of a semiconductor device 300 according to a third embodiment of the invention. As shown in FIG. 12, recessed potions 58, recessed portions 68, and protrusion portions 60 are formed in the back surface of the semiconductor device 300, and extend linearly in the planer direction of the semiconductor substrate 70. In FIG. 12, the protrusion portions 60 are indicated as the hutched regions for the sake of clarity. The recessed portion 58 differs from the recessed portion 68 in the width of the bottom face. As exemplified herein, uneven portions may be linearly formed and disposed with uneven pitches.
[0031] FIG. 13 is an enlarged view showing the structure of a back surface of a semiconductor device 400 according to a fourth embodiment of the invention. Uneven portions formed in the back surface of the semiconductor device 400 each include a recessed portion and a protrusion portion. A bottom face 46 of the recessed portion and a side face 44 of the protrusion portion form an obtuse angle therebetween. The length of a gap L5 between the bottom faces 46 of the adjacent recessed portions is set to a value that is equal to or smaller than 70% of the thickness Ll of the dopant diffusion region. A collector electrode 52 is formed on the entire area of the back surface of the semiconductor device 400. Therefore, contact resistance of the collector electrode 52 is small in the semiconductor device 400.
[0032] While the invention has been described with reference to example embodiments thereof, it should be understood that the invention is not limited to the example embodiments or constructions. To the contrary, the invention is intended to cover various modifications and equivalent arrangements. In addition, while the various elements of the example embodiments are shown in various combinations and configurations, which are exemplary, other combinations and configurations, including more, less or only a single element, are also within the scope of the invention. For example, in the embodiments described above, the semiconductor device is a vertical IGBT. However, the invention may be applied to other types of vertical semiconductor devices. The technical elements described in the specification or the drawings achieve technical effectiveness independently of each other or in various combinations, and the invention is not limited to the combinations described in this specification. For example, the invention may be implemented regardless of whether the surface of the protrusion portion is flat. Further, when the IGBT is manufactured, the collector electrode may be formed only on the bottom face of each recessed portion. Alternatively, the collector electrode may be formed on both the bottom face of each recessed portion and the surface of each protrusion portion. Further, the collector electrode may be additionally formed on the side face of each protrusion portion if necessary.

Claims

CLAIMS:
1. A vertical semiconductor device in which a surface electrode is formed in a surface of a semiconductor substrate and a back surface electrode is formed in a back surface of the semiconductor substrate, the vertical semiconductor device characterized in that: a plurality of uneven portions is formed in the back surface of the semiconductor substrate, and each of the uneven portions includes a recessed portion having a flat bottom face; a dopant diffusion region is formed in the semiconductor substrate, at a certain depth from the bottom faces of the recessed portions; and a length of a gap between the bottom faces of the adjacent recessed portions is a value that is equal to or smaller than 70% of a thickness of the dopant diffusion region.
2. The vertical semiconductor device according to claim 1, wherein the dopant diffusion region is formed as a continuously extending region that includes a portion which corresponds to the gap between the recessed portions, and that is at the certain depth from the bottom faces of the recessed portions.
3. The vertical semiconductor device according to claim 2, wherein the dopant diffusion region extends continuously in a planar direction of the semiconductor substrate.
4. The vertical semiconductor device according to any one of claims 1 to 3, wherein the plurality of uneven portions extends linearly in the planar direction of the semiconductor substrate.
5. The vertical semiconductor device according to any one of claims 1 to 3, wherein the plurality of uneven portions is formed in a reticular pattern, and extend in the planar direction of the semiconductor substrate.
6. The vertical semiconductor device according to any one of claims 1 to 5, wherein: the bottom face of the recessed portion and a side face of a projection portion of each of the uneven portions form an obtuse angle; and the back surface electrode is formed in an entire area of the back surface of the semiconductor substrate.
7. The vertical semiconductor device according to any one of claims 1 to 6, wherein: the semiconductor device is an insulated gate bipolar transistor; the dopant diffusion region forms a buffer layer that separates a collector layer and a drift layer from each other; and the buffer layer is formed at the certain depth from the bottom faces of the recessed portions and extends continuously in the planar direction of the semiconductor substrate, regardless of configuration of the uneven portions formed in the back surface of the semiconductor substrate.
8. The vertical semiconductor device according to claim 7, wherein the collector layer is formed at a certain depth from the bottom faces of the recessed portions, and extends discontinuously in the planar direction of the semiconductor substrate.
9. A method of manufacturing a vertical semiconductor device in which a surface electrode is formed in a surface of a semiconductor substrate and a back surface electrode is formed in a back surface of the semiconductor substrate, the method characterized by comprising: forming a plurality of uneven portions in the back surface of the semiconductor substrate, each of the uneven portions including a recessed portion having a flat bottom face; doping a dopant into the semiconductor substrate from at least the bottom faces of the recessed portions at an energy level at which the dopant is allowed to reach a certain depth from the bottom faces of the recessed portions; and diffusing the dopant doped into the semiconductor substrate by thermally treating the semiconductor substrate, wherein a length of a gap between the bottom faces of the adjacent recessed portions is a value equal to or smaller than 70% of a thickness of the dopant diffusion region in which the dopant is diffused.
10. The method according to claim 9, wherein forming the uneven portions in the back surface of the semiconductor substrate includes forming a film made of a photo resist on part of the back surface of the semiconductor substrate and etching the back surface of the semiconductor substrate.
11. A vertical semiconductor device comprising: a semiconductor substrate in which a surface electrode is formed in a surface and a back surface electrode is formed in a back surface, and a plurality of uneven portions is formed in the back surface, each of the uneven portions including a recessed portion having a flat bottom face, wherein a dopant diffusion region is formed in the semiconductor substrate, at a certain depth from the bottom faces of the recessed portions, and a length of a gap between the bottom faces of the adjacent recessed portions is a value equal to or smaller than 70% of a thickness of the dopant diffusion region.
12. A method of manufacturing a vertical semiconductor device, comprising: forming a surface electrode in a surface of a semiconductor substrate; forming a back surface electrode in a back surface of the semiconductor substrate; forming a plurality of uneven portions in the back surface of the semiconductor substrate, each of the uneven portions including a recessed portion having a flat bottom face; doping a dopant into the semiconductor substrate from at least the bottom faces of the recessed portions at an energy level at which the dopant is allowed to reach a certain depth from the bottom faces of the recessed portions; and diffusing the dopant doped into the semiconductor substrate by thermally treating the semiconductor substrate, wherein a length of a gap between the bottom faces of the adjacent recessed portions is a value equal to or smaller than 70% of a thickness of the dopant diffusion region in which the dopant is diffused.
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