JP2009182217A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can reduce an ON resistance while suppressing reduction in strength, and also a method of manufacturing the semiconductor device. <P>SOLUTION: An SBD (Schottky Barrier Diode) 1 includes a SiC substrate 10 and an n-SiC layer 20 formed on one main surface 10A of the SiC substrate 10. A plurality of recesses 11 are formed in the other main surface 10B opposed to one main surface 10A of the SiC substrate 10. The recesses 11 are filled with a material having an electrical conductivity higher than that of SiC forming the material of the SiC substrate 10. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device capable of reducing on-resistance and a manufacturing method thereof.

  With the recent improvement in performance of automobiles, home appliances, etc., power devices, which are semiconductor devices in the field of power electronics used for them, have reduced on-resistance from the viewpoint of power saving and suppression of heat generation during operation. Is required. In consideration of the breakdown voltage of the device and the like, many vertical power devices in which current flows in the thickness direction (stacking direction) of the semiconductor device are adopted as power devices. Elements of the on-resistance in this vertical power device include a drift resistance that is a resistance of the drift layer, a contact resistance that is a resistance between a metal constituting the electrode and a semiconductor, and a substrate resistance that is a resistance of the substrate. Among these, since the contact resistance is negligibly small compared to the drift resistance and the substrate resistance, suppression of the drift resistance and the substrate resistance is a problem in the power device.

On the other hand, as a technology that contributes to suppression of drift resistance, instead of silicon (Si) that has been widely used as a material for conventional semiconductor devices, a wide band gap semiconductor that is a semiconductor material having a larger band gap than Si is used. It has been proposed to employ it as a material (for example, see Non-Patent Document 1). Further, as a technique that contributes to suppression of substrate resistance, it has been proposed to remove a part of a substrate by dry etching (see, for example, Patent Document 1), and various dry etching techniques have been proposed (for example, Non-patent document 2).
JP 2003-303966 A Co-edited by Kazuo Arai and Sadafumi Yoshida, “Basics and Applications of SiC Devices”, Ohm Company, March 26, 2003 P. H. YiH et. al, “A Review of SiC Reactive Ion Etching in Fluorinated Plasma”, Phys. stat. sol (b), 1997, vol. 202, p.605

  As described above, the drift resistance can be reduced by using a wide band gap semiconductor as a material. However, for example, when silicon carbide (SiC), which is a wide band gap semiconductor, is used as a material for a semiconductor device, the substrate resistance has an effect on the on-resistance under conditions where the breakdown voltage is 2 kV or less. On the other hand, the substrate resistance can be suppressed by taking a measure for removing a part of the substrate. However, if the thickness of a part of the substrate is reduced by removing a part of the substrate, the strength of the part is reduced and the part is likely to be damaged. Therefore, it cannot be said that the above conventional measures are sufficient.

  Accordingly, an object of the present invention is to provide a semiconductor device capable of reducing on-resistance while suppressing a decrease in strength and a method for manufacturing the same.

  A semiconductor device according to the present invention includes a substrate made of a semiconductor material and a semiconductor layer formed on one main surface of the substrate. A concave portion is formed on the other main surface of the substrate, which is the main surface opposite to the one main surface. And the said recessed part is filled with the high conductivity material whose electrical conductivity is higher than the semiconductor material which comprises a board | substrate.

  In the semiconductor device of the present invention, the substrate resistance is reduced by forming the recess in the substrate. And the said recessed part can suppress the fall of the intensity | strength of a semiconductor device, maintaining the state where board | substrate resistance was reduced by being filled with high-conductivity material. As a result, according to the semiconductor device of the present invention, it is possible to provide a semiconductor device capable of reducing on-resistance while suppressing a decrease in strength.

  Here, in the semiconductor device of the present invention, when silicon (Si) is adopted as the semiconductor material constituting the substrate, magnesium (Mg), aluminum (Al), gold (Au), silver as the high conductivity material. (Ag), copper (Cu), diamond and the like can be employed. Further, when silicon carbide (SiC) is employed as the semiconductor material, Cu, Ag, diamond, or the like can be employed as the high conductivity material. Furthermore, when gallium nitride (GaN) is employed as the semiconductor material, Mg, Al, Au, Ag, Cu, diamond, or the like can be employed as the high conductivity material.

  In the semiconductor device, the high conductivity material is preferably a material having a higher thermal conductivity than the semiconductor material constituting the substrate. Thereby, the heat dissipation of the semiconductor device is improved, and the temperature rise during the operation of the semiconductor is suppressed.

  Here, in the semiconductor device of the present invention, when Si is adopted as the semiconductor material constituting the substrate, Mg, Al, Au, Ag, Cu, diamond or the like can be adopted as the high conductivity material. When SiC is employed as the semiconductor material, Cu, Ag, diamond, or the like can be employed as the high conductivity material. Furthermore, when GaN is employed as the semiconductor material, Mg, Al, Au, Ag, Cu, diamond, or the like can be employed as the high conductivity material.

  Preferably, in the semiconductor device, the concave portion is formed in a stripe shape or a lattice shape when viewed from the side facing the other main surface.

  As a result, at the time of manufacturing the semiconductor device, the manufacturing process proceeds in a state where a plurality of semiconductor devices are connected in a planar manner (wafer shape), and the recess is formed at an appropriate stage, for example, after the step of forming the recess. By separating them along, it becomes easy to separate them into individual semiconductor devices (chips). In addition, since the contact area between the substrate and the high conductivity material increases, if a material having a higher thermal conductivity than the semiconductor material constituting the substrate is adopted as the high conductivity material, the heat dissipation performance Is further improved.

  Preferably, in the semiconductor device, a plurality of recesses are arranged in a distributed manner on the other main surface.

  Thereby, compared with the case where a single big recessed part is formed, the fall of the intensity | strength of a semiconductor device can be suppressed further. In addition, since the contact area between the substrate and the high conductivity material increases, if a material having a higher thermal conductivity than the semiconductor material constituting the substrate is adopted as the high conductivity material, the heat dissipation performance Is further improved. The plurality of recesses can be arranged at regular intervals, for example, in a matrix. Moreover, the substrate may have a honeycomb shape, for example, by forming a plurality of recesses.

  Preferably, in the semiconductor device, an ohmic electrode made of a material capable of being in ohmic contact with the substrate is further formed in a region in contact with the bottom surface of the recess. Thereby, the on-resistance of the semiconductor device can be further suppressed. Here, as a material constituting the ohmic electrode, nickel (Ni) can be used in the n-type region, and a Ti—Al alloy can be used in the p-type region.

  Preferably, in the semiconductor device, a conductive film made of a conductor having better adhesion than the high conductivity material is disposed on the other main surface. Thereby, the semiconductor device can be firmly fixed at the time of mounting. Here, as the conductor having excellent adhesion, a material having better adhesion than the above high conductivity material such as aluminum (Al), copper (Cu), titanium (Ti), tungsten (W) is adopted. be able to.

  Preferably, in the semiconductor device, the semiconductor material forming the substrate is any material selected from the group consisting of silicon (Si), gallium nitride (GaN), and silicon carbide (SiC). These semiconductor materials are suitable for improving the performance of the semiconductor device.

  The semiconductor device is preferably any semiconductor device selected from the group consisting of a Schottky diode, a pn diode, a MOSFET, and a JFET. The semiconductor device can be particularly advantageously applied to Schottky diodes, pn diodes, MOSFETs, and JFETs.

  A method of manufacturing a semiconductor device according to the present invention includes a substrate preparation step in which a substrate made of a semiconductor material is prepared, a semiconductor layer formation step in which a semiconductor layer is formed on one main surface of the substrate, A recess forming step in which a recess is formed on the other main surface, which is the main surface opposite to the one main surface, and the recess is made of a high conductivity material having a higher electrical conductivity than the semiconductor material constituting the substrate. And a high-conductivity material placement step to be filled.

  According to the method for manufacturing a semiconductor device of the present invention, the semiconductor device of the present invention having the above-described excellent characteristics can be easily manufactured.

  Preferably, the semiconductor device of the present invention further includes a dividing step in which the substrate on which the semiconductor layer is formed is divided after the recess forming step. In the recess forming step, the recess is formed in a stripe shape or a lattice shape when viewed from the side facing the other main surface. In the dividing step, the substrate is divided at the recess.

  Thereby, at the time of manufacturing the semiconductor device, the manufacturing process proceeds in a state in which a plurality of semiconductor devices are connected in a planar manner (wafer shape), and in the dividing process, the semiconductor devices are separated along the recesses, thereby individual semiconductors. It can be easily separated into devices (chips). As a result, the semiconductor device of the present invention can be efficiently manufactured.

  As is apparent from the above description, according to the semiconductor device of the present invention, it is possible to provide a semiconductor device capable of reducing the on-resistance while suppressing a decrease in strength. In addition, according to the method for manufacturing a semiconductor device of the present invention, the semiconductor device of the present invention can be easily manufactured.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

(Embodiment 1)
FIG. 1 is a schematic cross-sectional view showing a configuration of a Schottky diode (SBD) as a semiconductor device according to the first embodiment which is an embodiment of the present invention. With reference to FIG. 1, the structure of a Schottky diode which is a semiconductor device according to the first embodiment of the present invention will be described.

  Referring to FIG. 1, SBD 1 in the first embodiment of the present invention is formed on SiC substrate 10 made of SiC, which is a semiconductor material, and one main surface 10A of SiC substrate 10, and has n-type conductivity. And an n-SiC layer 20 as a semiconductor layer containing a certain impurity (n-type impurity). A plurality of recesses 11 are formed on the other main surface 10B which is the main surface opposite to one main surface 10A of SiC substrate 10. An ohmic electrode 50 made of nickel (Ni), which is a material capable of making ohmic contact with the SiC substrate, is formed so as to contact the bottom surface 11A of the recess 11 and the other main surface 10B of the SiC substrate 10. Further, in the recess 11, a recess filling layer 30 made of a high conductivity material having higher electrical conductivity than SiC, for example, Cu, diamond, Ag, or the like is formed so as to fill the recess 11. That is, the recess 11 is filled with a high conductivity material having a higher electrical conductivity than SiC constituting the SiC substrate 10, and the region in contact with the bottom surface 11 </ b> A of the recess 11 can be in ohmic contact with the SiC substrate 10. An ohmic electrode made of Ni is formed.

  On the other main surface 10B, the conductive film 40 is disposed so as to extend over the other main surface 10B so as to be in contact with the ohmic electrode 50 and the concave filling layer 30. As a material for the conductive film 40, for example, a metal having high adhesion, such as Al, Cu, or Au, can be used. By disposing the conductive film 40, the bonding strength can be improved when the SBD 1 is mounted. Further, the ohmic electrode 50 is interposed between the main body portion 10C of the SiC substrate 10 and the conductive film 40, and between the main body portion 10C of the SiC substrate 10 and the recessed filling layer 30, so that ohmic contact is achieved. Contacts are held.

  Furthermore, an oxide film 60 as an insulating film made of an insulator is formed on the second surface 20B which is the surface opposite to the first surface 20A which is the surface on the SiC substrate 10 side of the n-SiC layer 20. Is formed. In addition, a window 61 is formed in the oxide film 60, and the n-SiC layer 20 is exposed in the window 61. Further, a Ti electrode 71 as an anode electrode made of titanium (Ti) as a conductor is formed so as to cover the whole window portion 61 and extend onto the oxide film 60 which is a region other than the window portion 61. Yes. The Ti electrode 71 is in contact with the n-SiC layer 20 in the window portion 61 to form a Schottky junction.

  Next, the operation of the SBD 1 will be described. Referring to FIG. 1, when a reverse voltage is applied (when SBD 1 is in an off state), that is, when a negative voltage is applied to the Ti electrode 71 side, which is the anode electrode side, n-SiC layer 20 and Ti A depletion layer is formed from the interface with the electrode 71 toward the n-SiC layer 20 side. As a result, no current flows through the n-SiC layer 20, and a predetermined breakdown voltage is ensured. On the other hand, when a forward voltage is applied (when SBD 1 is on), that is, when a positive voltage is applied to the Ti electrode 71 side, which is the anode electrode side, the depletion layer does not spread in the n-SiC layer 20. Therefore, a current flows using the n-SiC layer 20 as a current path.

  At this time, in the SBD 1, since the recess 11 is formed in the SiC substrate 10, the substrate resistance is reduced. And the said recessed part 11 suppresses the fall of the intensity | strength of SBD1, maintaining the state where board | substrate resistance was reduced by being filled with the ohmic electrode 50 and recessed part filling layer 30 which consist of high conductivity materials. it can. As a result, according to the SBD 1 as the semiconductor device of the present embodiment, the on-resistance can be reduced while suppressing a decrease in strength.

  Furthermore, in SBD 1 of the present embodiment, recess filling layer 30 made of a high conductivity material is preferably a material having a higher thermal conductivity than SiC constituting SiC substrate 10. For example, the concave filling layer 30 is preferably made of diamond. Thereby, the heat dissipation of SBD1 improves and the temperature rise at the time of operation | movement of SBD1 is suppressed.

  Next, the detail of the structure of the recessed part 11 in this Embodiment is demonstrated. FIG. 2 is a schematic plan view of the SiC substrate in the first embodiment. FIG. 2 shows a plan view of SiC substrate 10 as viewed from the other main surface 10B side. FIG. 3 is a schematic sectional view taken along line III-III in FIG.

  Referring to FIGS. 2 and 3, in SiC substrate 10 in the present embodiment, recess 11 is formed in a stripe shape when viewed from the side facing the other main surface 10B. More specifically, the recess 11 is formed as a plurality of parallel grooves on the other main surface 10B.

  As a result, when the SBD 1 is manufactured, the manufacturing process proceeds in a state where a plurality of SBDs 1 are connected in a planar manner (wafer shape). By separating them along, it becomes easy to separate them into SBD1 (chip). Further, since the contact area between the SiC substrate 10 and the high conductivity material is increased, when a material having a higher thermal conductivity than SiC is adopted as the high conductivity material, the heat dissipation is further improved. To do.

  Next, a first modification of the structure of the recess 11 in the present embodiment will be described. FIG. 4 is a schematic plan view of the SiC substrate in the first modification of the first embodiment. FIG. 4 shows a plan view of SiC substrate 10 as viewed from the other main surface 10B side. FIG. 5 is a schematic cross-sectional view taken along line VV in FIG.

  Referring to FIGS. 4 and 5, in SiC substrate 10 in the first modification, recesses 11 are formed in a lattice shape when viewed from the side facing the other main surface 10B. More specifically, the recess 11 is formed as a plurality of grooves intersecting (orthogonal) with each other on the other main surface 10B.

  As a result, when the SBD 1 is manufactured, the manufacturing process proceeds in a state where a plurality of SBDs 1 are connected in a planar manner (wafer shape). By separating them along, it becomes easier to separate into SBD1 (chip). Further, since the contact area between the SiC substrate 10 and the high conductivity material is increased, when a material having a higher thermal conductivity than SiC is adopted as the high conductivity material, the heat dissipation is further improved. To do.

As shown in FIGS. 2 and 3, when SiC substrate 10 has a thickness of 200 μm and recesses 11 are formed in stripes having a width of 100 μm and a depth of 100 μm, for example, every 100 μm, the substrate resistance is It becomes about 0.26 mΩ · cm ² . This means that a reduction of about 63% is realized with respect to a substrate resistance of about 0.7 mΩ · cm ² of a general SiC substrate (thickness 400 μm), and about 26% with respect to a SiC substrate with a thickness of 200 μm. . Furthermore, compared with the case where the other main surface 10B is a general single plane, the surface area is increased by about twice, and the heat radiation amount is twice (thermal resistance is 0.5 times). .

Further, as shown in FIGS. 4 and 5, when the recesses 11 are formed in a lattice shape on the SiC substrate 10, the substrate resistance becomes 0.14 mΩ · cm ² and the surface area increases by about 1.7 times. Therefore, the heat dissipation amount is 1.7 times (thermal resistance is 0.58 times).

  Next, a second modification of the structure of the recess 11 in the present embodiment will be described. FIG. 6 is a schematic plan view of the SiC substrate in the second modification of the first embodiment. FIG. 6 shows a plan view of SiC substrate 10 as seen from the other main surface 10B side. FIG. 7 is a schematic cross-sectional view taken along line VII-VII in FIG.

  Referring to FIGS. 6 and 7, in SiC substrate 10 in the second modification, a plurality of recesses 11 are arranged in a distributed manner on the other main surface 10B. More specifically, a plurality of recesses 11 are formed in a dispersed manner so as to extend from the other main surface 10B toward the one main surface 10A side. The shape of the recess 11 is a columnar shape, and the cross-sectional shape perpendicular to the extending direction of the recess 11 may be a polygon such as a square as shown in FIGS. 6 and 7, or a shape such as a circle or an ellipse. May be.

  Thereby, compared with the case where the single big recessed part 11 is formed, the fall of the intensity | strength of SBD1 can be suppressed further. Further, since the contact area between the SiC substrate 10 and the high conductivity material is increased, when a material having a higher thermal conductivity than SiC is adopted as the high conductivity material, the heat dissipation is further improved. To do.

  Next, a method for manufacturing SBD 1 as a semiconductor device in the present embodiment will be described. FIG. 8 is a flowchart showing an outline of the method of manufacturing the SBD in the first embodiment. 9 to 14 are schematic cross-sectional views for explaining the method for manufacturing the SBD in the first embodiment. With reference to FIGS. 8 to 14, a method of manufacturing the SBD in the first embodiment will be described.

  Referring to FIG. 8, in the SBD manufacturing method according to the first embodiment, first, a substrate preparation step in which a substrate made of a semiconductor material is prepared is performed. Specifically, referring to FIG. 9, the semiconductor material is SiC, and has a thickness of 200 μm or more and 1000 μm or less, such as 400 μm, and a diameter of 2 inches or more and 5 inches or less, such as 2 inches. The SiC substrate 10 containing is prepared.

  Next, referring to FIG. 8, a semiconductor layer forming step is performed in which a semiconductor layer is formed on one main surface of the substrate. Specifically, referring to FIG. 9, n-SiC layer 20 made of SiC containing n-type impurities is formed on one main surface 10 </ b> A of SiC substrate 10. The formation of the n-SiC layer 20 can be performed, for example, by vapor phase epitaxial growth (CVD or the like) using a source gas containing n-type impurities.

  Next, referring to FIG. 8, a recess forming step is performed in which a recess is formed on the other main surface of the substrate, which is the main surface opposite to the one main surface. Specifically, referring to FIG. 10, the other main surface 10B side is etched over, for example, the entire surface of 200 μm by RIE (Reactive Ion Etching), and then the etched surface (the other main surface). A mask layer is formed on the surface of 10B). Further, a resist is applied on the mask layer, and after patterning according to the shape of the recess by photolithography, the mask layer is etched using this as a mask. Further, using this mask layer as a mask, the recess 11 is formed by RIE, for example.

  Here, as the material of the mask layer, for example, aluminum (Al), Ni silicide (nickel silicide; NiSi), nickel (Ni), chromium (Cr), or ITO (indium tin oxide) can be employed.

Moreover, as RIE for forming the recessed part 11, CCP (Capacitive Coupled Plasma) -RIE is used, and CF ₄ (carbon tetrafluoride), SF ₆ (sulfur hexafluoride), CHF is used as an etching gas. ₃ (Methane trifluoride), NF ₃ (nitrogen trifluoride), a method of using a gas in which O ₂ (oxygen) and N ₂ (nitrogen) are mixed, ECR (Electron Cyclotron Resonance; electron cyclotron resonance) ) -RIE and etching gas using a mixed gas of O ₂ and Ar (argon) in at least one of CF ₄ and SF ₆ , etching using ICP (Inductive Coupled Plasma) -RIE CF ₄ , SF ₆ , NF as gas _For example, a method in which a gas in which O ₂ and Ar are mixed with at least one of ₃ can be employed.

Among these, as a particularly preferable method, ICP-RIE is employed, a gas in which O ₂ is mixed with CF ₄ as an etching gas (SF ₆ / O ₂ : 50/10 sccm) is adopted, and Ni having a high selectivity with respect to SiC is used. A mask layer having a thickness of 3 μm can be employed. Further, the pressure condition at that time can be set to 1 Pa, for example, and the RF condition can be set to 1000 W / 100 W, for example.

  Next, referring to FIG. 8, an oxide film is formed on n-SiC layer 20 as a semiconductor layer, and damage formed in a region adjacent to the other main surface 10B of SiC substrate 10 as a semiconductor substrate. An oxide film forming step for removing the region is performed. Specifically, referring to FIG. 11, the SiC substrate 10 on which the n-SiC layer 20 is formed is thermally oxidized, whereby the first surface which is a surface in contact with the SiC substrate 10 in the n-SiC layer 20. Thermal oxide film 91 is formed on second surface 20B, which is the surface opposite to surface 20A, and on the other main surface 10B of SiC substrate 10.

  Next, referring to FIG. 8, an ohmic electrode is formed on the bottom surface 11 </ b> A of the recess 11 and the other main surface 10 </ b> B of the SiC substrate 10. The ohmic electrode is made of a material capable of making ohmic contact with SiC constituting the SiC substrate 10. An electrode forming step is performed. Specifically, first, referring to FIGS. 11 and 12, after applying a resist on thermal oxide film 91 formed on second surface 20B of n-SiC layer 20, the SiC substrate is etched. The thermal oxide film 91 formed on the other main surface 10B of 10 is removed. Thereafter, as shown in FIG. 12, Ni capable of ohmic contact with SiC is deposited on bottom surface 11 </ b> A of recess 11 and on the other main surface 10 </ b> B of SiC substrate 10. Then, the ohmic electrode 50 is formed by heating to 1000 ° C., for example.

  Next, referring to FIG. 8, a high-conductivity material filling step is performed in which recess 11 is filled with a high-conductivity material having a higher electrical conductivity than SiC constituting SiC substrate 10. Specifically, referring to FIG. 12, Cu (copper), Ag (silver), diamond or the like is filled in the recess 11 by a method such as EB (Electron Beam) vapor deposition, sputter deposition, plating, etc. The filling layer 30 is formed.

  Next, referring to FIG. 8, an anode electrode forming step of forming an anode electrode is performed. Specifically, referring to FIGS. 12 and 13, the resist formed on thermal oxide film 91 is patterned into a desired window 61 shape by photolithography, and thermal oxide film 91 is etched using the resist as a mask. As a result, the oxide film 60 having the window portion 61 is formed. At this time, the etching of the thermal oxide film 91 can be performed at a rate of about 54 nm / min. Using, for example, buffered hydrofluoric acid (BHF). Thereafter, referring to FIG. 14, by forming the Ti film so as to cover the entire window part 61 by sputtering, for example, and to extend to the region on the oxide film 60 other than the window part 61, the anode electrode is formed. Ti electrode 71 is formed. Here, the Ti film can be formed to a thickness of 150 nm, for example. At this time, the upper electrode may be formed by further depositing about 2 μm of Al on the Ti electrode 71. In addition to Ti, Ni, Cu or the like can be adopted as a material for the anode electrode.

  Next, referring to FIG. 8, a conductive film forming step is performed in which a conductive film made of a material such as metal having excellent adhesion is formed. Specifically, referring to FIG. 1, a metal such as Al, Cu, for example, is deposited on SiC substrate 10 on the other main surface 10B so as to extend over the other main surface 10B. A conductive film 40 is formed.

  Next, as shown in FIG. 8, a dividing step is performed in which the SiC substrate 10 on which the n-SiC layer 20 is formed is divided. In this dividing step, SiC substrate 10 is divided in recesses 11 formed in a stripe shape or a lattice shape. Specifically, referring to FIG. 1, wafer-like SiC substrates 10 to be a plurality of SBDs 1 that have been manufactured in a planar connection state are cut at recesses 11 by, for example, dicing, Divided into individual SBD1. Thereby, the SBD 1 as the semiconductor device in the present embodiment is completed. Thereafter, the SBD 1 is fixed and mounted by bonding.

  According to the method of manufacturing the SBD as the semiconductor device in the present embodiment, the SBD of the present embodiment having the above-described excellent characteristics can be manufactured easily and efficiently.

(Embodiment 2)
Next, SBD which is a semiconductor device in Embodiment 2 of this invention is demonstrated. FIG. 15 is a schematic cross-sectional view showing a configuration of an SBD as a semiconductor device according to the second embodiment which is an embodiment of the present invention.

  Referring to FIG. 15, SBD 1 in the second embodiment and SBD 1 in the first embodiment described with reference to FIG. 1 have basically the same configuration and operate in the same manner. However, the configuration of the conductive film 40 is different from the SBD 1 of FIG.

  That is, referring to FIG. 15, a part of conductive film 40 formed on the other main surface 10B of SiC substrate 10 in SBD 1 in the second embodiment enters recess 11 and is a recess made of a high conductivity material. It is in contact with the packed bed 30.

  Thereby, in SBD1 as a semiconductor device in Embodiment 2, the contact area of the electrically conductive film 40 and the recessed filling layer 30 and the ohmic electrode 50 made of a highly conductive material increases. As a result, the SBD 1 can be firmly fixed at the time of mounting.

  Next, a method for manufacturing SBD 1 in the second embodiment will be described. The SBD 1 in the second embodiment can be manufactured basically by the same method as the SBD 1 in the first embodiment described with reference to FIGS. However, the manufacturing method of the conductive film 40 is partially different due to the difference from the SBD 1 in the first embodiment.

  That is, in the manufacturing method of SBD 1 in the second embodiment, referring to FIG. 8 and FIG. 15, when high conductivity material such as Ni is filled in recess 11 in the high conductivity material filling step, recess 11 is formed. The process is completed without being completely satisfied. Thereafter, when a highly adhesive metal such as Al or Cu is deposited in the conductive film forming step, a part of the metal enters the recess 11 and is conductive so as to contact the recess filling layer 30 made of a high conductivity material. A film 40 is formed.

(Embodiment 3)
Next, a pn diode that is a semiconductor device according to Embodiment 3 of the present invention will be described. FIG. 16 is a schematic cross-sectional view showing a configuration of a pn diode as a semiconductor device according to the third embodiment which is an embodiment of the present invention.

  Referring to FIG. 16, the pn diode 2 in the third embodiment and the SBD 1 in the first embodiment described with reference to FIG. 1 have basically the same configuration and the same operational effects. However, the configuration is partially different from the SBD 1 in FIG.

That, pn diode 2, and ⁿ + -SiC substrate 15 made of SiC containing a high concentration n-type ^impurities, is formed on one main surface 15A of n + -SiC substrate ^15, from the n + -SiC substrate 15 And an n ⁻ -SiC layer 25 as a semiconductor layer containing a low concentration n-type impurity. A plurality of recesses 11 are formed on the other main surface 15B of the n ⁺ -SiC substrate 15 which is the main surface opposite to the one main surface 15A. And it consists of Ni which is a high conductivity material higher in electrical conductivity than SiC so as to be in contact with the bottom surface 11 ^</ b> A of the recess 11, the side wall 11 ^</ b> B, and the other main surface 15 ^</ b> B of the n ⁺ -SiC substrate 15. An ohmic electrode 50 is formed. Furthermore, a recess filling layer 30 made of a high conductivity material having a higher electrical conductivity than SiC is formed in the recess 11 so as to fill the recess 11. The configuration of the conductive film 40, the oxide film 60, and the Ti electrode 71 is basically the same as that of the SBD 1 of the first embodiment.

The n ⁻ —SiC layer 25 covers the entire region in contact with the Ti electrode 71, and is conductive so as to extend to a region in contact with the oxide film 60, which is a region other than the region in contact with the Ti electrode 71. A p-SiC region 81 containing an impurity whose type is p-type is formed.

Next, the operation of the pn diode 2 will be described. Referring to FIG. 16, when a reverse voltage is applied (when pn diode 2 is in an off state), that is, when a negative voltage is applied to Ti electrode 71 side, which is the anode electrode side, n ⁻ −SiC layer A depletion layer is formed at the interface between 25 and the p-SiC region 81. As a result, no current flows through the n ⁻ -SiC layer 25 and a predetermined breakdown voltage is ensured. On the other hand, when a forward voltage is applied (when the pn diode 2 is in an on state), that is, when a positive voltage is applied to the Ti electrode 71 side that is the anode electrode side, the n ⁻ −SiC layer 25 and the p-SiC Since the depletion layer does not spread at the interface with the region 81, a current flows using the n ⁻ -SiC layer 25 as a current path.

Next, a method for manufacturing the pn diode 2 in the third embodiment will be described. The manufacturing method of the pn diode 2 in the third embodiment is basically the same as the manufacturing method of the SBD 1 in the first embodiment described with reference to FIGS. However, it differs from the method of manufacturing SBD 1 in the first embodiment in that it includes a step of forming p-SiC region 81 in n ⁻ -SiC layer 25.

That is, in the manufacturing method of the pn diode 2 in the third embodiment, with reference to FIG. 8, first, ⁿ + -SiC substrate 15 is prepared in the substrate preparation step, in the semiconductor layer formation ^step, n + -SiC substrate An n ⁻ -SiC layer 25 is formed on 15. These steps can be performed basically in the same manner as in the first embodiment.

Thereafter, after the recess forming step is performed as in the first embodiment, before the oxide film forming step is performed, p-SiC region 81 as a p-type region is formed in n ⁻ -SiC layer 25. A p-type region process forming step is performed. Specifically, a mask layer forming process is performed in which a mask layer having an opening corresponding to the shape of the desired p-SiC region 81 is formed on the n ⁻ -SiC layer 25 using photolithography or the like. The Then, using the mask layer as a mask, an impurity introduction step in which p-type impurities are introduced into the n ⁻ -SiC layer 25 by ion implantation or the like is performed, and a p-SiC region 81 is formed. Thereby, the p-type region process formation process is completed.

  Further, subsequent to the p-type region process formation process, the pn diode 2 according to the third embodiment can be manufactured by performing steps from the oxide film formation process to the dividing process as in the first embodiment.

  In the pn diode of the third embodiment, unlike the first and second embodiments, the ohmic electrode 50 is formed not only on the bottom surface 11A but also on the side wall 11B in the recess 11. Similarly to Embodiments 1 and 2, it may be formed only on bottom surface 11A. In the first and second embodiments, it may be formed not only on the bottom surface 11A but also on the side wall 11B.

(Embodiment 4)
Next, an oxide film field effect transistor (MOSFET) which is a semiconductor device according to the fourth embodiment of the present invention will be described. FIG. 17 is a schematic cross-sectional view showing a configuration of a MOSFET as a semiconductor device according to the fourth embodiment which is an embodiment of the present invention.

Referring to FIG. 17, MOSFET 3 (trench MOS) in the fourth embodiment, SBD 1 in the first embodiment explained based on FIG. 1, and pn diode 2 in the third embodiment explained based on FIG. The n ⁺ -SiC substrate 15, the recess 11, the recess filling layer 30, the ohmic electrode 50, the conductive film 40, etc. have basically the same configuration and the same operational effects. However, the configuration of the device formed on the n ⁺ -SiC substrate 15 is different from the SBD 1 in FIG. 1 and the pn diode in FIG.

That is, the MOSFET 3 includes the n ⁺ -SiC substrate 15 having the recess 11 filled with the recess filling layer 30, the ohmic electrode 50, and the conductive film 40, similar to the pn diode 2, and is formed on the n ⁺ -SiC substrate 15. The n ⁻ -SiC layer 25 is formed. Here, the conductive film 40 functions as a drain electrode in the MOSFET 3. On the n ⁻ -SiC layer 25, a p ⁻ −SiC layer 82 is formed as a low concentration p-type semiconductor layer containing a low concentration p-type impurity. Further, in the p ⁻ −SiC layer 82, the p ⁻ −SiC layer 82 penetrates from the second surface 82 B that is the surface opposite to the first surface 82 A that is the surface on the n ⁻ −SiC layer 25 side. A trench 89 having a bottom in the n ⁻ -SiC layer 25 is formed in the MOSFET 3.

^Further, p - on -SiC layer ^82, p - in contact with -SiC layer 82, the oxide film 60 as an insulating film made of an insulator, cover the bottom and side walls of the groove 89, and groove 89 It is formed to extend to a region on p ⁻ -SiC layer 82 that is not formed. The oxide film 60 functions as a gate oxide film in the MOSFET 3. An Al electrode 72 made of Al as a conductor is formed on the oxide film 60 so as to be in contact with the oxide film 60. The Al electrode 72 functions as a gate electrode in the MOSFET 3.

Further, n ^{+ made of} SiC containing high-concentration n-type impurities so as to extend in a direction away from the groove 89 in the region in contact with the groove 89, including the second surface 82 </ b> B of the p ⁻ -SiC layer 82. Region 83 is formed. Further, in the region including the second surface 82B of the p ⁻ -SiC layer 82 on the side opposite to the trench 89 when viewed from the n ⁺ region 83, the p ⁺ region 84 containing a high concentration p-type impurity is n ^+. The region 83 is formed apart from the region 83. ^Then, p - on the second surface 82B of the -SiC layer ^82, p - in contact with -SiC layer 82, extends from the region ^{where the n +} region 83 is formed to a ^{region p +} region 84 is formed Thus, a Ni electrode 73 made of Ni as a conductor is formed. The Ni electrode 73 functions as a source electrode in the MOSFET 3.

Next, the operation of MOSFET 3 in the fourth embodiment will be described. Referring to FIG. 17, when the voltage of Al electrode 72 as the gate electrode is 0 V, that is, in the off state, p ⁻ −SiC layer 82 and n ⁻ −SiC layer 25 in contact with oxide film 60 as the gate oxide film A gap is reversely biased and a non-conduction state is established. On the other hand, when a positive voltage is applied to the Al electrode 72 that is the gate electrode, an inversion layer is formed in the vicinity of the p ⁻ -SiC layer 82 in contact with the oxide film 60 that is the gate oxide film. As a result, the n ⁺ region 83 and the n ⁻ −SiC layer 25 are electrically connected, and an electric current flows as the electrons move along the electron flow α. At this time, the current flows through the n ⁺ -SiC substrate 15 to the conductive film 40 functioning as a drain electrode. As described above, the n ⁺ -SiC substrate 15 has the recess 11 filled with the recess filling layer 30. As a result, the on-resistance of MOSFET 3 is reduced and a reduction in loss is achieved.

Next, a method for manufacturing MOSFET 3 which is a semiconductor device in the fourth embodiment will be described. The method for manufacturing MOSFET 3 in the fourth embodiment has been described based on FIGS. 1 to 14 in the step of forming n ⁺ -SiC substrate 15, recess 11, recess filling layer 30, ohmic electrode 50, and conductive film 40. This is basically the same as the manufacturing method of SBD 1 in the first embodiment. However, the step of forming a device arranged on n ⁺ -SiC substrate 15 is different from the method of manufacturing SBD 1 in the first embodiment.

That is, in the manufacturing method of MOSFET3 in the fourth embodiment, with reference to FIG. 8, first, ⁿ + -SiC substrate 15 is prepared in the substrate preparation step, in the semiconductor layer formation ^step, n + -SiC substrate 15 on Then, an n ⁻ -SiC layer 25 is formed. These steps can be performed basically in the same manner as in the first embodiment.

Thereafter, after the recess forming step is performed in the same manner as in the first embodiment, before the oxide film forming step is performed, the components of MOSFET 3 arranged on one main surface 15A of n ⁺ -SiC substrate 15 The step of forming is performed.

That is, first, a low-concentration p-type semiconductor layer forming step for forming a p-type semiconductor layer containing a low-concentration p-type impurity on the n ⁻ -SiC layer 25 is performed. Specifically, a p ⁻ −SiC layer 82 made of SiC containing a low-concentration p-type impurity is formed on first surface 25A of n ⁻ −SiC layer 25. The formation of the p ⁻ −SiC layer 82 can be performed by vapor phase epitaxial growth (CVD or the like) using a source gas containing a p-type impurity, for example.

Next, a high concentration n-type region forming step including a high concentration n-type impurity and a high concentration p-type region forming step including a high concentration p-type impurity are performed on the p ⁻ -SiC layer 82. Specifically, a mask layer forming step is performed in which a mask layer having an opening corresponding to the desired shape of the n ⁺ region 83 is formed on the p ⁻ -SiC layer 82 using photolithography or the like. . Then, using the mask layer as a mask, an impurity introduction step is performed in which an n-type impurity is introduced into the p ⁻ -SiC layer 82 by ion implantation or the like, and an n ⁺ region 83 is formed. Thereby, the high concentration n-type region forming step is completed. Also, the high concentration p-type region forming step can be performed by introducing a p-type impurity in place of the n-type impurity in the high concentration n-type region forming step.

Next, a groove forming step for forming the groove 89 is performed. Specifically, there is a mask layer forming step in which a mask layer such as an oxide layer having an opening corresponding to the shape of the desired groove 89 is formed on the p ⁻ -SiC layer 82 using photolithography or the like. To be implemented. Then, using the mask layer as a mask, a groove 89 is formed by RIE or the like.

Thereafter, a gate oxide film forming step for forming a gate oxide film is performed. Specifically, p ^- as the insulating film so as to extend to a region on -SiC layer 82 ^- on the -SiC layer 82 covers the bottom and side walls of the groove 89, and p is not formed a groove 89 An oxide film 60 is formed. Formation of oxide film 60 can be performed by, for example, CVD, thermal oxidation, or the like. Further, a gate electrode forming step is performed in which an Al electrode 72 as a gate electrode is formed on the oxide film 60 as a gate oxide film. The Al electrode 72 can be formed by, for example, a vapor deposition method. ^Further, p - on the second surface 82B to the -SiC layer ^82, p - in contact with -SiC layer 82, extends from the region ^{where the n +} region 83 is formed to a ^{region p +} region 84 is formed Thus, a source electrode forming step for forming the Ni electrode 73 as the source electrode is performed. The Ni electrode 73 can be formed by, for example, a vapor deposition method.

  Then, the MOSFET 3 in the fourth embodiment can be manufactured by performing the steps from the ohmic electrode forming step to the dividing step in the same manner as in the first embodiment following the above steps.

  In the first to fourth embodiments, the case where SiC is employed as the material of the substrate has been described. However, the semiconductor device of the present invention is not limited to this. As a material of the substrate in the semiconductor device of the present invention, semiconductor materials such as silicon (Si) and gallium nitride (GaN) can be employed in addition to SiC. In particular, it is preferable to employ a wide band gap semiconductor, which is a semiconductor having a larger band gap than Si, as the material of the substrate.

  In addition, as described above, the semiconductor device of the present invention is particularly characterized in the structure of the substrate, and has the effect of achieving suppression of on-resistance by reducing substrate resistance. Therefore, in the first to fourth embodiments, the case where the configuration of the SBD, the pn diode, and the MOSFET is adopted as the semiconductor device has been described. However, the semiconductor device of the present invention is not limited to this, and the junction field effect transistor ( Various semiconductor devices including a junction field effect transistor (JFET), in particular, a configuration of a vertical device can be employed.

  The embodiment disclosed this time is to be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  The semiconductor device and the manufacturing method thereof according to the present invention can be particularly advantageously applied to a semiconductor device and a manufacturing method thereof that require a reduction in on-resistance.

1 is a schematic cross-sectional view illustrating a configuration of a Schottky diode as a semiconductor device according to a first embodiment. FIG. 3 is a schematic plan view of the SiC substrate in the first embodiment. It is a schematic sectional drawing in alignment with line segment III-III of FIG. 6 is a schematic plan view of a SiC substrate in a first modification of the first embodiment. FIG. It is a schematic sectional drawing in alignment with line segment VV of FIG. 6 is a schematic plan view of an SiC substrate in a second modification of the first embodiment. FIG. It is a schematic sectional drawing in alignment with line segment VII-VII of FIG. 3 is a flowchart showing an outline of a method of manufacturing an SBD in the first embodiment. FIG. 5 is a schematic cross sectional view for illustrating the method for manufacturing the SBD in the first embodiment. FIG. 5 is a schematic cross sectional view for illustrating the method for manufacturing the SBD in the first embodiment. FIG. 5 is a schematic cross sectional view for illustrating the method for manufacturing the SBD in the first embodiment. FIG. 5 is a schematic cross sectional view for illustrating the method for manufacturing the SBD in the first embodiment. FIG. 5 is a schematic cross sectional view for illustrating the method for manufacturing the SBD in the first embodiment. FIG. 5 is a schematic cross sectional view for illustrating the method for manufacturing the SBD in the first embodiment. 6 is a schematic cross-sectional view showing a configuration of an SBD as a semiconductor device of a second embodiment. FIG. 6 is a schematic cross-sectional view showing a configuration of a pn diode as a semiconductor device of a third embodiment. FIG. FIG. 10 is a schematic cross-sectional view showing a configuration of a MOSFET as a semiconductor device of a fourth embodiment.

Explanation of symbols

1 SBD, 2 pn diode, 3 MOSFET, 10 SiC substrate, 10A one main surface, 10B other main surface, 10C main body portion, 11 recess, 11A bottom surface, 11B side wall, 15 n ⁺ -SiC substrate, 15A one main surface Surface, 15B other main surface, 20 n-SiC layer, 20A first surface, 20B second surface, 25 n ⁻ -SiC layer, 25A first surface, 30 recess filling layer, 40 conductive film, 50 ohmic Electrode, 60 oxide film, 61 window, 71 Ti electrode, 72 Al electrode, 73 Ni electrode, 81 p-SiC region, 82 p ⁻ —SiC layer, 82A first surface, 82B second surface, 83 n ⁺ Region, 84 p ⁺ region, 89 trench, 91 thermal oxide film.

Claims (10)

A substrate made of a semiconductor material;
A semiconductor layer formed on one main surface of the substrate,
A concave portion is formed on the other main surface of the substrate, which is the main surface opposite to the one main surface,
The semiconductor device, wherein the recess is filled with a high conductivity material having a higher electrical conductivity than a semiconductor material constituting the substrate.   The semiconductor device according to claim 1, wherein the high conductivity material is a material having higher thermal conductivity than a semiconductor material constituting the substrate.   The semiconductor device according to claim 1, wherein the recess is formed in a stripe shape or a lattice shape when viewed from a side facing the other main surface.   The semiconductor device according to claim 1, wherein a plurality of the recesses are arranged in a distributed manner on the other main surface.   The semiconductor device according to claim 1, wherein an ohmic electrode made of a material capable of being in ohmic contact with the substrate is further formed in a region in contact with the bottom surface of the recess.   The semiconductor device according to claim 1, wherein a conductive film made of a conductor having better adhesion than the high conductivity material is disposed on the other main surface.   The semiconductor device according to claim 1, wherein the semiconductor material constituting the substrate is any material selected from the group consisting of silicon, gallium nitride, and silicon carbide.   The semiconductor device according to claim 1, which is any semiconductor device selected from the group consisting of a Schottky diode, a pn diode, a MOSFET, and a JFET. A substrate preparation step in which a substrate made of a semiconductor material is prepared;
A semiconductor layer forming step in which a semiconductor layer is formed on one main surface of the substrate;
A recess forming step in which a recess is formed on the other main surface of the substrate that is the main surface opposite to the one main surface;
A method of manufacturing a semiconductor device, comprising: a high conductivity material filling step in which the recess is filled with a high conductivity material having a higher electrical conductivity than the semiconductor material constituting the substrate. After the recess forming step, further comprising a dividing step in which the substrate on which the semiconductor layer is formed is divided,
In the concave portion forming step, the concave portion is formed in a stripe shape or a lattice shape when viewed from the side facing the other main surface,
The method for manufacturing a semiconductor device according to claim 9, wherein in the dividing step, the substrate is divided in the concave portion.

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