JP2008177515A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology capable of smoothly discharging holes generated during the operation of a semiconductor device utilizing a nitride semiconductor. <P>SOLUTION: The semiconductor device 1 has a p-type gallium nitride region 16 of gallium nitride which has a high dislocation density region 18 and a low dislocation density region 19. In a plane view of a semiconductor device 2, a switching structure is formed in a range wherein the low dislocation density region 19 exists. The semiconductor device 2 is further provided with a body electrode 20 brought into contact with the p-type gallium nitride region 16. The body electrode 20 is brought into contact with the high dislocation density region 18. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device composed of a nitride semiconductor and a manufacturing method thereof. In particular, the present invention relates to a semiconductor device improved so that the contact resistance between a p-type nitride semiconductor region containing a p-type impurity and an electrode formed on the surface thereof is lowered.

  Development of a semiconductor device composed of a nitride semiconductor is in progress. For example, the development of MISFETs (Metal Insulated Semiconductor Field Effect Transistors), IGBTs (Insulated Gate Bipolar Transistors), HEMTs (High Electron Mobility Transistors), diodes, and the like made of nitride semiconductors is underway. Non-Patent Document 1 discloses a MOSFET composed of a nitride semiconductor.

  FIG. 27 schematically shows a cross-sectional view of MOSFET 100 disclosed in Non-Patent Document 1. MOSFET 100 includes a p-type body region 116 formed on the surface of substrate 110, an n-type drain region 122 and an n-type source region 124 formed on the surface of body region 116. The drain region 122 and the source region 124 are separated by the body region 116. The MOSFET 100 further includes a gate electrode 130 facing the body region 116 that separates the drain region 122 and the source region 124 with a gate insulating film 129 interposed therebetween. The drain region 122 is electrically connected to the drain electrode 126, and the source region 124 is electrically connected to the source electrode 128. MOSFET 100 further includes a body electrode 120 that is electrically connected to body region 116. Body electrode 120 discharges holes from body region 116.

Y. Irokawa et. Al., Appl. Phys. Lett., 2004, vol.84, No.15, p. 2919

In general, it is known that p-type impurities contained in nitride semiconductors have a low activation rate. For this reason, there is a problem that it is difficult to reduce the contact resistance between the body electrode 120 and the body region 116.
The above problem is not limited to the MOSFET 100. In other types of semiconductor devices, electrodes may be formed on the surface of the p-type nitride semiconductor region. Also in this case, there is a problem that it is difficult to reduce the contact resistance between the p-type nitride semiconductor region and the electrode.
The present invention relates to a semiconductor device in which an electrode is formed on the surface of a p-type nitride semiconductor region. An object of the present invention is to provide a semiconductor device in which a contact resistance between a p-type nitride semiconductor region and an electrode is kept small. The present invention also aims to provide a method of manufacturing such a semiconductor device.

  The technique disclosed in this specification positively utilizes dislocations existing in the p-type nitride semiconductor crystal in order to reduce the contact resistance between the p-type nitride semiconductor region and the electrode. According to the inventors' research, when an electrode is formed on the surface of a region where many dislocations exist (a region having a high dislocation density, which is called a high dislocation density region in the present invention), the conductive material forming the electrode is dislocated. It has been found that the contact resistance between the p-type nitride semiconductor region and the electrode decreases as it enters the p-type semiconductor region. The technology disclosed in this specification utilizes the knowledge.

A semiconductor device disclosed in this specification includes a p-type nitride semiconductor region having a high dislocation density region and a low dislocation density region and containing p-type impurities, and a surface of a high dislocation density region of the p-type nitride semiconductor region. The electrode formed in at least one part of is provided.
In the semiconductor device, since the electrode is formed on the surface of the high dislocation density region where the dislocation density is high, the contact resistance between the p-type nitride semiconductor region and the electrode can be kept low. In the case of this semiconductor device, holes can be smoothly discharged from the p-type nitride semiconductor region when it is necessary to prevent holes from accumulating in the p-type nitride semiconductor region. Alternatively, when it is necessary to stabilize the potential of the p-type nitride semiconductor region, the potential can be stabilized.

The semiconductor device disclosed in this specification preferably further includes a lattice mismatching layer facing the electrode via a high dislocation density region. In this case, the lattice constants of the lattice mismatching layer and the p-type nitride semiconductor region are mismatched.
If the lattice constants of the lattice mismatching layer and the p-type nitride semiconductor region do not match, when the p-type nitride semiconductor region is crystal-grown from the surface of the lattice mismatching layer, there is a dislocation on the surface of the lattice mismatching layer. A high dislocation density region having a high density is formed. The semiconductor device has a configuration in which a high dislocation density region can be easily formed in a part of the p-type nitride semiconductor region.

In the semiconductor device disclosed in this specification, the lattice mismatch layer is preferably formed in a part of the p-type nitride semiconductor region. In this case, a high dislocation density region exists between the lattice mismatch layer and the electrode.
Here, “the lattice mismatching layer is formed in a part of the p-type nitride semiconductor region” means a form in which the lattice mismatching layer is surrounded by the p-type nitride semiconductor region. This means that the matching layer is separated from other regions by the p-type nitride semiconductor region.
In the semiconductor device of the above aspect, the high dislocation density region does not exist through the p-type nitride semiconductor region, but exists in a limited range between the lattice mismatch layer and the electrode. For this reason, the range affected by the high dislocation density region can be limited to a limited range between the lattice mismatch layer and the electrode, and as a result, the semiconductor device capable of suppressing an increase in leakage current and a change in breakdown voltage characteristics. Is obtained.

The technology disclosed in this specification can be embodied in a semiconductor device having a switching function, such as a MOS or an IGBT. One specific semiconductor device disclosed in this specification includes a nitride semiconductor underlayer, a lattice mismatching layer formed on a part of the surface of the underlayer, and an underlayer to a lattice mismatching layer. A p-type nitride semiconductor region formed on the surface of the underlying layer and the lattice mismatching layer extending in a straddle and containing p-type impurities, and a p-type in a range where the lattice mismatching layer exists when viewed in plan An electrode formed on at least a part of the surface of the nitride semiconductor region, and a switching structure formed in a range where the lattice mismatching layer does not exist when seen in a plan view. In the semiconductor device disclosed in this specification, the difference in lattice constant between the base layer and the p-type nitride semiconductor region is smaller than the difference in lattice constant between the lattice mismatch layer and the p-type nitride semiconductor region.
According to the above semiconductor device, since the difference in lattice constant between the base layer and the p-type nitride semiconductor region is smaller than the difference in lattice constant between the lattice mismatch layer and the p-type nitride semiconductor region, the lattice mismatch with the base layer When a p-type nitride semiconductor region is crystal-grown from the surface of the layer, a region with few dislocations is formed on the surface of the underlayer, whereas a region with many dislocations is formed on the surface of the lattice mismatch layer. The When an electrode is formed on the surface of the p-type nitride semiconductor region in a range where the lattice mismatching layer exists when seen in a plan view, the electrode is in contact with the high dislocation density region formed in the p-type nitride semiconductor region. As a result, the contact resistance between the electrode and the p-type nitride semiconductor region decreases, and holes generated by the avalanche phenomenon when a high voltage is applied between the drain electrode and the source electrode are smoothly transferred from the p-type nitride semiconductor region to the electrode. To be discharged. When viewed in a plan view, the region where no lattice mismatching layer exists is a clean crystal with few dislocations. Since the switching structure is formed in this low dislocation density region, the switching structure exhibits excellent characteristics.

Another specific semiconductor device disclosed in this specification includes a nitride semiconductor underlayer, a p-type nitride semiconductor region formed on the surface of the underlayer, and including a p-type impurity. And a lattice mismatching layer formed in a part of the p-type nitride semiconductor region, and at least a part of the surface of the p-type nitride semiconductor region in a range where the lattice mismatching layer exists in a plan view. And a switching structure formed in a range where the lattice mismatching layer does not exist when viewed in a plan view. In another specific semiconductor device disclosed in this specification, the difference between the lattice constants of the base layer and the p-type nitride semiconductor region is the lattice constant of the lattice mismatch layer and the p-type nitride semiconductor region. Smaller than the difference.
In the above semiconductor device, the lattice mismatch layer is separated from the base layer via the p-type nitride semiconductor region. For this reason, since a p-type nitride semiconductor region with few dislocations exists between the lattice mismatch layer and the underlayer, stable characteristics of the semiconductor device can be obtained.

  Various switching structures can be incorporated in the semiconductor device disclosed in this specification. For example, a MISFET structure can be incorporated. In this case, the switching structure is formed on a part of the surface of the p-type nitride semiconductor region in a range where the lattice mismatching layer does not exist when viewed in plan, and includes a drain region including an n-type impurity, The p-type nitride semiconductor region is formed on a part of the surface of the p-type nitride semiconductor region where no lattice mismatching layer exists when viewed, and the n-type impurity is separated from the drain region by the p-type nitride semiconductor region. And a gate electrode facing the p-type nitride semiconductor region separating the source region and the drain region with a gate insulating film interposed therebetween.

  Alternatively, a HEMT structure can be incorporated. The switching structure in that case is formed on the surface of the nitride semiconductor lower layer formed on the surface of the p-type semiconductor region in a range where the lattice mismatching layer does not exist when viewed in plan, and on the surface of the nitride semiconductor lower layer A nitride semiconductor upper layer; a drain electrode formed on a part of the surface of the nitride semiconductor upper layer; a source electrode formed on another part of the surface of the nitride semiconductor upper layer; a drain electrode and a source electrode; A gate electrode formed on at least a part of the surface of the separated nitride semiconductor upper layer is provided. In the above, the band gap width of the nitride semiconductor lower layer is smaller than the band gap width of the nitride semiconductor upper layer. The gate electrode may be formed directly on the surface of the nitride semiconductor upper layer, or a gate insulating film may be interposed between the gate electrode and the nitride semiconductor upper layer.

  Alternatively, a HEMT structure capable of flowing a current in the vertical direction can be incorporated. In this case, the switching structure has an n-type impurity that penetrates from the front surface to the back surface of the p-type nitride semiconductor region in a range where the lattice mismatching layer does not exist when seen in a plan view and includes an n-type impurity. Nitride semiconductor region, p-type nitride semiconductor region in a range where no lattice mismatching layer exists when viewed in plan, nitride semiconductor lower layer formed on the surface of n-type nitride semiconductor region, and nitride semiconductor A nitride semiconductor upper layer formed on the surface of the lower layer, a source electrode formed on a part of the surface of the nitride semiconductor upper layer in a range where the n-type nitride semiconductor region does not exist when viewed in plan, A gate electrode formed on at least a part of the surface of the upper layer of the nitride semiconductor that separates the source electrode and the n-type nitride semiconductor region in plan view, and electrically connected to the back surface of the base layer Dray And a electrode. Also in this case, the band gap width of the nitride semiconductor lower layer is smaller than the band gap width of the semiconductor upper layer. The gate electrode may be formed on the surface of the nitride semiconductor upper layer, or a gate insulating film may be interposed between the gate electrode and the nitride semiconductor upper layer.

In the semiconductor device disclosed in this specification, it is preferable that the same type of semiconductor is used for the base layer and the p-type nitride semiconductor region.
In this case, the lattice constants of the underlayer and the p-type semiconductor region are the same. Therefore, when the p-type semiconductor region is crystal-grown from the surface of the underlayer, a low dislocation density region with few dislocations is formed above the underlayer.

  In the semiconductor device disclosed in this specification, gallium nitride is preferably used for the base layer and the p-type nitride semiconductor region, and aluminum nitride is preferably used for the lattice mismatch layer. Since aluminum nitride has a smaller lattice constant than gallium nitride, the lattice constants of the lattice mismatch layer and the p-type nitride semiconductor region do not match. Therefore, when the p-type semiconductor region is crystal-grown from the surface of the lattice mismatch layer, a high dislocation density region with many dislocations is formed above the lattice mismatch layer.

  According to the technique disclosed in this specification, when forming an electrode on the surface of the p-type nitride semiconductor region, in order to form the electrode in a region having a high dislocation density existing in the p-type nitride semiconductor region, The conductive material forming the electrode enters the p-type nitride semiconductor region along the dislocation. Therefore, the contact resistance between the p-type nitride semiconductor region and the electrode can be lowered. As a result, for example, holes generated in the p-type nitride semiconductor region during operation of the semiconductor device can be smoothly discharged to the electrode. Alternatively, the potential of the p-type nitride semiconductor region can be stabilized.

Preferred features of the technology disclosed in this specification are listed.
(First Feature) As the p-type impurity, it is preferable to use magnesium, beryllium, or calcium.
(Second Feature) As the n-type impurity, it is preferable to use silicon, selenium or the like.
(Third feature) The nitride semiconductor has a general formula of Al _X Ga _Y In _1-XY N (where 0 ≦ X ≦ 1, 0 ≦ Y ≦ 1, 0 ≦ 1-X−Y ≦ 1). Is preferred.
(Fourth feature) The lattice mismatch layer is preferably a nitride semiconductor. In this case, the general formula of the nitride forming the base layer, the lattice mismatching layer, and the p-type nitride semiconductor region is Al _X Ga _Y In _1-XY N (where 0 ≦ X ≦ 1, 0 ≦ Y ≦ 1, It is preferable that 0 ≦ 1−X−Y ≦ 1). In this case, X, Y, 1-XY in the general formula of the nitride forming the lattice mismatching layer is X, Y in the general formula of the nitride forming the base layer and the p-type nitride semiconductor region. , 1-XY is preferred.
(Fifth feature) The lattice mismatch layer is formed in a part of the p-type nitride semiconductor region, and the thickness of the p-type nitride semiconductor region existing above the lattice mismatch layer and the lattice mismatch layer It is preferable that the thickness of the p-type nitride semiconductor region existing below is substantially equal.

(First embodiment)
FIG. 1 schematically shows a cross-sectional view of a semiconductor device 1 having a MISFET structure as a switching structure. The semiconductor device 1 includes a substrate 10 and a base layer 12 formed on the substrate 10. Sapphire (Al ₂ O ₃ ) is used as the material of the substrate 10. As a material of the substrate 10, silicon (Si), silicon carbide (SiC), or gallium nitride (GaN) may be used. The underlying layer 12 is made of gallium nitride that does not contain impurities. An aluminum nitride lattice mismatch layer 14 is formed on a part of the surface of the underlayer 12. The lattice mismatching layer 14 is formed on a part of the peripheral edge of the surface of the underlayer 12 and has a thickness of about 10 nm. A p-type gallium nitride region 16 (an example of a p-type nitride semiconductor region) containing a p-type impurity is formed on the surface of the base layer 12 and the lattice mismatch layer 14. The p-type gallium nitride region 16 is continuously formed in a range extending from the surface of the underlayer 12 to the surface of the lattice mismatch layer 14. Magnesium (Mg) is used as an impurity in the p-type gallium nitride region 16, and its carrier concentration is adjusted to about 1 × 10 ¹⁷ cm ⁻³ . The thickness of the p-type gallium nitride region 16 is about 1000 nm. The p-type gallium nitride region 16 includes a high dislocation density region 18 where dislocations exist in the crystal at a high density and a low dislocation density region 19 where dislocations exist only at a low density. The high dislocation density region 18 is formed in a range where the lattice mismatching layer 14 exists when viewed in plan. The low dislocation density region 19 is formed in a range where the lattice mismatching layer 14 does not exist when viewed in plan.

  The semiconductor device 1 further includes a body electrode 20 formed on the surface of the p-type gallium nitride region 16. The body electrode 20 is formed on at least a part of the surface of the high dislocation density region 18 in the p-type gallium nitride region 16. Nickel (Ni) is used as the material of the body electrode 20.

The semiconductor device 1 further includes a drain region 22 and a source region 24 formed on the surface of the low density region 19 of the p-type gallium nitride region 16. The drain region 22 and the source region 24 contain n-type impurities. Silicon is used for the n-type impurity. The drain region 22 and the source region 24 are separated by the p-type gallium nitride region 16. The source region 24 is disposed on the body electrode 20 side. The drain region 22 is electrically connected to the drain electrode 26, and the source region 24 is electrically connected to the source electrode 28.
The semiconductor device 1 further includes a gate electrode 30. The gate electrode 30 is opposed to the surface of the p-type gallium nitride region 16 that separates the drain region 22 and the source region 24 with a gate insulating film 29 interposed therebetween. The gate electrode 30 is made of nickel (Ni), aluminum (Al), polycrystalline silicon (Poly-Si), or the like. As the gate insulating film 29, a silicon oxide film (SiO) or a silicon nitride film (SiN) is used.

Next, the operation of the semiconductor device 1 will be described.
The drain region 22 and the source region 24 are separated by the p-type gallium nitride region 16. When no voltage is applied to the gate electrode 30, no inversion layer is formed in the p-type gallium nitride region 16 that separates the drain region 22 and the source region 24, and a current path is formed between the drain region 22 and the source region 24. Is not formed.
When a positive voltage is applied to the gate electrode 30, electrons are induced at the interface between the p-type gallium nitride region 16 and the gate insulating film 29, and the p-type gallium nitride region 16 separating the drain region 22 and the source region 24. An n-type inversion layer is formed. Therefore, a current path is formed between the drain region 22 and the source region 24.

When a high voltage is applied between the drain electrode 26 and the source electrode 28, holes are generated due to the avalanche phenomenon. When the generated holes are accumulated in the p-type gallium nitride region 16, the potential of the p-type gallium nitride region 16 rises, and the parasitic transistor operates to break the device. Therefore, it is desirable that the generated holes are quickly discharged from the p-type gallium nitride region 16.
In the semiconductor device 1, the body electrode 20 is formed on the surface of the high dislocation density region 18 in the p-type gallium nitride region 16. In the high dislocation density region 18, dislocations are present at a high density. When the body electrode 20 is formed on the surface of the high dislocation density region 18, the conductive material forming the body electrode 20 enters the high dislocation density region 18 along the dislocation. When the body electrode 20 is formed on the surface of the high dislocation density region 18, the contact resistance between the body electrode 20 and the high dislocation density region 18 is lowered. For this reason, the holes generated in the p-type gallium nitride region are smoothly discharged to the body electrode 20.

Next, a method for manufacturing the semiconductor device 1 will be described.
First, as shown in FIG. 7, a substrate 10 made of sapphire or the like as a main material is prepared, and a gallium nitride layer serving as a gallium nitride underlayer 12 is crystal-grown on the entire surface using MOCVD. Impurities are not introduced into the underlayer 12. Next, an aluminum nitride lattice mismatch layer 14 is grown on the entire surface of the underlayer 12 by MOCVD. The temperature for crystal growth of the underlayer 12 is adjusted to about 1100 ° C., and the temperature for crystal growth of the lattice mismatch layer 14 is adjusted to about 600 ° C. or less.
Next, as shown in FIG. 8, the insulating film 13 mainly composed of a silicon oxide film or a silicon nitride film is patterned on the surface of the lattice mismatch layer 14. Next, using the wet etching technique, a part of the exposed lattice mismatching layer 14 is removed. For wet etching, wet etching based on potassium hydroxide (KOH) (JRMileham et.al., Appl. Phys. Lett., Vol. 67 (1995), p. 1119, etc.) can be used. Instead of wet etching, ICP dry etching or the like may be used.
After removing a part of the lattice mismatching layer 14, the insulating film 13 is removed, and as shown in FIG. 9, a p-type impurity is formed from the surfaces of the lattice mismatching layer 14 and the underlayer 12 using the MOCVD method. Crystal growth of gallium nitride containing. As the p-type impurity, magnesium (Mg) or the like is doped. Thereby, the p-type gallium nitride region 16 is formed. The p-type gallium nitride region 16 and the underlayer 12 are both gallium nitride, and the lattice constants of both are the same. On the other hand, since the lattice mismatching layer 14 is aluminum nitride, the lattice constants of the p-type gallium nitride region 16 and the lattice mismatching layer 14 do not match. Therefore, when the p-type gallium nitride region 16 is crystal-grown, a high dislocation density region 18 in which dislocations exist at a high density is formed on the surface of the lattice mismatch layer 14 due to the difference in lattice constant. On the other hand, since the lattice constants coincide with each other, a low dislocation density region 19 in which dislocations exist only at a low density is formed on the surface of the underlayer 12.
Thereafter, after all the natural oxide film is removed, an insulating film 29 is again formed on the entire surface as shown in FIG. Next, a part of the insulating film 29 corresponding to the low dislocation density region 19 is removed, and the drain region 22 and the source region 24 are formed. The drain region 22 and the source region 24 can be formed using an ion implantation technique. Thereafter, after all the insulating film 29 is removed, the insulating film 29 is formed again on the entire surface as shown in FIG. Thereafter, the insulating film 29 corresponding to the high dislocation density region 18 is removed, and the body electrode 20 is formed on the surface of the high dislocation density region 18. Next, as shown in FIG. 1, a part of the insulating film 29 inside the drain region 22 and the source region 24 is removed, and a drain electrode 26 is formed on a part of the surface of the drain region 22. A source electrode 28 is formed on a part of the surface. Finally, a gate electrode 30 mainly composed of nickel (Ni), aluminum (Al), polycrystalline silicon (Poly-Si) or the like is formed on the surface of the insulating film 29 that separates the drain region 22 and the source region 24. . Through these steps, the semiconductor device 1 shown in FIG. 1 can be formed.

(Second embodiment)
FIG. 2 schematically shows a cross-sectional view of another semiconductor device 2 having a MISFET structure as a switching structure. The structure of the semiconductor device 2 is different from that of the semiconductor device 1 in that a lattice mismatch layer 14 is formed in a part of the p-type gallium nitride region 16. The lattice mismatch layer 14 is separated from the base layer 12 by a p-type gallium nitride region 16. The p-type gallium nitride region 16 includes a high dislocation density region 18 where dislocations exist in the crystal at a high density and a low dislocation density region 19 where dislocations exist only at a low density. The high dislocation density region 18 is formed above the lattice mismatch layer 14 in a range where the lattice mismatch layer 14 exists when viewed in plan. That is, the high dislocation density region 18 is localized in a region between the lattice mismatch layer 14 and the body electrode 20. On the other hand, the low dislocation density region 19 is formed below the lattice mismatching layer 14 in a range where the lattice mismatching layer 14 does not exist and a range where the lattice mismatching layer 14 exists when viewed in plan.

  Since the operation of the semiconductor device 2 and the discharge of holes are the same as those in the first embodiment, the description thereof is omitted. In the structures of the semiconductor device 1 and the semiconductor device 2, the base layer 12 containing no impurities serves as a buffer layer for improving crystallinity. Depending on the state of the underlayer 10, when the p-type gallium nitride region 16 is crystal-grown from the surface of the underlayer 10, crystal defects and interface states exist at the interface between the p-type gallium nitride region 16 and the underlayer 10. Sometimes. In the semiconductor device 1 of the first embodiment, the lattice mismatch layer 14 is formed on the surface of the base layer 10, and the lattice mismatch layer 14 is caused by the mismatch of the lattice constant between the lattice mismatch layer 14 and the base layer 12. When crystals are grown from the surface of the underlayer 12, dislocations are often formed also in the lattice mismatch layer 14. In this case, the interface between the base layer 12 and the p-type gallium nitride region 16 and the body electrode 20 are electrically connected via dislocations in the high dislocation density region 19 and dislocations in the lattice mismatch layer 14. Current may flow laterally through the interface between the p-type gallium nitride region 16 and the p-type gallium nitride region 16. Therefore, when the semiconductor device 1 of FIG. 1 is turned off, a leak current may flow between the drain electrode 26 and the body electrode 20. However, in the semiconductor device 2 of the second embodiment, the lattice mismatching layer 14 is separated from the base layer 12 by the p-type gallium nitride region 16. Since the p-type gallium nitride region 16 between the lattice mismatching layer 14 and the underlayer 12 is a region with few dislocations, the lattice mismatching layer 14 and the underlayer 12 are electrically insulated by this region with few dislocations. When the lattice mismatch layer 14 is formed in the p-type gallium nitride region 16, the leakage current is suppressed.

Next, a method for manufacturing the semiconductor device 2 will be described.
The process up to the step of crystal growth of the underlayer 12 is the same as the procedure shown in the manufacturing method of the first embodiment, and thus the description thereof is omitted. Next, as shown in FIG. 11, gallium nitride containing p-type impurities is grown from the surface of the underlayer 12 to about half the thickness of the desired p-type gallium nitride region 16. Thereby, the p-type gallium nitride region 16a is formed. Next, the lattice mismatch layer 14 of aluminum nitride is crystal-grown on the entire surface of the p-type gallium nitride region 16a using the MOCVD method. Next, as shown in FIG. 12, after patterning the insulating film 13 on the surface of the lattice mismatch layer 14, a part of the lattice mismatch layer 14 is removed. In this step, a wet etching technique can be used as in the first embodiment.
After removing a part of the lattice mismatching layer 14, the insulating film 13 is removed and, as shown in FIG. 13, using the MOCVD method, the surface of the lattice mismatching layer 14 and the p-type gallium nitride region 16a is removed. Crystal growth of gallium nitride containing a p-type impurity is further grown to about half the thickness of the desired gallium nitride region 16. As a result, the lattice mismatch layer 14 is formed in the p-type gallium nitride region 16. Due to the difference in lattice constant, a high dislocation density region 18 in which dislocations exist at a high density is formed on the surface of the lattice mismatching layer 14. On the other hand, since the lattice constants coincide with each other, a low dislocation density region 19 in which dislocations exist only at a low density is formed on the surface of the underlayer 12 including the region on the lower surface of the lattice mismatch layer 14.
Next, after all the natural oxide film is removed, an insulating film 29 is formed again on the entire surface as shown in FIG. Next, since the process of forming the switching structure is the same as that of the first embodiment, the description thereof is omitted. Through the process of forming the switching structure, the semiconductor device 2 shown in FIG. 2 can be formed.

(Third embodiment)
FIG. 3 schematically shows a cross-sectional view of a semiconductor device 3 having a horizontal HEMT structure as a switching structure. The structure from the substrate 10 to the p-type gallium nitride region 16 is the same as that of the semiconductor device 1 having the MISFET structure shown in FIG.
The semiconductor device 3 includes a nitride semiconductor lower layer 52 formed on the surface of the low dislocation density region 19. The nitride semiconductor lower layer 52 is formed of gallium nitride containing n-type impurities. Silicon (Si) is used as the n-type impurity, and its carrier concentration is adjusted to about 1 × 10 ¹⁶ cm ⁻³ . The thickness of the nitride semiconductor lower layer 52 is about 50 nm to 300 nm.
The semiconductor device 3 further includes a nitride semiconductor upper layer 54 formed on the surface of the nitride semiconductor lower layer 52. The nitride semiconductor upper layer 54 is made of aluminum gallium nitride (AlGaN) that does not contain impurities. The thickness of the nitride semiconductor upper layer 54 is about 30 nm. The band gap width of the nitride semiconductor lower layer 52 formed of gallium nitride is smaller than the band gap width of the nitride semiconductor upper layer 54 formed of aluminum gallium nitride. The junction surface between the nitride semiconductor upper layer 54 and the nitride semiconductor lower layer 52 is a heterojunction, and a two-dimensional electron gas layer 53 is formed in the vicinity of the interface.

The semiconductor device 3 further includes a drain electrode 66 and a source electrode 68 formed on the surface of the nitride semiconductor upper layer 54. The drain electrode 66 is opposed to the semiconductor lower layer 52 through a part of the nitride semiconductor upper layer 54. The source electrode 68 is opposed to the nitride semiconductor lower layer 52 through another part of the nitride semiconductor upper layer 54. The source electrode 68 is disposed on the body electrode 20 side. The materials used for the drain electrode 66, the source electrode 68, and the body electrode 20 are the same as those of the semiconductor device 1. An n-type impurity may be introduced into a part of the nitride semiconductor upper layer 54, and the drain electrode 66 and the semiconductor lower layer 52 may be connected via a region into which the n-type impurity is introduced. Similarly, an n-type impurity may be introduced into a part of the nitride semiconductor upper layer 54, and the source electrode 68 and the semiconductor lower layer 52 may be connected via a region into which the n-type impurity is introduced.
The semiconductor device 3 further includes a gate electrode 60 disposed between the drain electrode 66 and the source electrode 68. The gate electrode 60 faces the surface of the nitride semiconductor upper layer 54 with a gate insulating film 59 interposed therebetween. The material of the gate electrode 60 is nickel (Ni), aluminum (Al), polycrystalline silicon (Poly-Si), or the like. As a material of the gate insulating film 59, a silicon oxide film (SiO) or a silicon nitride film (SiN) is used. The gate insulating film can be omitted. Even if the gate insulating film 59 is omitted, the gate electrode 60 and the nitride semiconductor upper layer 54 are not in ohmic contact. The gate electrode 60 is formed on the surface of the low dislocation density region 19, has a high contact resistance, and has a Schottky characteristic.

Next, the operation of the semiconductor device 3 will be described.
As described above, the two-dimensional electron gas layer 53 is formed near the interface between the nitride semiconductor lower layer 52 and the nitride semiconductor upper layer 54. Therefore, in a state where no voltage is applied to the gate electrode 60, the two-dimensional electron gas layer 53 serves as a channel, and a current path is formed from the drain electrode 66 to the source electrode 68. The semiconductor device 3 operates as a normally-on.
When a negative voltage is applied to the gate electrode 60, a depletion layer is formed in a part of the two-dimensional electron gas layer 53, and movement of electrons is blocked. The semiconductor device 3 can switch the conduction state and the non-conduction state with time by switching the voltage applied to the gate electrode 60.

  When a high voltage is applied between the drain electrode 66 and the source electrode 68, holes are generated by an avalanche phenomenon. The generated holes move to the p-type gallium nitride region 16 and are smoothly discharged to the body electrode 20 formed in the high dislocation density region 18 and having a low contact resistance.

  The semiconductor device 3 can also be operated as normally-off. When the semiconductor device 3 is operated normally off, it is desirable to form the nitride semiconductor lower layer 52 with a thickness of 50 nm or less. When the thickness of the nitride semiconductor lower layer 52 is 50 nm or less, the n-type nitride is formed from the junction surface between the p-type nitride semiconductor region 16 and the n-type nitride semiconductor lower layer 52 in a state where no voltage is applied to the gate electrode 60. The depletion layer extends toward the semiconductor lower layer 52, and the depletion layer reaches the interface between the nitride semiconductor lower layer 52 and the nitride semiconductor upper layer 54. Therefore, the current path from the drain electrode 66 to the source electrode 68 is cut off when no voltage is applied to the gate electrode 60. On the other hand, when a positive voltage is applied to the gate electrode 60, the extension of the depletion layer is contracted, and a two-dimensional electron gas layer can be generated at the interface between the nitride semiconductor lower layer 52 and the nitride semiconductor upper layer 54. That is, when the thickness of the nitride semiconductor lower layer 52 is formed to be 50 nm or less, the semiconductor device 3 operates as normally-off.

Next, a method for manufacturing the semiconductor device 3 will be described.
The steps up to the step of crystal growth of the p-type gallium nitride region 16 (from FIG. 7 to FIG. 9) are the same as the procedure shown in the manufacturing method of the first embodiment, and thus the description thereof is omitted.
After proceeding to the state of FIG. 9, a nitride semiconductor lower layer 52 containing an n-type impurity is epitaxially grown on the surface of the p-type gallium nitride region 16 as shown in FIG. As an n-type impurity, silicon is doped. Further, the nitride semiconductor upper layer 54 not containing impurities is epitaxially grown on the surface of the nitride semiconductor lower layer 52.
Next, as shown in FIG. 16, an insulating film 59 is formed on the surface of the nitride semiconductor upper layer 54. Next, the nitride semiconductor lower layer 52, the nitride semiconductor upper layer 54 and the insulating film 59 formed on the surface of the high dislocation density region 18 are removed, and the body electrode 20 is formed on the surface of the high dislocation density region 18. Next, the insulating film 59 corresponding to the drain electrode 66 and the source electrode 68 is removed, and the drain electrode 66 and the source electrode 68 are formed. Finally, a gate electrode 60 mainly composed of nickel (Ni), aluminum (Al), polycrystalline silicon (Poly-Si) or the like is formed on the surface of the insulating film 59 between the drain electrode 66 and the source electrode 68. . Through these steps, the semiconductor device 3 shown in FIG. 3 can be formed.

(Fourth embodiment)
FIG. 4 schematically shows a cross-sectional view of another semiconductor device 4 having a horizontal HEMT structure as a switching structure. The structure of the semiconductor device 4 is different from that of the semiconductor device 3 in that the lattice mismatch layer 14 is formed in a part of the p-type gallium nitride region 16.

  Since the operation of the semiconductor device 4 and the discharge of holes are the same as in the third embodiment, the description thereof is omitted. In the semiconductor device 3 and the semiconductor device 4, as in the structures of the semiconductor device 1 and the semiconductor device 2, the base layer 12 that does not contain an impurity serves as a buffer layer. Therefore, when the lattice mismatch layer 14 is formed in the p-type gallium nitride region 16 as in the semiconductor device 4, the p-type gallium nitride region 16 between the lattice mismatch layer 14 and the underlying layer 12 has few dislocations. There is a region, and the lattice mismatching layer 14 and the underlayer 12 are electrically insulated by the region having few dislocations. As a result, according to the form of the semiconductor device 4, the leakage current is suppressed.

  The manufacturing method of the semiconductor device 4 is the same as the procedure shown in the manufacturing method of Example 2 until the step of crystal growth of the p-type gallium nitride region 16 (FIGS. 11 to 13) is omitted. . Thereafter, the semiconductor device 4 shown in FIG. 4 can be formed through the same procedure as that shown in the manufacturing method of Example 3 (FIGS. 17 and 18).

(5th Example)
FIG. 5 schematically shows a cross-sectional view of a semiconductor device 5 provided with a HEMT structure capable of causing a current to flow in the vertical direction as a switching structure. The semiconductor device 5 is a modification of the semiconductor device 3 of the third embodiment. The following description will focus on the differences from the semiconductor device 3 of the third embodiment.
The substrate 70 and the base layer 12 of the semiconductor device 5 are characterized by containing n-type impurities. Further, when viewed in plan, the semiconductor device 5 penetrates from the front surface to the back surface of the p-type nitride semiconductor region 19 in a range where the lattice mismatching layer 14 does not exist, and is in contact with the base layer 12, so that the n-type impurity The n-type nitride semiconductor region 12a of gallium nitride containing is included. Thereby, the foundation layer 12 and the nitride semiconductor lower layer 52 are electrically connected via the n-type nitride semiconductor region 12a. The semiconductor device 5 is formed on the back surface of the base layer 12 and includes a semiconductor substrate 70 of gallium nitride containing n-type impurities. The semiconductor substrate 70 can also be evaluated as a part of the base layer 12. Silicon is used for n-type impurities in the n-type nitride semiconductor region 12 a, the underlayer 12, and the semiconductor substrate 70. The semiconductor device 5 further includes a drain electrode 86 formed on the back surface of the semiconductor substrate 70. Unlike the semiconductor device 3 of the third embodiment, the drain electrode 86 is disposed on the back surface side.

  The source electrode 68 is formed on a part of the surface of the nitride semiconductor upper layer 54 in a range where the n-type nitride semiconductor region 12a does not exist when seen in a plan view. The source electrode 68 is opposed to the nitride semiconductor 52 through the nitride semiconductor upper layer 54. The gate electrode 60 faces the nitride semiconductor upper layer 54 and the nitride semiconductor lower layer 52 with the gate insulating film 59 interposed therebetween. The gate electrode 60 is formed on the surface of the nitride semiconductor upper layer 54 that separates at least the source electrode 68 and the n-type nitride semiconductor region 12a. Also in this case, the gate insulating film 59 can be omitted. Even if the gate insulating film 59 is omitted, the gate electrode 60 and the nitride semiconductor upper layer 54 are not in ohmic contact. The gate electrode 60 is formed on the surface of the low dislocation density region 19, has a high contact resistance, and has a Schottky characteristic.

Next, the operation of the semiconductor device 5 will be described. A two-dimensional electron gas layer 53 is formed in the vicinity of the interface between the nitride semiconductor lower layer 52 and the nitride semiconductor upper layer 54. For this reason, in a state where no voltage is applied to the gate electrode 60, a large amount of electrons are induced in the two-dimensional electron gas layer 53. These electrons move vertically in the nitride semiconductor lower layer 52, the n-type semiconductor region 12 a, the n-type underlayer 12, and the n-type semiconductor substrate 70 and reach the drain electrode 86. In the semiconductor device 5, since a current path is formed between the source electrode 68 and the drain electrode 86 in a state where no voltage is applied to the gate electrode 60, the semiconductor device 5 operates as normally-on.
When a negative voltage is applied to the gate electrode 60, a depletion layer is formed at a part of the junction surface between the nitride semiconductor lower layer 52 and the nitride semiconductor upper layer 54, and the junction surface between the nitride semiconductor lower layer 52 and the nitride semiconductor upper layer 54 is formed. A state is formed in which some electrons cannot exist. In the semiconductor device 5, since the gate electrode 60 is disposed in a range separating the source electrode 68 and the n-type nitride semiconductor region 12 a when viewed in plan, the nitride semiconductor lower layer 52 immediately below the gate electrode 60. Thus, a state in which electrons cannot exist is formed on the bonding surface of the nitride semiconductor upper layer 54. As a result, the movement of electrons is blocked between the source electrode 68 and the n-type semiconductor region 12 a, so that no current can flow between the source electrode 68 and the drain electrode 86. The semiconductor device 5 can switch the conduction state and the non-conduction state with time by switching the voltage applied to the gate electrode 60.

  When a high voltage is applied between the drain electrode 86 and the source electrode 68, holes are generated by an avalanche phenomenon. The generated holes move to the p-type gallium nitride region 16 and are smoothly discharged to the body electrode 20 formed in the high dislocation density region 18 and having a low contact resistance.

Note that the semiconductor device 5 can also be operated as normally-off. When operating as normally-off, the nitride semiconductor lower layer 52 is preferably formed to a thickness of 50 nm or less. When the thickness of the nitride semiconductor lower layer 52 is 50 nm or less, the nitride semiconductor is formed from the junction surface between the p-type nitride semiconductor region 12 and the nitride semiconductor lower layer 52 in a state where no voltage is applied to the gate electrode 60. The depletion layer extends toward the lower layer 52, and the depletion layer reaches the interface between the nitride semiconductor lower layer 52 and the nitride semiconductor upper layer 54. Therefore, the current path from the drain electrode 86 to the source electrode 68 is cut off when no voltage is applied to the gate electrode 60. On the other hand, when a positive voltage is applied to the gate electrode 60, the extension of the depletion layer is contracted, and a two-dimensional electron gas layer can be generated at the interface between the nitride semiconductor lower layer 52 and the nitride semiconductor upper layer 54. That is, if the thickness of the nitride semiconductor lower layer 52 is 50 nm or less, the semiconductor device 5 can be operated as normally-off.
In the present embodiment, since the body electrode 20 is formed in the high dislocation density region 18, the contact resistance between the body electrode 20 and the p-type nitride semiconductor region 12 is low, and the potential of the p-type nitride semiconductor region 12 is stabilized. be able to. The operation of the semiconductor device 5 can be stabilized.

Next, a method for manufacturing the semiconductor device 5 will be described.
First, as shown in FIG. 19, a gallium nitride semiconductor substrate 70 containing silicon as an n-type impurity is prepared, and the underlayer 12 containing silicon as an n-type impurity is crystal-grown on the entire surface using MOCVD. . Thereafter, the procedure up to the step of forming the p-type gallium nitride region 16 is the same as the procedure shown in the semiconductor device manufacturing method of the first embodiment.
Next, as shown in FIG. 20, a trench penetrating the p-type gallium nitride 16 in the low dislocation density region 19 is formed using a dry etching technique.
Next, as shown in FIG. 21, an n-type nitride semiconductor is continuously epitaxially grown on the surfaces of the p-type gallium nitride region 16 and the foundation layer 12. As a result, a nitride semiconductor lower layer 52 is formed on the surfaces of the n-type nitride semiconductor 12a and the p-type gallium nitride region 16 in the trench. Silicon that is an n-type impurity is introduced into the n-type nitride semiconductor 12 a and the n-type nitride semiconductor lower layer 52.
Further, the nitride semiconductor upper layer 54 not containing impurities is epitaxially grown on the surface of the nitride semiconductor lower layer 52. The material of the nitride semiconductor upper layer 54 is aluminum gallium nitride (AlGaN). The nitride semiconductor upper layer 54 is not doped with impurities.
Next, as shown in FIG. 22, an insulating film 59 is formed on the surface of the nitride semiconductor upper layer 54. Thereafter, the nitride semiconductor lower layer 52, the nitride semiconductor upper layer 54 and the insulating film 59 formed on the surface of the high dislocation density region 18 are removed, and the body electrode 20 is formed on the surface of the high dislocation density region 18. Next, the insulating film 59 in a region corresponding to the pair of source electrodes 68 is removed, and a pair of source electrodes 68 is formed. Next, a gate electrode 60 mainly composed of nickel (Ni), aluminum (Al), polycrystalline silicon (Poly-Si), or the like is formed on the surface of the insulating film 59 that separates the pair of source electrodes 68. . Finally, the drain electrode 86 is formed on the entire back surface of the semiconductor substrate 70. Through these steps, the semiconductor device 5 shown in FIG. 5 can be formed.

(Sixth embodiment)
FIG. 6 schematically shows a cross-sectional view of another semiconductor device 6 provided with a HEMT structure capable of causing a current to flow in the vertical direction as a switching structure. The structure of the semiconductor device 6 is different from that of the semiconductor device 5 in that a lattice mismatch layer 14 is formed in a part of the p-type gallium nitride region 16.

Since the operation of the semiconductor device 6 and the discharge of holes are the same as in the third embodiment, the description thereof is omitted.
The p-type gallium nitride region 16 is electrically connected to the body electrode 20. Since the body electrode 20 and the source electrode 68 have the same potential, a high voltage is applied to the pn junction between the p-type gallium nitride region 16 and the base layer 12 as the drain-source voltage. For example, when the lattice mismatching layer 14 is provided on the lower surface of the p-type gallium nitride region 16 as in the semiconductor device 3, the dislocation is also present in the lattice mismatching layer 14 as described above. A high voltage is applied between the lattice mismatching layer 14 and the underlayer 12, causing an increase in leakage current and a deterioration in breakdown voltage. However, in the semiconductor device 6, the lattice mismatching layer 14 is formed in the p-type gallium nitride region 16 and is separated from the base layer 12. For this reason, since a good pn junction is formed between the p-type gallium nitride region 16 and the underlayer 12, an increase in leakage current and a breakdown voltage are suppressed.

About the manufacturing method of the semiconductor device 6, since it is the same as the procedure shown with the manufacturing method of Example 5 until the process of crystal-growing the underlayer 12, description is abbreviate | omitted. Next, as shown in FIG. 23, gallium nitride containing p-type impurities is grown from the surface of the underlayer 12 to about half the film thickness of the desired gallium nitride region 16. Thereby, the p-type gallium nitride region 16a is formed. Next, the lattice mismatch layer 14 of aluminum nitride is crystal-grown on the entire surface of the p-type gallium nitride region 16a using the MOCVD method. Next, the insulating film 13 is patterned on the surface of the lattice mismatching layer 14 to remove a part of the lattice mismatching layer 14, and then the insulating film 13 is removed. Since this process is the same as the procedure shown in the manufacturing method of Example 5, the description thereof is omitted.
After removing a part of the lattice mismatch layer 14, gallium nitride containing a p-type impurity from the surface of the lattice mismatch layer 14 and the p-type gallium nitride region 16 a is converted into a desired gallium nitride region 16 using the MOCVD method. The crystal is further grown to about half the film thickness. As a result, the lattice mismatch layer 14 is formed in the p-type gallium nitride region 16.
Thereafter, as shown in FIG. 24, a trench penetrating the p-type gallium nitride region 16 is formed. Since the process of forming the HEMT structure (FIGS. 25 and 26) is the same as the procedure shown in the manufacturing method of the fifth embodiment, the description thereof is omitted. Through these steps, the semiconductor device 6 shown in FIG. 6 can be formed.

  In the semiconductor devices according to the second embodiment, the fourth embodiment, and the sixth embodiment, the lattice mismatch layer is preferably formed at a position that is half the film thickness of the p-type nitride semiconductor region 16. This is because the balance between the carrier discharge effect and the pressure resistance effect is the best. Such a form can be easily realized by crystal growth of gallium nitride to half the desired film thickness of the gallium nitride region 16.

  The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

A cross-sectional view of an embodiment of a transistor is shown.
1 is a cross-sectional view of a semiconductor device 1. FIG. A cross-sectional view of the semiconductor device 2 is shown. A cross-sectional view of the semiconductor device 3 is shown. A cross-sectional view of the semiconductor device 4 is shown. A cross-sectional view of the semiconductor device 5 is shown. A cross-sectional view of the semiconductor device 6 is shown. A process of manufacturing the semiconductor device 1 will be described. A process of manufacturing the semiconductor device 1 will be described. A process of manufacturing the semiconductor device 1 will be described. A process of manufacturing the semiconductor device 1 will be described. A process of manufacturing the semiconductor device 2 will be described. A process of manufacturing the semiconductor device 2 will be described. A process of manufacturing the semiconductor device 2 will be described. A process of manufacturing the semiconductor device 2 will be described. A process of manufacturing the semiconductor device 3 will be described. A process of manufacturing the semiconductor device 3 will be described. A process of manufacturing the semiconductor device 4 will be described. A process of manufacturing the semiconductor device 4 will be described. A process of manufacturing the semiconductor device 5 will be described. A process of manufacturing the semiconductor device 5 will be described. A process of manufacturing the semiconductor device 5 will be described. A process of manufacturing the semiconductor device 5 will be described. A process of manufacturing the semiconductor device 6 will be described. A process of manufacturing the semiconductor device 6 will be described. A process of manufacturing the semiconductor device 6 will be described. A process of manufacturing the semiconductor device 6 will be described. A MOSFET 100 is shown as an example of a semiconductor device having a MOSFET structure.

Explanation of symbols

10, 110: Substrate 12: Semiconductor underlayer 13, 29, 59, 129: Insulating film 14: Lattice mismatch layer 16, 16a, 116: p-type nitride semiconductor region (p-type gallium nitride region)
18: High dislocation density region 19: Low dislocation density region 20, 120: Body electrode 22, 122: Drain region 24, 124: Source regions 26, 66, 86, 126: Drain electrodes 28, 68, 128: Source electrode 30, 60, 130: gate electrode 52: semiconductor lower layer 53: two-dimensional electron gas layer 54: semiconductor upper layer 70: semiconductor substrate

Claims (17)

A p-type nitride semiconductor region having a high dislocation density region and a low dislocation density region and containing a p-type impurity;
an electrode formed on at least a part of the surface of the high dislocation density region of the p-type nitride semiconductor region;
A semiconductor device comprising: Further comprising a lattice mismatch layer facing the electrode through a high dislocation density region;
2. The semiconductor device according to claim 1, wherein the lattice constants of the lattice mismatching layer and the p-type nitride semiconductor region are mismatched. The lattice mismatch layer is formed in a part of the p-type nitride semiconductor region,
3. The semiconductor device according to claim 2, wherein a high dislocation density region exists between the lattice mismatch layer and the electrode. A nitride semiconductor underlayer;
A lattice mismatching layer formed on a part of the surface of the underlayer;
A p-type nitride semiconductor region formed on the surface of the base layer and the lattice mismatch layer in a range extending from the base layer to the lattice mismatch layer;
An electrode formed on at least a part of the surface of the p-type nitride semiconductor region in a range where the lattice mismatching layer exists when seen in a plan view;
And a switching structure formed in a range where no lattice mismatching layer exists when seen in a plan view,
A semiconductor device characterized in that a difference in lattice constant between the base layer and the p-type nitride semiconductor region is smaller than a difference in lattice constant between the lattice mismatching layer and the p-type nitride semiconductor region. A nitride semiconductor underlayer;
A p-type nitride semiconductor region formed on the surface of the underlayer and containing p-type impurities;
a lattice mismatching layer formed in a part of the p-type nitride semiconductor region;
An electrode formed on at least a part of the surface of the p-type nitride semiconductor region in a range where the lattice mismatching layer exists when seen in a plan view;
And a switching structure formed in a range where no lattice mismatching layer exists when seen in a plan view,
A semiconductor device characterized in that a difference in lattice constant between the base layer and the p-type nitride semiconductor region is smaller than a difference in lattice constant between the lattice mismatching layer and the p-type nitride semiconductor region. The switching structure is
A drain region containing an n-type impurity and formed on a part of the surface of the p-type nitride semiconductor region in a range where the lattice mismatching layer does not exist when seen in a plan view;
It is formed on a part of the surface of the p-type nitride semiconductor region in a range where the lattice mismatching layer does not exist when seen in a plan view, is separated from the drain region by the p-type nitride semiconductor region, and is n-type A source region containing impurities;
6. The semiconductor device according to claim 4, further comprising a gate electrode facing the p-type nitride semiconductor region separating the drain region and the source region via a gate insulating film. The switching structure is
A nitride semiconductor lower layer formed on the surface of the p-type nitride semiconductor region in a range where the lattice mismatching layer does not exist when seen in a plan view;
A nitride semiconductor upper layer formed on the surface of the nitride semiconductor lower layer;
A drain electrode formed on a part of the surface of the nitride semiconductor upper layer;
A source electrode formed on another part of the surface of the nitride semiconductor upper layer;
A gate electrode formed on at least a part of the surface of the nitride semiconductor upper layer separating the drain electrode and the source electrode;
6. The semiconductor device according to claim 4, wherein the band gap width of the nitride semiconductor lower layer is smaller than the band gap width of the nitride semiconductor upper layer. The switching structure is
An n-type nitride semiconductor region containing an n-type impurity and penetrating from the front surface to the back surface of the p-type nitride semiconductor region in a range in which no lattice mismatching layer exists when viewed in plan,
A nitride semiconductor lower layer formed on the surface of the p-type nitride semiconductor region and the n-type nitride semiconductor region in a range where the lattice mismatching layer does not exist when viewed in plan,
A nitride semiconductor upper layer formed on the surface of the nitride semiconductor lower layer;
A source electrode formed on a part of the surface of the upper layer of the nitride semiconductor in a range where the n-type nitride semiconductor region does not exist when seen in a plan view;
A gate electrode formed on at least a part of the surface of the upper layer of the nitride semiconductor that separates the source electrode and the n-type nitride semiconductor region when viewed in plan,
It has a drain electrode that is electrically connected to the back surface of the underlayer,
6. The semiconductor device according to claim 4, wherein the band gap width of the nitride semiconductor lower layer is smaller than the band gap width of the nitride semiconductor upper layer.   9. The semiconductor device according to claim 4, wherein the same type of semiconductor is used for the underlayer and the p-type nitride semiconductor region. Gallium nitride is used for the underlayer and the p-type nitride semiconductor region,
Aluminum nitride is used for the lattice mismatch layer,
The semiconductor device according to claim 9. A method for manufacturing a semiconductor device, comprising:
Forming a lattice mismatch layer on a portion of the surface of the underlying layer of the nitride semiconductor;
A step of crystal-growing a p-type nitride semiconductor region on the surface of the base layer and the lattice mismatch layer in a range extending from the base layer to the lattice mismatch layer;
Forming an electrode on at least a part of the surface of the p-type nitride semiconductor region in a range where the lattice mismatching layer exists when seen in a plan view;
And a step of forming a switching structure in a range where the lattice mismatching layer does not exist when seen in a plan view,
A manufacturing method characterized in that a difference in lattice constant between the underlayer and the p-type nitride semiconductor region is smaller than a difference in lattice constant between the lattice mismatching layer and the p-type nitride semiconductor region. A method for manufacturing a semiconductor device, comprising:
A step of crystal-growing a p-type nitride semiconductor region on the surface of the underlayer;
forming a lattice mismatch layer on a part of the surface of the p-type nitride semiconductor region;
a step of crystal-growing a p-type nitride semiconductor region on the surface of the p-type nitride semiconductor region in a range extending from the surface of the p-type nitride semiconductor region to the lattice mismatch layer and a surface of the lattice mismatch layer;
Forming an electrode on at least a part of the surface of the p-type nitride semiconductor region in a range where the lattice mismatching layer exists when seen in a plan view;
And a step of forming a switching structure in a range where the lattice mismatching layer does not exist when seen in a plan view,
A manufacturing method characterized in that a difference in lattice constant between the underlayer and the p-type nitride semiconductor region is smaller than a difference in lattice constant between the lattice mismatching layer and the p-type nitride semiconductor region. Forming the switching structure comprises:
Forming a drain region containing an n-type impurity in a part of the surface of the p-type nitride semiconductor region in a range where the lattice mismatching layer does not exist when seen in a plan view;
An n-type impurity is introduced into a part of the surface of the p-type nitride semiconductor region in a range where the lattice mismatch layer does not exist when seen in a plan view and separated from the drain region by the p-type nitride semiconductor region. A step of forming a source region including a step of forming a gate electrode facing the p-type nitride semiconductor region separating the drain region and the source region through a gate insulating film;
The manufacturing method of Claim 11 or 12 characterized by the above-mentioned. Forming the switching structure comprises:
Forming a nitride semiconductor lower layer on the surface of the p-type nitride semiconductor region in a range where the lattice mismatching layer does not exist when seen in a plan view;
Forming a nitride semiconductor upper layer on the surface of the semiconductor lower layer;
Forming a drain electrode on a portion of the surface of the nitride semiconductor upper layer;
Forming a source electrode on another part of the surface of the nitride semiconductor upper layer;
Forming a gate electrode on at least a portion of the surface of the semiconductor upper layer separating the drain electrode and the source electrode;
The manufacturing method of Claim 11 or 12 characterized by the above-mentioned. The step of forming the switching function structure is as follows:
An n-type nitride semiconductor region containing an n-type impurity is formed while penetrating from the front surface to the back surface of the p-type nitride semiconductor region in a range where no lattice mismatching layer exists when viewed in plan. And a process of
Forming a nitride semiconductor lower layer on the surface of the p-type nitride semiconductor region and the n-type nitride semiconductor region in a range where the lattice mismatching layer does not exist when seen in a plan view;
Forming a nitride semiconductor upper layer on the surface of the nitride semiconductor lower layer;
Forming a source electrode on a part of the surface of the nitride semiconductor upper layer in a range where the n-type semiconductor region does not exist when viewed in plan;
Forming a gate electrode on at least a part of the surface of the semiconductor upper layer separating the source electrode and the n-type semiconductor region when viewed in plan;
The manufacturing method of Claim 11 or 12 characterized by the above-mentioned.   16. The manufacturing method according to claim 11, wherein the same type of semiconductor is used for the underlayer and the p-type nitride semiconductor region. Gallium nitride is used for the underlayer and the p-type nitride semiconductor region,
Aluminum nitride is used for the lattice mismatch layer,
The manufacturing method according to claim 16.

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