JP2008227432A - Nitride compound semiconductor element and its production process - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a highly efficient nitride compound semiconductor element and its manufacturing method, which prevents impairment of breakdown voltage caused by thinning of oxide film or insulating film, and a deterioration of DC gain gm caused by excess of thickness. <P>SOLUTION: In a selective growth method, n+ contact regions 8 and 9 in ohmic contact with a source electrode and a drain electrode, respectively, and an n- region 10 called a reduced surface field layer (reduced surface field region) aiming at relaxation of electric field concentration, are respectively formed. After the formation of the n+ contact regions 8 and 9 and the n- region 10 in the selective growth method, protruded portions 8a, 9a, and 10a produced by the selective growth, respectively, in the n+ contact regions 8 and 9 and the n- region 10, are flattened by chemimechanical polishing (CMP) method. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a nitride compound semiconductor device using a nitride compound semiconductor such as a group III-V nitride compound semiconductor and a method for manufacturing the same.

  Wide bandgap semiconductors represented by III-V nitrides have high dielectric breakdown voltage, good electron transport properties, and good thermal conductivity, and are very attractive as high-temperature and high-power devices. Among various group III-V nitrides, AlGaN / GaN heterostructures have attracted much attention due to the two-dimensional electron gas with high electron mobility and carrier density due to the piezoelectric effect. Heterojunction FETs (HFETs) using AlGaN / GaN heterostructures have low on-resistance, fast switching speed, and high temperature operation. These features are very suitable for power switching applications. However, a normal AlGaN / GaN HFET has a normally-on operation in which a current flows when the gate is not biased and the current is cut off by applying a negative potential to the gate. In power switching applications, a normally-off operation is preferred in which no current flows when a gate bias is not applied and a current flows when a positive potential is applied to the gate in order to ensure safety when the device is broken.

In order to realize normally-off operation, it is necessary to introduce a MOSFET structure. FIG. 5 shows a schematic diagram of a conventional MOSFET. In this MOSFET, n ⁺ contact regions (n ⁺ regions) 108 and 109 are formed in the p-GaN layer 103 by ion implantation in order to make ohmic contact between the source and drain regions. In order to improve the breakdown voltage, an n ⁻ region (resurf region) 110 called a RESURF layer is formed between the gate and drain by ion implantation. Thereafter, an insulating film 106 such as SiO 2 is formed on the p-GaN layer 103, and a gate electrode 107 is formed on the insulating film 106. Polysilicon is generally used as the gate electrode 107. Next, the source electrode 104 and the drain electrode 105 are formed on the n ⁺ contact regions 108 and 109, respectively.

  In the MOSFET, it is important to keep the interface state of the oxide film / semiconductor interface low in order to improve the channel mobility. In a normal Si-based MOSFET, a thermal oxide film SiO2 of Si is used as an oxide film, and a very good interface is realized. In the case of a nitride semiconductor, since a good thermal oxide film cannot be obtained, it is common to attach an oxide film such as SiO 2 by the p-CVD method.

In many cases, ion implantation is used to form the n ⁺ contact regions 108 and 109 and the n ⁻ region 110 (see, for example, Non-Patent Document 1). In ion implantation, annealing is performed to recover crystal defects after the implantation and to activate implanted impurities. In the case of GaN, since the crystals are strong, activation was insufficient even when annealing was performed at a high temperature of 1000 ° C. or higher. There is a report that GaN on sapphire substrate has a high activation rate by high-temperature annealing at 1400 ° C, but GaN on Si substrate has a high activation rate because the substrate Si melts at 1200 ° C or higher. It was difficult to get.

One method for avoiding this is an n-layer formation technique by selective growth.
IEEE TRANCEACTIONS ON ELECTRON DEVICE.Vol 52, No.1 2005, pp.6-10

When the n ⁺ contact regions 108 and 109 and the n ⁻ region 110 are formed by ion implantation, activation annealing at 1200 ° C. or higher is required, and pits are generated on the epi surface during annealing, thereby degrading mobility. In order to avoid this, there is a method of selectively growing n layers. A MOSFET fabricated using this technique is shown in FIG. In this method, convex portions 108a, 109a, and 110a are formed at the edge portions of the contact regions 108 and 109 and the n ⁻ region 110 due to the migration of the raw material in the lateral direction during selective growth. When the insulating film 106 is formed on the contact regions 108 and 109 and the n ⁻ region 110 having such convex portions, the insulating film 106 is partially thinned at the convex portions 108a, 109a, and 110a, so that the withstand voltage is reduced. Causes deterioration. If the gate oxide film 106 is deposited so that the insulating film 106 is sufficiently thick at the convex portions 108a, 109a, and 110a, the insulating film 106 becomes thicker than designed, and the DC gain gm is reduced.

  The present invention has been made in view of such conventional problems, and its purpose is that the breakdown voltage deteriorates due to partial thinning of the oxide film or insulating film, and that the thickness becomes excessive. It is an object of the present invention to provide a high performance nitride compound semiconductor device capable of preventing a decrease in direct current gain gm due to, and a method for manufacturing the same.

  In order to solve the above-described problem, a method of manufacturing a nitride compound semiconductor device according to the first aspect of the present invention includes a method of manufacturing a nitride compound semiconductor device using a nitride compound semiconductor as an epitaxial layer material. A first contact region and a second contact region that are in ohmic contact with the source electrode and the drain electrode, respectively, are formed on the epitaxial layer by a selective growth method, and after the formation of the first and second contact regions by the selective growth method, The convex portions respectively formed in the first and second contact regions by the selective growth are planarized by a chemical mechanical polishing method.

  According to this aspect, since the first contact region and the second contact region are formed in the epitaxial layer by the selective growth method, the implanted impurities are activated as in the case where these regions are formed by ion implantation. High temperature annealing is not required. In addition, since the convex portions respectively generated in the first and second contact regions by the selective growth are planarized by the chemical mechanical polishing method, the oxide film or the insulating film is partially formed by performing a normal semiconductor element manufacturing process thereafter. Therefore, it is possible to prevent the breakdown voltage from deteriorating due to the thinning and the direct current gain gm from decreasing due to excessive thickness. Thereby, a high performance nitride compound semiconductor device can be realized.

The “Chemical Mechanical Polishing (CMP) method” here refers to the surface chemical action of the abrasive (abrasive grain) itself or the action of chemical components contained in the polishing liquid.
1174007585953_0
And a mechanical polishing (surface removal) effect by the relative movement of the polishing object and a high-speed and smooth polishing surface.

  The method for manufacturing a nitride compound semiconductor device according to the second aspect of the present invention is a method for manufacturing a nitride compound semiconductor device using a nitride compound semiconductor as a material for the epitaxial layer. A third region for the purpose of selective growth is formed by a selective growth method, and after the formation of the third region by the selective growth method, a convex portion generated in the third region by the selective growth is planarized by a chemical mechanical polishing method. It is characterized by.

  According to this aspect, since the third region for reducing the electric field concentration is formed in the epitaxial layer by the selective growth method, the implanted impurity is activated as in the case of forming this region by ion implantation. High temperature annealing is not required. Further, since the convex portion generated in the third region by the selective growth is planarized by the chemical mechanical polishing method, the oxide film or the insulating film is partially thinned by performing a normal semiconductor element manufacturing process thereafter. It is possible to prevent the deterioration of the withstand voltage and the decrease in the direct current gain gm due to the excessive thickness. Thereby, a high performance nitride compound semiconductor device can be realized.

  In the method of manufacturing a nitride compound semiconductor device according to another aspect of the present invention, a third region for the purpose of relaxing electric field concentration is formed in the epitaxial layer by a selective growth method, and the third method by the selective growth method. After the formation of the region, the convex portion generated in the third region by selective growth is planarized by a chemical mechanical polishing method.

  According to this aspect, since the convex portions respectively generated in the first, second and third regions by the selective growth are planarized by the chemical mechanical polishing method, the oxide film can be obtained by performing a normal semiconductor element manufacturing process thereafter. Alternatively, it is possible to prevent the breakdown voltage from deteriorating due to partial thinning of the insulating film and the decrease in DC gain gm due to excessive thickness. Thereby, a high performance nitride compound semiconductor device can be realized.

  In the method for manufacturing a nitride compound semiconductor device according to another aspect of the present invention, the epitaxial layer is formed using a III-V nitride compound semiconductor such as GaN as the nitride compound semiconductor, and the chemical mechanical polishing is performed. After planarization by a method, a gate oxide film is formed between the source electrode and the drain electrode on the surface of the epitaxial layer, and a gate electrode is formed on the gate oxide film to produce a MOS field effect transistor. Features.

  According to this aspect, it is possible to prevent deterioration in breakdown voltage due to partial thinning of the gate oxide film and reduction in DC gain gm due to excessive thickness, and high performance III-V group nitriding A MOS field effect transistor using a physical compound semiconductor can be realized.

  In the method for manufacturing a nitride compound semiconductor device according to another aspect of the present invention, the epitaxial layer is formed using a III-V nitride compound semiconductor such as GaN as the nitride compound semiconductor, and the chemical mechanical polishing is performed. A heterojunction field effect transistor is manufactured after planarization by a method.

  According to this aspect, a high-performance III-V nitride compound semiconductor that can reduce the contact resistance due to the n + contact layer without incurring an increase in leakage current due to a convex portion having insufficient crystallinity is used. The heterojunction field effect transistor can be realized.

  A nitride compound semiconductor device according to a third aspect of the present invention is a nitride compound semiconductor device using a nitride compound semiconductor as an epitaxial layer material, and is formed on the epitaxial layer by a selective growth method. A first contact region and a second contact region that are in ohmic contact with the drain electrode, respectively, are provided, and the first and second contact regions are flattened by a chemical mechanical polishing method on a convex portion generated by selective growth. It is characterized by that. According to this aspect, it is possible to realize a high-performance nitride compound semiconductor element that suppresses deterioration of breakdown voltage and reduction in DC gain gm.

  A nitride compound semiconductor device according to another aspect of the present invention is a nitride compound semiconductor device using a nitride compound semiconductor as an epitaxial layer material, which reduces electric field concentration formed in the epitaxial layer by a selective growth method. The target third region is provided, and the third region is characterized in that a convex portion generated by selective growth is planarized by a chemical mechanical polishing method. According to this aspect, it is possible to realize a high-performance nitride compound semiconductor element that suppresses deterioration of breakdown voltage and reduction in DC gain gm.

  A nitride compound semiconductor device according to another aspect of the present invention includes a third region for reducing electric field concentration formed in the epitaxial layer by a selective growth method, and the third region is selectively grown. The convex portions generated by the above are flattened by a chemical mechanical polishing method. According to this aspect, it is possible to realize a high-performance nitride compound semiconductor element that suppresses deterioration of breakdown voltage and reduction in DC gain gm.

  A nitride compound semiconductor device according to another aspect of the present invention is configured as a MOS field effect transistor using a III-V nitride compound semiconductor such as GaN as the nitride compound semiconductor. According to this aspect, it is possible to realize a high-performance MOS type field effect transistor that suppresses deterioration of breakdown voltage and reduction of DC gain gm.

  A nitride compound semiconductor device according to another aspect of the present invention is configured as a heterojunction field effect transistor using a III-V nitride compound semiconductor such as GaN as the nitride compound semiconductor. . According to this aspect, it is possible to realize a high-performance heterojunction field effect transistor that can reduce the contact resistance due to the n + contact layer without incurring an increase in leakage current due to a convex portion having insufficient crystallinity. it can.

  According to the present invention, it is possible to prevent deterioration in breakdown voltage due to partial thinning of an oxide film or insulating film and reduction in DC gain gm due to excessive thickness, and a high performance nitride compound A semiconductor element can be realized.

Embodiments embodying the present invention will be described with reference to the drawings. In the description of each embodiment, the same parts are denoted by the same reference numerals, and redundant description is omitted.
(First embodiment)
FIG. 1 shows a schematic configuration of a MOS field effect transistor 1 as a nitride compound semiconductor device according to the first embodiment.

  This MOS field effect transistor (hereinafter referred to as MOSFET) 1 uses GaN (III-V nitride compound semiconductor) as a material of the epitaxial layer 3 as a nitride compound semiconductor.

  The MOSFET 1 is formed by a selective growth method using a substrate 2 such as sapphire or Si, a buffer layer (not shown) formed on the substrate 2, an epitaxial layer 3 made of GaN grown on the buffer layer, and the like. And an impurity layer under an ohmic electrode.

This MOSFET 1 has a source n ⁺ contact region (first contact region: n ⁺ region) 8 for making an ohmic contact with the source region as an impurity layer under the ohmic electrode and an ohmic contact with the drain region. For this purpose, a drain n ⁺ contact region (second contact region: n ⁺ region) 9 is provided. The n ⁺ contact region 8 is formed in a region below the source electrode 4 on the surface of the epitaxial layer 3, and the n ⁺ contact region 9 is formed in a region below the drain electrode 5 on the surface of the epitaxial layer 3.

MOSFET 1 includes an n ⁻ region (third region) 10 called a RESURF layer for the purpose of relaxing electric field concentration in a region between gate electrode 7 and drain electrode 5 on the surface of epitaxial layer 3. .

Further, in MOSFET 1, n ⁺ source electrode 4 on the contact region 8, the drain electrode 5 are formed on the n ⁺ contact region 9. In the region between the source electrode 4 and the drain electrode 5 on the surface of the epitaxial layer 3, a gate oxide film 6 made of an oxide film such as SiO2 is formed by a p-CVD method or the like. A gate electrode 7 is formed on the gate oxide film 6.

The epitaxial layer 3 is a p-GaN layer obtained by epitaxially growing, for example, GaN doped with a predetermined amount of Mg on the substrate 2 such as sapphire or Si by MOCVD. Further, each of the n ⁺ contact region 8 and the n ⁺ contact region 9 is an n ⁺ -GaN layer formed by growing GaN added with Si or the like to a desired concentration by MOCVD.

The n ⁻ region 10 is formed by growing a GaN to which Si or the like is added to a desired concentration lower than that of the n ⁺ contact regions 8 and 9 by MOCVD.

  The characteristic of MOSFET 1 having such a configuration is as follows.

An n ⁺ contact region 8 and an n ⁺ contact region 9 that are in ohmic contact with the source electrode 4 and the drain electrode 5, respectively, are formed by a selective growth method.

After the n ⁺ contact region 8 and the n ⁺ contact region 9 are formed by the selective growth method, the convex portions generated in the n ⁺ contact regions 8 and 9 by the selective growth are flattened by the chemical mechanical polishing (CMP) method.

  A method of manufacturing MOSFET 1 having the above configuration will be described with reference to FIGS. 2 (A) to (D) and FIGS. 3 (A) and 3 (B). 2A to 2D and FIGS. 3A and 3B show a series of manufacturing steps.

  (Step 1) First, as shown in FIG. 2A, a buffer layer (not shown) is formed on the substrate 2, and an epitaxial layer (p-GaN layer) 3 is epitaxially grown on the entire buffer layer. .

  (Step 2) Next, a dielectric film 21 such as SiO 2 is deposited on the entire surface of the epitaxial layer 3 (see FIG. 2B).

  (Step 3) Next, a resist is applied on the dielectric film 21.

(Step 4) Next, the resist is patterned by photolithography so that the region where the n ⁺ contact regions 8 and 9 are to be formed becomes an opening, thereby forming a resist pattern.

  (Step 5) Next, the dielectric film 21 such as SiO2 is opened by etching using the patterned resist as a mask.

  (Step 6) Next, the resist is removed, and then the epitaxial layer 3 is etched using the dielectric film 21 such as SiO2 as a mask. By this etching, recesses 22 and 23 are formed in the epitaxial layer 3 (see FIG. 2B).

  (Step 7) Next, GaN is epitaxially grown in the recesses 22 and 23 of the etched epitaxial layer 3 under appropriate growth conditions.

As a result, GaN does not grow on the dielectric film 21 such as SiO 2, and the n ⁺ contact regions 8 and 9 can be grown only in the recesses 22 and 23 of the epitaxial layer 3 (see FIG. 2C). . In this way, n ⁺ contact regions 8 and 9 are formed in the recesses 22 and 23 of the epitaxial layer 3 by a selective growth method. At the time of this selective growth, convex portions 8a and 9a are formed at the edge portions of the n ⁺ contact regions 8 and 9 due to the lateral migration of the raw materials (see FIG. 2C).

(Step 8) Next, a resist is applied on the dielectric film 21 shown in FIG. 2C, and the resist is patterned by photolithography so that the region where the n ⁻ region 10 is formed becomes an opening. Then, a resist pattern is formed.

  (Step 9) Next, the dielectric film 21 is opened by etching using the patterned resist as a mask.

  (Step 10) Next, the resist is removed, and then the epitaxial layer 3 is etched using the dielectric film 21 as a mask. By this etching, a recess 26 is formed in the epitaxial layer 3 (see FIG. 2D).

(Step 11) Next, GaN is epitaxially grown in the recesses 26 of the etched epitaxial layer 3 under appropriate growth conditions. Thereby, the n ⁻ region 10 can be grown only in the concave portion 26 (see FIG. 2D). In this way, the n ⁻ region 10 is formed in the recess 26 of the epitaxial layer 3 by the selective growth method. During this selective growth, convex portions 10a are also formed at the edge portion of the n ⁻ region 10 due to the migration of the raw material in the lateral direction (see FIG. 2D). Thereafter, the dielectric film 21 remaining on the epitaxial layer 3 is removed.

(Step 12) Next, the convex portions 8a, 9a and 10a generated in the n ⁺ contact regions 8 and 9 and the n ⁻ region 10 by selective growth are planarized by a chemical mechanical polishing method (see FIG. 3A). ).

  (Step 13) Next, a gate oxide film (insulating film) 6 made of an oxide film such as SiO 2 is formed on the planarized epitaxial layer 3 by a p-CVD method or the like (see FIG. 3B).

(Step 14) Next, regions on the n ⁺ contact regions 8 and 9 of the gate oxide film 6 are opened.

(Step 15) A source electrode 4 and a drain electrode 5 are formed on the n ⁺ contact region 8 and the n ⁺ contact region 9 exposed through the opening, respectively (see FIG. 3B). As the source electrode 4 and the drain electrode 5, metals that form ohmic contact with the n ⁺ contact regions 8 and 9 such as Ti / Al and Ti / AlSi / Mo, respectively, are used.

  (Step 16) Next, a gate electrode 7 is formed on the gate oxide film 6 (see FIG. 3B). Polysilicon is used as the gate electrode 7. As the gate electrode 7, a metal electrode such as Ni / Au or WSi may be used.

  (Step 17) Thereafter, if necessary, an interlayer insulating film, wiring, and a surface passivation layer are formed to complete the MOSFET 1 (see FIG. 3B).

  According to 1st Embodiment comprised as mentioned above, there exist the following effects.

In the epitaxial layer 3, the n ⁺ contact region 8, the n ⁺ contact region 9, and the n ⁻ region 10 called a RESURF layer are formed by the selective growth method, respectively, so that these regions are formed by ion implantation. High-temperature annealing for activating the implanted impurities is not necessary.

O The convex portions 8a, 9a and 10a (see FIG. 2D) generated in the n ⁺ contact region 8, the n ⁺ contact region 9 and the n ⁻ region 10 by the selective growth are subjected to chemical mechanical polishing in the above (step 12). Flatten by the method. For this reason, after the planarization, by performing a normal semiconductor element manufacturing process as in the above (Step 13) to (Step 17), the gate oxide film 6 is partially reduced in thickness, It is possible to prevent a decrease in DC gain gm due to an excessive thickness. Thereby, a high-performance MOSFET 1 can be realized.
(Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to FIG.

  In the first embodiment, an example in which the present invention is applied to a MOSFET has been described. In the second embodiment, the present invention is applied to a heterojunction field effect transistor 30 using an AlGaN / GaN heterostructure. Will be described.

  As shown in FIG. 4, a heterojunction field effect transistor (hereinafter referred to as HFET) 30 as a nitride compound semiconductor device according to the second embodiment is formed on an undoped GaN (Sapphire, Si, etc.) substrate 31. It has a structure in which an electron transit layer 32 made of i-GaN) and an electron supply layer 33 made of undoped AlGaN (i-AlGaN) are sequentially stacked. As the substrate 31, a SiC substrate, a Si substrate, or the like may be used.

This HFET30 includes a n ⁺ contact regions (first contact region) 38 for the source for taking an ohmic contact of the source region, n ⁺ contact region for a drain for ohmic contact of the drain region (second Contact region) 39. The n ⁺ contact region 38 is formed in a region below the source electrode 34 on the surface of the electron supply layer 33 made of i-AlGaN, and the n ⁺ contact region 39 is formed in a region below the drain electrode 35 on the surface of the electron supply layer 33. Yes.

In the HFET 30, the source electrode 34 is formed on the n ⁺ contact region 38, and the drain electrode 35 is formed on the n ⁺ contact region 39. A gate electrode 36 is formed in a region between the source electrode 34 and the drain electrode 35 on the surface of the electron supply layer 33. A passivation film (insulating film) 37 is formed in a region between the source electrode 34 and the gate electrode 36 and a region between the gate electrode 36 and the drain electrode 35 on the surface of the electron supply layer 33.

  The characteristics of the HFET 30 having such a configuration are as follows.

An n ⁺ contact region 38 and an n ⁺ contact region 39 that are in ohmic contact with the source electrode 34 and the drain electrode 35, respectively, are formed by a selective growth method.

After the formation of the n ⁺ contact region 38 and the n ⁺ contact region 39 by the selective growth method, the convex portions generated in the n ⁺ contact regions 38 and 39 by the selective growth are flattened by the chemical mechanical polishing (CMP) method.

  Next, a method for manufacturing the HFET 30 having the above configuration will be briefly described.

  First, an electron transit layer 32 made of i-GaN and an electron supply layer 33 made of i-AlGaN are sequentially formed on the substrate 31 by the MOCVD method.

Next, after isolation of the element region (element isolation) is performed by mesa etching, a dielectric film such as SiO2 is formed on the electron supply layer 33 so that the regions to be the n ⁺ contact regions 38 and 39 become openings. Pattern.

Next, the electron supply layer 33 is etched using this dielectric film as a mask, and the n ⁺ contact region 38 and the n ⁺ contact region 39 are selectively grown in the recesses of the electron supply layer 33 formed by etching by MOCVD or the like.

  Next, the electron supply layer 33 after the selective growth is polished and planarized by a chemical mechanical polishing (CMP) method.

  Next, a passivation film (insulating film) 37 is formed on the planarized electron supply layer 33.

Next, regions on the n ⁺ contact regions 38 and 39 of the passivation film 37 are opened, and ohmic electrodes such as Ti / Al (source electrodes 34 and 39) are formed on the n ⁺ contact regions 38 and 39 exposed by the openings. A drain electrode 35) is formed respectively.

  Next, the gate electrode 36 is formed on the electron supply layer 33 between the ohmic electrodes. If necessary, an interlayer insulating film, wiring, and a surface passivation layer are formed, and the HFET 30 is completed.

  According to 2nd Embodiment comprised as mentioned above, there exist the following effects similarly to the said 1st Embodiment.

In the electron supply layer 33 made of i-AlGaN, n ⁺ contact regions 38 and 39 are formed by selective growth, respectively, so that these impurities are activated as in the case of forming these regions by ion implantation. High temperature annealing is not required.

O The convex portions generated in the n ⁺ contact regions 38 and 39 by the selective growth are flattened by a chemical mechanical polishing method. For this reason, by performing a normal semiconductor element manufacturing process after the planarization, it is possible to reduce the contact resistance due to the n + contact layer without causing an increase in leakage current due to a convex portion having insufficient crystallinity. . Thereby, a high-performance HFET 30 can be realized.

In addition, this invention can also be changed and embodied as follows.
In each of the above embodiments, a nitride compound semiconductor element using a group III-V nitride compound semiconductor such as GaN or AlGaN as the nitride compound semiconductor has been described as an epitaxial layer material. The present invention is also applicable to a nitride compound semiconductor element using a nitride compound semiconductor. For example, the present invention can be applied to a heterojunction field effect transistor (HFET) using an AlGaAs / GaAs heterostructure.

  The present invention is also applicable to a MIS (Metal Insulator Semiconductor) type field effect transistor using a III-V nitride compound semiconductor.

1 is a cross-sectional view showing a schematic configuration of a MOSFET according to a first embodiment. (A) thru | or (D) is explanatory drawing which shows the manufacturing method of MOSFET. (A), (B) is explanatory drawing which shows the manufacturing method of MOSFET following FIG.2 (D). Sectional drawing which shows schematic structure of HFET concerning 2nd Embodiment. Sectional drawing which shows schematic structure of the conventional MOSFET which formed the n ^<+> layer by ion implantation. Explanatory drawing of the n ⁺ layer formation technique by the selective growth method.

Explanation of symbols

1 ... MOS field effect transistor (MOSFET)
DESCRIPTION OF SYMBOLS 2,31 ... Substrate 3 ... Epitaxial layer 4,34 ... Source electrode 5,35 ... Drain electrode 6 ... Gate oxide film 7, 36 ... Gate electrode 8, 9, 38, 39 ... n ⁺ contact region 10 ... n < ^- > region 8a , 9a, 10a ... convex part 30 ... heterojunction field effect transistor (HFET)
32 ... Electron traveling layer 33 ... Electron supply layer 37 ... Passivation film (insulating film)

Claims (10)

In a method for manufacturing a nitride compound semiconductor element using a nitride compound semiconductor as an epitaxial layer material,
Forming a first contact region and a second contact region in ohmic contact with the source electrode and the drain electrode, respectively, on the epitaxial layer by a selective growth method;
After the first and second contact regions are formed by the selective growth method, the convex portions respectively formed in the first and second contact regions by the selective growth are planarized by a chemical mechanical polishing method. A method for manufacturing a nitride compound semiconductor device. In a method for manufacturing a nitride compound semiconductor element using a nitride compound semiconductor as an epitaxial layer material,
Forming a third region in the epitaxial layer for reducing electric field concentration by a selective growth method;
A method for producing a nitride compound semiconductor device, comprising: forming a third region by selective growth, and then planarizing a convex portion generated in the third region by selective growth by chemical mechanical polishing. Forming a third region in the epitaxial layer for reducing electric field concentration by a selective growth method;
2. The nitride compound according to claim 1, wherein after the formation of the third region by the selective growth method, a convex portion generated in the third region by the selective growth is planarized by a chemical mechanical polishing method. A method for manufacturing a semiconductor device. The epitaxial layer is formed using a III-V nitride compound semiconductor such as GaN as the nitride compound semiconductor,
After planarization by the chemical mechanical polishing method, a gate oxide film is formed between the source electrode and the drain electrode on the surface of the epitaxial layer,
4. The method for manufacturing a nitride compound semiconductor device according to claim 1, wherein a MOS field effect transistor is manufactured by forming a gate electrode on the gate oxide film. The epitaxial layer is formed using a III-V nitride compound semiconductor such as GaN as the nitride compound semiconductor,
4. The method of manufacturing a nitride compound semiconductor device according to claim 1, wherein a heterojunction field effect transistor is manufactured after the planarization by the chemical mechanical polishing method. . In a nitride compound semiconductor device using a nitride compound semiconductor as an epitaxial layer material,
A first contact region and a second contact region respectively formed on the epitaxial layer by a selective growth method and in ohmic contact with the source electrode and the drain electrode, respectively;
In the nitride compound semiconductor device, the first and second contact regions have a convex portion formed by selective growth planarized by a chemical mechanical polishing method. In a nitride compound semiconductor device using a nitride compound semiconductor as an epitaxial layer material,
A third region for reducing the electric field concentration formed in the epitaxial layer by a selective growth method;
The nitride compound semiconductor device, wherein in the third region, a convex portion generated by selective growth is planarized by a chemical mechanical polishing method. A third region for reducing the electric field concentration formed in the epitaxial layer by a selective growth method;
The nitride compound semiconductor device according to claim 6, wherein in the third region, a convex portion generated by selective growth is flattened by a chemical mechanical polishing method.   The nitride compound according to any one of claims 6 to 8, wherein a III-V nitride compound semiconductor such as GaN is used as the nitride compound semiconductor, and is configured as a MOS field effect transistor. Semiconductor element.   The nitride according to any one of claims 6 to 9, wherein a III-V nitride compound semiconductor such as GaN is used as the nitride compound semiconductor, and is configured as a heterojunction field effect transistor. Compound semiconductor device.

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