JP4920519B2 - Nitride semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device using a nitride semiconductor and a manufacturing method thereof.

A semiconductor device using a nitride semiconductor is known. In a semiconductor device using a nitride semiconductor, a p-type nitride semiconductor region is generally formed by doping Mg, which is a p-type impurity.
A semiconductor structure may be formed by crystal growth of a nitride semiconductor containing no p-type impurities on the surface of a nitride semiconductor substrate containing p-type impurities. At that time, as shown in FIG. 10 attached to the present specification, the nitride semiconductor substrate containing the p-type impurity is heated to about 1050 ° C., and then the nitride semiconductor containing no p-type impurity is crystal-grown. In FIG. 10, the temperature T of the nitride semiconductor substrate containing the p-type impurity reaches 1050 ° C. at time s11. Thereafter, in a period L from time s12 to time s13, a gas containing a material constituting the nitride semiconductor that does not contain p-type impurities is supplied. Thereby, a crystal of a nitride semiconductor not containing the p-type impurity is grown from the surface of the nitride semiconductor substrate containing the p-type impurity. In general, hydrogen is used as the carrier gas.

A nitride semiconductor (particularly GaN) has a low activation rate relative to the amount of p-type impurity (particularly Mg) to be implanted. For this reason, when trying to obtain a p-type nitride semiconductor region, a large amount of energy is required to activate the implanted p-type impurity. In addition, it is necessary to implant a large amount of p-type impurities.
Therefore, even if a source gas containing a material constituting a nitride semiconductor not containing p-type impurities is supplied to the surface of the nitride semiconductor substrate containing a large amount of such p-type impurities, the intended result can be obtained. Absent. That is, even if a source gas containing no p-type impurity is supplied, the p-type impurity escapes from the substrate containing the p-type impurity and enters the nitride semiconductor growing on the substrate surface. It is difficult to grow a nitride semiconductor that does not contain a p-type impurity on the surface of the nitride semiconductor that contains a p-type impurity.

In order to solve the above problem, Patent Document 1 discloses a technique using nitrogen as a carrier gas. When nitrogen is used as the carrier gas, the crystallinity of the nitride semiconductor that grows on the surface of the substrate is worse than when hydrogen is used as the carrier gas. In Patent Document 1, utilizing the deterioration of crystallinity, Mg contained in the nitride semiconductor substrate is prevented from entering the nitride semiconductor growing on the substrate surface.
JP 2003-88641 A

However, even if nitrogen is used as the carrier gas, the p-type impurity contained in the nitride semiconductor substrate cannot be sufficiently prevented from entering the nitride semiconductor grown on the substrate surface. In the prior art, the effect of suppressing the migration of p-type impurities to the crystal growth layer has been insufficient. Further, there is a need for a technique that can effectively prevent the p-type impurity from moving to the crystal growth layer.
The present invention has been devised to solve the above problems.

  The method created by the present invention relates to a method for manufacturing a semiconductor device, comprising a step of crystal-growing a second nitride semiconductor on the surface of a first nitride semiconductor containing a p-type impurity. In the manufacturing method of the present invention, the step of crystal growth of the second nitride semiconductor is divided into a first half step and a second half step. In the first half step, the second nitride semiconductor is crystal-grown on the surface of the first nitride semiconductor within the first temperature range. In the second half step, the second nitride semiconductor is further crystal-grown on the surface of the second nitride semiconductor formed in the first half step within the second temperature range. In the above, the second temperature range is higher than the first temperature range.

  The temperature at which the second nitride semiconductor grows greatly affects the physical properties of the grown second nitride semiconductor. In addition, the temperature at which the second nitride semiconductor grows greatly affects the crystal growth rate of the second nitride semiconductor. In the conventional technique, a nitride semiconductor substrate containing a p-type impurity is heated to a temperature of about 1050 ° C., heated to about 1050 ° C., maintained at that temperature, and maintained at about 1050 ° C. The supply of the source gas containing the material constituting the nitride semiconductor and not containing the p-type impurity is started. Since the supply of the source gas is started while the temperature is maintained at a constant temperature, the physical properties of the second nitride semiconductor in which the crystal grows are stabilized. Moreover, since the crystal is grown at about 1050 ° C., a practical crystal growth rate can be obtained. However, according to this method, p-type impurities are introduced into the second nitride semiconductor. Even if nitrogen is used as the carrier gas, the introduction of p-type impurities into the second nitride semiconductor cannot be sufficiently suppressed.

According to the researches of the present inventors, it has been found that a nitride semiconductor grows even at an ambient temperature lower than the conventional crystal growth temperature. However, in order to grow a high-quality nitride semiconductor crystal at a low ambient temperature, it is necessary to slow the crystal growth rate, and it is practically acceptable to obtain the thickness necessary to realize a semiconductor structure. The crystal cannot be grown within the given time. For this reason, conventional research has not focused on crystal growth of nitride semiconductors at low temperatures.
However, as a result of studies by the present inventors, it is sufficiently confirmed that when a nitride semiconductor crystal is grown at a low temperature, the p-type impurity is introduced into the nitride semiconductor crystal-grown on the surface of the nitride semiconductor substrate containing the p-type impurity. It was found that it can be suppressed. Furthermore, if the surface of the nitride semiconductor containing p-type impurities is covered with a nitride semiconductor with a small amount of introduced p-type impurities even though it is thin, then the crystal growth temperature is increased and the crystal growth rate is increased. However, it has been found that introduction of p-type impurities into a nitride semiconductor growing at a practical rate can be sufficiently suppressed.

  The method of the present invention was created based on the above findings. In the method of the present invention, the second nitride semiconductor is grown on the surface of the first nitride semiconductor at a temperature at which the crystal growth rate is slow but the introduction of p-type impurities can be sufficiently suppressed. Although the low-temperature crystal growth layer formed in this way is thin, the amount of p-type impurities introduced is small, and the migration of p-type impurities is effectively suppressed. In the method of the present invention, the crystal growth temperature is subsequently increased to increase the crystal growth rate. Since the crystal growth rate is increased, the required thickness nitride semiconductor can be grown within an allowable time. Since the high-temperature crystal growth layer is grown on the surface of the low-temperature crystal growth layer with a small amount of p-type impurity introduced, the introduction of the p-type impurity into the high-temperature crystal growth layer can be sufficiently suppressed.

In the first half step of growing the low-temperature crystal growth layer, it is preferable to maintain the first nitride semiconductor at a constant temperature. That is, it is preferable to grow the second nitride semiconductor while maintaining the first nitride semiconductor at the first temperature within the first temperature range.
In this case, a low-temperature crystal growth layer with stable physical properties can be obtained. In addition, a low-temperature crystal growth layer having a stable thickness can be obtained in the first half step.

In order to obtain a low-temperature crystal growth layer crystal-grown at a constant temperature, it is preferable to perform the first temperature raising step for raising the temperature of the first nitride semiconductor to the first temperature prior to the first half step. It is possible to obtain a low-temperature crystal growth layer in which crystals are grown at a constant temperature.
It is also preferable to perform a second temperature raising step of raising the temperature from the first temperature to the second temperature after the low-temperature crystal growth layer having a thickness that suppresses the movement of the p-type impurity in the first half step grows. The crystal growth temperature of the low-temperature crystal growth layer can be kept constant until the low-temperature crystal growth layer reaches a certain thickness.

Even in the latter half of the process of growing the high-temperature crystal growth layer, it is preferable to maintain the first nitride semiconductor and the second nitride semiconductor (formed in the first half) at a constant temperature. That is, it is preferable that the second nitride semiconductor is further crystal grown while maintaining the first nitride semiconductor and the second nitride semiconductor at a second temperature within the second temperature range.
In this case, a high-temperature crystal growth layer with stable physical properties can be obtained. In addition, a high-temperature crystal growth layer having a stable thickness can be obtained in the latter half of the process.

In order to obtain a high-temperature crystal growth layer crystal-grown at a constant temperature, after the low-temperature crystal growth layer has grown, a second temperature raising step of raising the temperature from the first temperature to the second temperature is performed, and the second temperature rise It is preferable to temporarily stop the supply of the source gas during the process.
Since the crystal is grown at a constant temperature, a high-temperature crystal growth layer having stable physical properties can be obtained.

Maintaining the crystal growth temperature constant in the first half step of growing the low-temperature crystal growth layer is preferable but not essential. Instead of maintaining a constant temperature, the time until the temperature rises to the second temperature range after passing through the first temperature range is such that the second nitride semiconductor having a thickness that suppresses the migration of the p-type impurity in the first half process The temperature rising pattern (relationship between temperature and time) in the first half process may be set because it is longer than the time required to do this.
That is, if the temperature is raised to the second temperature range after the low-temperature crystal growth layer is grown to a thickness that suppresses the migration of p-type impurities, the crystal growth temperature of the low-temperature crystal growth layer may change gradually.

The first temperature range is preferably 600 ° C to 1000 ° C. If the temperature is 600 ° C. or higher, the nitride semiconductor crystal grows. If the temperature is 1000 ° C. or lower, the introduction of p-type impurities into the crystal-grown nitride semiconductor is effectively suppressed.
In particular, the temperature is more preferably 800 ° C to 900 ° C. If it is 800 degreeC or more, the crystal quality of a low-temperature crystal growth layer will improve, and if it is 900 degrees C or less, it will suppress notably that p-type impurity is introduce | transduced into the nitride semiconductor which carries out crystal growth.

In both the first half process and the second half process, it is preferable to grow the second nitride semiconductor using the metal organic vapor phase method.
The materials other than the impurities constituting the first nitride semiconductor and the second nitride semiconductor may be made of the same material or may have different compositions.
The present invention is particularly useful when the material other than the impurities constituting the first nitride semiconductor is composed of GaN. In this case, the second nitride semiconductor may also be GaN, but may not be GaN. A _{Al x In y Ga (1-} x-y) N may be. Here, 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, and 0 ≦ 1-xy ≦ 1.

  The second nitride semiconductor can be a nitride semiconductor other than p-type. For example, an n-type or i-type (undoped) nitride semiconductor in contact with the surface of the p-type first nitride semiconductor can be formed. Alternatively, it can also be applied to stack a second nitride semiconductor containing a p-type impurity at a lower concentration than the first nitride semiconductor.

The present invention also realizes a novel semiconductor device. The semiconductor device realized by the present invention includes a first nitride semiconductor containing a p-type impurity and a second nitride semiconductor in contact with the surface of the first nitride semiconductor. The second nitride semiconductor includes a low-temperature crystal growth layer grown at a low temperature and a high-temperature crystal growth layer grown at a high temperature, and the first nitride semiconductor, the low-temperature crystal growth layer, and the high-temperature crystal growth layer are stacked in this order. It is characterized by being.
In this semiconductor device, the p-type impurity concentration in the second nitride semiconductor in the range separated by 50 nm or more from the junction surface of the first nitride semiconductor and the second nitride semiconductor is p-type in the first nitride semiconductor. The impurity concentration can be 1 percent or less.

  According to the present invention, it is possible to effectively suppress the phenomenon that the p-type impurity contained in the first nitride semiconductor moves to the second nitride semiconductor that is crystal-grown on the surface of the first nitride semiconductor. A desired characteristic can be realized on the bonding surface of the first nitride semiconductor and the second nitride semiconductor, and a semiconductor device having excellent characteristics can be manufactured.

The main features of the embodiments described below are listed.
(First Feature) The lower limit temperature of the first temperature range is a lower limit temperature at which a second nitride semiconductor not containing a p-type impurity can be crystal-grown on the surface of the first nitride semiconductor containing a p-type impurity.
(Second Feature) The upper limit temperature of the first temperature range is lower than the lower limit temperature at which the phenomenon of detaching the p-type impurity from the surface of the first nitride semiconductor containing the p-type impurity occurs.
(Third Feature) A source gas is provided on the surface of the first nitride semiconductor in the first temperature range. The source gas does not cause a phenomenon that the p-type impurities are separated from the surface of the first nitride semiconductor.
(Fourth Feature) The lower limit temperature of the second temperature range is a lower limit temperature at which a phenomenon that the p-type impurity is detached from the surface of the first nitride semiconductor containing the p-type impurity occurs.
(Fifth Feature) If there is no low-temperature crystal growth layer, that is, if a high-temperature crystal growth layer is grown directly on the surface of the first nitride semiconductor, the p-type impurity contained in the first nitride semiconductor is high-temperature. The high temperature crystal growth layer is grown at a temperature that would be introduced into the crystal growth layer.
(Sixth feature) A vertical HEMT is formed using a nitride semiconductor. The HEMT includes a drain electrode formed on the back surface of an n-type GaN substrate, a layer formed on the surface of the GaN substrate and mainly made of n ⁻ -type GaN, and an n ⁻ -type GaN layer thereof. A first nitride semiconductor region mainly formed of p-type GaN and covering the surfaces of the n ⁻ -type GaN layer and the first nitride semiconductor region. And a second nitride semiconductor mainly made of n-type GaN, and a layer formed on the second nitride semiconductor and made mainly of AlGaN.
(Seventh feature) The p-type impurity is magnesium, zinc, beryllium, or calcium. These are easily introduced into the nitride semiconductor when the nitride semiconductor is crystal-grown, and the effect of the present invention is high.

Below, the manufacturing method of the semiconductor device 1 of a present Example is demonstrated with reference to FIGS. In this embodiment, the present invention is applied to a method of manufacturing a semiconductor device 1 which is a vertical HEMT using a GaN substrate.
FIG. 1 shows a cross-sectional view of a semiconductor device 1 of this embodiment. 2 to 7 show the manufacturing process of the semiconductor device 1. FIG. 8 shows the relationship between the temperature and time of the semiconductor substrate 2 when the semiconductor substrate 2 is heated to form an n-type GaN layer 50 on the surface of the p-type GaN layer 40 described later. FIG. 9 shows the amount of introduced p-type impurity (Mg) transferred from the p-type GaN layer 40 into the n-type GaN layer 50 grown on the surface of the p-type GaN layer 40 by the manufacturing method of this embodiment. It is a figure explaining that there are few.

As shown in FIG. 1, the semiconductor device 1 is manufactured using an n ⁺ -type GaN substrate 20. A drain electrode 10 is formed on the back surface of the n ⁺ -type GaN substrate 20. The drain electrode 10 is formed of a laminate of titanium (Ti) and aluminum (Al). On the surface of the n ⁺ -type GaN substrate 20, an n ⁻ -type GaN layer 30 containing n ⁻ -type GaN as a main material is formed. A p-type GaN layer 40 (an embodiment of the first nitride semiconductor containing a p-type impurity of the present invention) is formed in a range facing a part of the surface 31 of the n ⁻ -type GaN layer 30. In FIG. 1, p-type GaN layers 40 are formed on both ends of an n ⁻ -type GaN layer 30. The p-type GaN layer 40 extends in the depth direction in the n ⁻ -type GaN layer 30, but does not reach the n ⁺ -type GaN substrate 20. Magnesium (Mg) is used for the p-type impurities of the p-type GaN layers 40 and 40. The concentration of Mg is adjusted to about 1 × 10 ¹⁹ / cm ³ or more.
An n ^- type GaN layer 50 is formed on the surfaces of the n ⁻ -type GaN layer 30 and the p-type GaN layers 40 and 40 (second nitride semiconductor embodiment of the present invention). The n-type GaN layer 50 is formed over both the surface 41 of the p-type GaN layer 40 and the surface 31 of the n ⁻ -type GaN layer 30. The n-type GaN layer 50 includes a low-temperature crystal growth layer 52 and a high-temperature crystal growth layer 51. Details of the low-temperature crystal growth layer 52 and the high-temperature crystal growth layer 51 will be described later.
An i-type AlGaN layer 60 is formed on the n-type GaN layer 50. A heterojunction is constituted by the n-type GaN layer 50 and the i-type AlGaN layer 60. Since the crystal structure of the AlGaN layer 60 contains aluminum, the band gap of the AlGaN layer 60 is wider than the band gap of the n-type GaN layer 50. A quantum well is formed at the heterojunction surface between the n-type GaN layer 50 and the i-type AlGaN layer 60.

Source electrodes 70 are formed on both ends of the AlGaN layer 60, the n-type GaN layer 50, and the p-type GaN layer 40. The source electrode 70 penetrates the AlGaN layer 60 and the n-type GaN layer 50 and extends in the depth direction in the p-type GaN layer 40, and does not reach the n ⁻ -type GaN layer 30. The source electrode 70 protrudes from the surface of the AlGaN layer 60. The source electrode 70 is formed by laminating titanium and aluminum.
On the i-type AlGaN layer 60, a gate electrode 80 made mainly of nickel (Ni) is formed. The gate electrode 80 is a part of the surface of the i-type AlGaN layer 60 and is formed in a range not in contact with the source electrode 70. The gate electrode 80 is formed in a range covering at least the upper part of the n ⁻ -type GaN layer 30 between the p-type GaN layers 40 and 40.

The operation of the semiconductor device 1 configured as described above will be briefly described.
When a gate voltage higher than the threshold is applied to the gate electrode 80, a two-dimensional electron gas layer is generated on the n-type GaN layer 50 side in the heterojunction of the n-type GaN layer 50 and the i-type AlGaN layer 60. The two-dimensional electron gas layer extends between the source electrodes 70 and 70. The electrons move to the drain electrode 10 side through the n ⁻ -type GaN layer 30, whereby a current flows between the source electrode 70 and the drain electrode 10, and the semiconductor device 1 is turned on. When a voltage lower than the threshold is applied to the gate electrode 80, the two-dimensional electron gas layer in the range where the gate electrode 80 is formed above the two-dimensional electron gas layer disappears. A depletion layer spreads from the interface between the p-type GaN layers 40 and 40 and the n ⁻ -type GaN layer 30 in FIG. As a result, the semiconductor device 1 is turned off.

A method for manufacturing the semiconductor device 1 will be described with reference to FIGS.
First, as shown in FIG. 2, an n ⁻ type GaN layer 30 having a thickness of 5 μm is grown on the surface of an n ⁺ type GaN substrate 20. Si is used as an n-type impurity included in the n ⁻ -type GaN layer 30.
Next, as shown in FIG. 3, both ends of the n ⁻ -type GaN layer 30 are etched to form convex portions 32. The convex portion 32 is formed to have a width of 1 μm and a depth of 1.6 μm. The etched and recessed portion is referred to as a recess 34.
Next, at a temperature of 1050 ° C., a 2 μm-thick p-type GaN layer 40 is crystal-grown on the surface of the n ⁻ -type GaN layer 30 where the convex portions 32 and the concave portions 34 are formed. As a result, the recess 34 is completely filled with the p-type GaN layer 40. Mg is used for the p-type impurity. The concentration of the p-type impurity is adjusted to about 1 × 10 ¹⁹ cm ⁻³ .
Next, as shown in FIG. 4, etching is performed until the surface 31 of the convex portion 32 is exposed. The semiconductor substrate 2 including the n ⁺ -type GaN substrate 20, the n ⁻ -type GaN layer 30, and the p-type GaN layers 40 and 40 is formed.

Next, as shown in FIG. 5, metal organic vapor phase epitaxy (MOCVD method) is applied to the surface 2a of the semiconductor substrate 2 (the surface 41 of the p-type GaN layer 40 and the surface 31 of the n ⁻ -type GaN layer 30). ) To grow the n-type GaN layer 50. The step of crystal growth of the n-type GaN layer 50 includes a low-temperature crystal growth layer formed of an n-type GaN layer on the surface 41 of the p-type GaN layers 40 and 40 and the surface 31 of the n ⁻ -type GaN layer 30. A low temperature crystal growth stage (first half step) for crystal growth of 52, and a high temperature crystal for growing a high temperature crystal growth layer 51 formed of an n-type GaN layer on the surface of the low temperature crystal growth layer 52 formed in the first half step. It has a growth stage (second half process).

Details of the process of forming the GaN layer 50 will be described with reference to FIGS. FIG. 8 shows the relationship between the temperature T and the time S of the semiconductor substrate 2 when the GaN layer 50 is formed.
First, the semiconductor substrate 2 is heated in a carrier gas containing NH ₃ until the temperature reaches 800 ° C.
At time s1 in FIG. 8, the supply of the source gas containing the material of the GaN layer 50 (TMGa containing Ga and SiH ₄ containing Si as an n-type impurity) is started. The carrier gas may be H ₂ or N ₂ . As a result, the low-temperature crystal growth layer 52 formed of n-type GaN grows on the surface 2 a of the semiconductor substrate 2. The thickness of the low-temperature crystal growth layer 52 that has grown is grown to a thickness (50 nm in this embodiment) that can prevent Mg as a p-type impurity contained in the p-type GaN layers 40 and 40 from being taken into the source gas. At this stage (time s2 in FIG. 8), the supply of the source gas is stopped. The n-type impurity concentration in the low-temperature crystal growth layer 52 is adjusted to 1 × 10 ¹⁶ cm ⁻³ .
In the low-temperature crystal growth stage, since the low-temperature crystal growth layer 52 is crystal-grown at a low temperature of 800 ° C., the surface 41 of the p-type GaN layer 40 is difficult to be etched during the crystal growth process. Mg contained in the p-type GaN layer 40 is difficult to separate. Thereby, the amount of Mg introduced into the low-temperature crystal growth layer 52 is very small.

  Next, the semiconductor substrate 2 is heated until the temperature reaches 1050 ° C. After reaching 1050 ° C., the supply of the source gas containing the material of the n-type GaN layer 50 is resumed at time s3 in FIG. The source gas may be the same as the source gas supplied in the low temperature crystal growth stage. As a result, the high-temperature crystal growth layer 51 made of n-type GaN grows on the low-temperature crystal growth layer 52. When the high-temperature crystal growth layer 51 has grown to the thickness required for the semiconductor device 1 (time s4 in FIG. 8), the supply of the source gas is stopped. In the high-temperature crystal growth stage, the high-temperature crystal growth layer 51 is crystal-grown at a constant temperature of 1050 ° C. Therefore, the crystallinity of the high-temperature crystal growth layer 51 is improved, the physical properties are stable, and the necessary thickness is crystallized in a short time. Can be grown.

Thereafter, the source gas containing the material of the n-type GaN layer 50 is exhausted, and the source gas containing the material of the i-type AlGaN layer 60 is supplied as shown in FIG. The i-type AlGaN layer 60 is grown.
Next, the source electrode 70, the gate electrode 80, and the drain electrode 10 (see FIG. 1) are formed by a known method.

With reference to FIG. 9, according to the present embodiment, it is suppressed that the p-type impurity (Mg) contained in the p-type GaN layer 40 is moved to the adjacent n-type GaN layer 50. explain.
9 represents the depth of the p-type GaN layer 40 and the n-type GaN layer 50, and the interface between the p-type GaN layer 40 and the n-type GaN layer 50 (p-type GaN layer). The position of the front surface 41) of 40 is a reference position, and the reference position is shown at a substantially intermediate position. The horizontal axis indicates the distance from the reference position. The p-type GaN layer 40 is on the right side of the reference position, and the n-type GaN layer 50 is on the left side of the reference position. The vertical axis in FIG. 9 indicates the Mg concentration. The concentration of Mg is shown as a percentage with the concentration at the interface being 100 percent.
The graph M1 shows the concentration profile of Mg in the p-type GaN layer 40 and the n-type GaN layer 50 formed by the manufacturing method of this example. Graph M2 shows the concentration profile of Mg in the p-type GaN layer and the n-type GaN layer formed by the conventional manufacturing method.
The graph M2 indicates that the Mg concentration in the n-type GaN layer 50 is higher than that in the graph M1. In the graph M2, the Mg concentration is about 1% of the Mg concentration at the interface at a position of about 150 nm from the interface, whereas in the graph M1, the Mg concentration at the position of about 50 nm from the interface is the Mg concentration at the interface. It is suppressed to less than 1 percent of the concentration.

As in the prior art, when the GaN layer 50 is crystal grown after the temperature of the semiconductor substrate is raised to 1050 degrees, the surface of the p-type GaN layer 40 is etched by the source gas, and p-type impurities are mixed in the source gas. It was. As a result, a considerable amount of Mg was mixed in the n-type GaN layer 50 that grew on the surface of the p-type GaN layer 40.
In the method described in this embodiment, the GaN layer 50 is formed by the low temperature crystal growth layer 52 and the high temperature crystal growth layer 51. Since the low-temperature crystal growth layer 52 is grown at a low temperature, the degree to which the surface 41 of the p-type GaN layer 40 is etched by the source gas of the low-temperature crystal growth layer 52 is suppressed. The amount of Mg introduced into the low-temperature crystal growth layer 52 is very small as compared to the graph M2 in the case of the prior art, as shown by the graph M1 in FIG. The low temperature crystal growth layer 52 suppresses the introduction of Mg. The low temperature crystal growth layer 52 can effectively suppress the phenomenon that Mg is introduced into the GaN layer 50.
In this embodiment, the high temperature crystal growth layer 51 is formed on the low temperature crystal growth layer 52. The high temperature crystal growth layer 51 has fewer defects and better crystallinity than the low temperature crystal growth layer 52. In addition, crystals can be grown quickly. Since the high-temperature crystal growth layer 51 is formed after the low-temperature crystal growth layer 52 is formed, it is possible to prevent Mg from entering the high-temperature crystal growth layer 51.

In this embodiment, the temperature of the semiconductor substrate 2 is maintained at a temperature of 800 ° C. in the low temperature crystal growth stage. While maintaining a constant temperature, the speed of crystal growth is maintained at approximately the same speed. A low-temperature crystal growth layer 52 having a stable thickness can be obtained. In addition, the low-temperature crystal growth layer 52 having stable physical properties can be obtained.
The temperature of the semiconductor substrate 2 in the low-temperature crystal growth stage is preferably between 600 ° C. and 1000 ° C. More preferably, this temperature is between 800 ° C and 900 ° C.
In this embodiment, the temperature of the semiconductor substrate 2 is maintained at a temperature of 1050 ° C. during the high-temperature crystal growth stage. A high-temperature crystal growth layer 51 having a stable thickness can be obtained. In addition, a stable high temperature crystal growth layer 51 can be obtained.

  In this embodiment, when the low-temperature crystal growth layer 52 is crystal-grown, the source gas of the n-type GaN layer 50 is supplied to the semiconductor substrate 2 at time s1 after the temperature of the semiconductor substrate 2 reaches 600 ° C. I'm starting. Further, when the high-temperature crystal growth layer 51 is grown, after the temperature of the semiconductor substrate 2 reaches 1050 ° C., the source gas of the n-type GaN layer 50 starts to be supplied to the semiconductor substrate 2 at time s3. That is, no source gas is supplied at the stage where the semiconductor substrate 2 is heated. It is easy to control the time for performing crystal growth until the low-temperature crystal growth layer 52 and the high-temperature crystal growth layer 51 each have a desired thickness.

In the method of this embodiment, a low-temperature crystal growth step is first performed on the surface of the p-type GaN layer 40 to form a low-temperature crystal growth layer 52 of n-type GaN, and then the surface of the low-temperature crystal growth layer 52 is formed. A high-temperature crystal growth step for forming the n-type GaN high-temperature crystal growth layer 51 is performed. The conductivity types of the low-temperature crystal growth layer 52 and the high-temperature crystal growth layer 51 are not limited to n-type. It may be i-type. Or it may be p ^- type.

In the method of this embodiment, the temperature of the semiconductor substrate 2 is maintained at 800 ° C. and the low-temperature crystal growth layer 52 is crystal-grown at the low-temperature crystal growth stage. The temperature at this stage of the present invention may not be maintained at a constant temperature, for example, may gradually increase.
In the method of this embodiment, the temperature of the semiconductor substrate 2 is maintained at 1050 ° C. to grow the high-temperature crystal growth layer 51 in the high-temperature crystal growth stage. The temperature at this stage of the present invention may not be maintained at a constant temperature, for example, may gradually increase.

  In the method of this embodiment, the case where the low-temperature crystal growth layer 52 is crystal-grown on the surface 41 of the p-type GaN layer 40 has been described. The low-temperature crystal growth layer 52 of the present invention may be between the surface 41 of the p-type GaN layer 40 and the high-temperature crystal growth layer 51, and may not be in contact with the surface 41 of the p-type GaN layer 40.

In the method of the present embodiment, the case where the n-type GaN layer 50 is crystal-grown from the surface of the p-type GaN layer 40 containing Mg has been described. The p-type impurity contained in the p-type GaN layer 40 is not limited to Mg. For example, the p-type impurity may be beryllium or calcium.
In the present embodiment, the case where the n-type GaN layer 50 is formed from the surface of the p-type GaN layer 40 has been described. However, both may not be layers of the same material. Moreover, the material of both layers is not limited to GaN.
In the present embodiment, the case where the present invention is applied to the HEMT type semiconductor device 1 has been described. However, the method of the present invention can be applied to the surface of a p-type nitride semiconductor containing a p-type impurity that is easily moved. The present invention can be widely applied to crystal growth of n-type, i-type and p ⁻ -type nitride semiconductors. The semiconductor device manufactured by the method of the present invention is not limited to a HEMT type semiconductor device.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
In addition, the technical elements described in the present specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology illustrated in the present specification or the drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of the objects.

1 is a cross-sectional view of a semiconductor device 1. FIG. 6 is a diagram illustrating a process of manufacturing the semiconductor device 1. FIG. 6 is a diagram illustrating a process of manufacturing the semiconductor device 1. FIG. 6 is a diagram illustrating a process of manufacturing the semiconductor device 1. FIG. 6 is a diagram illustrating a process of manufacturing the semiconductor device 1. FIG. 6 is a diagram illustrating a process of manufacturing the semiconductor device 1. FIG. 6 is a diagram illustrating a process of manufacturing the semiconductor device 1. FIG. 6 is a diagram for explaining a relationship between a temperature T and a time S when heating the semiconductor substrate 2 when growing an n-type GaN layer 50 on the surface 2a of the semiconductor substrate 2. FIG. 4 is a diagram for explaining that the amount of p-type impurities (Mg) transferred from the p-type GaN layer 40 is small in the n-type GaN layer 50 crystal-grown on the surface of the p-type GaN layer 40. FIG. It is a figure explaining a prior art about the relationship between temperature T and time S when heating a semiconductor substrate, when growing an n-type GaN layer on the surface of a p-type GaN layer.

Explanation of symbols

1; semiconductor device 2; semiconductor substrate 2a; surface 10; the drain electrode 20; ^{n +} -type GaN layer 30; n ^- -type GaN layer 31; the surface (n ^- surface type GaN layer)
40; p-type GaN layer 41; p-type GaN layer surface 50; n-type GaN layer 51; high-temperature crystal growth layer 52; low-temperature crystal growth layer 60; i-type AlGaN layer 70; source electrode 80;

Claims (15)

A method for manufacturing a semiconductor device comprising a step of crystal-growing a second nitride semiconductor on a surface of a first nitride semiconductor containing a p-type impurity,
The step of crystal growth of the second nitride semiconductor has a first half step and a second half step,
In the first half step, the second nitride semiconductor is grown on the surface of the first nitride semiconductor within the first temperature range,
In the second half step, a second nitride semiconductor is further grown on the surface of the second nitride semiconductor in a second temperature range higher than the first temperature range.
A method for manufacturing a semiconductor device.   2. The method of manufacturing a semiconductor device according to claim 1, wherein, in the first half step, the first nitride semiconductor is maintained at a first temperature within the first temperature range.   3. The method of manufacturing a semiconductor device according to claim 1, wherein in the second half step, the first nitride semiconductor and the second nitride semiconductor are maintained at a second temperature within the second temperature range. Method.   4. The method of manufacturing a semiconductor device according to claim 2, wherein a first temperature raising step of raising the temperature of the first nitride semiconductor to a first temperature is performed prior to the first half step. 5.   Performing the second temperature raising step of raising the temperature from the first temperature to the second temperature after the second nitride semiconductor having a thickness that suppresses the movement of the p-type impurity is grown in the first half step. The method for manufacturing a semiconductor device according to claim 3, wherein the method is a semiconductor device manufacturing method.   The second nitride semiconductor having a thickness that suppresses the movement of the p-type impurity in the first half step during the first half step until the temperature rises to the second temperature range after passing through the first temperature range. The method of manufacturing a semiconductor device according to claim 1, wherein the method is performed in a relationship that it is longer than a time required for the operation.   The method for manufacturing a semiconductor device according to claim 1, wherein the first temperature range is 600 ° C. to 1000 ° C. 7.   The method for manufacturing a semiconductor device according to claim 7, wherein the first temperature range is 800 ° C. to 900 ° C.   9. The method of manufacturing a semiconductor device according to claim 1, wherein the second nitride semiconductor is crystal-grown using an organic metal vapor phase method in the first half step and the second half step.   The method for manufacturing a semiconductor device according to claim 1, wherein materials other than impurities constituting the first nitride semiconductor and the second nitride semiconductor are the same material.   10. The method of manufacturing a semiconductor device according to claim 1, wherein the material other than the impurities constituting the first nitride semiconductor is GaN.   The method of manufacturing a semiconductor device according to claim 1, wherein the p-type impurity contained in the first nitride semiconductor is Mg.   The method for manufacturing a semiconductor device according to claim 1, wherein the second nitride semiconductor is a nitride semiconductor other than a p-type semiconductor. a first nitride semiconductor containing a p-type impurity;
A semiconductor device comprising a second nitride semiconductor in contact with the surface of the first nitride semiconductor;
The second nitride semiconductor includes a low-temperature crystal growth layer grown at a low temperature and a high-temperature crystal growth layer grown at a high temperature.
A semiconductor device, wherein a first nitride semiconductor, a low-temperature crystal growth layer, and a high-temperature crystal growth layer are stacked in this order.   The p-type impurity concentration in the second nitride semiconductor in a range of 50 nm or more away from the junction surface between the first nitride semiconductor and the second nitride semiconductor is p-type impurity in the first nitride semiconductor. The semiconductor device according to claim 14, wherein the concentration is 1 percent or less of the concentration.

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