JP5313816B2 - Nitride-based semiconductor device and method for manufacturing nitride-based semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nitride-based semiconductor element capable of reducing an offset voltage on an interface between a semiconductor layer on a gallium oxide substrate and a principal surface of the gallium oxide substrate. <P>SOLUTION: A group-III nitride crystal layer 15 covers the principal surface 13a of the gallium nitride substrate 13. The group-III nitride crystal layer 15 comprises a group-III nitride containing aluminum as a group-III constituent element and also containing at least two kinds of constituent elements other than aluminum. A semiconductor laminate 17 includes a gallium nitride semiconductor layer 25. A first electrode 19 is provided on a principal surface 17a of the semiconductor laminate 17. A second electrode 21 is provided on a reverse surface 13b of the gallium nitride substrate 13. A band gap E(15) of the group-III nitride crystal layer 15 is larger than a band gap E(GaN) of the gallium nitride semiconductor layer. The band gap E(15) of the group-III nitride crystal layer 15 is smaller than 4.8 eV (electronvolt). <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a nitride semiconductor device and a method for manufacturing a nitride semiconductor device.

Patent Document 1 describes a light-emitting element formed on a Ga ₂ O ₃ substrate. A buffer layer is grown on the Ga ₂ O ₃ substrate at a low temperature. The growth of the buffer layer is performed in a nitrogen atmosphere in the range of 350 degrees Celsius to 550 degrees Celsius. This buffer layer is an AlN layer or an AlGaN layer. The p-side electrode and the current diffusion layer of the light-emitting element are formed on the p-type GaN layer, and the n-side electrode of the light-emitting element is formed on the exposed surface of the n + -type GaN layer formed on the Ga ₂ O ₃ substrate. Has been. This n + GaN layer is a Si-doped GaN thick film grown directly on the low-temperature buffer layer. The thickness of the low temperature growth buffer layer is 20 nm to 30 nm. Since the growth of the low temperature growth buffer layer is performed by supplying hydrogen, ammonia, TMG and TMA to the growth reactor, no dopant is added to the low temperature growth buffer layer.

JP 2006-310765 A

In the light emitting element described in Patent Document 1, the current applied to the light emitting element is n from the p-side electrode through the p + type GaN layer, the p type AlGaN layer, the MQW layer, the n type AlGaN layer, and the n + GaN layer. Flows to the side electrode. The reason why the low-temperature buffer layer is formed on the gallium oxide substrate is as follows: Even if the low-temperature growth buffer layer is formed on the Ga ₂ O ₃ substrate in a hydrogen atmosphere, the low-temperature growth buffer does not alter the Ga ₂ O ₃ substrate. Grow layers.

  In a semiconductor element including an electrode formed on a gallium oxide substrate, a gallium nitride based semiconductor region is formed on the gallium oxide substrate. The current applied to the semiconductor element flows to the n-side electrode across the interface between the gallium nitride based semiconductor region and the main surface of the gallium oxide substrate. According to the inventors' knowledge, the above-described interface generates an offset voltage in the semiconductor element.

  The present invention has been made in view of such circumstances, and provides a nitride-based semiconductor element capable of reducing the offset voltage at the interface between the semiconductor layer on the gallium oxide substrate and the main surface of the gallium oxide substrate. It is another object of the present invention to provide a method of manufacturing a nitride semiconductor device using a gallium oxide substrate.

  According to one aspect of the present invention, a nitride-based semiconductor device includes: (a) a conductive gallium oxide substrate having a main surface and a back surface; and (b) a group III nitride covering the main surface of the gallium oxide substrate. A crystal layer, (c) a semiconductor stack that forms a heterojunction with the group III nitride crystal layer and includes a gallium nitride semiconductor layer, and (d) a first electrode provided on the semiconductor stack; (E) a second electrode provided on the back surface of the gallium oxide substrate, wherein a band gap of the group III nitride crystal layer is larger than a band gap of the gallium nitride semiconductor layer, and the group III nitride The band gap of the crystal layer is smaller than 4.8 electron volts, and the group III nitride crystal layer is made of a group III nitride containing aluminum as a group III constituent element and containing at least two kinds of constituent elements other than aluminum. .

  According to this nitride semiconductor device, the current applied to the nitride semiconductor device is transferred from the first electrode provided on the semiconductor stack to the second electrode provided on the back surface of the gallium oxide substrate. Flowing. A group III nitride crystal layer is provided on this current path. This group III nitride crystal layer contains aluminum as a group III constituent element, and its band gap is larger than the band gap of the gallium nitride semiconductor layer and smaller than 4.8 electron volts. This group III nitride crystal layer can reduce the offset voltage in the nitride semiconductor device.

  In the nitride semiconductor device according to the present invention, an offset voltage between the gallium nitride semiconductor layer closest to the substrate and the gallium oxide substrate can be 0.5 V or less. In the nitride semiconductor device according to the present invention, an offset voltage between the gallium nitride semiconductor layer closest to the substrate and the gallium oxide substrate can be 0.3 V or less. Furthermore, in the nitride semiconductor device according to the present invention, an offset voltage between the gallium nitride semiconductor layer closest to the substrate and the gallium oxide substrate can be 0.2 V or less.

In the nitride semiconductor device according to the present invention, the group III nitride crystal layer may include an n-type dopant, and the concentration of the n-type dopant may be 1 × 10 ¹⁶ cm ⁻³ or more. In this nitride-based semiconductor element, the resistance in the group III nitride crystal layer can be reduced.

In the nitride-based semiconductor device according to the present invention, the group III nitride crystal layer is an In _X Al _Y Ga _1-XY N layer (0 ≦ X <1, 0 <Y <1, 0 <X + Y ≦ 1). Can be included.

_{In X Al Y Ga 1-X} -Y N can be grown on gallium oxide substrate. In addition, a semiconductor layer applicable for a nitride-based semiconductor element can be grown on the In _X Al _Y Ga _1-XY N layer. With this structure, the offset voltage can be reduced.

In the nitride-based semiconductor device according to the present invention, the group III nitride crystal layer comprises _{Al Z Ga 1-Z} N layer, the _{Al Z Ga 1-Z} aluminum composition of the N layer is 0.2 or more 0,3 Can be:

According to the nitride semiconductor device, when the Al _Z Ga _1-Z N layer is provided on the gallium oxide substrate, the offset voltage at the interface between the gallium oxide substrate and the Al _Z Ga _1-Z N layer, and semiconductor stack and the offset voltage at the interface between the Al Z _Ga 1-Z _N layer for the nitride semiconductor device can be reduced.

In the nitride-based semiconductor device according to the present invention, the group III nitride crystal layer comprises _{In X Al Y Ga 1-X} -Y N layer, the indium composition of the _{In X Al Y Ga 1-X} -Y N layer X is 0.1 or less, the _{in X Al Y Ga 1-X} -Y N layer aluminum composition Y of is not less than 0.15, an aluminum content of the _{in X Al Y Ga 1-X} -Y N layer Y can be 0.35 or less.

According to this nitride-based semiconductor device, when the above In _X Al _Y Ga _1-XY N layer is provided on the gallium oxide substrate, the gallium oxide substrate and the In _X Al _Y Ga _1-XY N layer And the band gap difference at the interface between the semiconductor stack for the nitride semiconductor element and the In _X Al _Y Ga _1- XYN layer.

  In the nitride semiconductor device according to the present invention, the group III nitride crystal layer includes a plurality of InAlGaN layers arranged in a direction of a normal axis of a main surface of the gallium oxide substrate, and the bands of the plurality of InAlGaN layers. The gap can be reduced in the direction from the gallium oxide substrate to the gallium nitride semiconductor layer.

  By applying the group III nitride crystal layer including a plurality of InAlGaN layers, the lattice constant difference between the group III nitride crystal layer and the region adjacent to the group III nitride crystal layer can be reduced. Therefore, in the nitride-based semiconductor element, not only the offset voltage but also the lattice constant difference between the substrate and the semiconductor stack can be reduced.

  In the nitride semiconductor device according to the present invention, the group III nitride crystal layer includes an InAlGaN layer having a gradient composition, and a band gap of the InAlGaN layer is in a direction from the gallium oxide substrate to the gallium nitride semiconductor layer. Can be smaller.

  By applying the group III nitride crystal layer including the composition-graded InAlGaN layer, the lattice constant difference between the group III nitride crystal layer and the region adjacent to the group III nitride crystal layer can be reduced. Therefore, according to this nitride semiconductor device, not only the offset voltage but also the lattice constant difference can be reduced.

  In the nitride semiconductor device according to the present invention, the gallium oxide substrate is made of a single crystal, and the a-axis lattice constant in the group III nitride crystal layer is equal to the b-axis lattice constant in the gallium oxide substrate and the gallium nitride semiconductor. It can be between the a-axis lattice constant in the layer.

  By applying this group III nitride crystal layer, not only the offset voltage but also the lattice constant difference between the group III nitride crystal layer and the region adjacent to the group III nitride crystal layer can be reduced.

  In the nitride semiconductor device according to the present invention, the gallium oxide substrate has n conductivity, the semiconductor stack includes a p-type gallium nitride semiconductor layer and an active layer, and the gallium nitride semiconductor layer includes the oxide semiconductor layer. The active layer is provided between the gallium substrate and the active layer, the active layer is provided between the gallium nitride semiconductor layer and the p-type gallium nitride based semiconductor layer, and the semiconductor stack is formed of the group III nitride One or a plurality of gallium nitride based semiconductor layers provided between the material crystal layer and the active layer, and the band gap of the gallium nitride based semiconductor layer is smaller than the band gap of the group III nitride crystal layer, The nitride-based semiconductor device includes a light emitting device.

  This nitride-based semiconductor element can be applied to a light emitting element.

  In the nitride semiconductor device according to the present invention, the nitride semiconductor device includes a vertical electronic device in which a current flows from one of the first and second electrodes to the other of the first and second electrodes. . This nitride-based semiconductor element can be applied to a vertical structure diode or transistor. In the nitride semiconductor device according to the present invention, the nitride semiconductor device includes a diode in which a current flows from one of the first and second electrodes to the other of the first and second electrodes. This nitride-based semiconductor element can be applied to a vertical pn diode or Schottky diode.

  Another aspect of the present invention is a method for fabricating a nitride-based semiconductor device. This method includes (a) a step of placing a conductive gallium oxide substrate in a growth furnace, and (b) supplying the nitrogen gas to the growth furnace while the oxidation is performed in a temperature range of 600 degrees Celsius or higher and 700 degrees Celsius or lower. Increasing the temperature of the gallium substrate; (c) growing a group III nitride layer on the main surface of the gallium oxide substrate at a growth temperature within the temperature range; and (d) higher than the growth temperature. Performing a heat treatment of the group III nitride layer at a temperature to form a group III nitride crystal layer on the main surface so as to cover the main surface of the gallium oxide substrate; and (e) a gallium nitride semiconductor. And (f) forming a first electrode on the semiconductor stack and forming a second electrode on the back surface of the gallium oxide substrate. And a step of performing. The band gap of the group III nitride crystal layer is larger than the band gap of the gallium nitride semiconductor layer, the band gap of the group III nitride crystal layer is smaller than 4.8 electron volts, and the group III nitride crystal is III It consists of a group III nitride containing aluminum as a group constituent element and at least two kinds of constituent elements other than aluminum.

  According to this method, a group III nitride layer is grown on the main surface at the growth temperature so as to cover the main surface of the gallium oxide substrate, and the group III nitride layer is heat-treated at a temperature higher than the growth temperature. And a group III nitride crystal layer is formed on the main surface. Thereafter, a semiconductor stack for the nitride-based semiconductor element is grown on the group III nitride crystal layer. The band gap of the group III nitride crystal layer is larger than the band gap of the gallium nitride semiconductor layer and smaller than 4.8 electron volts. Therefore, in the manufacture of a nitride-based semiconductor device, it is possible to reduce an offset voltage caused by forming a semiconductor stack made of a gallium nitride-based semiconductor having a band gap smaller than that of the gallium oxide substrate on the gallium oxide substrate.

  In the method according to the present invention, the group III nitride layer may be grown while supplying an n-type dopant to the growth reactor. As a result, an n-type dopant is added to the group III nitride crystal layer. Series resistance due to the group III nitride crystal layer can be reduced.

  In the method according to the present invention, the gas supplied to the growth furnace can be switched from nitrogen gas to hydrogen gas during the growth of the group III nitride layer. According to this method, a semiconductor stack can be formed on a group III nitride crystal layer using a hydrogen carrier gas.

  In the method according to the present invention, the nitride crystal layer may include at least one of a ternary AlGaN layer and a quaternary InAlGaN layer.

In the method according to the present invention, the group III nitride crystal layer comprises _Al Z _{Ga 1-Z} N layer, the _Al Z _{Ga 1-Z} N layer aluminum composition Z in is 0.2 or more 0,3 or less .

  According to this method, in the manufacture of a nitride-based semiconductor device, ternary AlGaN is used, the interface between the nitride crystal layer on the gallium oxide substrate and the main surface of the gallium oxide substrate, and the nitride crystal layer and the semiconductor stack. The manufacturing method which can make small the band gap difference in an interface with can be provided.

In the method according to the present invention, the III-nitride crystal layer is _{In X Al Y Ga 1-X} -Y N includes a layer, the _{In X Al Y Ga 1-X} -Y indium composition X of the N layer is 0. 1 or less, wherein _{an in} X _Al Y aluminum composition Y of _{Ga 1-X-Y} N layer is less than 0.15, the _{in X Al Y Ga 1-X} -Y N layer aluminum composition Y of 0. It can be 35 or less.

  According to this method, it is possible to provide a manufacturing method capable of reducing the offset voltage at the interface using quaternary InAlGaN in the manufacture of a nitride semiconductor device.

  In the method according to the present invention, the group III nitride crystal layer includes a plurality of InAlGaN layers arranged in a direction of a normal axis of a main surface of the gallium oxide substrate, and a band gap of the plurality of InAlGaN layers is the oxidation It decreases in the direction from the gallium substrate to the gallium nitride semiconductor layer.

  According to this method, it is possible to provide a manufacturing method capable of reducing the offset voltage by using a quaternary InAlGaN in the manufacture of a nitride-based semiconductor element by changing the stepped band gap.

  In the method according to the present invention, the group III nitride crystal layer includes an InAlGaN layer having a gradient composition, and the band gap of the InAlGaN layer decreases in the direction from the gallium oxide substrate to the gallium nitride semiconductor layer.

  According to this method, it is possible to provide a manufacturing method capable of reducing an offset voltage by using a quaternary InAlGaN in the manufacture of a nitride-based semiconductor element by changing a band gap due to a gradient composition.

  In the method according to the present invention, the gallium nitride semiconductor layer is grown in contact with the group III nitride crystal layer in the formation of the semiconductor stack. According to this method, the offset voltage due to the band gap between the gallium nitride semiconductor and gallium oxide can be reduced.

  The above and other objects, features, and advantages of the present invention will become more readily apparent from the following detailed description of preferred embodiments of the present invention, which proceeds with reference to the accompanying drawings.

  As described above, according to one aspect of the present invention, there is provided a nitride-based semiconductor element that can reduce the offset voltage at the interface between the semiconductor layer on the gallium oxide substrate and the main surface of the gallium oxide substrate. According to another aspect of the present invention, a method for manufacturing this nitride-based semiconductor device is provided.

FIG. 1 is a drawing showing the structure of a nitride-based semiconductor optical device according to this embodiment. FIG. 2 is a drawing showing the layer structure of a group III nitride crystal layer. FIG. 3 is a drawing showing the main steps of a method for forming an epitaxial wafer and a method for manufacturing a semiconductor device according to the present embodiment. FIG. 4 is a view showing a gallium oxide substrate for an epitaxial wafer according to the present embodiment. FIG. 5 is a diagram illustrating a sequence for growing a group III nitride layer and a semiconductor stack. FIG. 6 is a drawing schematically showing main steps of the forming method and the manufacturing method according to the present embodiment. FIG. 7 is a drawing schematically showing main steps of the forming method and the manufacturing method according to the present embodiment. FIG. 8 is a diagram illustrating a device structure and a simulation result for device simulation. FIG. 9 is a drawing showing the structure of a diode manufactured as an example of an electronic device, its characteristics, and the characteristics of a comparative example.

  The knowledge of the present invention can be easily understood by considering the following detailed description with reference to the accompanying drawings shown as examples. Subsequently, embodiments of the nitride semiconductor device and the epitaxial substrate, and the method of manufacturing the nitride semiconductor device and the epitaxial substrate of the present invention will be described with reference to the accompanying drawings. Where possible, the same parts are denoted by the same reference numerals.

  FIG. 1 is a drawing showing the structure of a nitride-based semiconductor optical device according to this embodiment. The nitride-based semiconductor element 11 includes a conductive gallium oxide substrate 13, a group III nitride crystal layer 15, a semiconductor stack 17, a first electrode 19, and a second electrode 21. The gallium oxide substrate 13 has a main surface 13a and a back surface 13b. The group III nitride crystal layer 15 covers the main surface 13a of the gallium oxide substrate 13, and covers the entire main surface 13a in this embodiment. The group III nitride crystal layer 15 is made of a group III nitride containing aluminum as a group III constituent element and containing at least two kinds of constituent elements other than aluminum. The semiconductor stack 17 includes a gallium nitride semiconductor layer 25. The first electrode 19 is provided on the main surface 17a of the semiconductor stack 17, and makes contact with the main surface 17a, for example. The second electrode 21 is provided on the back surface 13b of the gallium oxide substrate 13, and makes contact with the back surface 13b, for example. The group III nitride crystal layer 15 forms a heterojunction 23 a with the semiconductor stack 17, and forms a heterojunction 23 b with the main surface 13 a of the gallium oxide substrate 13. The band gap E (15) of the group III nitride crystal layer 15 is larger than the band gap E (GaN) of the gallium nitride semiconductor layer. The band gap E (15) of the group III nitride crystal layer 15 is smaller than 4.8 electron volts, and this value is about the same as the band gap of single crystal gallium oxide, for example.

  According to this nitride-based semiconductor element 11, the current applied to this element flows from the first electrode 19 on the semiconductor stack 17 to the second electrode 21 on the back surface 13 b of the gallium oxide substrate 13. A group III nitride crystal layer 15 is provided on this current path. This group III nitride crystal layer 15 contains aluminum as a group III constituent element, and its band gap is larger than the band gap of the gallium nitride semiconductor layer and smaller than 4.8 electron volts. The group III nitride crystal layer 15 can reduce the offset voltage resulting from the formation of the layer 17 made of group III nitride on the gallium oxide substrate 13.

  When the group III nitride crystal layer 15 is composed of a single layer, among the group III nitride crystal layer 15, the gallium oxide substrate 13 and the semiconductor stack 17, the gallium oxide substrate 13, the group III nitride crystal layer 15, The sum of the offset voltage at the interface 23a and the offset voltage at the interface 23b between the semiconductor stack 17 and the group III nitride crystal layer 15 is smaller than the voltage offset due to the interface between the participating members and gallium nitride.

In the nitride-based semiconductor element 11, it is preferable that an n-type dopant is added to the group III nitride crystal layer 15. The concentration of this n-type dopant can be 1 × 10 ¹⁶ cm ⁻³ or more. Thereby, an effect of reducing the offset voltage can be provided, and the resistance in the group III nitride crystal layer 15 can be reduced.

In the nitride-based semiconductor device 11, the group III nitride crystal layer 15 includes an In _X Al _Y Ga _1-XY N layer (0 ≦ X <1, 0 <Y <1, 0 <X + Y ≦ 1). Is good. _In the group III nitride crystal layer _{X Al Y Ga 1-X-} Y N layers can be grown on the gallium oxide substrate. In addition, a semiconductor stack 17 applicable for a nitride-based semiconductor element can be grown on the In _X Al _Y Ga _1-XY N layer. The material of the group III nitride crystal layer 15 is, for example, ternary or quaternary group III nitride, and specific examples include AlGaN, InAlGaN, and the like. Ternary mixed crystal AlGaN has a band gap larger than that of GaN because of aluminum constituent elements having an atomic radius smaller than that of gallium. Quaternary mixed crystal InAlGaN can provide a band gap larger than the band gap of GaN by a combination of an indium constituent element having an atomic radius larger than gallium and an aluminum constituent element. The quaternary mixed crystal InAlGaN can provide a lattice constant between the lattice constant of GaN and the main lattice constant in the main surface of the gallium oxide substrate by a combination of an indium constituent element having an atomic radius larger than gallium and an aluminum constituent element.

III nitride crystal layer 15 can be a _{Al Z Ga 1-Z} N layer. When the above _{Al Z Ga 1-Z} N layer is provided gallium oxide substrate, an offset voltage in the gallium oxide substrate 13 and the _{Al Z Ga 1-Z} N layer and the interface 23b, and because of the nitride semiconductor device The sum of the offset voltage at the interface 23 a between the semiconductor stack 17 and the Al _Z Ga _1-Z N layer is smaller than the offset voltage at the interface between gallium oxide and gallium nitride. The aluminum composition of the Al _Z Ga _1-Z N layer of the group III nitride crystal layer 15 is preferably 0.2 or more and preferably 0.3 or less. AlGaN having this composition range can contribute to the reduction of the offset voltage. The band gap of the group III nitride crystal layer 15 is preferably in the range of, for example, 3.4 electron volts or more and 4.8 electron volts or less. The thickness of the _{Al Z Ga 1-Z} N layer for the group III nitride crystal layer 15 can be for example, a 10nm or more, and is 100nm or less.

Alternatively, III-nitride crystal layer 15 can be a _{In X Al Y Ga 1-X} -Y N layer. When the In _X Al _Y Ga _1- XYN layer is provided on the gallium oxide substrate 13, the offset voltage at the interface 23b between the gallium oxide substrate 13 and the In _X Al _Y Ga _1-XY N layer, Further, the sum of offset voltages at the interface 23a between the semiconductor stack 17 and the In _X Al _Y Ga _1-XY N layer can be made smaller than the offset voltage at the interface between gallium oxide and gallium nitride. The thickness of the In _X Al _Y Ga _1- XYN layer for the group III nitride crystal layer 15 may be, for example, 10 nm or more and 100 nm or less. If necessary, an AlGaN layer or InAlGaN layer equivalent to the band gap of gallium oxide may be further grown on the surface of the gallium oxide substrate. Further, the lowermost layer of the semiconductor stack may be formed on an InAlGaN layer having a band gap equivalent to the band gap of the lowermost layer.

Further, the indium composition X of the In _X Al _Y Ga _1- XYN layer is preferably larger than zero and 0.1 or less, and the aluminum composition Y of the In _X Al _Y Ga _1- XYN layer is 0. .15 or better. _{In X Al Y Ga 1-X} -Y N layer aluminum composition Y of may be 0.35 or less. InAlGaN having this composition can contribute to the reduction of the offset voltage.

  The group III nitride crystal layer 15 can have the following structure.

  For example, as shown in FIG. 2A, the group III nitride crystal layer 15 includes a plurality of group III nitride films 16a, 16b, 16c, 16d, 16e, and 16f having different compositions of constituent elements. Can do. The plurality of group III nitride films 16a to 16f are arranged in the direction of the normal axis Ax of the main surface 13a of the gallium oxide substrate 13 and the normal vector NV. Each of group III nitride films 16a to 16f is made of, for example, an InAlGaN layer or an AlGaN layer. The band gaps of the group III nitride films 16 a to 16 f become smaller in the direction from the gallium oxide substrate 13 to the semiconductor stack (gallium nitride semiconductor layer) 17. The film thickness of each of group III nitride films 16a to 16f can be 10 nm or more and 100 nm or less.

  By using the group III nitride crystal layer 15 including a plurality of InAlGaN layers, the lattice constant difference between the group III nitride crystal layer 15 and the regions 13 and 17 adjacent to the group III nitride crystal layer 15 is reduced. it can. Therefore, in the nitride-based semiconductor element 11, not only the offset voltage but also the lattice constant difference between the group III nitride crystal layer 15 and the semiconductor layer adjacent to this layer can be reduced.

  Alternatively, the group III nitride crystal layer 15 can include a group III nitride layer 14 having a gradient in the composition of the constituent elements, as shown in FIG. When the composition of an element smaller than the atomic radius of gallium, for example, aluminum as a constituent element, decreases in the direction from the gallium oxide substrate 13 to the semiconductor stack (gallium nitride semiconductor layer) 17, the band of the group III nitride layer 14 in the same direction. The gap becomes smaller. Further, when the composition of an element larger than the atomic radius of gallium, for example, indium as a constituent element, increases in the direction from the gallium oxide substrate 13 to the semiconductor stack (gallium nitride semiconductor layer) 17, the group III nitride layer 14 in the same direction. Band gap is reduced. It is convenient to perform a composition gradient on a single constituent element. When the group III nitride layer 14 includes a plurality of group III constituent elements, a composition gradient can be applied to one or a plurality of constituent elements.

  The group III nitride crystal layer 15 can include an InAlGaN layer having a gradient composition. The band gap of the InAlGaN layer decreases in the direction from the gallium oxide substrate 13 to the semiconductor stack (gallium nitride semiconductor layer) 17. Since group III nitride crystal layer 15 includes an InAlGaN layer having a composition gradient, the difference in lattice constant between group III nitride crystal layer 15 and regions 13 and 17 adjacent to this layer can be reduced. Therefore, in this nitride semiconductor device 11, the offset voltage and the lattice constant difference can be reduced.

  Referring to FIG. 1 again, in the nitride semiconductor device 11, the semiconductor stack 17 may include an active layer 27 and a p-type gallium nitride semiconductor layer 29. The gallium oxide substrate 13 has conductivity, and the gallium oxide substrate 13 exhibits n conductivity by addition of a dopant to gallium oxide. The active layer 27 is provided between the GaN semiconductor layer 25 and the p-type gallium nitride semiconductor layer 29. In the present embodiment, the nitride-based semiconductor element 11 is a light emitting element that emits light in response to application of current. The semiconductor multilayer 17 includes one or a plurality of gallium nitride based semiconductor layers (in this embodiment, a GaN layer 25 and an InGaN layer 31) provided between the group III nitride crystal layer 15 and the active layer 27. If necessary, the semiconductor stack 17 includes one or a plurality of gallium nitride semiconductor layers (undoped GaN layer 33 in this embodiment) provided between the p-type gallium nitride semiconductor layer 29 and the active layer 27. Can be included. In this embodiment, the GaN semiconductor layer 25 is provided between the gallium oxide substrate 13 and the active layer 25. This nitride-based semiconductor element 11 can reduce an offset voltage between gallium oxide and a semiconductor stack made of a gallium nitride-based semiconductor provided thereon, and can be applied to, for example, a light-emitting element.

  In the nitride semiconductor device 11, the active layer 27 can have, for example, a single quantum well structure or a multiple quantum well structure. The multiple quantum well structure includes alternately arranged barrier layers 27a and well layers 27b. The well layer 27b can be made of a gallium nitride semiconductor containing indium as a constituent element, such as InGaN, InAlGaN, or the like, and the barrier layer 27a can be made of a gallium nitride semiconductor, such as GaN, InGaN, InAlGaN, or the like. The p-type gallium nitride based semiconductor layer 29 can include an electron block layer 29a, a p-type gallium nitride based semiconductor layer 29b, and a p-type contact layer 29c.

  FIG. 3 is a drawing showing the main steps of a method for forming an epitaxial wafer and a method for manufacturing a semiconductor device according to the present embodiment. FIG. 4 is a view showing a gallium oxide substrate for an epitaxial wafer according to the present embodiment. FIG. 5 is a diagram illustrating a sequence for growing a group III nitride layer and a semiconductor stack. 6 and 7 are drawings schematically showing main steps of the forming method and the manufacturing method according to the present embodiment.

In step S101 of the process flow shown in FIG. 3, a gallium oxide substrate is prepared. Referring to FIG. 4 (a), a substrate 41 such as a gallium oxide wafer is shown. The gallium oxide substrate 41 includes a main surface 41a and a back surface 41b. This gallium oxide wafer is made of, for example, β-Ga ₂ O ₃ single crystal. The gallium oxide wafer includes a front surface and a back surface opposite to the front surface, and the front surface and the back surface are parallel to each other. The main surface 41a of the substrate 41 is, for example, a (100) plane of monoclinic gallium oxide. The main surface 41a can be inclined at an angle of, for example, 1 degree or less with respect to the (100) plane. FIG. 4A shows a crystal coordinate system CR, which has an a-axis, a b-axis, and a c-axis.

  Referring to FIG. 4B, a crystal lattice of monoclinic gallium oxide is shown. The lattice constants of the a-axis, b-axis, and c-axis of the monoclinic gallium oxide crystal lattice are 1.223 nm, 0.304 nm, and 0.58 nm, respectively. Vectors Va, Vb, and Vc indicate the directions of the a-axis, b-axis, and c-axis, respectively. The vectors Va and Vb define the (001) plane, the vectors Vb and Vc define the (100) plane, and the vectors Vc and Va define the (010) plane. The angle α formed by the vectors Va and Vb and the angle γ formed by the vectors Vb and Vc are 90 degrees, and the angle β formed by the vectors Vc and Va is 103.7 degrees. In order to show the inclination angle AOFF of the wafer main surface 11a, the main surface 41a is shown by a one-dot chain line in FIG.

  In step S102, the substrate 41 is disposed on the susceptor 10a of the growth reactor 10.

  In step S103, a group III nitride crystal layer is formed on the main surface 41a of the gallium oxide substrate 41 according to the sequence shown in FIG. In step S104, at time t0, the substrate temperature of the gallium oxide substrate 41 is started to increase in the nitrogen atmosphere toward the first film formation temperature TG1 for the subsequent growth of the group III nitride layer. At time t1, the film formation temperature TG1 is reached. The temperature at the film formation temperature TG1 of the group III nitride layer is 600 degrees Celsius or more and 700 degrees Celsius or less. The group III nitride layer is grown by, for example, a metal organic chemical vapor deposition (MOVPE) method. As shown in FIG. 6A, the temperature of the gallium oxide substrate 41 in the growth furnace 10 is changed while supplying the gas G0 to the growth furnace 10. The gas G0 is made of, for example, nitrogen gas substantially not containing hydrogen. Since the gallium oxide substrate 41 is in contact with the nitrogen supplied to the growth furnace 10, the gallium oxide substrate 41 is not attacked by hydrogen. Therefore, the substrate temperature can be increased compared to when hydrogen is supplied to the growth reactor 10. After the substrate temperature of the gallium oxide substrate 11 reaches the film formation temperature TG1, the substrate temperature of the gallium oxide substrate 41 is maintained at a temperature of 600 degrees Celsius, for example.

In step S105, at time t2 when the gallium oxide substrate 41 reaches a sufficiently stable first film formation temperature TG1, a film formation gas G1 is supplied to the growth reactor 10 as shown in FIG. A group III nitride layer 43 is grown. In step S105, at time t2, in addition to nitrogen (N ₂ ), an organic group III compound and a nitrogen source are supplied to the growth reactor 10, and growth of the group III nitride layer 43 is started on the main surface 41a. The group III nitride layer 43 is made of a group III nitride containing Al as at least a group III element, such as AlGaN and InAlGaN. When the group III nitride layer 43 is made of AlGaN, the growth reactor 10 includes, for example, a raw material containing nitrogen, a gallium raw material (trimethylgallium: TMG), an aluminum raw material (trimethylaluminum: TMA), and a nitrogen raw material (ammonia: NH ₃ ). Gas G1 is supplied. Alternatively, when the group III nitride layer 43 is made of InAlGaN, the growth reactor 10 includes, for example, nitrogen, a gallium source (trimethylgallium: TMG), an indium source (trimethylindium: TMI), an aluminum source (trimethylaluminum: TMA), and A source gas G1 containing a nitrogen source (ammonia: NH ₃ ) is supplied.

After the film formation of the group III nitride layer 43 is started, in step S105, supply of hydrogen (H ₂ ) is started in addition to the organometallic compound and the nitrogen raw material. In this embodiment, supply of hydrogen is started at time t3. When the group III nitride layer 43 is made of AlGaN, hydrogen, nitrogen, TMG, TMA, and ammonia are supplied to the growth reactor 10 at time t3. According to this method, the use of hydrogen reduces the contamination of impurities into the group III nitride layer 43. If necessary, the supply amount of nitrogen can be decreased after the supply of hydrogen is started, and the supply of nitrogen is preferably stopped during the growth of the group III nitride layer 43. In this embodiment, the supply amount of nitrogen is reduced between times t3 and t4, and the supply of nitrogen is stopped at time t4. Further, the supply amount of hydrogen is increased between times t3 and t4, and the increase in hydrogen is stopped at time t4 to supply a certain amount of hydrogen. At time t4, for example, hydrogen, TMG, TMA, and ammonia are supplied to the growth reactor 10. Therefore, the period from time t3 to t4 is a gas switching period. During the period from time t4 to time t5, for example, hydrogen, TMG, TMA, and ammonia are supplied to the growth reactor 10, and the remainder of the group III nitride layer 43 is grown.

  According to this method, since the supply of hydrogen is started during the growth of the group III nitride layer 43 without supplying hydrogen to the growth reactor 10a before the start of the growth of the group III nitride layer 43, the hydrogen is contained. It is possible to prevent the gallium oxide substrate 41 from being directly exposed to the atmosphere. Since the growth furnace 10a is in a nitrogen atmosphere at the start of growth of the group III nitride layer 43 and at the beginning of growth, the group III nitride layer 43 can be formed at a temperature of 600 ° C. or more. Since the supply of hydrogen to the growth furnace 10a is started during the growth of the group III nitride layer 43, the quality of the group III nitride layer 43 is improved. Further, the growth temperature of the group III nitride layer 43 may be 700 degrees Celsius or less. This is to prevent a reaction between the group III nitride layer 43 and the substrate 41 or damage to the substrate during the formation of the group III nitride layer 43.

  The thickness of the group III nitride layer 43 may be 1 micrometer or more. This is because unevenness such as pits does not occur on the surface of the nitride layer 43 according to this thickness. In addition, the quality of the gallium nitride based semiconductor layer grown on the group III nitride layer 43 is improved. The thickness of the group III nitride layer 43 may be 20 micrometers or less. According to this thickness, peeling of the gallium nitride semiconductor does not occur.

  Next, after the supply of TMG and TMA is stopped and the formation of the group III nitride layer 43 is completed, the substrate temperature of the gallium oxide substrate 41 is changed to the heat treatment temperature for annealing in step S106. At time t6, the substrate temperature starts to rise. During this temperature change, for example, hydrogen and ammonia are supplied to the growth furnace 10. At the time t8, the second film formation temperature TG2 is reached. Thereafter, the substrate temperature of the gallium oxide substrate 41 is maintained at the second film formation temperature TG2.

  In this embodiment, in step S106, heat treatment of the group III nitride layer 43 grown on the gallium oxide substrate 41 is performed in the growth furnace as shown in FIG. 7A during the period of time t7 to t8 to t9. 10 to form a group III nitride crystal layer 43. This heat treatment is performed at a temperature TAN higher than the growth temperature TG1, and the heat treatment temperature can be, for example, 1000 degrees Celsius or more, and can be 1100 degrees Celsius or less. During the heat treatment period, for example, a gas G2 containing ammonia and hydrogen is supplied to the growth reactor 10. Since the group III nitride layer 43 is grown at a relatively low temperature, recrystallization may occur during the heat treatment period.

  By the heat treatment, a group III nitride crystal layer 45 is formed so as to cover the entire main surface 41a of the gallium oxide substrate 41. The group III nitride crystal 45 is made of a group III nitride containing aluminum as a group III constituent element and containing at least two kinds of constituent elements other than aluminum. The band gap of group III nitride crystal layer 45 is larger than the band gap of the first semiconductor layer (for example, GaN) of the semiconductor stack grown on group III nitride crystal layer 45 in a later step. The band gap of the group III nitride crystal layer 45 is smaller than 4.8 electron volts.

  In step S107, after the temperature change is completed, in the growth furnace 10, a semiconductor stack for the group III nitride semiconductor element is grown on the group III nitride crystal layer 45 to form an epitaxial substrate. The semiconductor stack includes one or more hexagonal gallium nitride semiconductor epitaxial layers (hereinafter referred to as “epitaxial layers”) 47. The epitaxial layer 47 has a band gap smaller than that of gallium oxide. The band gap of the group III nitride crystal layer 45 is a value between the band gap of gallium oxide and the band gap of the epitaxial layer 47.

  In this embodiment, at times t10 to t11, in addition to hydrogen and ammonia, a raw material G3 containing an organic group III element source gas for a group III constituent element of the epitaxial layer 15 to be grown is supplied to the growth reactor 10. . This film formation is performed at the second film formation temperature TG2. In this embodiment, an organic group III element source gas G 2 such as TMG is supplied to grow a gallium nitride layer on the group III nitride crystal layer 45. The band gap of this GaN layer is smaller than that of gallium oxide. The band gap of the group III nitride crystal layer 45 is a value between the band gap of gallium oxide and the band gap of the GaN layer. Therefore, although the band gap difference between the band gap of gallium oxide and the band gap of the GaN layer is large, the heterojunction between the group III nitride crystal layer 45 and the gallium oxide substrate 41, and the group III nitride crystal layer 45 and GaN. By utilizing the heterojunction with the layer, the group III nitride crystal layer 45 can contribute to the reduction of the offset voltage of the semiconductor element.

  The semiconductor stack is composed of a hexagonal group III nitride layer such as GaN, AlGaN, InGaN, InAlGaN, or the like. The film thickness of the semiconductor stack can be, for example, 1 micrometer or more. Further, the film thickness of the semiconductor stack can be 20 micrometers or less. When the semiconductor laminated epitaxial layer 47 is made of GaN, the growth reactor 10 is supplied with a source gas G3 containing trimethylgallium (TMG) and ammonia. The growth temperature of GaN can be, for example, 900 degrees Celsius or more and 1200 degrees Celsius or less. The growth temperature of AlGaN can be, for example, 900 degrees Celsius or higher and 1300 degrees Celsius or lower. The growth temperature of InGaN can be, for example, not less than 600 degrees Celsius and not more than 1000 degrees Celsius. The growth temperature of InAlGaN can be, for example, 600 degrees Celsius or more and 1200 degrees Celsius or less.

Also, the semiconductor stack includes at least one semiconductor layer constituting a gallium nitride based semiconductor device, and the semiconductor layer can be undoped, p-type dopant added, and n-type dopant. In order to impart p conductivity or n conductivity to the epitaxial layer of the semiconductor stack, a dopant gas is supplied in addition to the source gas when the epitaxial layer 15 is grown. As the dopant, cyclopentadienyl magnesium (Cp ₂ Mg) can be used for p-type conductivity, and silane (eg, SiH ₄ ) can be used for n-type conductivity.

  When the main surface 41a of the gallium oxide substrate 41 is substantially a (100) plane, according to this method, the gallium nitride based semiconductor grown on the gallium oxide substrate 41 has a substantially c-plane surface.

  In the single crystal gallium oxide substrate 41, the a-axis lattice constant in the group III nitride crystal layer is between the b-axis lattice constant in the gallium oxide substrate 41 and the a-axis lattice constant in GaN. By applying the group III nitride crystal layer 45, the difference in lattice constant between the group III nitride crystal layer 45 and the region 47 adjacent to the group III nitride crystal layer 45 can be reduced. Therefore, not only the offset voltage of this nitride-based semiconductor element but also the lattice constant difference can be reduced.

  When the nitride-based semiconductor element is a light-emitting element (for example, a light-emitting diode), the epitaxial layer grown on the group III nitride crystal layer 45 has the first conductivity type. The first conductivity type epitaxial layer is made of hexagonal group III nitride such as n-type GaN, n-type AlGaN, n-type InAlGaN, or the like. When the first conductivity type epitaxial layer is made of GaN, AlGaN, InAlGaN, or the like, a source gas containing hydrogen, TMG, ammonia and silane is supplied to the growth furnace 10 to grow an n-type GaN film. When the first conductivity type epitaxial layer is made of GaN, the growth temperature of the first conductivity type epitaxial layer is in a range of, for example, 900 degrees Celsius or more and 1200 degrees Celsius or less, and the first conductivity type epitaxial layer includes a gallium nitride based semiconductor device. It is a semiconductor layer to constitute. Next, an active layer is formed on the first conductivity type epitaxial layer. The active layer includes well layers and barrier layers arranged alternately. The well layer is made of, for example, GaN, InGaN, InAlGaN, or the like. The barrier layer is made of, for example, GaN, InGaN, InAlGaN, or the like. The growth temperature of the well layer is, for example, in the range of 500 degrees Celsius or more and 900 degrees Celsius or less, and the growth temperature of the barrier layer is, for example, in the range of 550 degrees Celsius or more and 950 degrees Celsius or less. Thereafter, a second conductivity type epitaxial layer is formed on the active layer. The second conductivity type epitaxial layer can include, for example, a p-type electron block layer and a p-type contact layer. When the second conductivity type epitaxial layer is made of GaN, AlGaN, or InAlGaN, the growth temperature of the second conductivity type epitaxial layer is, for example, 1000 degrees Celsius.

  An epitaxial substrate can be obtained by the conventional deposition of a gallium nitride based semiconductor.

  Referring again to FIG. 3, in step S108, first and second electrodes are formed on the epitaxial substrate. For example, the first electrode is formed on the upper surface of the semiconductor stack of the epitaxial wafer, and the second electrode is formed on the rear surface of the epitaxial wafer. Through these steps, a substrate product for a gallium nitride based semiconductor light emitting device is produced. According to this method, a semiconductor light emitting device, a substrate product therefor, and an epitaxial substrate therefor can be produced on the gallium oxide substrate 41.

  According to this method, the group III nitride layer 43 is grown at the above growth temperature so as to cover the entire main surface 41a of the gallium oxide substrate 41, and the group III nitride layer 43 is heat-treated at a temperature higher than this growth temperature. To form a group III nitride crystal layer 45. Thereafter, a semiconductor stack for the nitride-based semiconductor element is grown on the group III nitride crystal layer 45. The band gap of the group III nitride crystal layer 45 is larger than the band gap of the gallium nitride semiconductor layer and smaller than 4.8 electron volts. Therefore, in the manufacture of the nitride-based semiconductor element, it is possible to reduce the offset voltage caused by forming the gallium oxide substrate 41 and the gallium nitride semiconductor having a smaller band gap on the gallium oxide substrate 41.

Example 1
Between the gallium oxide substrate and the GaN epitaxial _layer, using the Al _Z Ga _1-Z N device structure sandwiching a (0 <Z <0.5) layer was performed device simulations. FIG. 8A shows a device structure for device simulation. The device structure is defined using cylindrical coordinates based on the Z axis and the radius R. A device for simulation includes a substrate (thickness 10 micrometers, carrier concentration 5 × 10 ¹⁸ cm ⁻³ ), an AlGaN layer on the substrate, and a GaN layer (thickness 5 micrometers, carrier concentration 5 on the AlGaN layer). × 10 ¹⁸ cm ⁻³ ) and a cylindrical shape with a radius of 15 micrometers. A cathode is provided on the back surface of the substrate, and an anode is provided on the GaN layer. Using a model of the diode structure _was calculated the relationship between the _{Al Z Ga 1-Z N (} 0 <Z <0.5) different Al composition and the forward voltage Vf of the layer.

FIG. 8B is a diagram showing a device simulation result representing the relationship between the Al composition and the forward voltage Vf.
Al composition, forward voltage Vf
0.0, 0.525
0.1, 0.38
0.2, 0.28
0.3, 0.27
0.4, 0.35
0.5, 0.525.
The forward voltage at the Al composition (0.1 ≦ Z ≦ 0.4) is smaller than the forward voltage when the Al composition is zero and 0.5. Further, the forward voltage in the Al composition (0.2 ≦ Z ≦ 0.3) is smaller than the forward voltage in the Al compositions 0.1 and 0.4. As a result, when a group III nitride crystal layer made of AlGaN having an Al composition (0.2 ≦ Z ≦ 0.3) is used, the offset voltage is about half that of the direct contact between the gallium oxide and the GaN layer. Reduced to. The offset voltage can also be reduced by sandwiching AlGaN or InAlGaN having a step-like composition change that gradually changes the band gap stepwise between GaN and gallium oxide.

The above AlGaN (band gap Eg: 3.4 eV <Eg <4.8 eV) is interposed between the GaN (band gap: 3.4 eV) epitaxial growth film and the Ga ₂ O ₃ (band gap: 4.8 eV) substrate. Thus, the offset voltage generated between the GaN (3.4 eV) epitaxial growth film and the Ga ₂ O ₃ (4.8 eV) substrate can be reduced.

The group III nitride crystal layer can be composed of a single film or a multilayer film. The group III nitride crystal layer can have a substantially single composition in a single film, or the group III nitride crystal layer can have a graded composition of one or more constituent elements. Therefore, the group III nitride crystal layer can have a stepped or sloped band gap. For example, a ternary or quaternary mixed crystal having a band gap that changes stepwise or slopes in the range of 3.4 eV ≦ Eg ≦ 4.8 eV can be used. The group III nitride crystal layer can include, for example, InAlGaN in which the composition of at least one of Al and In changes monotonously or InAlGaN in which at least one of Al and In changes gradually. The InAlGaN multilayer film has a multilayer structure in which a layer closer to a Ga ₂ O ₃ substrate has a higher band gap and a layer closer to a semiconductor layer (for example, a GaN layer) has a lower band gap. When the Al composition of AlGaN is about 0.5, the band gap of AlGaN is about the same as the band gap of gallium oxide. In addition, since undoped InAlGaN has a high resistance, it is preferable to use n-type doping in InAlGaN in order to make use of the conductivity of the substrate. Since the reverse withstand voltage remains relatively large, when an LED structure is formed on the GaN epitaxial growth film, the n-electrode is preferably a gallium oxide substrate rather than an epitaxial film.

(Example 2)
A diode having a structure as shown in FIG. 9A was manufactured as an example of an electronic device. In this diode, an n-type GaN layer (thickness 3 μm) was grown on an n-type gallium oxide substrate (thickness 400 μm) via a group III nitride crystal layer (thickness 10 nm). A cathode electrode was formed on the back surface of the gallium oxide substrate, and an anode electrode (Schottky electrode) was formed on the surface of the n-type GaN layer. In the diode of FIG. 9B, an n-type GaN layer having a thickness of 3 μm was grown on an n-type gallium oxide substrate having a thickness of 400 μm via an Al _0.22 Ga _0.78 N layer. In the diode of FIG. 9C, an n-type GaN layer (thickness 3 μm) was grown on an n-type gallium oxide substrate (thickness 400 μm) via an AlN layer (thickness 10 nm). The offset voltage of the diode of FIG. 9C was reduced to about 0.3 volts compared to the diode of FIG. 9B. In these measurements, the offset voltage was defined by the intersection with the voltage axis of the approximate line.

(Example 3)
An InAlGaN layer was grown on a Ga ₂ O ₃ substrate to produce an epitaxial stack of LED structures using the following growth sequence. A Ga ₂ O ₃ substrate is set in a metal organic chemical vapor deposition (MOVPE) apparatus. After forming the nitrogen atmosphere in the growth apparatus, the substrate temperature is raised to a temperature of 600 degrees Celsius to 700 degrees Celsius (preferably 600 degrees Celsius). After the substrate temperature is stabilized, ammonia that is one of the source gases is supplied to the growth apparatus together with the nitrogen gas. Further, the group III raw materials TMA, TMI and TMG are supplied to the growth apparatus together with nitrogen gas and ammonia to start growing the InAlGaN layer. After the start of growth, the atmosphere gas is switched from nitrogen to hydrogen while supplying group V and group III source gases. Subsequently, an InAlGaN layer is grown. Thereby, it can be avoided that Ga ₂ O ₃ of the substrate is etched by hydrogen. By using the nitrogen atmosphere only at the initial stage of film formation, the group III nitride layer can be grown while protecting the Ga ₂ O ₃ substrate even at a relatively high temperature. While continuing to flow nitrogen gas and ammonia, the supply of TMA, TMI and TMG is stopped, and the growth of the InAlGaN layer is completed. Since this InAlGaN layer is grown at a relatively low temperature, the crystallinity may not be sufficiently good. The InAlGaN layer is recrystallized at an annealing temperature ranging from 1000 degrees Celsius to 1100 degrees Celsius. Ammonia and TMG are supplied to the growth apparatus, and a GaN epitaxial film is formed on the recrystallized InAlGaN layer. On top of this, epitaxial growth for a light emitting element or epitaxial growth for a vertical electronic device is performed. The offset voltage between the Ga ₂ O ₃ substrate (band gap 4.8 eV) and GaN (band gap 3.4 eV) epitaxial film can be 0.5 volts or less, or 0.3 volts or less, and even better The characteristic can be 0.2 to 0.1 volts or less.

  While the principles of the invention have been illustrated and described in the preferred embodiments, it will be appreciated by those skilled in the art that the invention can be modified in arrangement and detail without departing from such principles. Although the nitride semiconductor light emitting element such as a light emitting diode has been described in the present embodiment, the present invention is not limited to the specific configuration disclosed in the present embodiment. In this embodiment, a nitride semiconductor light emitting element is described as an example of a nitride semiconductor element. However, a nitride semiconductor element is, for example, a vertical transistor (for example, a vertical field effect transistor or a vertical HEMT). ) And vertical diodes (such as vertical pn diodes or vertical Schottky diodes). We therefore claim all modifications and changes that come within the scope and spirit of the following claims.

DESCRIPTION OF SYMBOLS 10 ... Growth furnace, 10a ... Susceptor, 11 ... Nitride type | system | group semiconductor element, 13 ... Gallium oxide board | substrate, 14 ... Group III nitride layer of composition inclination, 15 ... Group III nitride crystal layer, 16a, 16b, 16c, 16d 16e, 16f ... Group III nitride film, 17 ... Semiconductor stack, 19 ... First electrode, 21 ... Second electrode, 13a ... Main surface of gallium oxide substrate, 13b ... Back surface of gallium oxide substrate, 23a, 23b ... Hetero Junction (interface), 25 ... GaN semiconductor layer, 27 ... active layer, 29 ... p-type gallium nitride semiconductor layer, 31 ... InGaN layer, 33 ... undoped GaN layer, 27a ... barrier layer, 27b ... well layer, 29a ... electrons Block layer, 29b ... p-type gallium nitride based semiconductor layer, 29c ... p-type contact layer, 41 ... gallium oxide substrate, 41a ... gallium oxide substrate main surface, 41b ... gallium oxide substrate back surface, 3 ... III nitride layer, 45 ... III nitride crystal, 47 ... epitaxial layer

Claims (19)

A conductive gallium oxide substrate having a main surface and a back surface;
A group III nitride crystal layer covering the main surface of the gallium oxide substrate;
A semiconductor stack comprising a heterojunction with the group III nitride crystal layer and including a gallium nitride semiconductor layer;
A first electrode provided on the semiconductor stack;
A second electrode provided on the back surface of the gallium oxide substrate ;
With
The band gap of the group III nitride crystal layer is larger than the band gap of the gallium nitride semiconductor layer,
The band gap of the group III nitride crystal layer is smaller than 4.8 electron volts,
The group III nitride crystal layer, Ri Do III nitride containing at least two structural elements other than aluminum with contains aluminum as a group III constituent element,
The group III nitride crystal layer comprises _{In X Al Y Ga 1-X} -Y N layers,
Indium composition X of the In _X Al _Y Ga _1-XY N layer is 0.1 or less,
The aluminum composition Y of the In _X Al _Y Ga _1-XY N layer is 0.15 or more,
The nitride semiconductor device according to claim _1, wherein the In _X Al _Y Ga _1- XYN layer has an aluminum composition Y of 0.35 or less .   The nitride semiconductor device according to claim 1, wherein an offset voltage between the gallium nitride semiconductor layer closest to the substrate and the gallium oxide substrate is 0.5 V or less.   The nitride-based semiconductor device according to claim 1, wherein an offset voltage between the gallium nitride semiconductor layer closest to the substrate and the gallium oxide substrate is 0.3 V or less.   The nitride-based semiconductor device according to claim 1, wherein an offset voltage between the gallium nitride semiconductor layer closest to the substrate and the gallium oxide substrate is 0.2 V or less. The group III nitride crystal layer includes an n-type dopant,
The nitride semiconductor device according to claim 1, wherein the concentration of the n-type dopant is 1 × 10 ¹⁶ cm ⁻³ or more. The group III nitride crystal layer includes a plurality of InAlGaN layers arranged in a direction of a normal axis of the main surface of the gallium oxide substrate,
6. The nitride system according to claim 1, wherein a band gap of the plurality of InAlGaN layers decreases in a direction from the gallium oxide substrate to the gallium nitride semiconductor layer. Semiconductor element. The group III nitride crystal layer includes an InAlGaN layer having a gradient composition,
7. The nitride-based semiconductor device according to claim 1, wherein a band gap of the InAlGaN layer decreases in a direction from the gallium oxide substrate to the gallium nitride semiconductor layer. . The gallium oxide substrate is made of a single crystal,
The a-axis lattice constant in the group III nitride crystal layer is between the b-axis lattice constant in the gallium oxide substrate and the a-axis lattice constant in the gallium nitride semiconductor layer. The nitride semiconductor device according to claim 7 . The gallium oxide substrate has n conductivity,
The semiconductor stack includes a p-type gallium nitride based semiconductor layer and an active layer,
The gallium nitride semiconductor layer is provided between the gallium oxide substrate and the active layer,
The active layer is provided between the gallium nitride semiconductor layer and the p-type gallium nitride semiconductor layer,
The semiconductor stack includes one or more gallium nitride based semiconductor layers provided between the group III nitride crystal layer and the active layer,
The band gap of the gallium nitride based semiconductor layer is smaller than the band gap of the group III nitride crystal layer,
Is the nitride-based semiconductor device including a light-emitting element, a nitride-based semiconductor device according to any one of claims 1 to 8, characterized in that. The nitride-based semiconductor device, according to claim 1 wherein said first containing 1 and one vertical electronic device in which a current flows in the other of said first and second electrodes from the second electrode, it is characterized by The nitride-based semiconductor device according to any one of Items 9 . The nitride-based semiconductor device of claim 1 to claim 10, wherein the one from the first and second electrodes includes a first and second second current flows through the diode of the electrode, it is characterized by The nitride-based semiconductor device according to any one of the above. A method for producing a nitride-based semiconductor device, comprising:
Placing a conductive gallium oxide substrate in a growth furnace;
Increasing the temperature of the gallium oxide substrate to a temperature range of 600 degrees Celsius or more and 700 degrees Celsius or less while supplying nitrogen gas to the growth furnace;
Growing a group III nitride layer on the main surface of the gallium oxide substrate at a growth temperature within the temperature range;
Performing a heat treatment of the group III nitride layer at a temperature higher than the growth temperature to form a group III nitride crystal layer on the main surface so as to cover the main surface of the gallium oxide substrate;
Growing a semiconductor stack including a gallium nitride semiconductor layer on the group III nitride crystal layer;
Forming a first electrode on the semiconductor stack and forming a second electrode on the back surface of the gallium oxide substrate ;
With
The band gap of the group III nitride crystal layer is larger than the band gap of the gallium nitride semiconductor layer,
The band gap of the group III nitride crystal layer is smaller than 4.8 electron volts,
The group III nitride crystal layer contains aluminum as a group III constituent element. The method according to claim 12 , wherein the growth of the group III nitride layer is performed while supplying an n-type dopant to the growth furnace. The method according to claim 12 or 13 , wherein the gas supplied to the growth furnace is switched from nitrogen gas to hydrogen gas during the growth of the group III nitride layer. The group III nitride crystal layer comprises _{Al Z Ga 1-Z} N layer,
The aluminum composition Z of the Al _Z Ga _1-Z N layer is 0.2 or more and 0.3 or less,
The method according to any one of claims 12 to claim 14, wherein the band gap of the III-nitride crystal layer is in the range of less than 3.4 electron volt to 4.8 eV, characterized in that . The group III nitride crystal layer comprises _{In X Al Y Ga 1-X} -Y N layers,
Indium composition X of the In _X Al _Y Ga _1-XY N layer is 0.1 or less,
The _{In X Al Y Ga 1-X} -Y aluminum composition Y of N layers is 0.15 or more, the method according to any one of claims 12 to claim 14, characterized in that. The group III nitride crystal layer includes a plurality of InAlGaN layers arranged in the direction of the normal axis of the main surface of the gallium oxide substrate,
According to any one of the plurality of small band gap of the InAlGaN layer from the gallium oxide substrate in the direction to the gallium nitride semiconductor layer, according to claim 12 to claim 14, characterized in that, and claim 16 Way. The group III nitride crystal layer includes an InAlGaN layer having a gradient composition,
The band gap of the InAlGaN layer is reduced in the direction from the gallium oxide substrate to the gallium nitride semiconductor layer, and the band gap of the InAlGaN layer is described in any one of claims 12 to 14 and claim 16 . Method. 19. The method according to claim 12 , wherein, in the formation of the semiconductor stack, the gallium nitride semiconductor layer is grown so as to be in contact with the group III nitride crystal layer. .

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