KR20130106926A - Gallium nitride-based semiconductor device - Google Patents

Abstract

PURPOSE: A gallium nitride based semiconductor device is provided to improve the crystalline quality of semiconductor layers by arranging a middle layer between gallium nitride layers. CONSTITUTION: A lower gallium nitride layer (15) is positioned on the surface of a gallium nitride substrate. An n-type upper gallium nitride layer (19) is positioned on the upper part of the lower gallium nitride layer. A middle layer (17) is formed between the lower gallium nitride layer and an upper gallium nitride layer. The middle layer contains aluminum. The band gap of the middle layer is wider than the band gap of the gallium nitride layers. [Reference numerals] (b) Doping concentration (a. u.)

Description

Gallium nitride based semiconductor device {GALLIUM NITRIDE-BASED SEMICONDUCTOR DEVICE}

The present invention relates to a gallium nitride based semiconductor device, and more particularly to a gallium nitride based semiconductor device using a gallium nitride substrate as a growth substrate.

Gallium nitride compounds have been recognized as important materials for high power and high performance optical and electronic devices. In particular, nitrides of group III elements such as gallium nitride (GaN) have excellent thermal stability and have a direct transition type energy band structure, and thus have recently received a lot of attention as materials for light emitting devices in the visible and ultraviolet regions. have. In particular, blue and green light emitting devices using indium gallium nitride (InGaN) have been used in various applications such as large-scale color flat panel display devices, traffic lights, indoor lighting, high density light sources, high resolution output systems, and optical communications.

Such a nitride semiconductor layer of Group III elements is difficult to fabricate homogeneous substrates capable of growing them, and therefore, such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE), etc., on heterogeneous substrates having a similar crystal structure. It has been grown through the process of. A sapphire substrate having a hexagonal system structure is mainly used as a heterogeneous substrate.

However, epitaxial layers grown on dissimilar substrates have a relatively high dislocation density due to lattice mismatch with the growth substrate and differences in coefficient of thermal expansion. Epilayers grown on sapphire substrates are generally known to have dislocation densities of at least 1E8 / cm 2. The epitaxial layer having such a high dislocation density has a limit in improving the luminous efficiency of the light emitting diode.

Accordingly, studies are being made to reduce the dislocation density of gallium nitride based semiconductor layers. As one of such studies, there is an attempt to grow a semiconductor layer by using a gallium nitride substrate as a growth substrate instead of sapphire. Gallium nitride based semiconductor layers grown on gallium nitride substrates generally have better crystal quality than gallium nitride substrates grown on sapphire substrates. However, since gallium nitride substrates are relatively expensive compared to sapphire substrates, it is necessary to further improve the crystal quality of gallium nitride semiconductor layers grown on gallium nitride substrates to overcome these cost differences.

An object of the present invention is to improve the crystal quality of a gallium nitride based semiconductor layer grown on a gallium nitride substrate.

Another object of the present invention is to provide a gallium nitride based semiconductor device having excellent electrical and / or optical characteristics.

Another object of the present invention is to provide a light emitting diode that can lower the forward voltage.

A light emitting diode according to embodiments of the present invention, a gallium nitride substrate; A lower gallium nitride layer on the gallium nitride substrate; An n-type upper gallium nitride layer positioned on the lower gallium nitride layer; And an intermediate layer interposed between the lower gallium nitride layer and the upper gallium nitride layer. Here, the intermediate layer is a gallium nitride based semiconductor layer containing aluminum and having a wider band gap than the gallium nitride layer.

The intermediate layer may include an AlInN layer and may have an AlInN / GaN superlattice structure.

In some embodiments, the lower gallium nitride layer may be a semiconductor layer doped with n-type impurities, and the intermediate layer may be a semiconductor layer having a lower n-type doping concentration than the lower gallium nitride layer and the upper gallium nitride layer.

The semiconductor device may further include a p-type semiconductor layer on the upper semiconductor layer; And an active layer positioned between the p-type semiconductor layer and the n-type upper gallium nitride layer.

According to the present invention, the crystal quality of the semiconductor layers grown thereon can be improved by adopting a gallium nitride substrate, and further, the crystal quality of the semiconductor layers can be further improved by disposing the intermediate layer between the gallium nitride layers. In addition, the forward voltage of the light emitting diode may be lowered by adjusting the doping concentrations of the gallium nitride layers and the intermediate layer.

1 is a cross-sectional view illustrating a light emitting diode according to an embodiment of the present invention.
2 is for explaining an intermediate layer of a light emitting diode according to an embodiment of the present invention (a) is a schematic band diagram, (b) is a doping concentration profile.
3 is a cross-sectional view illustrating a superlattice layer according to an embodiment of the present invention.
4 is a cross-sectional view illustrating a superlattice layer according to another exemplary embodiment of the present invention.
5 is a cross-sectional view illustrating an active layer according to an embodiment of the present invention.
FIG. 6 is an energy band illustrating the active layer of FIG. 5.
7 is an optical photograph for explaining the surface morphology of the epi layer according to the use of the intermediate layer.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided by way of example so that those skilled in the art can fully understand the spirit of the present invention. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the same reference numerals denote the same elements, and the width, length, thickness, and the like of the elements may be exaggerated for convenience.

1 is a cross-sectional view illustrating a light emitting diode according to an embodiment of the present invention.

Referring to FIG. 1, the light emitting diode includes a gallium nitride substrate 11, a lower semiconductor layer 15, an intermediate layer 17, an n-type upper semiconductor layer 19, a superlattice layer 20, and an active layer 30. And a p-type semiconductor layer 43. In addition, the light emitting diode may include a p-type cladding layer 41, a transparent electrode layer 45, a first electrode 47, and a second electrode 49.

The gallium nitride substrate 11 may have a c-plane growth surface, but is not limited thereto. In addition, the growth surface of the gallium nitride substrate 11 may have an inclination angle to help the growth of the epi layer. Such gallium nitride substrate 11 can be manufactured using, for example, HVPE technology.

The lower semiconductor layer 15 is positioned on the gallium nitride substrate 11. The lower semiconductor layer 15 may be grown as a gallium nitride layer on the gallium nitride substrate 11. The lower semiconductor layer 15 may be grown to have an n-type impurity (eg, Si) concentration in the range of 5 × 10 ¹⁸ to 2 × 10 ¹⁹ / cm 3 at a temperature of about 1000 ° C. In the present embodiment, the lower semiconductor layer 15 is described as being doped with n-type impurities. In another embodiment, the lower semiconductor layer 15 may be an undoped GaN layer that is not intentionally doped with impurities. have.

The intermediate layer 17 is positioned on the lower semiconductor layer 15. The intermediate layer 17 is formed of a gallium nitride-based epi layer having a composition different from that of the lower semiconductor layer 15, and has a wider bandgap than the gallium nitride layer. For example, the intermediate layer 17 may be formed of AlInN, AlGaN or AlInGaN. In particular, the intermediate layer 17 may be formed of AlInN and may have the same lattice constant as that of the GaN layer. Furthermore, the intermediate layer 17 may have a superlattice structure in which the AlInN layer and the GaN layer are alternately stacked.

The lower semiconductor layer 15 and the n-type upper semiconductor layer 19 are grown at a high temperature of about 1000 ° C., but the intermediate layer 17 is grown at a temperature range of about 800 to 900 ° C. By forming an interlayer 17 having a different composition from GaN between the GaN layers 15 and 19, it is possible to induce strain in the upper semiconductor layer 19 formed on the interlayer 17, thereby using the crystalline structure of the multi-quantum well structure. Can improve. Furthermore, as shown in FIG. 2A, an intermediate layer 17 having a relatively wide bandgap is positioned between the GaN layers 15 and 19, thereby providing the GaN layers 15 and 19 using a two-dimensional electron gas. Current can be distributed evenly within

In addition, as shown in FIG. 2B, the intermediate layer 17 is formed to have a lower doping concentration than the upper semiconductor layer 19. For example, the intermediate layer 17 may have an n-type impurity (eg, Si) concentration of 1 × 10 ¹⁷ to 1 × 10 ¹⁸ / cm 3, and the upper semiconductor layer 19 may have 5 × 10 ¹⁸ to 2 × 10 ^19. It may have an n-type impurity concentration of / cm 3. Since the intermediate layer 17 has a doping concentration in the above concentration range, it is possible to lower the forward voltage of the light emitting diode while growing a good crystalline semiconductor layer.

In addition, the n-type upper semiconductor layer 19 is grown on the intermediate layer 17 as a gallium nitride layer. Meanwhile, the n electrode 47 may be positioned on the upper semiconductor layer 19. In the present embodiment, although the upper semiconductor layer 19 is shown as a single GaN layer, the n electrode 47 is located thereon, but is not limited thereto. That is, other gallium nitride based semiconductor layer (s) may be located between the n electrode 47 and the upper semiconductor layer 19.

Meanwhile, a superlattice layer 20 having a multilayer structure may be located on the n-type upper semiconductor layer 19. The superlattice layer 20 is located between the n-type upper semiconductor layer 19 and the active layer 30, and thus is located on the current path. The superlattice layer 20 may be formed by repeatedly stacking a pair of InGaN / GaN (for example, 15 to 20 cycles), but is not limited thereto. For example, as shown in FIG. 3, the three-layer structure of the InGaN layer 21 / AlGaN layer 22 / GaN layer 23 has a plurality of cycles (for example, about 10 to 20 cycles). ) May have a repeatedly stacked structure. The order of the AlGaN layer 22 and the InGaN layer 21 may be reversed. Here, the InGaN layer 21 has a wider band gap than the well layer in the active layer 30. In addition, the AlGaN layer 22 preferably has a wider band gap than the barrier layer in the active layer 30. Further, the InGaN layer 21 and the AlGaN layer 22 may be formed of an undoped layer that is not intentionally doped with impurities, and the GaN layer 23 may be formed of a Si doped layer. The uppermost layer of the superlattice layer 20 is preferably a GaN layer 23 doped with impurities.

By including the AlGaN layer 22 in the superlattice layer 20, it is possible to block holes in the active layer 30 from moving toward the n-type upper semiconductor layer 19, thereby improving the recombination rate of light emission in the active layer 30. Can be. The AlGaN layer 22 may be formed to a thickness of less than 1 nm.

On the other hand, since the superlattice layer 20 forms the AlGaN layer 22 on the InGaN layer 21, lattice mismatch between them is large and crystal defects are likely to be formed at the interface. Therefore, the GaN layer 24 can be inserted between the InGaN layer 21 and the AlGaN layer 22 as shown in FIG. 4. The GaN layer 24 may be formed of an undoped layer or a Si doped layer.

The active layer 30 of the multi-quantum well structure is positioned on the superlattice layer 20. As shown in FIG. 5, the active layer 30 has a structure in which barrier layers 31a and 31b and well layers 33n, 33, and 33p are alternately stacked. Here, 33n represents a well layer (first well layer) closest to the superlattice layer 20 or the n-type upper semiconductor layer 19, and 33p represents the p-type cladding layer 41 or the p-type semiconductor layer 23. The well layer (nth well layer) closest to) is shown. 6 illustrates an energy band of the active layer 30.

5 and 6, the (n-1) plurality of barrier layers 31a and 31b and the (n-2) plurality of well layers between the well layer 33n and the well layer 33p. The fields 33 are stacked alternately with each other. The barrier layers 31a have a thickness thicker than the average thickness of these (n-1) plurality of barrier layers 31a 31b, and the barrier layers 31b have a thickness thinner than the average thickness. Further, as shown, the barrier layers 31a are disposed close to the first well layer 33n and the barrier layers 31b are disposed close to the nth well layer 33p.

In addition, the barrier layer 31a may be positioned in contact with the uppermost layer of the superlattice layer 20. That is, the barrier layer 31a may be located between the superlattice layer 20 and the first well layer 33n. In addition, the barrier layer 35 may be positioned on the nth well layer 33p. The barrier layer 35 may have a relatively thicker thickness than the barrier layer 31a.

A relatively thin thickness of the barrier layers 31b close to the nth well layer 33p reduces the resistive component of the active layer 30 and also injects holes injected from the p-type semiconductor layer 43 into the active layer 30. It is possible to disperse the well layers 33, thereby lowering the forward voltage of the light emitting diode. In addition, by relatively thickening the thickness of the barrier layer 35, the crystallization of epitaxial layers formed thereon to heal crystal defects generated during the growth of the active layer 30, especially the well layers 33n, 33, 33p. Can be improved. However, when the number of the barrier layers 31b is greater than the number of the barrier layers 31a, the defect density may increase in the active layer 30, thereby reducing the light emission efficiency. Therefore, it is preferable to form the number of the barrier layers 31a more than the number of the barrier layers 31b.

On the other hand, the well layers 33n, 33, 33p may have almost the same thickness as each other, thereby emitting light having a very small half width. Alternatively, the thicknesses of the well layers 33n, 33, and 33p may be adjusted differently to emit light having a relatively wide half width. Furthermore, by making the thickness of the well layer 33 positioned between the barrier layers 31b relatively thin compared to the well layer 33 positioned between the barrier layers 31a, it is possible to prevent the formation of crystal defects. Can be. For example, the thickness of the well layers 33n, 33, 33p is, for example, in the range of 10 to 30 kPa, the thickness of the barrier layers 31a is in the range of 50 to 70 kPa, and the thickness of the barrier layers 31b. The thickness may be in the range of 30 to 50 mm 3.

In addition, the well layers 33n, 33, 33p may be formed of a gallium nitride based layer that emits light in the near ultraviolet or blue region. For example, the well layers 33n, 33, 33p may be formed of InGaN, and the In composition ratio is adjusted according to a required wavelength.

On the other hand, the barrier layers 31a and 31b are gallium nitride based layers having a wider bandgap than the well layers 33n, 33, 33p to trap electrons and holes in the well layers 33n, 33, 33p. Is formed. For example, the barrier layers 31a and 31b may be formed of GaN, AlGaN or AlInGaN. In particular, the barrier layers 31a and 31b may be formed of a gallium nitride based layer containing Al to further increase the band gap. The composition ratio of Al in the barrier layers 31a and 31b is preferably greater than 0 and less than 0.1, and in particular, may be 0.02 to 0.05. The light output can be increased by limiting the Al composition ratio within the above range.

In addition, a cap layer may be formed between the well layers 33n, 33, 33p and the barrier layers 31a and 31b disposed thereon. The cap layer is formed to prevent the well layer from being damaged while raising the chamber temperature to grow the barrier layers 31a and 31b. For example, the well layers 33n, 33, 33p may be grown at a temperature of about 780 ° C, and the barrier layers 31a, 31b may be grown at a temperature of about 800 ° C.

The p-type cladding layer 41 is positioned on the active layer 30 and may be formed of AlGaN. Alternatively, the p-type cladding layer 41 may have a superlattice structure in which InGaN / AlGaN is repeatedly stacked. The p-type cladding layer 41 is an electron blocking layer, and blocks electrons from moving to the p-type semiconductor layer 43 to improve luminous efficiency.

Referring back to FIG. 1, the p-type semiconductor layer 43 may be formed of GaN doped with Mg. The p-type semiconductor layer 43 is located on the p-type cladding layer 41. On the other hand, a transparent conductive layer 45 such as ITO or ZnO is formed on the p-type semiconductor layer 43 to make ohmic contact with the p-type semiconductor layer 43. Thus, the p-type semiconductor layer 43 functions as a p-type contact layer. On the other hand, the second electrode 49 is electrically connected to the p-type semiconductor layer 43. The second electrode 49 may be connected to the p-type semiconductor layer 43 through the transparent conductive layer 45.

Meanwhile, a portion of the p-type semiconductor layer 43, the p-type cladding layer 41, the active layer 30, and the superlattice layer 20 may be removed by an etching process to expose the n-type upper semiconductor layer 19. . The first electrode 47 may be formed on the exposed n-type upper semiconductor layer 19. Thus, the n-type upper semiconductor layer 19 functions as an n-type contact layer.

In the present embodiment, the epitaxial layers 15 to 43 grown on the gallium nitride substrate 11 may be formed using a MOCVD technique. In this case, TMAl, TMGa, and TMIn may be used as the sources of Al, Ga, and In, and NH3 may be used as the source of N. In addition, SiH 4 may be used as a source of Si which is an n-type impurity, and Cp ₂ Mg may be used as a source of Mg that is a p-type impurity.

Experimental Example

7 is an optical photograph for explaining the surface morphology of the epi layer according to the use of the intermediate layer. Where (a) is an n-type GaN layer 19, a superlattice layer 20, an active layer 30, a p-type AlGaN cladding layer 41 and a p-type GaN layer 43 on the gallium nitride substrate 11 without an intermediate layer. ), and then the surface photograph of a p-type GaN layer 43 taken by an optical microscope, after growing, (b) is Al _{0 .8} of less than 10nm between the lower GaN layer 15 and the n-type GaN layer 19 in _{0 .2} N intermediate layer 17 and the formation, n-type GaN layer 19 in the super lattice layer 20, an active layer (30), p-type AlGaN cladding layer 41 and p-type GaN layer 43 After growing in order, the surface photograph of the p-type GaN layer 43 taken with the optical microscope is shown. The gallium nitride substrate 11 used a c-plane growth substrate, and the substrate 11 had dislocation defect lines Ld formed parallel to the surface thereof. The lower GaN layer 15 and the n-type upper GaN layer 19 were formed under the same growth conditions at a temperature of about 1050 ° C to 1100 ° C, and the intermediate layer 17 was grown at a temperature of about 830 ° C.

Referring to FIG. 7A, when the intermediate layer 17 is not formed, the surface of the p-type GaN layer 43 as a final epitaxial layer is very rough. Crystal defect lines Ld of the substrate 11 are transferred to the p-type GaN layer 43 and observed on the surface. The surface appears worse at these crystal defect lines Ld. Furthermore, it can be seen that the surface of the region between the crystal defect lines Ld is also formed very roughly.

Referring to FIG. 7B, when the intermediate layer 17 is formed, the surface of the region between the crystal defect lines Ld is very smooth as well as the crystal defect lines Ld as compared to FIG. 7A. You can also see that the epi layer was cleanly grown.

In addition, light emitting diodes separated from each other on the gallium nitride substrate 11 were fabricated to compare the forward voltage according to whether the intermediate layer 17 was used at the wafer level. When the lower GaN layer 15 and the upper GaN layer 19 are relatively doped and the intermediate layer 17 is lightly doped, the forward voltage of the light emitting diodes using the intermediate layer 17 does not use the intermediate layer 17. It was about 0.13V smaller than the light emitting diodes. On the contrary, when the impurity was not doped in the intermediate layer 17, the forward voltage was similar to that of the light emitting diodes not using the intermediate layer 17.

Accordingly, it can be seen that the use of the intermediate layer 17 and the doping of impurities at a relatively low concentration in the intermediate layer 17 can improve the crystal quality and lower the forward voltage.

In the present embodiment, the light emitting diode has been described as an example, but the present invention is not limited to the light emitting diode and can be applied to all kinds of semiconductor devices employing a gallium nitride based semiconductor layer. Furthermore, in certain applications, the intermediate layer need not necessarily be an n-type semiconductor layer doped with n-type impurities, but may also be an undoped layer.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments or constructions. Various changes and modifications may be made without departing from the spirit and scope of the invention. have.

Claims (9)

Gallium nitride substrates;
A lower gallium nitride layer on the gallium nitride substrate;
An n-type upper gallium nitride layer positioned on the lower gallium nitride layer; And
Including an intermediate layer interposed between the lower gallium nitride layer and the upper gallium nitride layer,
And the intermediate layer is a gallium nitride based semiconductor layer containing aluminum and having a wider bandgap than the gallium nitride layer. The method according to claim 1,
The intermediate layer comprises an AlInN layer. The method according to claim 2,
The intermediate layer has a superlattice structure in which an AlInN layer and a GaN layer are alternately stacked. The method according to claim 2,
And the AlInN layer has the same lattice constant as the gallium nitride layer. The method according to claim 1,
The lower gallium nitride layer is a semiconductor layer doped with n-type impurities,
And the intermediate layer is a semiconductor layer having a lower n-type doping concentration than the lower gallium nitride layer and the upper gallium nitride layer. The method according to claim 5,
A p-type semiconductor layer on the upper semiconductor layer; And
And an active layer between the p-type semiconductor layer and the n-type upper gallium nitride layer. The method of claim 6,
An n-type electrode electrically connected to the upper gallium nitride layer; And
And a p-type electrode electrically connected to said p-type semiconductor layer. The method of claim 7,
And the n-type electrode is positioned above the intermediate layer and electrically connected to the upper gallium nitride layer. The method of claim 6,
The semiconductor device further comprises a superlattice layer of a multi-layer structure positioned between the upper gallium nitride layer and the active layer.

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