WO2013141618A1

WO2013141618A1 - Gallium nitride-based semiconductor device

Info

Publication number: WO2013141618A1
Application number: PCT/KR2013/002327
Authority: WO
Inventors: 정정환; 김재헌; 최승규
Original assignee: 서울옵토디바이스주식회사
Priority date: 2012-03-21
Filing date: 2013-03-21
Publication date: 2013-09-26
Also published as: KR20130106926A

Abstract

Disclosed is a gallium nitride-based semiconductor device. The semiconductor device comprises: a gallium nitride substrate; a lower gallium nitride layer formed on the gallium nitride substrate; an n-type upper gallium nitride layer formed on the lower gallium nitride layer; and an intermediate layer interposed between the lower gallium nitride layer and the upper gallium nitride layer. Here, the intermediate layer is a gallium nitride-based semiconductor layer that contains aluminum and has a band gap wider than that of a gallium nitride layer. The present invention provides a gallium nitride-based semiconductor layer having superior crystal quality on a gallium nitride substrate by adopting an intermediate layer.

Description

【Specification】

[Name of invention]

Gallium nitride based semiconductor device

Technical Field

The present invention relates to a gallium nitride based semiconductor device, and more particularly to a gallium nitride based semiconductor device using a gallium nitride substrate as a growth substrate.

Background Art

Gallium nitride compounds have been recognized as important materials for high power and high performance optical and electronic devices. In particular, nitrides of group m elements such as gallium nitride (GaN) have excellent thermal stability and have a direct transition type energy band structure, and thus have recently received a lot of attention as materials for light emitting devices in the visible and ultraviolet regions. have. In particular, blue and green light emitting devices using indium gallium nitride (InGaN) have been used in a variety of applications including large-scale color flat panel display devices, traffic lights, indoor lighting, high density light sources, high resolution output systems, and optical communications.

Since the nitride semiconductor layer of Group III elements is difficult to fabricate homogeneous substrates capable of growing it, metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) is performed on heterogeneous substrates having similar crystal structures. It has been grown through such a process. As a hetero substrate, a sapphire substrate having a hexagonal structure is mainly used.

However, epitaxial layers grown on heterogeneous substrates have relatively high dislocation densities due to lattice mismatch with the growth substrate and differences in thermal expansion coefficients. Epilayers grown on sapphire substrates are generally known to have dislocation densities of lE8 / cuf or more. The epitaxial layer having such a high dislocation density has a limit in improving the luminous efficiency of the light emitting diode.

Accordingly, a research to reduce the dislocation density of gallium nitride based semiconductor layer It's going on. As one of such studies, there is an attempt to grow a semiconductor layer by using a gallium nitride substrate as a growth substrate instead of sapphire. Gallium nitride-based semiconductor insects grown on gallium nitride substrates generally have better crystal quality than gallium nitride substrates grown on sapphire substrates. However, since gallium nitride substrates are relatively expensive compared to sapphire substrates, it is necessary to further improve the crystal quality of gallium nitride semiconductor layers grown on gallium nitride substrates in order to overcome such cost differences.

[Detailed Description of the Invention]

[Technical Challenges]

An object of the present invention is to improve the crystal quality of a gallium nitride based semiconductor layer grown on a gallium nitride substrate.

Another object of the present invention is to provide a gallium nitride-based semiconductor device excellent in electrical and / or optical properties.

Another object of the present invention is to provide a light emitting diode that can lower the forward voltage.

Technical Solution

A light emitting diode according to embodiments of the present invention, a gallium nitride substrate; A lower gallium nitride layer on the gallium nitride substrate; An n-type upper gallium nitride layer positioned on the lower gallium nitride layer; And an intermediate layer interposed between the lower gallium nitride layer and the upper gallium nitride layer. Here, the intermediate layer is a gallium nitride-based semiconductor layer containing aluminum and has a band ¾ wider than the gallium nitride layer.

The intermediate layer may include an AlInN layer, and may have an AlInN / GaN superlattice structure.

In some embodiments, the lower gallium nitride layer is doped with n-type impurities The intermediate layer may be a semiconductor layer having a lower _n- type doping concentration than the lower gallium nitride layer and the upper gallium nitride layer.

The semiconductor device may further include a p-type semiconductor layer on the upper semiconductor layer; And an active layer positioned between the p-type semiconductor layer and the n-type upper gallium nitride layer.

Advantageous Effects

According to the present invention, the crystal quality of semiconductor layers grown thereon can be improved by adopting a gallium nitride substrate, and further, the crystal quality of semiconductor layers can be further improved by arranging intermediate charges between the gallium nitride layers. . In addition, the forward voltage of the light emitting diode may be lowered by adjusting the doping concentrations of the gallium nitride layers and the intermediate layer.

[Brief Description of Drawings]

1 is a cross-sectional view illustrating a light emitting diode according to an embodiment of the present invention.

2 is for explaining an intermediate layer of a light emitting diode according to an embodiment of the present invention (a) is a schematic band diagram, (b) is a doping concentration profile.

3 is a cross-sectional view illustrating a superlattice layer according to an embodiment of the present invention.

4 is a cross-sectional view illustrating a superlattice layer according to another exemplary embodiment of the present invention.

5 is a cross-sectional view illustrating an active layer according to an embodiment of the present invention. FIG. 6 is an energy band illustrating the active layer of FIG. 5.

7 is an optical photograph for explaining the surface morphology of the epi layer according to the use of the intermediate layer. [Form for implementation of invention]

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided as examples to enable those skilled in the art to fully convey the spirit of the present invention. Accordingly, the present invention is not limited to the embodiments described below and may be embodied in other forms. In the drawings, the same reference numerals denote the same components, and the width, length, thickness, etc. of the components may be exaggerated for convenience.

Referring to FIG. 1, the light emitting diode includes a gallium nitride substrate 11, a lower semiconductor layer 15, an intermediate layer 17, an n-type upper semiconductor layer 19, a superlattice layer 20, and an active layer 30. And a p-type semiconductor layer 43. Furthermore, the light emitting diode may include a p-type cladding layer 41, a transparent electrode layer 45, a first electrode 47, and a second electrode 49.

The gallium nitride substrate 11 may have a c-plane growth surface, but is not limited thereto. In addition, the growth surface of the gallium nitride substrate 11 may have an inclination angle to help the growth of the epi layer. Such gallium nitride substrate 11 can be produced, for example, using HVPE technology.

The lower semiconductor layer 15 is positioned on the gallium nitride substrate 11. The lower semiconductor layer 15 may be grown as a gallium nitride layer on the gallium nitride substrate 11. The lower semiconductor layer 15 is 5xl0 ¹⁸ ~ 2xl0 ¹⁹ / ciii ^! It can be grown to have a concentration of n-type impurities (eg, Si). In this embodiment, the lower semiconductor layer 15 is described as being doped with n-type impurities. In another embodiment, the lower semiconductor layer 15 may be an undoped GaN layer intentionally doped with no impurities. have. The intermediate layer 17 is positioned on the lower semiconductor layer 15. The intermediate layer 17 is formed of a gallium nitride-based epi layer having a composition different from that of the lower semiconductor layer 15, and has a wider band gap than the gallium nitride layer. For example, the intermediate layer 17 may be formed of AlInN, AlGaN or AlInGaN. In particular, the intermediate layer 17 may be formed of AlInN and may have the same lattice constant as that of the GaN layer. Furthermore, the intermediate layer 17 may have a superlattice structure in which the AlInN layer and the GaN layer are alternately stacked. The lower semiconductor layer 15 and the n-type upper semiconductor layer 19 are grown at a high temperature of about 100 CTC, but the intermediate layer 17 is grown at a temperature range of about 800 to 900 ^° C. By forming an intermediate layer 17 having a different composition from GaN between the GaN layers 15 and 19, strain may be induced in the upper semiconductor layer 19 formed on the intermediate layer 17, and the multi-quantum well structure is determined using the intermediate layer 17. It can improve quality. Furthermore, ^• GaN layers (15, 19) between in Fig. 2 (a) one by a position intermediate layer 17 having a relatively wide band gap, using the two-dimensional electron gas the GaN layers, as shown in (15, 19) The current can be evenly distributed in the circuit.

In addition, as shown in FIG. 2B, the intermediate layer 17 is formed to have a lower doping concentration than the upper semiconductor layer 19. For example, the intermediate layer 17 may have an n-type impurity (eg, Si) concentration of lxi0 ¹⁷ to lxl0 ¹⁸ / cirf, and the upper semiconductor layer 19 may have a η-type impurity concentration of δΧΐΟ ^ ΖΧΐΟ ¹⁹ / ^. Can be. Since the intermediate layer 17 has a doping concentration in the above concentration range, it is possible to grow a good crystalline semiconductor layer while lowering the forward reflection voltage of the light emitting diode.

In addition, the η-type upper semiconductor layer 19 is grown on the intermediate layer 17 as a gallium nitride layer. Meanwhile, the ^η electrode 47 may be positioned on the upper semiconductor layer 19. In the present embodiment, the upper semiconductor layer 19 is shown as a single GaN layer, and the n electrode 47 is positioned thereon, but is not limited thereto. no. In other words, another gallium nitride based semiconductor layer (s) may be disposed between the _n electrode 47 and the upper semiconductor layer 19.

Meanwhile, a superlattice layer 20 having a multilayer structure may be positioned on the n-type upper semiconductor layer 19. The superlattice layer 20 is located between the n-type upper semiconductor layer 19 and the active layer 30, and thus is located on the current path. The superlattice layer 20 may be formed by repeatedly stacking a pair of InGaN / GaN (for example, 15 to 20 cycles), but is not limited thereto. For example, as shown in FIG. 3, the superlattice layer 20 has a three-layer structure having an InGaN layer 21 / AlGaN layer 22 / GaN layer 23 having a plurality of cycles (for example, about 10 to 20 cycles). ) May have a repeatedly stacked structure. The order of the AlGaN layer 22 and the InGaN layer 21 may be reversed. Here, the InGaN layer 21 has a wider band gap than the well layer in the active layer 30. In addition, the AlGaN layer 22 preferably has a wider bandgap than the barrier layer in the active layer 30. In addition, the InGaN layer 21 and the AlGaN layer 22 may be formed of an undoped layer that is not intentionally doped with impurities, and the GaN layer 23 may be formed of a Si doped layer. The uppermost layer of the superlattice layer 20 is preferably a GaN layer 23 doped with impurities.

By including the AlGaN charge 22 in the superlattice layer 20, it is possible to block holes in the active layer 30 from moving toward the _n- type upper semiconductor layer 19, thereby improving the recombination rate of light emission in the active layer 30. Can kill. The AlGaN layer 22 may be formed to a thickness of less than lnm.

On the other hand, since the superlattice layer 20 forms the AlGaN layer 22 on the InGaN layer 21, the lattice mismatch between them is large, and crystal defects are likely to form at the interface. Therefore, the GaN layer 24 can be inserted between the InGaN layer 21 and the AlGaN layer 22 as shown in FIG. The GaN layer 24 may be formed of an undoped layer or a Si doped layer. The active layer 30 of the multi-quantum well structure is positioned on the superlattice layer 20. As shown in FIG. 5, the active layer 30 has a structure in which barrier layers 3 la and 31b and well layers 33η, 33, 33ρ are alternately stacked. Here, 33η represents the well layer (first well layer) closest to the superlattice layer 20 or the η-type upper semiconductor layer 19, and 33ρ is the ρ-type cladding layer 41 or the ρ-type semiconductor layer 23. The well layer (the (eta) well layer) closest to) is shown. 6 shows an energy band of the active layer 30.

5 and 6, a plurality of (η-1) barrier layers 31a and 31b and (n-2) a plurality of well layers between the well worm 33η and the well layer 33ρ. The fields 33 are stacked alternately with each other. The barrier layers 31a have a thickness thicker than the average thickness of these (n-1) plurality of barrier layers 31a 31b, and the barrier layers 31b have a thickness thinner than the average thickness. Further, as shown, barrier layers 31a are disposed close to the first well layer 33η, and barrier layers 31b are disposed close to the nth well layer 33p.

Furthermore, the barrier layer 31a may be located in contact with the uppermost layer of the superlattice layer 20. That is, the barrier layer 31a may be located between the superlattice layer 20 and the first well layer 33η. In addition, the barrier layer 35 may be positioned on the nth well layer 33p. The barrier layer 35 may have a relatively thicker thickness than the barrier layer 31a.

I, by reducing the thickness of the near barrier layers (31b) on In the well layer (33p) to the ^"relative decrease a resistance component of the active layer 30, and also the active layer 30, the holes injected from the p-type semiconductor layer 43 It can be dispersed in the well layers 33 in the interior, thereby lowering the forward voltage of the light emitting diode. In addition, by relatively thickening the barrier layer 35, the crystal defects generated during the growth of the active layer 30, especially the well layers 33? It can be improved. However, than the number of the barrier layers 31a When the number of the barrier layers 31b is increased, the defect density increases in the active layer 30 and thus the luminous efficiency may be reduced. Therefore, it is preferable to form the number of the barrier layers 31a more than the number of the barrier layers 31b.

Meanwhile, the well layers 33η, 33, and 33ρ may have almost the same thickness, and thus may emit light having a very small half width. Alternatively, the thicknesses of the well layers 33η, 33 and 33ρ may be adjusted differently to emit light having a relatively wide half width. Furthermore, the crystal defect is generated by making the thickness of the well layer 33 positioned between the barrier layers 3 lb relatively thin, compared to the well layer 33 positioned between the barrier layers 31a. It can prevent. For example, the thickness of the well layers 33η, 33, 33ρ is, for example, in the range of 10 to 30 A, the thickness of the barrier layers 3 la is in the range of 50 to 70 A, and the barrier layers 31b. ) May have a thickness in the range of 30-50A.

In addition, the well layers 33η, 33, 33ρ may be formed of a gallium nitride-based layer that emits light in the near ultraviolet or blue region. For example, the well layers 33 ^η , 33, 33ρ may be formed of InGaN, and the In composition ratio is adjusted according to the required wavelength.

On the other hand, the barrier layers 31a and 31b are gallium nitride based having a wider bandgap than the well layers 33η, 33 and 33ρ to trap electrons and holes in the well layers 33η, 33 and 33ρ. It is formed into layers. For example, the barrier layers 31a and 31b may be formed of GaN, AlGaN or AlInGaN. In particular, the barrier layers 31a and 31b may be formed of a gallium nitride based layer containing A1 to further increase the band gap. The composition ratio of A1 in the barrier layers 3 la and 31b is preferably greater than 0 and less than 0.1, and in particular, may be from 02 to 0.05. The light output can be increased by limiting the A1 composition ratio within the above range.

In addition, each of the well layers 33η, 33 and 33ρ and the barrier layers 31a disposed thereon Although not shown between 31b), a cap layer may be formed. The cap layer is formed to prevent the well layer from being damaged while lowering the chamber temperature to grow the barrier layers 31a and 31b. For example, the well layers 33η, 33, 33ρ may be grown at a temperature of about 780 ^° C, and the barrier layers 31a, 31b may be grown at a temperature of about 800 ^° C. The p-type cladding layer 41 is positioned on the active layer 30 and may be formed of AlGaN. Alternatively, the p-type cladding layer 41 may be formed in a superlattice structure in which InGaN / AlGaN is repeatedly stacked. The p-type cladding layer 41 is an electron blocking layer, and blocks electrons from moving to the P-type semiconductor layer 43 to improve luminous efficiency.

Referring back to FIG. 1, the p-type semiconductor layer 43 may be formed of GaN doped with Mg. The p-type semiconductor layer 43 is located on the p-type cladding layer 41. On the other hand, a transparent conductive layer 45 such as ITO or Zn® is formed on the P-type semiconductor layer 43 so that the p-type semiconductor layer 43 can be in ohmic contact. Thus, the p-type semiconductor layer 43 functions as a p-type contact layer. On the other hand, the second electrode 49 is electrically connected to the p-type semiconductor layer 43. The second electrode 49 may be connected to the p-type semiconductor layer 43 through the transparent conductive layer 45. ᅳ

Meanwhile, a portion of the p-type semiconductor layer 43, the p-type cladding layer 41, the active layer 30, and the superlattice layer 20 may be removed by an etching process to expose the n-type upper semiconductor layer 19. The first electrode 47 may be formed on the exposed n-type upper semiconductor layer 19. Therefore, the n-type upper semiconductor layer 19 functions as an n-type contact layer. The epitaxial layers 15 to 43 grown on the gallium nitride substrate 11 may be formed using a MOCVD technique, in which TMAl, TMGa, and TMIn may be used as the sources of Al, Ga, and In, respectively. In addition, NH3 may be used as a source of N. In addition, SiH4 may be used as a source of Si, which is an n-type impurity, and Cp ₂ Mg may be used as a source of Mg, which is a p-type impurity. (Experimental example)

7 is an optical picture for explaining the surface morphology of the epi layer according to the use of the intermediate layer. Where (a) is an n-type GaN layer 19, a superlattice layer 20, an active layer 30, a p-type AlGaN cladding layer 41 and a p-type GaN layer 43 on a gallium nitride substrate 11 without an intermediate layer. ) Is a surface photograph of the p-type GaN layer 43 photographed by optical microscopy after growth), and (b) is less than 10 nm of Al ₀ between the lower GaN layer 15 and the n-type GaN layer 19. _{An 8} In _0.2 N intermediate layer 17 is formed, and the superlattice layer 20, the active layer 30, the p-type AlGaN cladding layer 41 and the p-type GaN layer 43 are formed on the n-type GaN layer 19. After growing in turn, the surface photograph of the p-type GaN layer 43 taken with the optical microscope is shown. The gallium nitride substrate 11 used a c-plane growth substrate, and the substrate 11 had dislocation defect lines Ld formed parallel to the surface thereof. The lower GaN layer 15 and the n-type upper GaN layer 19 were formed under the same growth conditions at a temperature of about 1050 ^° C. to 1100 ^° C., and the intermediate layer 17 was grown at a temperature of about 83 CTC. .

Referring to FIG. 7A, when the intermediate layer 17 is not formed, the surface of the p-type GaN layer 43 as a final epitaxial layer is very rough. Crystal defect lines Ld of the substrate 11 are transferred to the p-type GaN layer 43 and observed on the surface. In these crystal defect lines Ld the surface appears to be worse. Moreover, it can be seen that the surface of the region between the crystal defect lines Ld is also formed very roughly. Referring to FIG. 7B, when the intermediate layer 17 is formed, the surface of the region between the crystal defect lines Ld is very smooth, as well as the crystal defect lines Ld, in contrast to FIG. 7A. You can also see that the epi layer grows clean.

In addition, light emitting diodes separated from each other on the gallium nitride substrate 11 were fabricated to compare the forward voltage according to the use of the intermediate layer 17 at the wafer level. When the lower GaN layer 15 and the upper GaN layer 19 are relatively doped and the intermediate layer 17 is lightly doped, the light emitting diodes using the intermediate layer 17 The forward voltage was generally about 0.13V lower than that of light emitting diodes without the intermediate layer 17. On the contrary, when the impurity was not doped in the intermediate layer 17, the forward voltage was similar to that of the light emitting diodes without the intermediate layer 17.

. Accordingly, it can be seen that the use of the intermediate layer 17 and the doping of impurities at a relatively low concentration in the intermediate layer 17 can improve the crystal quality and lower the forward voltage.

Although the light emitting diode has been described as an example in the present embodiment, the present invention is not limited to the light emitting diode and can be applied to all kinds of semiconductor devices employing a gallium nitride based semiconductor layer. Furthermore, in a specific example, the intermediate layer need not necessarily be an n-type semiconductor layer doped with n-type impurities, or may be an undoped layer.

In the above, various embodiments and features of the present invention have been described, but the present invention is not limited to the embodiments and features described above, and various modifications may be made without departing from the spirit of the present invention. have.

Claims

[Range of request]

[Claim 1]

Gallium nitride substrates;

A lower gallium nitride layer on the gallium nitride substrate;

An n-type upper gallium nitride layer positioned on the lower gallium nitride layer; And an intermediate layer interposed between the lower gallium nitride layer and the upper gallium nitride layer.

The intermediate layer is a gallium nitride-based semiconductor layer containing aluminum and has a band ¾ wider than the gallium nitride layer.

[Claim 2]

The method according to claim 1,

The intermediate layer comprises an AlInN layer.

[Claim 3]

The method according to claim 2,

The intermediate layer has a superlattice structure in which an AlInN layer and a GaN layer are alternately stacked.

[Claim ⁴ ]

The method according to claim 2,

And the AlInN layer has the same lattice constant as the gallium nitride layer.

[Claim 5]

The method according to claim 1,

The lower gallium nitride layer is a semiconductor layer doped with n-type impurities,

And the intermediate layer is a semiconductor layer having a lower n-type doping concentration than the lower gallium nitride layer and the upper gallium nitride layer.

[Claim 6] The method according to claim 5,

A p-type semiconductor layer on the upper semiconductor layer; And

And an active layer between the p-type semiconductor layer and the n-type upper gallium nitride layer.

[Claim 7]

The method according to claim 6,

An n-type electrode electrically connected to the upper gallium nitride layer; And

And a p-type electrode electrically connected to the p-type semiconductor layer.

[Claim 8]

The method according to claim 7,

And the n-type electrode is positioned above the intermediate layer and electrically connected to the upper gallium nitride layer.

[Claim 9]

The method according to claim 6,

And a superlattice layer having a multilayer structure positioned between the upper gallium nitride layer and the active layer.