WO2016152106A1 - Semiconductor wafer, semiconductor device, and semiconductor wafer manufacturing method - Google Patents

Semiconductor wafer, semiconductor device, and semiconductor wafer manufacturing method Download PDF

Info

Publication number
WO2016152106A1
WO2016152106A1 PCT/JP2016/001529 JP2016001529W WO2016152106A1 WO 2016152106 A1 WO2016152106 A1 WO 2016152106A1 JP 2016001529 W JP2016001529 W JP 2016001529W WO 2016152106 A1 WO2016152106 A1 WO 2016152106A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
iii nitride
group iii
nitride semiconductor
semiconductor layer
Prior art date
Application number
PCT/JP2016/001529
Other languages
French (fr)
Japanese (ja)
Inventor
哲生 成田
紘子 井口
伊藤 健治
伸幸 大竹
真一 星
Original Assignee
株式会社デンソー
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社デンソー filed Critical 株式会社デンソー
Publication of WO2016152106A1 publication Critical patent/WO2016152106A1/en

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02455Group 13/15 materials
    • H01L21/02458Nitrides
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/34Nitrides
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02Epitaxial-layer growth
    • C30B25/16Controlling or regulating
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10Inorganic compounds or compositions
    • C30B29/38Nitrides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02494Structure
    • H01L21/02496Layer structure
    • H01L21/02505Layer structure consisting of more than two layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02538Group 13/15 materials
    • H01L21/0254Nitrides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/80Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/812Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate

Definitions

  • the present disclosure relates to a semiconductor wafer, a semiconductor device, and a method for manufacturing a semiconductor wafer.
  • Patent Document 1 discloses a technique for growing a buffer layer on a silicon substrate and growing a group III nitride semiconductor layer (main functional layer) on the buffer layer.
  • high concentration (1 ⁇ 10 18 cm ⁇ 3 ) carbon is introduced into the buffer layer and / or the buffer layer side of the group III nitride semiconductor layer.
  • the group III nitride semiconductor is heated from a high temperature (during vapor phase growth) to a low temperature (typically room temperature). It is known that a tensile strain is generated in a group III nitride semiconductor when cooled to a low temperature.
  • a group III nitride semiconductor layer is grown on a buffer layer having a compressive strain to cancel tensile strain generated in the group III nitride semiconductor layer.
  • An object of the present disclosure is to provide a semiconductor wafer having a smooth surface of a group III nitride semiconductor layer, a manufacturing method thereof, and a semiconductor device including the semiconductor wafer while preventing leakage current from flowing.
  • the semiconductor wafer includes a substrate, a buffer layer provided on the substrate, and a group III nitride semiconductor layer provided on the buffer layer.
  • the buffer layer has a smaller lattice constant than the group III nitride semiconductor layer.
  • the group III nitride semiconductor layer contains carbon.
  • the peak of the carbon concentration of the group III nitride semiconductor layer is the group III nitride semiconductor. Located away from both the front and back of the layer.
  • the group III nitride semiconductor layer contains carbon, a leakage current of a semiconductor device manufactured using the semiconductor wafer can be prevented.
  • the carbon concentration in the middle part of the group III nitride semiconductor layer a position away from both the front surface and the back surface
  • the carbon concentration necessary to prevent leakage current is set to the group III nitride semiconductor layer.
  • the carbon concentration of the group III nitride semiconductor layer can be lowered on the buffer layer side (the back side of the group III nitride semiconductor layer). By suppressing the carbon concentration on the buffer layer side, it is possible to suppress the occurrence of strain-induced step bunching in the group III nitride semiconductor layer.
  • the semiconductor wafer described above can smooth the surface of the group III nitride semiconductor layer while preventing leakage current from flowing.
  • a semiconductor device includes a substrate, a buffer layer provided on the substrate, a group III nitride semiconductor layer provided on the buffer layer, and a group III nitride semiconductor layer. And a semiconductor element.
  • the lattice constant (average lattice constant) of the buffer layer is smaller than the lattice constant (average lattice constant) of the group III nitride semiconductor layer.
  • the group III nitride semiconductor layer contains carbon.
  • the peak of the carbon concentration of the group III nitride semiconductor layer is the same as the surface of the group III nitride semiconductor layer. Located away from both sides.
  • a method for manufacturing a semiconductor wafer including a substrate and a group III nitride semiconductor layer provided on the substrate includes forming a buffer layer and a group III nitride semiconductor layer. Forming. In forming the buffer layer, a buffer layer having a lattice constant smaller than that of the group III nitride semiconductor layer is vapor-phase grown on the substrate. In forming the group III nitride semiconductor layer, the group III nitride semiconductor layer is vapor-phase grown on the buffer layer. The growth pressure of the group III nitride semiconductor layer is minimized during the formation of the group III nitride semiconductor layer.
  • the carbon concentration introduced into the group III nitride semiconductor layer is increased. Therefore, according to the manufacturing method described above, it is possible to manufacture a semiconductor wafer having the highest carbon concentration in the middle portion of the group III nitride semiconductor layer.
  • FIG. 4 is a photograph showing the surface of the semiconductor wafer of Experimental Example 1.
  • FIG. 3B is a diagram of the photograph of FIG. 3A.
  • 6 is a photograph showing the surface of the semiconductor wafer of Experimental Example 2.
  • FIG. 4B is a diagram of the photograph of FIG. 4A.
  • the semiconductor wafer includes a substrate, a buffer layer provided on the substrate, and a group III nitride semiconductor layer provided on the buffer layer.
  • the substrate has a smaller coefficient of thermal expansion than the group III nitride semiconductor layer.
  • the temperature integral value of the linear expansion coefficient of 300 to 1300K is smaller than the temperature integral value of the linear expansion coefficient of 300 to 1300K in the a-axis direction of the material constituting the group III nitride semiconductor layer.
  • the material of the substrate is silicon (Si) or silicon carbide (SiC).
  • the thickness of the substrate is 0.1 to 2 mm.
  • an interface layer and an aluminum nitride (AlN) layer are provided between the substrate and the buffer layer.
  • Aluminum oxide (Al2O3) can be used as the material for the interface layer.
  • the interface layer can be omitted.
  • the thickness of the aluminum nitride layer is 10 to 500 nm.
  • the aluminum nitride layer preferably has a thickness of 50 to 500 nm.
  • the thickness of the aluminum nitride layer is preferably 10 to 100 nm.
  • Aluminum nitride has the smallest lattice constant among group III nitride semiconductors.
  • the aluminum nitride layer by providing the aluminum nitride layer, a necessary amount of compressive strain can be applied to the buffer layer.
  • the interface layer and the aluminum nitride layer can be omitted, and the buffer layer can be formed directly on the surface of the substrate.
  • the buffer layer has a smaller lattice constant than the group III nitride semiconductor layer.
  • the lattice constant (average lattice constant) of the buffer layer is the lattice constant (average lattice constant) of the group III nitride semiconductor layer. Smaller than.
  • the buffer layer has a compressive strain.
  • the material of the buffer layer is AlxGa1-xN (0 ⁇ x ⁇ 1).
  • a buffer layer made of AlxGa1-xN (0 ⁇ x ⁇ 1) a multilayer structure including buffer layers having different values of “x” can be used.
  • the value of “x” becomes smaller toward the surface (the group III nitride semiconductor layer side). That is, it is preferable that the buffer layer made of AlxGa1-xN (0 ⁇ x ⁇ 1) has a smaller Al composition toward the surface.
  • the buffer layer a multilayer structure in which different materials are repeatedly stacked can be used.
  • the buffer layer may be repeatedly provided with a laminated structure of AlN and GaN.
  • the buffer layer may be repeatedly provided with a laminated structure of AlN and AlGaN.
  • the thickness of the buffer layer can be 0.5 to 10 ⁇ m.
  • the “buffer layer” in the present embodiment does not mean a so-called “low-temperature buffer layer” for reducing the lattice constant difference between the substrate and the group III nitride semiconductor layer, but a group III nitride. This is to apply a surface force to the semiconductor layer to alleviate thermal strain generated in the group III nitride semiconductor layer when the group III nitride semiconductor layer changes from a high temperature to a low temperature after film formation.
  • the buffer layer has a smaller lattice constant than the group III nitride semiconductor layer
  • the buffer layer has a lattice constant (average lattice constant) when the entire buffer layer and the entire group III nitride semiconductor layer are compared. ) Is smaller than the lattice constant (average lattice constant) of the group III nitride semiconductor layer. Therefore, when comparing a part of the buffer layer and a part of the group III nitride semiconductor layer, the lattice constant of a part of the buffer layer may be larger than the lattice constant of a part of the group III nitride semiconductor layer.
  • the group III nitride semiconductor layer contains carbon.
  • the surface on the buffer layer side of the group III nitride semiconductor layer is the back surface, and the surface opposite to the back surface is the surface.
  • the peak of the carbon concentration of the group III nitride semiconductor layer is located away from both the front surface and the back surface (surface in contact with the buffer layer) of the group III nitride semiconductor layer.
  • the carbon concentration on the surface of the group III nitride semiconductor layer is preferably lower than the carbon concentration on the back surface. Specifically, when the carbon concentration peak of the group III nitride semiconductor layer is an intermediate part, the surface side is the front part from the intermediate part, and the back side is the back part from the intermediate part.
  • a functional layer through which a current flows may be formed on the surface portion.
  • the carbon concentration of the surface (surface portion) of the group III nitride semiconductor layer is lowered, the carbon concentration of the functional layer can be kept low, and a semiconductor element with a small loss (resistance) can be obtained. Note that if the functional layer contains a large amount of carbon, the current flow may be hindered by the presence of carbon.
  • the group III nitride semiconductor layer preferably includes a plurality of layers having different concentrations of contained carbon.
  • the nitride semiconductor layer has a stacked structure in which the first layer, the second layer, and the third layer are stacked in this order from the buffer layer side, and the average value of the carbon concentration is second layer> first layer. It is preferable to satisfy the relationship. It is particularly preferable that the average value of the carbon concentration of each layer satisfies the relationship of second layer> first layer> third layer. Note that at least the first layer and the second layer preferably have a larger lattice constant than the buffer layer.
  • the material of the first layer and the second layer is preferably a group III nitride semiconductor mainly composed of gallium (Ga).
  • the “group III nitride semiconductor mainly composed of gallium” typically means gallium nitride (GaN), and as an impurity, B, Al, In, on the order of atomic percent of less than 1% with respect to GaN. Those containing elements such as S, As, and Sb are also included in the “Group III nitride semiconductor mainly composed of gallium”.
  • strain relaxation can be efficiently caused between the buffer layer and the second layer using the thin first layer.
  • the group III nitride semiconductor constituting the first layer contains a large amount of aluminum, the difference in lattice constant between the buffer layer and the first layer is small, and the thin first layer is sufficient between the buffer layer and the second layer. Distortion is less likely to occur. Further, by using a group III nitride semiconductor mainly composed of gallium as the material of the second layer, it is possible to suppress the occurrence of new strain between the first layer and the second layer. That is, since a material close to the lattice constant of the first layer is laminated as the second layer, new strain is unlikely to occur between the first layer and the second layer.
  • the thickness of the first layer is preferably 0.05 to 0.5 ⁇ m.
  • the thickness of the first layer is less than 0.05 ⁇ m, strain relaxation is not easily caused. Further, when the thickness of the first layer is thicker than 0.5 ⁇ m, the effect of suppressing the leakage current cannot be sufficiently obtained. From the viewpoint of suppressing the leakage current, more preferably, the thickness of the first layer is 0.05 to less than 0.2 ⁇ m. If the first layer is sufficiently thinner than the second layer, it is possible to prevent the leakage current suppressing effect from being lowered.
  • the carbon concentration of the first layer is preferably 1 ⁇ 10 16 to 1 ⁇ 10 18 cm ⁇ 3 . More preferably, the carbon concentration of the first layer is 1 ⁇ 10 16 to 5 ⁇ 10 17 cm ⁇ 3 . By making the carbon concentration of the first layer lower than that of the second layer, the compressive strain inherent in the buffer layer can be relaxed.
  • the thickness of the second layer is preferably 0.2 to 3.0 ⁇ m.
  • the carbon concentration of the second layer is preferably 5 ⁇ 10 17 to 1 ⁇ 10 20 cm ⁇ 3 . More preferably, the carbon concentration of the second layer is 1 ⁇ 10 18 cm ⁇ 3 to 1 ⁇ 10 20 cm ⁇ 3 from the viewpoint of suppressing leakage current. If the thickness of the second layer is sufficiently thicker than that of the first layer, the leakage current suppressing effect can be sufficiently exerted.
  • Gallium nitride can be used as the material for the third layer.
  • the third layer can be used as a functional layer (a layer constituting a semiconductor element).
  • the carbon concentration of the third layer is preferably less than 1 ⁇ 10 17 cm ⁇ 3 .
  • the third layer is substantially free of carbon.
  • the thickness of the third layer can be appropriately adjusted according to the target semiconductor device.
  • a plurality of layers (fourth layer, fifth layer, etc.) can be further provided on the surface of the third layer.
  • an HEMT (High Electron Mobility Transistor) including a heterojunction can be manufactured by forming an AlGaN layer (fourth layer) on the surface of a gallium nitride layer (third layer).
  • the semiconductor wafer 1 includes a silicon substrate 2, an interface layer 4 formed on the silicon substrate 2, an AlN layer 6 formed on the interface layer 4, a buffer layer 8 formed on the AlN layer 6, a buffer A group III nitride semiconductor layer 10 formed on the layer 8 is provided.
  • the thickness T2 of the silicon substrate 2 is 675 ⁇ m.
  • the material of the interface layer 4 is aluminum oxide.
  • the thickness T4 of the interface layer 4 is adjusted to be less than 3 nm.
  • the thickness T6 of the AlN layer 6 is adjusted to 0.3 ⁇ m.
  • the material of the buffer layer 8 is AlxGa1-xN.
  • the thickness T8 of the buffer layer 8 is adjusted to 2.5 ⁇ m.
  • the buffer layer 8 has a multilayer structure, and a layer having a larger value of “x” is formed toward the AlN layer 6 side.
  • the group III nitride semiconductor layer 10 includes a first GaN layer 10a, a second GaN layer 10b, and a third GaN layer 10c.
  • the material of the group III nitride semiconductor layer 10 is gallium nitride (GaN).
  • the first GaN layer 10a contains 2 ⁇ 10 16 cm ⁇ 3 of carbon.
  • the second GaN layer 10b contains 4 ⁇ 10 18 cm ⁇ 3 of carbon.
  • the third GaN layer 10c does not substantially contain carbon (may contain inevitable carbon).
  • the group III nitride semiconductor layer 10 is formed using a metal organic chemical vapor deposition method.
  • the thickness T10a of the first GaN layer 10a is adjusted to 0.1 ⁇ m
  • the thickness T10b of the second GaN layer 10b is adjusted to 0.5 ⁇ m
  • the thickness T10c of the third GaN layer 10c is adjusted to 0.4 ⁇ m.
  • another nitride semiconductor layer may be formed on the surface of the third GaN layer 10c.
  • the third GaN layer 10c may contain n-type impurities (Si or the like) and p-type impurities (Mg or the like).
  • the first GaN layer 10a, the second GaN layer 10b, and the third GaN layer 10c are examples of the first layer, the second layer, and the third layer, respectively.
  • a nitride stack (typically AlGaN) having a heterojunction is formed on the surface of the group III nitride semiconductor layer 10 (the surface of the third GaN layer 10c).
  • a semiconductor device having a HEMT structure that operates as a heterojunction two-dimensional electron gas and a channel can be manufactured.
  • the interface layer 4 is formed on the silicon substrate 2 using an atomic layer deposition method (ALD method). Thereafter, an AlN layer 6 and a buffer layer 8 are formed in this order on the interface layer 4 using a metal organic chemical vapor deposition method (MOCVD method) (buffer layer forming step).
  • MOCVD method metal organic chemical vapor deposition method
  • buffer layer forming step trimethylaluminum is used as the Al material, trimethylgallium is used as the Ga material, and ammonia is used as the N material.
  • the growth temperature is about 1000 ° C.
  • the first GaN layer 10a is formed on the buffer layer 8 at a growth pressure of 300 Torr.
  • the second GaN layer 10b is formed on the first GaN layer 10a at a growth pressure of 50 Torr.
  • the carbon concentration (4 ⁇ 10 18 cm ⁇ 3 ) of the second GaN layer 10 b is higher than the carbon concentration (2 ⁇ 10 16 cm ⁇ 3 ) of the first GaN layer 10 a.
  • the third GaN layer 10c is formed on the second GaN layer 10b at a growth pressure of 300 Torr.
  • the carbon concentration of the third GaN layer 10c (substantially does not contain carbon) is adjusted to be lower than the carbon concentrations of the first GaN layer 10a and the second GaN layer 10b using parameters other than the growth pressure.
  • the lattice constant (lattice constant in the a-plane direction) of the buffer layer 8 is smaller than the lattice constant of the group III nitride semiconductor layer (lattice constant in the a-plane direction of GaN) 10. Therefore, the buffer layer 8 applies compressive strain to the group III nitride semiconductor layer 10.
  • the group III nitride semiconductor layer 10 tends to undergo tensile strain in the process of temperature drop after growth.
  • the buffer layer 8 cancels the tensile strain generated in the group III nitride semiconductor layer 10 and suppresses the group III nitride semiconductor layer 10 from warping and generating cracks and the like.
  • FIG. 2 shows the carbon concentration of the group III nitride semiconductor layer 10.
  • the horizontal axis of the graph represents the carbon concentration (cm ⁇ 3 ), and the vertical axis represents each layer (first GaN layer 10a to third GaN layer 10c).
  • the carbon concentration shown in FIG. 2 has shown the average value of each layer.
  • the carbon concentration of the second GaN layer 10b is 4 ⁇ 10 18 cm ⁇ 3 .
  • the concentration of carbon contained in the GaN layer is higher than 1 ⁇ 10 18 cm ⁇ 3 , the leakage current can be suppressed.
  • the thickness T10a of the first GaN layer 10a is thinner than the thickness T10b of the second GaN layer 10b.
  • the thickness T10a is increased, the effect of suppressing leakage current may be reduced.
  • the thickness T10a thinner than the thickness T10b the effect of suppressing leakage current can be improved.
  • the carbon concentration (2 ⁇ 10 16 cm ⁇ 3 ) of the first GaN layer 10a is lower than the carbon concentration (4 ⁇ 10 18 cm ⁇ 3 ) of the second GaN layer 10b. That is, the first GaN layer 10a does not contain carbon at a concentration sufficient to suppress leakage current.
  • the first GaN layer 10a having a low carbon concentration is formed on the buffer layer 8, effective strain relaxation occurs.
  • the carbon concentration of the first GaN layer 10a is high (for example, 1 ⁇ 10 18 cm ⁇ 3 or more that is effective in suppressing leakage current)
  • the group III nitride semiconductor layer with the compressive strain of the buffer layer 8 inherently contained 10 grows. As a result, distortion-induced step bunching occurs and it is difficult to smooth the surface of the semiconductor wafer 1.
  • the characteristics of the semiconductor device may deteriorate.
  • “Distortion-induced step bunching” is a mechanism of step bunching occurrence discovered and proposed by Tersoff et al., And disclosed in “Physical Review Letters Volume 75 2730 (1995)”.
  • the mechanism is that when a strain is generated on a semiconductor surface formed by periodic step terraces, an attractive force between steps is proportional to the square of the strain and inversely proportional to the distance between steps.
  • the attractive force between steps forms a bundle of steps (step bunching) one after another, and a step is formed on the surface of the semiconductor wafer, so that the surface smoothness of the semiconductor wafer is lowered. Therefore, generation of step bunching can be suppressed by reducing the distortion of the semiconductor surface.
  • Strain-induced step bunching becomes more prominent in a wafer (so-called off-angle wafer) whose principal axis is slightly inclined with respect to a perpendicular perpendicular to the growth surface.
  • the c-axis is generally the main axis. Therefore, in the case of a group III nitride semiconductor, it can be said that the state where the c-axis is inclined with respect to the normal of the growth surface has an off angle.
  • the growth surface has a periodic structure in which step terraces are regularly repeated, and the flatness of the wafer surface can be improved.
  • the strain-induced step bunching in the nitride semiconductor layer is more prominent in a group III nitride semiconductor containing gallium as a main group element. Step bunching occurs in the process where group III atomic species on the terrace are diffused into the step edge. Therefore, step bunching is likely to occur in an environment that satisfies the condition of “average distance between steps ⁇ (1/2) ⁇ surface diffusion length of group III atomic species”. In group III atomic species, gallium is known to have a longer surface diffusion length than aluminum and indium. Therefore, strain-induced step bunching is likely to occur in a group III nitride semiconductor mainly containing gallium, particularly gallium nitride. Note that “gallium nitride” in this embodiment includes gallium nitride containing impurities (Al, In, Mg, Si, Ge, C, Fe, etc.) less than 1%.
  • the compressive strain of the buffer layer 8 is reduced in the first GaN layer 10a by making the carbon concentration of the first GaN layer 10a lower than the carbon concentration of the second GaN layer 10b.
  • the compressive strain of the buffer layer 8 is reduced in the first GaN layer 10a by making the carbon concentration of the first GaN layer 10a lower than the carbon concentration of the second GaN layer 10b.
  • the carbon concentration of the group III nitride semiconductor layer 10 can be controlled by the growth pressure of the group III nitride semiconductor layer. When other growth conditions are the same, the carbon concentration of the group III nitride semiconductor layer increases as the growth pressure decreases.
  • the carbon concentration of the second GaN layer 10b can be increased by adjusting the growth pressure low after crystal growth of the first GaN layer 10a.
  • the compressive strain of the buffer layer 8 is reduced as the thickness of the second GaN layer 10b increases.
  • the warpage of the semiconductor wafer varies depending on the product of the group III nitride semiconductor layer 10 “strain” and “film thickness”. That is, when the second GaN layer 10b is formed directly on the buffer layer 8, since the “strain” is large, the amount of warpage of the semiconductor wafer greatly changes due to a slight change in the “film thickness”. For this reason, it is difficult to control the amount of warpage of the semiconductor wafer in the method of forming the second GaN layer 10b containing high-concentration carbon thickly.
  • FIG. 3A is an optical micrograph of the surface S1 of a semiconductor wafer in which an interface layer, an AlN layer, a buffer layer, a first GaN layer, and a second GaN layer are grown in this order on a silicon substrate
  • FIG. 3B is a photograph of FIG. 3A.
  • the carbon concentration of the first GaN layer is 2 ⁇ 10 16 cm ⁇ 3 (growth pressure 300 Torr), and the carbon concentration of the second GaN layer is 4 ⁇ 10 18 cm ⁇ 3 (growth pressure 50 Torr).
  • step flow growth was confirmed, and it was confirmed that a semiconductor wafer having a smooth surface was obtained.
  • the residual strain in the a-axis direction of the GaN layer was 0.11%.
  • the c-axis of the first GaN layer 10a was inclined 0.26 degrees in the m-axis direction with respect to the normal to the growth surface.
  • FIG. 4A is an optical micrograph of the surface S2 of a semiconductor wafer in which an interface layer, an AlN layer, a buffer layer, a second GaN layer, and a first GaN layer are grown in this order on a silicon substrate
  • FIG. 4B is a photograph of FIG. 3B.
  • the order of growing the first GaN layer and the second GaN layer is opposite to that of the semiconductor wafer of Experimental Example 1. That is, in the semiconductor wafer of Experimental Example 2, the second GaN layer containing a high concentration of carbon is grown on the surface of the buffer layer.
  • the group III nitride semiconductor layer includes the first GaN layer 10a, the second GaN layer 10b, and the third GaN layer 10c has been described.
  • the present disclosure can also be applied to a semiconductor wafer in which another nitride semiconductor layer is formed on the surface of the third GaN layer 10c.
  • the first GaN layer 10a, the second GaN layer 10b, and the third GaN layer 10c are examples of a group III nitride semiconductor layer
  • the first GaN layer 10a, the second GaN layer 10b, and the third GaN layer 10c are a group III mainly composed of GaN. It can also be made of a nitride semiconductor.
  • the group III nitride semiconductor layer may have a structure in which the carbon concentration continuously changes from the back surface (buffer layer side) to the front surface.
  • the group III nitride semiconductor layer may not form a clear layer structure. Even in such a case, the peak of the carbon concentration of the group III nitride semiconductor layer is located away from both the front surface and the back surface of the group III nitride semiconductor layer. The surface of the wafer can be smoothed.
  • the semiconductor wafer 1 in which the group III nitride semiconductor layer 10 has the carbon concentration of the second GaN layer 10b> the first GaN layer 10a> the third GaN layer 10c has been described.
  • the present disclosure is effective when the peak of the carbon concentration of the group III nitride semiconductor layer is located away from both the front surface and the back surface. That is, if the condition that the carbon concentration of the second GaN layer 10b is the highest among the group III nitride semiconductor layers 10 is satisfied, the carbon concentration is: second GaN layer 10b> third GaN layer 10c> first GaN layer 10a. Even if there is an effect. If the peak of the carbon concentration of the group III nitride semiconductor layer is at a position away from both the front surface and the back surface, distortion-induced step bunching can be suppressed while suppressing leakage current.

Abstract

Disclosed is a semiconductor wafer (1) wherein a III nitride semiconductor layer (10) is provided on a substrate (2) with a buffer layer (8) therebetween. The buffer layer (8) has a lattice constant that is smaller than that of the III nitride semiconductor layer (10). The III nitride semiconductor layer (10) contains carbon. The carbon concentration peak of the III nitride semiconductor layer (10) is at a position separated from both the front surface and the rear surface of the III nitride semiconductor layer (10). As a result, the semiconductor wafer having the smooth front surface of the III nitride semiconductor layer can be achieved, while preventing a leak current from flowing.

Description

半導体ウエハ、半導体装置及び半導体ウエハの製造方法Semiconductor wafer, semiconductor device, and semiconductor wafer manufacturing method 関連出願の相互参照Cross-reference of related applications
 本出願は、2015年3月26日に出願された日本出願番号2015-64107号に基づくもので、ここにその記載内容を援用する。 This application is based on Japanese Application No. 2015-64107 filed on March 26, 2015, the contents of which are incorporated herein by reference.
本開示は、半導体ウエハ、半導体装置及び半導体ウエハの製造方法に関するものである。 The present disclosure relates to a semiconductor wafer, a semiconductor device, and a method for manufacturing a semiconductor wafer.
 基板上にIII族窒化物半導体層を気相成長させて半導体ウエハを製造する技術の研究が行われている。特許文献1には、シリコン基板上にバッファ層を成長させ、バッファ層上にIII族窒化物半導体層(主機能層)を成長する技術が開示されている。また、特許文献1では、バッファ層、及び/又は、III族窒化物半導体層のバッファ層側に高濃度(1×1018cm-3)の炭素を導入する。炭素を導入した半導体ウエハを用いて半導体装置を製造すると、半導体装置をオフしているときにリーク電流が流れることを防止することができる。なお、III族窒化物半導体層を成長させる基板としてIII族窒化物半導体より熱膨張係数が小さい材料を用いると、III族窒化物半導体が高温(気相成長中)から低温(典型的に室温)に冷却されるときに、III族窒化物半導体に引張歪みが生じることが知られている。特許文献1では、圧縮歪みを有するバッファ層上にIII族窒化物半導体層を成長することによって、III族窒化物半導体層に生じる引張歪みを相殺している。 Research has been conducted on a technique for producing a semiconductor wafer by vapor-phase-growing a group III nitride semiconductor layer on a substrate. Patent Document 1 discloses a technique for growing a buffer layer on a silicon substrate and growing a group III nitride semiconductor layer (main functional layer) on the buffer layer. In Patent Document 1, high concentration (1 × 10 18 cm −3 ) carbon is introduced into the buffer layer and / or the buffer layer side of the group III nitride semiconductor layer. When a semiconductor device is manufactured using a semiconductor wafer into which carbon is introduced, leakage current can be prevented from flowing when the semiconductor device is turned off. If a material having a smaller thermal expansion coefficient than the group III nitride semiconductor is used as the substrate on which the group III nitride semiconductor layer is grown, the group III nitride semiconductor is heated from a high temperature (during vapor phase growth) to a low temperature (typically room temperature). It is known that a tensile strain is generated in a group III nitride semiconductor when cooled to a low temperature. In Patent Document 1, a group III nitride semiconductor layer is grown on a buffer layer having a compressive strain to cancel tensile strain generated in the group III nitride semiconductor layer.
特開2010-287882号公報JP 2010-287882 A
 しかしながら、バッファ層、及び/又は、III族窒化物半導体層(主機能層)のバッファ層側に高濃度の炭素を導入すると、III族窒化物半導体層は、圧縮歪みを内在したまま成長する。その結果、III族窒化物半導体層に歪み誘因ステップバンチングが発生しやすくなり、III族窒化物半導体層の表面を平滑にすることが難しい。
本開示では、リーク電流が流れることを防止することができるとともに、III族窒化物半導体層の表面が平滑な半導体ウエハ、およびその製造方法と、その半導体ウエハを備える半導体装置を提供することを目的とする。
However, when a high concentration of carbon is introduced into the buffer layer and / or the buffer layer side of the group III nitride semiconductor layer (main functional layer), the group III nitride semiconductor layer grows with inherent compression strain. As a result, strain-induced step bunching is likely to occur in the group III nitride semiconductor layer, and it is difficult to smooth the surface of the group III nitride semiconductor layer.
An object of the present disclosure is to provide a semiconductor wafer having a smooth surface of a group III nitride semiconductor layer, a manufacturing method thereof, and a semiconductor device including the semiconductor wafer while preventing leakage current from flowing. And
 本開示の第一の態様によれば、半導体ウエハは、基板と、基板上に設けられたバッファ層と、バッファ層上に設けられたIII族窒化物半導体層と、を備える。バッファ層は、III族窒化物半導体層より格子定数が小さい。III族窒化物半導体層は、炭素を含んでいる。また、半導体ウエハでは、III族窒化物半導体層のバッファ層側の面を裏面、裏面の反対側の面を表面とすると、III族窒化物半導体層の炭素濃度のピークが、III族窒化物半導体層の表面と裏面の双方から離れた位置にある。 According to the first aspect of the present disclosure, the semiconductor wafer includes a substrate, a buffer layer provided on the substrate, and a group III nitride semiconductor layer provided on the buffer layer. The buffer layer has a smaller lattice constant than the group III nitride semiconductor layer. The group III nitride semiconductor layer contains carbon. Further, in the semiconductor wafer, when the surface of the group III nitride semiconductor layer on the buffer layer side is the back surface and the surface opposite to the back surface is the surface, the peak of the carbon concentration of the group III nitride semiconductor layer is the group III nitride semiconductor. Located away from both the front and back of the layer.
 上記半導体ウエハでは、III族窒化物半導体層が炭素を含んでいることにより、上記半導体ウエハを用いて製造される半導体装置のリーク電流を防止することができる。また、III族窒化物半導体層の中間部分(表面と裏面の双方から離れた位置)の炭素濃度を最も高くすることにより、リーク電流を防止するために必要な炭素濃度をIII族窒化物半導体層内に導入しつつ、バッファ層側(III族窒化物半導体層の裏面)においてはIII族窒化物半導体層の炭素濃度を低くすることができる。バッファ層側の炭素濃度を低く抑えることにより、III族窒化物半導体層に歪み誘因ステップバンチングが発生することを抑制することができる。上記の半導体ウエハは、リーク電流が流れることを防止しながら、III族窒化物半導体層の表面を平滑にすることができる。 In the semiconductor wafer, since the group III nitride semiconductor layer contains carbon, a leakage current of a semiconductor device manufactured using the semiconductor wafer can be prevented. In addition, by making the carbon concentration in the middle part of the group III nitride semiconductor layer (a position away from both the front surface and the back surface) the highest, the carbon concentration necessary to prevent leakage current is set to the group III nitride semiconductor layer. The carbon concentration of the group III nitride semiconductor layer can be lowered on the buffer layer side (the back side of the group III nitride semiconductor layer). By suppressing the carbon concentration on the buffer layer side, it is possible to suppress the occurrence of strain-induced step bunching in the group III nitride semiconductor layer. The semiconductor wafer described above can smooth the surface of the group III nitride semiconductor layer while preventing leakage current from flowing.
 本開示の第二の態様によれば、半導体装置は、基板と、基板上に設けられたバッファ層と、バッファ層上に設けられたIII族窒化物半導体層と、III族窒化物半導体層上に設けられた半導体素子と、を備える。この半導体装置では、バッファ層の格子定数(平均格子定数)は、III族窒化物半導体層の格子定数(平均格子定数)より小さい。III族窒化物半導体層は、炭素を含んでいる。また、III族窒化物半導体層のバッファ層側の面を裏面、裏面の反対側の面を表面とすると、III族窒化物半導体層の炭素濃度のピークは、III族窒化物半導体層の表面と裏面の双方から離れた位置にある。 According to the second aspect of the present disclosure, a semiconductor device includes a substrate, a buffer layer provided on the substrate, a group III nitride semiconductor layer provided on the buffer layer, and a group III nitride semiconductor layer. And a semiconductor element. In this semiconductor device, the lattice constant (average lattice constant) of the buffer layer is smaller than the lattice constant (average lattice constant) of the group III nitride semiconductor layer. The group III nitride semiconductor layer contains carbon. Further, when the surface of the group III nitride semiconductor layer on the buffer layer side is the back surface and the surface opposite to the back surface is the surface, the peak of the carbon concentration of the group III nitride semiconductor layer is the same as the surface of the group III nitride semiconductor layer. Located away from both sides.
 本開示の第三の態様によれば、基板と、基板上に設けられたIII族窒化物半導体層を備える半導体ウエハの製造方法は、バッファ層を形成することと、III族窒化物半導体層を形成することとを備えている。バッファ層を形成することでは、基板上に、III族窒化物半導体層より格子定数が小さいバッファ層を気相成長する。III族窒化物半導体層を形成することでは、バッファ層上に、III族窒化物半導体層を気相成長する。III族窒化物半導体層を形成することの途中でIII族窒化物半導体層の成長圧力を最小にする。 According to the third aspect of the present disclosure, a method for manufacturing a semiconductor wafer including a substrate and a group III nitride semiconductor layer provided on the substrate includes forming a buffer layer and a group III nitride semiconductor layer. Forming. In forming the buffer layer, a buffer layer having a lattice constant smaller than that of the group III nitride semiconductor layer is vapor-phase grown on the substrate. In forming the group III nitride semiconductor layer, the group III nitride semiconductor layer is vapor-phase grown on the buffer layer. The growth pressure of the group III nitride semiconductor layer is minimized during the formation of the group III nitride semiconductor layer.
 III族窒化物半導体層の成長圧力を小さくすると、III族窒化物半導体層に導入される炭素濃度が高くなる。そのため、上記の製造方法によると、III族窒化物半導体層の中間部分において炭素濃度が最も高くなる半導体ウエハを製造することができる。 When the growth pressure of the group III nitride semiconductor layer is reduced, the carbon concentration introduced into the group III nitride semiconductor layer is increased. Therefore, according to the manufacturing method described above, it is possible to manufacture a semiconductor wafer having the highest carbon concentration in the middle portion of the group III nitride semiconductor layer.
 本開示についての上記目的およびその他の目的、特徴や利点は、添付の図面を参照しながら下記の詳細な記述により、より明確になる。
第1実施例の半導体ウエハの断面図を模式的に示す図。 III族窒化物半導体層内の位置と炭素濃度の関係を示す図。 実験例1の半導体ウエハの表面を示す写真。 図3Aの写真の線図。 実験例2の半導体ウエハの表面を示す写真。 図4Aの写真の線図。 III族窒化物半導体層内の位置と炭素濃度の関係を示す図。
The above and other objects, features, and advantages of the present disclosure will become more apparent from the following detailed description with reference to the accompanying drawings.
The figure which shows typically sectional drawing of the semiconductor wafer of 1st Example. The figure which shows the relationship between the position in a group III nitride semiconductor layer, and carbon concentration. 4 is a photograph showing the surface of the semiconductor wafer of Experimental Example 1. FIG. 3B is a diagram of the photograph of FIG. 3A. 6 is a photograph showing the surface of the semiconductor wafer of Experimental Example 2. FIG. 4B is a diagram of the photograph of FIG. 4A. The figure which shows the relationship between the position in a group III nitride semiconductor layer, and carbon concentration.
以下、本開示を実施するための形態を説明する。半導体ウエハは、基板と、基板上に設けられているバッファ層と、バッファ層上に設けられているIII族窒化物半導体層を備えている。基板は、III族窒化物半導体層より熱膨張係数が小さい。具体的には、基板は、300~1300Kの線膨張係数の温度積分値が、III族窒化物半導体層を構成する材料のa軸方向の300~1300Kの線膨張係数の温度積分値より小さい。より具体的には、基板の材料は、シリコン(Si)、シリコンカーバイド(SiC)である。基板の厚みは0.1~2mmである。好ましくは、基板とバッファ層の間に、界面層、窒化アルミニウム(AlN)層を設ける。界面層の材料は、酸化アルミニウム(Al2O3)を用いることができる。界面層を設けることにより、バッファ層,III族窒化物半導体層の結晶性を向上させることができる。なお、界面層は省略することもできる。窒化アルミニウム層の厚みは10~500nmである。なお、基板がシリコンの場合、窒化アルミニウム層の厚みは50~500nmであることが好ましい。基板がシリコンカーバイドの場合、窒化アルミニウム層の厚みは10~100nmであることが好ましい。窒化アルミニウムは、III族窒化物半導体の中で最も格子定数が小さい。そのため、窒化アルミニウム層を設けることにより、バッファ層に必要な量の圧縮歪みを与えることができる。なお、上記したように、界面層,窒化アルミニウム層を省略し、基板の表面に直接バッファ層を形成することもできる。 Hereinafter, embodiments for carrying out the present disclosure will be described. The semiconductor wafer includes a substrate, a buffer layer provided on the substrate, and a group III nitride semiconductor layer provided on the buffer layer. The substrate has a smaller coefficient of thermal expansion than the group III nitride semiconductor layer. Specifically, in the substrate, the temperature integral value of the linear expansion coefficient of 300 to 1300K is smaller than the temperature integral value of the linear expansion coefficient of 300 to 1300K in the a-axis direction of the material constituting the group III nitride semiconductor layer. More specifically, the material of the substrate is silicon (Si) or silicon carbide (SiC). The thickness of the substrate is 0.1 to 2 mm. Preferably, an interface layer and an aluminum nitride (AlN) layer are provided between the substrate and the buffer layer. Aluminum oxide (Al2O3) can be used as the material for the interface layer. By providing the interface layer, the crystallinity of the buffer layer and the group III nitride semiconductor layer can be improved. The interface layer can be omitted. The thickness of the aluminum nitride layer is 10 to 500 nm. When the substrate is silicon, the aluminum nitride layer preferably has a thickness of 50 to 500 nm. When the substrate is silicon carbide, the thickness of the aluminum nitride layer is preferably 10 to 100 nm. Aluminum nitride has the smallest lattice constant among group III nitride semiconductors. Therefore, by providing the aluminum nitride layer, a necessary amount of compressive strain can be applied to the buffer layer. As described above, the interface layer and the aluminum nitride layer can be omitted, and the buffer layer can be formed directly on the surface of the substrate.
 バッファ層は、III族窒化物半導体層より格子定数が小さい。具体的には、バッファ層の全体とIII族窒化物半導体層の全体を比較したときに、バッファ層の格子定数(平均格子定数)が、III族窒化物半導体層の格子定数(平均格子定数)より小さい。バッファ層は、圧縮歪みを有している。好ましくは、バッファ層の材料は、AlxGa1-xN(0<x<1)である。AlxGa1-xN(0<x<1)を材料とするバッファ層は、「x」の値が異なるバッファ層からなる多層構造を用いることができる。また、好ましくは、「x」の値は、表面(III族窒化物半導体層側)に向かうに従って小さくなる。すなわち、AlxGa1-xN(0<x<1)を材料とするバッファ層は、表面に向かうに従ってAl組成が小さくなることが好ましい。バッファ層は、異なる材料を繰り返し積層した多層構造を用いることができる。例えば、バッファ層は、AlNとGaNの積層構造が繰り返し設けられていることがある。あるいは、バッファ層は、AlNとAlGaNの積層構造が繰り返し設けられていることがある。バッファ層の厚みは0.5~10μmにすることができる。バッファ層を設けることにより、III族窒化物半導体層の温度が成長温度(高温)から室温(低温)に変化するときに、III族窒化物半導体層に生じる引張歪みを相殺することができる。 The buffer layer has a smaller lattice constant than the group III nitride semiconductor layer. Specifically, when comparing the entire buffer layer and the entire group III nitride semiconductor layer, the lattice constant (average lattice constant) of the buffer layer is the lattice constant (average lattice constant) of the group III nitride semiconductor layer. Smaller than. The buffer layer has a compressive strain. Preferably, the material of the buffer layer is AlxGa1-xN (0 <x <1). As a buffer layer made of AlxGa1-xN (0 <x <1), a multilayer structure including buffer layers having different values of “x” can be used. Further, preferably, the value of “x” becomes smaller toward the surface (the group III nitride semiconductor layer side). That is, it is preferable that the buffer layer made of AlxGa1-xN (0 <x <1) has a smaller Al composition toward the surface. As the buffer layer, a multilayer structure in which different materials are repeatedly stacked can be used. For example, the buffer layer may be repeatedly provided with a laminated structure of AlN and GaN. Alternatively, the buffer layer may be repeatedly provided with a laminated structure of AlN and AlGaN. The thickness of the buffer layer can be 0.5 to 10 μm. By providing the buffer layer, the tensile strain generated in the group III nitride semiconductor layer can be offset when the temperature of the group III nitride semiconductor layer changes from the growth temperature (high temperature) to room temperature (low temperature).
 なお、本実施形態でいう「バッファ層」とは、基板とIII族窒化物半導体層の間の格子定数差を緩和するための所謂「低温バッファ層」を意味するものではなく、III族窒化物半導体層に面方向の力を加え、III族窒化物半導体層が成膜後に高温から低温に変化するときにIII族窒化物半導体層に生じる熱歪みを緩和するためのものである。 The “buffer layer” in the present embodiment does not mean a so-called “low-temperature buffer layer” for reducing the lattice constant difference between the substrate and the group III nitride semiconductor layer, but a group III nitride. This is to apply a surface force to the semiconductor layer to alleviate thermal strain generated in the group III nitride semiconductor layer when the group III nitride semiconductor layer changes from a high temperature to a low temperature after film formation.
また、「バッファ層は、III族窒化物半導体層より格子定数が小さい」とは、バッファ層の全体とIII族窒化物半導体層の全体を比較したときに、バッファ層の格子定数(平均格子定数)が、III族窒化物半導体層の格子定数(平均格子定数)より小さいことを意味する。そのため、バッファ層の一部分とIII族窒化物半導体層の一部分とを比較したときに、バッファ層の一部分の格子定数が、III族窒化物半導体層の一部分の格子定数より大きくなることもある。 In addition, “the buffer layer has a smaller lattice constant than the group III nitride semiconductor layer” means that the buffer layer has a lattice constant (average lattice constant) when the entire buffer layer and the entire group III nitride semiconductor layer are compared. ) Is smaller than the lattice constant (average lattice constant) of the group III nitride semiconductor layer. Therefore, when comparing a part of the buffer layer and a part of the group III nitride semiconductor layer, the lattice constant of a part of the buffer layer may be larger than the lattice constant of a part of the group III nitride semiconductor layer.
III族窒化物半導体層は、炭素を含んでいる。ここで、III族窒化物半導体層のバッファ層側の面を裏面、裏面の反対側の面を表面とする。III族窒化物半導体層の炭素濃度のピークは、III族窒化物半導体層の表面と裏面(バッファ層と接する面)の双方から離れた位置にある。また、III族窒化物半導体層の表面の炭素濃度は、裏面の炭素濃度より低いことが好ましい。具体的には、III族窒化物半導体層の炭素濃度のピークが存在する部分を中間部とし、中間部分より表面側を表面部とし、中間部分より裏面側を裏面部としたときに、炭素濃度は、中間部>裏面部>表面部の関係を満足していることが好ましい。例えば、表面部には、電流が流れる機能層が作りこまれることがある。III族窒化物半導体層の表面(表面部)の炭素濃度を低くすると、機能層の炭素濃度を低く抑えることができ、損失(抵抗)の小さい半導体素子を得ることができる。なお、機能層に炭素が多く含まれていると、炭素の存在により電流の流れが阻害されることがある。 The group III nitride semiconductor layer contains carbon. Here, the surface on the buffer layer side of the group III nitride semiconductor layer is the back surface, and the surface opposite to the back surface is the surface. The peak of the carbon concentration of the group III nitride semiconductor layer is located away from both the front surface and the back surface (surface in contact with the buffer layer) of the group III nitride semiconductor layer. Further, the carbon concentration on the surface of the group III nitride semiconductor layer is preferably lower than the carbon concentration on the back surface. Specifically, when the carbon concentration peak of the group III nitride semiconductor layer is an intermediate part, the surface side is the front part from the intermediate part, and the back side is the back part from the intermediate part. Preferably satisfies the relationship of intermediate portion> back surface portion> front surface portion. For example, a functional layer through which a current flows may be formed on the surface portion. When the carbon concentration of the surface (surface portion) of the group III nitride semiconductor layer is lowered, the carbon concentration of the functional layer can be kept low, and a semiconductor element with a small loss (resistance) can be obtained. Note that if the functional layer contains a large amount of carbon, the current flow may be hindered by the presence of carbon.
 III族窒化物半導体層は、含まれる炭素の濃度が異なる複数の層を備えることが好ましい。具体的には、窒化物半導体層は、バッファ層側から第1層、第2層、第3層の順に積層された積層構造を備え、炭素濃度の平均値が第2層>第1層の関係を満足することが好ましい。各層の炭素濃度の平均値は、第2層>第1層>第3層の関係を満足することが特に好ましい。なお、少なくとも第1層及び第2層は、バッファ層より格子定数が大きいことが好ましい。 The group III nitride semiconductor layer preferably includes a plurality of layers having different concentrations of contained carbon. Specifically, the nitride semiconductor layer has a stacked structure in which the first layer, the second layer, and the third layer are stacked in this order from the buffer layer side, and the average value of the carbon concentration is second layer> first layer. It is preferable to satisfy the relationship. It is particularly preferable that the average value of the carbon concentration of each layer satisfies the relationship of second layer> first layer> third layer. Note that at least the first layer and the second layer preferably have a larger lattice constant than the buffer layer.
 第1層及び第2層の材料は、ガリウム(Ga)を主体とするIII族窒化物半導体であることが好ましい。なお、「ガリウムを主体とするIII族窒化物半導体」とは、典型的には窒化ガリウム(GaN)を意味し、不純物としてGaNに対して1%未満の原子%のオーダーでB、Al、In、S、As、Sb等の元素を含むものも「ガリウムを主体とするIII族窒化物半導体」に含まれる。第1層の材料としてガリウムを主体とするIII族窒化物半導体を用いることにより、薄い第1層を用いて、バッファ層と第2層の間で効率的に歪み緩和を起こすことができる。例えば第1層を構成するIII族窒化物半導体がアルミニウムを多く含む場合、バッファ層と第1層の格子定数の差が小さくなり、薄い第1層ではバッファ層と第2層の間で十分な歪み緩和が起こりにくくなる。また、第2層の材料としてガリウムを主体とするIII族窒化物半導体を用いることにより、第1層と第2層の間で新たな歪みが生じることを抑制することができる。すなわち、第1層の格子定数に近い材料が第2層として積層されるので、第1層と第2層の間で新たな歪みが生じにくい。 The material of the first layer and the second layer is preferably a group III nitride semiconductor mainly composed of gallium (Ga). The “group III nitride semiconductor mainly composed of gallium” typically means gallium nitride (GaN), and as an impurity, B, Al, In, on the order of atomic percent of less than 1% with respect to GaN. Those containing elements such as S, As, and Sb are also included in the “Group III nitride semiconductor mainly composed of gallium”. By using a group III nitride semiconductor mainly composed of gallium as the material of the first layer, strain relaxation can be efficiently caused between the buffer layer and the second layer using the thin first layer. For example, when the group III nitride semiconductor constituting the first layer contains a large amount of aluminum, the difference in lattice constant between the buffer layer and the first layer is small, and the thin first layer is sufficient between the buffer layer and the second layer. Distortion is less likely to occur. Further, by using a group III nitride semiconductor mainly composed of gallium as the material of the second layer, it is possible to suppress the occurrence of new strain between the first layer and the second layer. That is, since a material close to the lattice constant of the first layer is laminated as the second layer, new strain is unlikely to occur between the first layer and the second layer.
 第1層の厚みは、0.05~0.5μmであることが好ましい。第1層の厚みが0.05μmより薄い場合、歪み緩和が十分に起こりにくくなる。また、第1層の厚みが0.5μmより厚い場合、リーク電流の抑制効果が十分に得られない。リーク電流を抑制するという観点より、より好ましくは、第1層の厚みは、0.05~0.2μm未満である。なお、第1層が第2層より十分に膜厚が薄ければ、リーク電流の抑制効果が低下することを防止できる。第1層の炭素濃度は、1×1016~1×1018cm-3であることが好ましい。より好ましくは、第1層の炭素濃度は、1×1016~5×1017cm-3である。第1層の炭素濃度を第2層より低くすることにより、バッファ層が内在する圧縮歪みを緩和することができる。 The thickness of the first layer is preferably 0.05 to 0.5 μm. When the thickness of the first layer is less than 0.05 μm, strain relaxation is not easily caused. Further, when the thickness of the first layer is thicker than 0.5 μm, the effect of suppressing the leakage current cannot be sufficiently obtained. From the viewpoint of suppressing the leakage current, more preferably, the thickness of the first layer is 0.05 to less than 0.2 μm. If the first layer is sufficiently thinner than the second layer, it is possible to prevent the leakage current suppressing effect from being lowered. The carbon concentration of the first layer is preferably 1 × 10 16 to 1 × 10 18 cm −3 . More preferably, the carbon concentration of the first layer is 1 × 10 16 to 5 × 10 17 cm −3 . By making the carbon concentration of the first layer lower than that of the second layer, the compressive strain inherent in the buffer layer can be relaxed.
 第2層の厚みは、0.2~3.0μmであることが好ましい。第2層の炭素濃度は、5×1017~1×1020cm-3であることが好ましい。リーク電流を抑制するという観点より、より好ましくは、第2層の炭素濃度は、1×1018cm-3~1×1020cm-3である。第2層の厚みが第1層より十分に厚ければ、リーク電流の抑制効果を十分に発揮することができる。第3層の材料として、窒化ガリウムを用いることができる。また、第3層は、機能層(半導体素子を構成する層)として利用することができる。第3層の炭素濃度は、1×1017cm-3未満であることが好ましい。より好ましくは、第3層は実質的に炭素を含んでいないことである。第3層の厚みは、目的とする半導体装置に応じて適宜調整することができる。なお、第3層の表面にさらに複数の層(第4層、第5層等)を設けることもできる。例えば、窒化ガリウム層(第3層)の表面にAlGaN層(第4層)を形成し、ヘテロ接合を備えるHEMT(High Electron Mobility Transistor)を製造することもできる。 The thickness of the second layer is preferably 0.2 to 3.0 μm. The carbon concentration of the second layer is preferably 5 × 10 17 to 1 × 10 20 cm −3 . More preferably, the carbon concentration of the second layer is 1 × 10 18 cm −3 to 1 × 10 20 cm −3 from the viewpoint of suppressing leakage current. If the thickness of the second layer is sufficiently thicker than that of the first layer, the leakage current suppressing effect can be sufficiently exerted. Gallium nitride can be used as the material for the third layer. The third layer can be used as a functional layer (a layer constituting a semiconductor element). The carbon concentration of the third layer is preferably less than 1 × 10 17 cm −3 . More preferably, the third layer is substantially free of carbon. The thickness of the third layer can be appropriately adjusted according to the target semiconductor device. A plurality of layers (fourth layer, fifth layer, etc.) can be further provided on the surface of the third layer. For example, an HEMT (High Electron Mobility Transistor) including a heterojunction can be manufactured by forming an AlGaN layer (fourth layer) on the surface of a gallium nitride layer (third layer).
(第1実施例)
 図1及び図2を参照し、半導体ウエハ1について説明する。半導体ウエハ1は、シリコン基板2と、シリコン基板2上に形成された界面層4と、界面層4上に形成されたAlN層6と、AlN層6上に形成されたバッファ層8と、バッファ層8上に形成されたIII族窒化物半導体層10を備えている。シリコン基板2の厚みT2は675μmである。界面層4の材料は酸化アルミニウムである。界面層4の厚みT4は3nm未満に調整されている。AlN層6の厚みT6は0.3μmに調整されている。バッファ層8の材料はAlxGa1-xNである。バッファ層8の厚みT8は2.5μmに調整されている。バッファ層8は多層構造であり、AlN層6側に向かうに従って「x」の値が大きな層が形成されている。
(First embodiment)
The semiconductor wafer 1 will be described with reference to FIGS. The semiconductor wafer 1 includes a silicon substrate 2, an interface layer 4 formed on the silicon substrate 2, an AlN layer 6 formed on the interface layer 4, a buffer layer 8 formed on the AlN layer 6, a buffer A group III nitride semiconductor layer 10 formed on the layer 8 is provided. The thickness T2 of the silicon substrate 2 is 675 μm. The material of the interface layer 4 is aluminum oxide. The thickness T4 of the interface layer 4 is adjusted to be less than 3 nm. The thickness T6 of the AlN layer 6 is adjusted to 0.3 μm. The material of the buffer layer 8 is AlxGa1-xN. The thickness T8 of the buffer layer 8 is adjusted to 2.5 μm. The buffer layer 8 has a multilayer structure, and a layer having a larger value of “x” is formed toward the AlN layer 6 side.
 III族窒化物半導体層10は、第1GaN層10a、第2GaN層10b、第3GaN層10cを備えている。III族窒化物半導体層10の材料は、窒化ガリウム(GaN)である。第1GaN層10aは、炭素を2×1016cm-3含んでいる。第2GaN層10bは、炭素を4×1018cm-3含んでいる。第3GaN層10cは、実質的に炭素を含んでいない(不可避の炭素を含んでいることはある)。III族窒化物半導体層10は、有機金属気相成長法を用いて形成されている。第1GaN層10aの厚みT10aは0.1μmに調整されており、第2GaN層10bの厚みT10bは0.5μmに調整されており、第3GaN層10cの厚みT10cは0.4μmに調整されている。なお、第3GaN層10cの表面に、さらに他の窒化物半導体層を形成することもある。また、第3GaN層10cの内部にn型不純物(Si等),p型不純物(Mg等)が含まれていることもある。第1GaN層10a,第2GaN層10b,第3GaN層10cは、各々第1層,第2層,第3層の一例である。 The group III nitride semiconductor layer 10 includes a first GaN layer 10a, a second GaN layer 10b, and a third GaN layer 10c. The material of the group III nitride semiconductor layer 10 is gallium nitride (GaN). The first GaN layer 10a contains 2 × 10 16 cm −3 of carbon. The second GaN layer 10b contains 4 × 10 18 cm −3 of carbon. The third GaN layer 10c does not substantially contain carbon (may contain inevitable carbon). The group III nitride semiconductor layer 10 is formed using a metal organic chemical vapor deposition method. The thickness T10a of the first GaN layer 10a is adjusted to 0.1 μm, the thickness T10b of the second GaN layer 10b is adjusted to 0.5 μm, and the thickness T10c of the third GaN layer 10c is adjusted to 0.4 μm. . Further, another nitride semiconductor layer may be formed on the surface of the third GaN layer 10c. The third GaN layer 10c may contain n-type impurities (Si or the like) and p-type impurities (Mg or the like). The first GaN layer 10a, the second GaN layer 10b, and the third GaN layer 10c are examples of the first layer, the second layer, and the third layer, respectively.
 一例として、III族窒化物半導体層10の表面(第3GaN層10cの表面)に、ヘテロ接合を有する窒化物積層体(典型的にAlGaN)が形成される。それにより、ヘテロ接合の2次元電子ガスとチャネルとして動作するHEMT構造を備える半導体装置を製造することができる。 As an example, a nitride stack (typically AlGaN) having a heterojunction is formed on the surface of the group III nitride semiconductor layer 10 (the surface of the third GaN layer 10c). Thereby, a semiconductor device having a HEMT structure that operates as a heterojunction two-dimensional electron gas and a channel can be manufactured.
 半導体ウエハ1の製造方法を説明する。まず、原子層堆積法(ALD法)を用いて、シリコン基板2上に、界面層4を形成する。その後、有機金属気相成長法(MOCVD法)を用いて、界面層4上に、AlN層6,バッファ層8をこの順に形成する(バッファ層形成工程)。バッファ層形成工程では、Al原料としてトリメチルアルミニウム、Ga原料としてトリメチルガリウム、N原料としてアンモニアを用いる。また、成長温度はおよそ1000℃である。 A method for manufacturing the semiconductor wafer 1 will be described. First, the interface layer 4 is formed on the silicon substrate 2 using an atomic layer deposition method (ALD method). Thereafter, an AlN layer 6 and a buffer layer 8 are formed in this order on the interface layer 4 using a metal organic chemical vapor deposition method (MOCVD method) (buffer layer forming step). In the buffer layer forming step, trimethylaluminum is used as the Al material, trimethylgallium is used as the Ga material, and ammonia is used as the N material. The growth temperature is about 1000 ° C.
 次に、バッファ層8上に、第1GaN層10aを成長圧力300Torrで形成する。その後、第1GaN層10a上に、第2GaN層10bを成長圧力50Torrで形成する。これにより、第2GaN層10bの炭素濃度(4×1018cm-3)が、第1GaN層10aの炭素濃度(2×1016cm-3)より高くなる。次に、第2GaN層10b上に、第3GaN層10cを成長圧力300Torrで形成する。第3GaN層10cの炭素濃度(実質的に炭素が含まれていない)は、成長圧力以外のパラメータを用いて第1GaN層10a及び第2GaN層10bの炭素濃度より低く調整される。 Next, the first GaN layer 10a is formed on the buffer layer 8 at a growth pressure of 300 Torr. Thereafter, the second GaN layer 10b is formed on the first GaN layer 10a at a growth pressure of 50 Torr. As a result, the carbon concentration (4 × 10 18 cm −3 ) of the second GaN layer 10 b is higher than the carbon concentration (2 × 10 16 cm −3 ) of the first GaN layer 10 a. Next, the third GaN layer 10c is formed on the second GaN layer 10b at a growth pressure of 300 Torr. The carbon concentration of the third GaN layer 10c (substantially does not contain carbon) is adjusted to be lower than the carbon concentrations of the first GaN layer 10a and the second GaN layer 10b using parameters other than the growth pressure.
 上記したように、バッファ層8の格子定数(a面方向の格子定数)は、III族窒化物半導体層(GaNのa面方向の格子定数)10の格子定数より小さい。そのため、バッファ層8は、III族窒化物半導体層10に圧縮歪みを加える。III族窒化物半導体層10には、成長後、降温の過程で引張歪みが生じようとする。バッファ層8は、III族窒化物半導体層10に生じる引張歪みを相殺し、III族窒化物半導体層10に反り、クラック等が発生することを抑制する。 As described above, the lattice constant (lattice constant in the a-plane direction) of the buffer layer 8 is smaller than the lattice constant of the group III nitride semiconductor layer (lattice constant in the a-plane direction of GaN) 10. Therefore, the buffer layer 8 applies compressive strain to the group III nitride semiconductor layer 10. The group III nitride semiconductor layer 10 tends to undergo tensile strain in the process of temperature drop after growth. The buffer layer 8 cancels the tensile strain generated in the group III nitride semiconductor layer 10 and suppresses the group III nitride semiconductor layer 10 from warping and generating cracks and the like.
 半導体ウエハ1の利点を説明する。図2は、III族窒化物半導体層10の炭素濃度を示している。グラフの横軸は炭素濃度(cm-3)を示し、縦軸は各層(第1GaN層10a~第3GaN層10c)を示している。なお、図2に示している炭素濃度は、各層の平均値を示している。上記したように、第2GaN層10bの炭素濃度は4×1018cm-3である。GaN層に含まれる炭素濃度を1×1018cm-3より濃くすると、リーク電流を抑制することができる。そのため、半導体ウエハ1を用いて半導体装置を作製したときに、III族窒化物半導体層10とシリコン基板2間にリーク電流が流れることを抑制できる。また、上記したように、第1GaN層10aの厚みT10aは、第2GaN層10bの厚みT10bより薄い。厚みT10aが厚くなると、リーク電流の抑制効果が低下することがある。厚みT10aを厚みT10bより薄くすることにより、リーク電流の抑制効果を向上させることができる。 Advantages of the semiconductor wafer 1 will be described. FIG. 2 shows the carbon concentration of the group III nitride semiconductor layer 10. The horizontal axis of the graph represents the carbon concentration (cm −3 ), and the vertical axis represents each layer (first GaN layer 10a to third GaN layer 10c). In addition, the carbon concentration shown in FIG. 2 has shown the average value of each layer. As described above, the carbon concentration of the second GaN layer 10b is 4 × 10 18 cm −3 . When the concentration of carbon contained in the GaN layer is higher than 1 × 10 18 cm −3 , the leakage current can be suppressed. Therefore, when a semiconductor device is manufactured using the semiconductor wafer 1, it is possible to suppress a leak current from flowing between the group III nitride semiconductor layer 10 and the silicon substrate 2. Further, as described above, the thickness T10a of the first GaN layer 10a is thinner than the thickness T10b of the second GaN layer 10b. When the thickness T10a is increased, the effect of suppressing leakage current may be reduced. By making the thickness T10a thinner than the thickness T10b, the effect of suppressing leakage current can be improved.
 図2に示しているように、第1GaN層10aの炭素濃度(2×1016cm-3)は、第2GaN層10bの炭素濃度(4×1018cm-3)より低い。すなわち、第1GaN層10aは、リーク電流を抑制するのに十分な濃度の炭素を含んでいない。炭素濃度が低い第1GaN層10aをバッファ層8上に形成すると、効果的な歪み緩和が起こる。なお、仮に第1GaN層10aの炭素濃度が高い(例えば、リーク電流の抑制に効果を奏する1×1018cm-3以上)場合、バッファ層8の圧縮歪みを内在したままIII族窒化物半導体層10が成長する。その結果、歪み誘因ステップバンチングが発生し、半導体ウエハ1の表面を平滑にすることが難しい。表面平滑性が悪い半導体ウエハを用いて半導体装置を製造すると、半導体装置の特性が低下することがある。 As shown in FIG. 2, the carbon concentration (2 × 10 16 cm −3 ) of the first GaN layer 10a is lower than the carbon concentration (4 × 10 18 cm −3 ) of the second GaN layer 10b. That is, the first GaN layer 10a does not contain carbon at a concentration sufficient to suppress leakage current. When the first GaN layer 10a having a low carbon concentration is formed on the buffer layer 8, effective strain relaxation occurs. Note that if the carbon concentration of the first GaN layer 10a is high (for example, 1 × 10 18 cm −3 or more that is effective in suppressing leakage current), the group III nitride semiconductor layer with the compressive strain of the buffer layer 8 inherently contained 10 grows. As a result, distortion-induced step bunching occurs and it is difficult to smooth the surface of the semiconductor wafer 1. When a semiconductor device is manufactured using a semiconductor wafer having poor surface smoothness, the characteristics of the semiconductor device may deteriorate.
「歪み誘因ステップバンチング」とは、Tersoffらが発見し、提唱したステップバンチング発生のメカニズムであり、「Physical Review Letters Volume 75 2730(1995)」に開示されている。そのメカニズムは、周期的なステップ・テラスで形成される半導体表面に歪みが発生すると、歪みの2乗に比例し、ステップ間の距離に反比例したステップ間引力が働くというものである。ステップ間引力がステップの束(ステップバンチング)を次々と形成し、半導体ウエハの表面に段差が形成され、半導体ウエハの表面平滑性が低下する。そのため、半導体表面の歪みを小さくすることにより、ステップバンチングの発生を抑制することができる。 “Distortion-induced step bunching” is a mechanism of step bunching occurrence discovered and proposed by Tersoff et al., And disclosed in “Physical Review Letters Volume 75 2730 (1995)”. The mechanism is that when a strain is generated on a semiconductor surface formed by periodic step terraces, an attractive force between steps is proportional to the square of the strain and inversely proportional to the distance between steps. The attractive force between steps forms a bundle of steps (step bunching) one after another, and a step is formed on the surface of the semiconductor wafer, so that the surface smoothness of the semiconductor wafer is lowered. Therefore, generation of step bunching can be suppressed by reducing the distortion of the semiconductor surface.
歪み誘因ステップバンチングは、成長面に対して垂直な垂線に対して主軸が微傾斜したウエハ(所謂オフ角を有するウエハ)において、より顕著となる。例えばIII族窒化物半導体の場合、一般的にc軸が主軸となる。そのため、III族窒化物半導体場合、c軸が成長面の垂線に対して傾斜している状態がオフ角を有するといえる。典型的に、オフ角を設けることにより、成長表面をステップ・テラスが規則的に繰り返す周期構造となり、ウエハ表面の平坦性を向上させることができる。また、オフ角を設けることにより、急峻なヘテロ接合を実現したり、ウエハ上に形成する半導体素子の界面特性が向上するといった利点も得られる。しかしながら、歪み誘因ステップ間引力が働く状況下では、オフ角を有するウエハ表面のステップ間距離が小さい。ステップ間引力が無視できない働きをするので、歪み誘因ステップ間引力が働く状況下では、ステップバンチングが発生しやすい。 Strain-induced step bunching becomes more prominent in a wafer (so-called off-angle wafer) whose principal axis is slightly inclined with respect to a perpendicular perpendicular to the growth surface. For example, in the case of a group III nitride semiconductor, the c-axis is generally the main axis. Therefore, in the case of a group III nitride semiconductor, it can be said that the state where the c-axis is inclined with respect to the normal of the growth surface has an off angle. Typically, by providing an off-angle, the growth surface has a periodic structure in which step terraces are regularly repeated, and the flatness of the wafer surface can be improved. In addition, by providing an off-angle, it is possible to obtain advantages such as realizing a steep heterojunction and improving the interface characteristics of a semiconductor element formed on a wafer. However, the distance between steps on the wafer surface having an off angle is small under a situation where a strain-induced step attractive force is applied. Since the step-to-step attractive force cannot be ignored, step bunching is likely to occur under the situation where the strain-induced step-by-step attractive force is applied.
 窒化物半導体層における歪み誘因ステップバンチングは、III族元素としてガリウムを主成分とするIII族窒化物半導体でより顕著である。ステップバンチングは、テラス上のIII族原子種が表面拡散してステップ端に取り込まれる過程で起こる。そのため、ステップバンチングは、「ステップ間平均距離×(1/2)≦III族原子種の表面拡散長」の条件を満足する環境下で起こりやすい。III族原子種において、ガリウムは、アルミニウムやインジウムと比較して表面拡散長が長いことが知られている。そのため、歪み誘因ステップバンチングは、ガリウムを主成分とするIII族窒化物半導体、特に窒化ガリウムで発生しやすい。なお、本実施例でいう「窒化ガリウム」には、1%未満の不純物(Al,In,Mg,Si,Ge,C,Fe等)を含有している窒化ガリウムも含まれる。 The strain-induced step bunching in the nitride semiconductor layer is more prominent in a group III nitride semiconductor containing gallium as a main group element. Step bunching occurs in the process where group III atomic species on the terrace are diffused into the step edge. Therefore, step bunching is likely to occur in an environment that satisfies the condition of “average distance between steps × (1/2) ≦ surface diffusion length of group III atomic species”. In group III atomic species, gallium is known to have a longer surface diffusion length than aluminum and indium. Therefore, strain-induced step bunching is likely to occur in a group III nitride semiconductor mainly containing gallium, particularly gallium nitride. Note that “gallium nitride” in this embodiment includes gallium nitride containing impurities (Al, In, Mg, Si, Ge, C, Fe, etc.) less than 1%.
 半導体ウエハ1は、第1GaN層10aの炭素濃度を第2GaN層10bの炭素濃度より低くすることにより、第1GaN層10aにおいてバッファ層8の圧縮歪みが緩和される。第1GaN層10aにおいてバッファ層8の圧縮歪みを緩和することにより、第2GaN層10bに高濃度の炭素が含まれていても、歪み誘因ステップバンチングが発生することを抑制することができる。以上より、半導体ウエハ1の表面を平滑にすることができ、良好な特性を示す半導体装置を製造することができる。 In the semiconductor wafer 1, the compressive strain of the buffer layer 8 is reduced in the first GaN layer 10a by making the carbon concentration of the first GaN layer 10a lower than the carbon concentration of the second GaN layer 10b. By reducing the compressive strain of the buffer layer 8 in the first GaN layer 10a, it is possible to suppress the occurrence of strain-induced step bunching even if the second GaN layer 10b contains a high concentration of carbon. As described above, the surface of the semiconductor wafer 1 can be smoothed, and a semiconductor device exhibiting good characteristics can be manufactured.
 なお、上記したように、III族窒化物半導体層10の炭素の濃度は、III族窒化物半導体層の成長圧力で制御することができる。他の成長条件が同じ場合、成長圧力が低くなるに従ってIII族窒化物半導体層の炭素濃度は高くなる。第1GaN層10aを結晶成長させた後に成長圧力を低く調整することにより、第2GaN層10bの炭素濃度を高くすることができる。 As described above, the carbon concentration of the group III nitride semiconductor layer 10 can be controlled by the growth pressure of the group III nitride semiconductor layer. When other growth conditions are the same, the carbon concentration of the group III nitride semiconductor layer increases as the growth pressure decreases. The carbon concentration of the second GaN layer 10b can be increased by adjusting the growth pressure low after crystal growth of the first GaN layer 10a.
 例えば、バッファ層8上に、第1GaN層10aを形成することなく第2GaN層10bを厚く結晶成長させても、第2GaN層10bの厚みが増加するに従い、バッファ層8の圧縮歪みを緩和することができる。しかしながら、半導体ウエハの反りは、III族窒化物半導体層10「歪み」と「膜厚」の積に応じて変化する。すなわち、バッファ層8上に直接第2GaN層10bを形成すると、「歪み」が大きいので、僅かな「膜厚」の変化によって半導体ウエハの反り量が大きく変化する。そのため、高濃度の炭素を含む第2GaN層10bを厚く形成する方法では、半導体ウエハの反り量を制御することが困難になる。上記したように、半導体ウエハ1では、第1GaN層10aでバッファ層8の圧縮歪みを緩和した後に、高濃度の炭素を含む第2GaN層10bを結晶成長させる。そのため、III族窒化物半導体層10の膜厚に誤差が生じても、バッチ間の反り量のばらつきを抑制することができる。半導体ウエハ1は、反り量の制御のロバスト性を向上させることもできる。
(実験例)
 図3Aは、シリコン基板上に、界面層、AlN層、バッファ層、第1GaN層、第2GaN層をこの順に成長させた半導体ウエハの表面S1の光学顕微鏡写真であり、図3Bは図3Aの写真の線図である(実験例1)。第1GaN層の炭素濃度は2×1016cm-3(成長圧力300Torr)であり、第2GaN層の炭素濃度は4×1018cm-3(成長圧力50Torr)である。炭素濃度を第1GaN層<第2GaN層にすることにより、ステップフロー成長が確認され、表面が平滑な半導体ウエハが得られることが確認された。なお、X線逆格子マップ測定の結果、GaN層のa軸方向の残留歪みは、0.11%であった。また、第1GaN層10aのc軸は、成長面の垂線に対してm軸方向に0.26度傾斜していた。
For example, even if the second GaN layer 10b is grown thick without forming the first GaN layer 10a on the buffer layer 8, the compressive strain of the buffer layer 8 is reduced as the thickness of the second GaN layer 10b increases. Can do. However, the warpage of the semiconductor wafer varies depending on the product of the group III nitride semiconductor layer 10 “strain” and “film thickness”. That is, when the second GaN layer 10b is formed directly on the buffer layer 8, since the “strain” is large, the amount of warpage of the semiconductor wafer greatly changes due to a slight change in the “film thickness”. For this reason, it is difficult to control the amount of warpage of the semiconductor wafer in the method of forming the second GaN layer 10b containing high-concentration carbon thickly. As described above, in the semiconductor wafer 1, after the compressive strain of the buffer layer 8 is relaxed by the first GaN layer 10a, the second GaN layer 10b containing a high concentration of carbon is crystal-grown. Therefore, even if an error occurs in the film thickness of the group III nitride semiconductor layer 10, variation in the amount of warpage between batches can be suppressed. The semiconductor wafer 1 can also improve the robustness of warpage control.
(Experimental example)
FIG. 3A is an optical micrograph of the surface S1 of a semiconductor wafer in which an interface layer, an AlN layer, a buffer layer, a first GaN layer, and a second GaN layer are grown in this order on a silicon substrate, and FIG. 3B is a photograph of FIG. 3A. (Experimental example 1). The carbon concentration of the first GaN layer is 2 × 10 16 cm −3 (growth pressure 300 Torr), and the carbon concentration of the second GaN layer is 4 × 10 18 cm −3 (growth pressure 50 Torr). By setting the carbon concentration to the first GaN layer <the second GaN layer, step flow growth was confirmed, and it was confirmed that a semiconductor wafer having a smooth surface was obtained. As a result of the X-ray reciprocal lattice map measurement, the residual strain in the a-axis direction of the GaN layer was 0.11%. The c-axis of the first GaN layer 10a was inclined 0.26 degrees in the m-axis direction with respect to the normal to the growth surface.
 図4Aは、シリコン基板上に、界面層、AlN層、バッファ層、第2GaN層、第1GaN層をこの順に成長させた半導体ウエハの表面S2の光学顕微鏡写真であり、図4Bは図3Bの写真の線図である(実験例2)。実験例1の半導体ウエハとは、第1GaN層と第2GaN層を成長する順序が反対である。すなわち、実験例2の半導体ウエハは、バッファ層の表面に、高濃度の炭素を含む第2GaN層を成長させている。図4Aおよび図4Bから明らかなように、第2GaN層、第1GaN層の順に成長させると、表面に縞状の模様が形成されており、ステップの束(ステップバンチング)SBが形成されていることが確認できる。100μm視野角の原子間力顕微鏡(Atomic Force Microscope)で測定した結果、ステップの束の段差は、最大で80nmであった。X線逆格子マップ測定によるGaN層のa軸方向の残留歪みは、0.42%であった。また、第1GaN層10aのc軸は、成長面の垂線に対してm軸方向に0.26度傾斜していた。 4A is an optical micrograph of the surface S2 of a semiconductor wafer in which an interface layer, an AlN layer, a buffer layer, a second GaN layer, and a first GaN layer are grown in this order on a silicon substrate, and FIG. 4B is a photograph of FIG. 3B. (Experimental example 2). The order of growing the first GaN layer and the second GaN layer is opposite to that of the semiconductor wafer of Experimental Example 1. That is, in the semiconductor wafer of Experimental Example 2, the second GaN layer containing a high concentration of carbon is grown on the surface of the buffer layer. As apparent from FIGS. 4A and 4B, when the second GaN layer and the first GaN layer are grown in this order, a striped pattern is formed on the surface, and a bundle of steps (step bunching) SB is formed. Can be confirmed. As a result of measurement with an atomic force microscope (Atomic Force Microscope) having a viewing angle of 100 μm, the step difference of the bundle of steps was 80 nm at the maximum. The residual strain in the a-axis direction of the GaN layer measured by X-ray reciprocal lattice map was 0.42%. The c-axis of the first GaN layer 10a was inclined 0.26 degrees in the m-axis direction with respect to the normal to the growth surface.
 上記実験例1,2の結果より、炭素を含むGaN層を備える半導体ウエハにおいて、GaN層の炭素濃度をバッファ層の接する部分で低くすることにより、GaN層の歪みを抑制し、半導体ウエハの表面に歪み誘因ステップバンチングが形成されることを抑制できることが確認された。 From the results of the above experimental examples 1 and 2, in a semiconductor wafer having a carbon-containing GaN layer, by reducing the carbon concentration of the GaN layer at the portion in contact with the buffer layer, the distortion of the GaN layer is suppressed, and the surface of the semiconductor wafer It was confirmed that strain-induced step bunching can be suppressed.
 上記実施例ではIII族窒化物半導体層が第1GaN層10a,第2GaN層10b,第3GaN層10cを備えている例について説明した。しかしながら、本開示は、第3GaN層10cの表面に、さらに別の窒化物半導体層が形成されている半導体ウエハにも適用することができる。また、第1GaN層10a,第2GaN層10b,第3GaN層10cはIII族窒化物半導体層の一例であり、第1GaN層10a,第2GaN層10b,第3GaN層10cはGaNを主体とするIII族窒化物半導体で構成することもできる。 In the above embodiment, the example in which the group III nitride semiconductor layer includes the first GaN layer 10a, the second GaN layer 10b, and the third GaN layer 10c has been described. However, the present disclosure can also be applied to a semiconductor wafer in which another nitride semiconductor layer is formed on the surface of the third GaN layer 10c. The first GaN layer 10a, the second GaN layer 10b, and the third GaN layer 10c are examples of a group III nitride semiconductor layer, and the first GaN layer 10a, the second GaN layer 10b, and the third GaN layer 10c are a group III mainly composed of GaN. It can also be made of a nitride semiconductor.
 また、図5に示すように、III族窒化物半導体層は、炭素濃度が裏面(バッファ層側)から表面に向けて連続的に変化する構造も取り得る。この場合、III族窒化物半導体層は、明確な層構造を形成していない場合もあり得る。このような場合であっても、III族窒化物半導体層の炭素濃度のピークがIII族窒化物半導体層の表面と裏面の双方から離れた位置にあることにより、リーク電流を抑制しつつ、半導体ウエハの表面を平滑にすることができる。 Further, as shown in FIG. 5, the group III nitride semiconductor layer may have a structure in which the carbon concentration continuously changes from the back surface (buffer layer side) to the front surface. In this case, the group III nitride semiconductor layer may not form a clear layer structure. Even in such a case, the peak of the carbon concentration of the group III nitride semiconductor layer is located away from both the front surface and the back surface of the group III nitride semiconductor layer. The surface of the wafer can be smoothed.
 上記実施例では、III族窒化物半導体層10の炭素濃度が、第2GaN層10b>第1GaN層10a>第3GaN層10cである半導体ウエハ1について説明した。しかしながら、本開示は、III族窒化物半導体層の炭素濃度のピークが、表面と裏面の双方から離れた位置にあれば効果を奏する。すなわち、第2GaN層10bの炭素濃度がIII族窒化物半導体層10の中で最も高いという条件を満たしていれば、炭素濃度は、第2GaN層10b>第3GaN層10c>第1GaN層10aであっても効果を奏する。III族窒化物半導体層の炭素濃度のピークが表面と裏面の双方から離れた位置にあれば、リーク電流を抑制しつつ、歪み誘因ステップバンチングを抑制することができる。 In the above embodiment, the semiconductor wafer 1 in which the group III nitride semiconductor layer 10 has the carbon concentration of the second GaN layer 10b> the first GaN layer 10a> the third GaN layer 10c has been described. However, the present disclosure is effective when the peak of the carbon concentration of the group III nitride semiconductor layer is located away from both the front surface and the back surface. That is, if the condition that the carbon concentration of the second GaN layer 10b is the highest among the group III nitride semiconductor layers 10 is satisfied, the carbon concentration is: second GaN layer 10b> third GaN layer 10c> first GaN layer 10a. Even if there is an effect. If the peak of the carbon concentration of the group III nitride semiconductor layer is at a position away from both the front surface and the back surface, distortion-induced step bunching can be suppressed while suppressing leakage current.
 本開示は、実施形態、実施例、実験例に準拠して記述されたが、本開示は当該実施例や構造に限定されるものではないと理解される。本開示は、様々な変形例や均等範囲内の変形をも包含する。加えて、様々な組み合わせや形態、さらには、それらに一要素のみ、それ以上、あるいはそれ以下、を含む他の組み合わせや形態をも、本開示の範疇や思想範囲に入るものである。 Although the present disclosure has been described based on the embodiments, examples, and experimental examples, it is understood that the present disclosure is not limited to the examples and structures. The present disclosure includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, as well as other combinations and forms including only one element, more or less, are within the scope and spirit of the present disclosure.

Claims (9)

  1.  基板(2)と、前記基板上に設けられたバッファ層(8)と、前記バッファ層上に設けられたIII族窒化物半導体層(10)と、を備える半導体ウエハであって、
     前記バッファ層は、前記III族窒化物半導体層より格子定数が小さく、
     前記III族窒化物半導体層は、炭素を含んでおり、
     前記III族窒化物半導体層の前記バッファ層側の面を裏面、前記裏面の反対側の面を表面とし、
     前記III族窒化物半導体層の炭素濃度のピークが、前記III族窒化物半導体層の前記表面と前記裏面の双方から離れた位置にある半導体ウエハ。
    A semiconductor wafer comprising a substrate (2), a buffer layer (8) provided on the substrate, and a group III nitride semiconductor layer (10) provided on the buffer layer,
    The buffer layer has a smaller lattice constant than the group III nitride semiconductor layer,
    The group III nitride semiconductor layer contains carbon,
    The surface of the group III nitride semiconductor layer on the buffer layer side is the back surface, and the surface opposite to the back surface is the surface,
    A semiconductor wafer in which a peak of the carbon concentration of the group III nitride semiconductor layer is located away from both the front surface and the back surface of the group III nitride semiconductor layer.
  2.  前記III族窒化物半導体層の前記表面の炭素濃度が、前記裏面の炭素濃度より低い請求項1に記載の半導体ウエハ。 The semiconductor wafer according to claim 1, wherein a carbon concentration of the front surface of the group III nitride semiconductor layer is lower than a carbon concentration of the back surface.
  3.  前記III族窒化物半導体層は、第1層、第2層、第3層を備えており、
     前記第1層は、前記バッファ層の上に設けられ、
     前記第2層は、前記第1層の上に設けられ、
     前記第3層は、前記第2層の上に設けられ、
     前記第2層の炭素濃度の平均値が、前記第1層の炭素濃度の平均値及び前記第3層の炭素濃度の平均値の双方より高い請求項1又は2に記載の半導体ウエハ。
    The group III nitride semiconductor layer includes a first layer, a second layer, and a third layer,
    The first layer is provided on the buffer layer,
    The second layer is provided on the first layer;
    The third layer is provided on the second layer;
    3. The semiconductor wafer according to claim 1, wherein an average value of carbon concentration of the second layer is higher than both of an average value of carbon concentration of the first layer and an average value of carbon concentration of the third layer.
  4.  前記第3層の炭素濃度の平均値が、前記第1層の炭素濃度の平均値より低い請求項3に記載の半導体ウエハ。 4. The semiconductor wafer according to claim 3, wherein an average value of carbon concentration of the third layer is lower than an average value of carbon concentration of the first layer.
  5.  前記第1層の材料が、窒化ガリウムである請求項3または4に記載の半導体ウエハ。 The semiconductor wafer according to claim 3 or 4, wherein the material of the first layer is gallium nitride.
  6.  前記III族窒化物半導体層のc軸が、成長面の垂線に対して傾斜している請求項1から5のいずれか一項に記載の半導体ウエハ。 The semiconductor wafer according to claim 1, wherein a c-axis of the group III nitride semiconductor layer is inclined with respect to a normal to the growth surface.
  7.  前記基板の材料が、シリコンである請求項1から6のいずれか一項に記載の半導体ウエハ。 The semiconductor wafer according to any one of claims 1 to 6, wherein a material of the substrate is silicon.
  8.  基板と、前記基板上に設けられたバッファ層と、前記バッファ層上に設けられたIII族窒化物半導体層と、前記III族窒化物半導体層上に設けられた半導体素子と、を備える半導体装置であって、
     前記バッファ層は、前記III族窒化物半導体層より格子定数が小さく、
     前記III族窒化物半導体層は、炭素を含んでおり、
    前記III族窒化物半導体層の前記バッファ層側の面を裏面、前記裏面の反対側の面を表面とし、
     前記III族窒化物半導体層の炭素濃度のピークが、前記III族窒化物半導体層の前記表面と前記裏面の双方から離れた位置にある半導体装置。
    A semiconductor device comprising: a substrate; a buffer layer provided on the substrate; a group III nitride semiconductor layer provided on the buffer layer; and a semiconductor element provided on the group III nitride semiconductor layer Because
    The buffer layer has a smaller lattice constant than the group III nitride semiconductor layer,
    The group III nitride semiconductor layer contains carbon,
    The surface of the group III nitride semiconductor layer on the buffer layer side is the back surface, and the surface opposite to the back surface is the surface,
    A semiconductor device in which a peak of a carbon concentration of the group III nitride semiconductor layer is located away from both the front surface and the back surface of the group III nitride semiconductor layer.
  9.  基板と、前記基板上に設けられたIII族窒化物半導体層を備える半導体ウエハの製造方法であり、
     前記基板上に、前記III族窒化物半導体層より格子定数が小さいバッファ層を気相成長させてバッファ層を形成することと、
     前記バッファ層上に、前記III族窒化物半導体層を気相成長させてIII族窒化物半導体層を形成することと、
     を備えており、
     前記III族窒化物半導体層を形成することの途中で前記III族窒化物半導体層の成長圧力を最小にする半導体ウエハの製造方法。
    A method for producing a semiconductor wafer comprising a substrate and a group III nitride semiconductor layer provided on the substrate,
    Forming a buffer layer on the substrate by vapor-phase growth of a buffer layer having a lattice constant smaller than that of the group III nitride semiconductor layer;
    Forming a group III nitride semiconductor layer by vapor-phase-growing the group III nitride semiconductor layer on the buffer layer;
    With
    A method of manufacturing a semiconductor wafer, wherein the growth pressure of the group III nitride semiconductor layer is minimized during the formation of the group III nitride semiconductor layer.
PCT/JP2016/001529 2015-03-26 2016-03-17 Semiconductor wafer, semiconductor device, and semiconductor wafer manufacturing method WO2016152106A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2015-064107 2015-03-26
JP2015064107A JP2016184663A (en) 2015-03-26 2015-03-26 Semiconductor wafer, semiconductor device, and method of manufacturing semiconductor wafer

Publications (1)

Publication Number Publication Date
WO2016152106A1 true WO2016152106A1 (en) 2016-09-29

Family

ID=56979010

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2016/001529 WO2016152106A1 (en) 2015-03-26 2016-03-17 Semiconductor wafer, semiconductor device, and semiconductor wafer manufacturing method

Country Status (2)

Country Link
JP (1) JP2016184663A (en)
WO (1) WO2016152106A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6784861B1 (en) * 2020-03-18 2020-11-11 住友化学株式会社 Nitride semiconductor substrate

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003069156A (en) * 2001-08-29 2003-03-07 Sharp Corp Nitride compound semiconductor laminate, light-emitting device, optical pickup system, and manufacturing method of nitride compound semiconductor laminate
JP2005255440A (en) * 2004-03-10 2005-09-22 Univ Meijo Method for making group iii nitride semiconductor and group iii nitride semiconductor
JP2007251144A (en) * 2006-02-20 2007-09-27 Furukawa Electric Co Ltd:The Semiconductor element
JP2011166067A (en) * 2010-02-15 2011-08-25 Panasonic Corp Nitride semiconductor device
JP2012243886A (en) * 2011-05-18 2012-12-10 Sharp Corp Semiconductor device
WO2013145404A1 (en) * 2012-03-28 2013-10-03 株式会社豊田中央研究所 Laminated substate of silicon single crystal and group iii nitride single crystal with off angle

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003069156A (en) * 2001-08-29 2003-03-07 Sharp Corp Nitride compound semiconductor laminate, light-emitting device, optical pickup system, and manufacturing method of nitride compound semiconductor laminate
JP2005255440A (en) * 2004-03-10 2005-09-22 Univ Meijo Method for making group iii nitride semiconductor and group iii nitride semiconductor
JP2007251144A (en) * 2006-02-20 2007-09-27 Furukawa Electric Co Ltd:The Semiconductor element
JP2011166067A (en) * 2010-02-15 2011-08-25 Panasonic Corp Nitride semiconductor device
JP2012243886A (en) * 2011-05-18 2012-12-10 Sharp Corp Semiconductor device
WO2013145404A1 (en) * 2012-03-28 2013-10-03 株式会社豊田中央研究所 Laminated substate of silicon single crystal and group iii nitride single crystal with off angle

Also Published As

Publication number Publication date
JP2016184663A (en) 2016-10-20

Similar Documents

Publication Publication Date Title
JP5785103B2 (en) Epitaxial wafers for heterojunction field effect transistors.
JP5804768B2 (en) Semiconductor device and manufacturing method thereof
TWI611576B (en) Semiconductor substrate and method for making a semiconductor substrate
JP5117609B1 (en) Nitride semiconductor wafer, nitride semiconductor device, and method for growing nitride semiconductor crystal
JP5495069B2 (en) Semiconductor device and manufacturing method thereof
JP5912383B2 (en) Nitride semiconductor substrate
JP2013026321A (en) Epitaxial wafer including nitride-based semiconductor layer
JP2019110344A (en) Nitride semiconductor device and nitride semiconductor substrate
CN111406306A (en) Method for manufacturing semiconductor device, and semiconductor device
JP4468744B2 (en) Method for producing nitride semiconductor thin film
JP5159858B2 (en) Gallium nitride compound semiconductor substrate and manufacturing method thereof
JP4888537B2 (en) Group III nitride semiconductor laminated wafer and group III nitride semiconductor device
JP6239017B2 (en) Nitride semiconductor substrate
JP6173493B2 (en) Epitaxial substrate for semiconductor device and method of manufacturing the same
CN112687732B (en) Semiconductor thin film structure and electronic device including the same
JP6084254B2 (en) Compound semiconductor substrate
JP6089122B2 (en) Nitride semiconductor laminate, method for manufacturing the same, and nitride semiconductor device
JP2013145782A (en) Epitaxial wafer for hetero-junction field effect transistor
WO2016152106A1 (en) Semiconductor wafer, semiconductor device, and semiconductor wafer manufacturing method
JP2015103665A (en) Nitride semiconductor epitaxial wafer and nitride semiconductor
US9401420B2 (en) Semiconductor device
WO2016166949A1 (en) Semiconductor wafer and semiconductor device
JP2014039034A (en) Semiconductor light-emitting element
JP5705179B2 (en) Nitride semiconductor wafer, nitride semiconductor device, and method for growing nitride semiconductor crystal
TWI728498B (en) Nitride semiconductor substrate

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16768013

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 16768013

Country of ref document: EP

Kind code of ref document: A1