JP5159858B2 - Gallium nitride compound semiconductor substrate and manufacturing method thereof - Google Patents

Gallium nitride compound semiconductor substrate and manufacturing method thereof Download PDF

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JP5159858B2
JP5159858B2 JP2010224558A JP2010224558A JP5159858B2 JP 5159858 B2 JP5159858 B2 JP 5159858B2 JP 2010224558 A JP2010224558 A JP 2010224558A JP 2010224558 A JP2010224558 A JP 2010224558A JP 5159858 B2 JP5159858 B2 JP 5159858B2
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俊一 鈴木
浩司 大石
純 小宮山
健一 江里口
芳久 阿部
晃 吉田
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Coorstek KK
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本発明は、電子素子用の化合物半導体に用いられる、窒化ガリウム系化合物半導体基板とその製造方法に関する。 The present invention relates to a gallium nitride compound semiconductor substrate used for a compound semiconductor for an electronic device and a method for manufacturing the same.

窒化ガリウム(GaN)系化合物半導体は、シリコン(Si)と比べて広いバンドギャップを有しており、各種電子素子用の半導体として応用が期待されている。 Gallium nitride (GaN) -based compound semiconductors have a wider band gap than silicon (Si), and are expected to be applied as semiconductors for various electronic devices.

この窒化ガリウム系化合物半導体に用いられる基板の作製方法として、例えば、シリコン(Si)単結晶基板上に、気相成長法によって、複数の化合物半導体層を介して窒化ガリウム系化合物半導体を形成する方法がある。この方法は、他の方法に比べて生産性や放熱性の点で比較的優位であり、さらに改良が進められている。 As a method for manufacturing a substrate used for the gallium nitride compound semiconductor, for example, a method of forming a gallium nitride compound semiconductor on a silicon (Si) single crystal substrate by a vapor deposition method through a plurality of compound semiconductor layers. There is. This method is relatively superior to other methods in terms of productivity and heat dissipation, and further improvements are being made.

例えば、特許文献1には、Si基材上に形成された第1のAlaGaIn1-a-b0≦a≦1、0≦b≦1、かつ0≦a+b≦1)層と、前記第1のAlaGaIn1-a-b層上に形成された第2のAlcGaIn1-c-dw(0≦c≦1、0≦d≦1、かつ0≦c+ d≦1)層と、前記第2のAlcGadIn1 - c - d層上に位置し、第3のAle GafIn1 - e - f0≦e≦1、0≦f≦1、かつ0≦e+f≦1)層及び第4のAlgGahIn1-g-h0≦g≦1、0≦h≦1、かつ0≦g+h≦1)層を交互に積層した多層膜と、前記多層膜上に形成された第5のAliGajIn1-i-j(0≦i≦1、0≦j≦1、かつ0≦i+j≦1)層と、を具備し、前記多層膜における前記第3のAle GafIn1 - e - f層と前記第4のAlgGahIn1-g-h層の積層数は160層以下であることを特徴とする半導体基板が開示されている。 For example, Patent Document 1 discloses a first Al a Ga b In 1 -ab N v 0 ≦ a ≦ 1, 0 ≦ b ≦ 1, and 0 ≦ a + b ≦ 1) layer formed on a Si base material. , Second Al c Ga d In 1-cd N w (0 ≦ c ≦ 1, 0 ≦ d ≦ 1, and 0 ≦ n) formed on the first Al a Ga b In 1-ab Nv layer. c + d ≦ 1) layer and the second Al c Ga d in 1 - c - d N w located on the layer, the third Al e Ga f in 1 - e - f N x 0 ≦ e ≦ 1 the 0 ≦ f ≦ 1, and 0 ≦ e + f ≦ 1) layer and the fourth Al g Ga h in 1-gh N y 0 ≦ g ≦ 1,0 ≦ h ≦ 1, and 0 ≦ g + h ≦ 1) layer Alternating multilayer films and fifth Al i Ga j In 1-ij N z (0 ≦ i ≦ 1, 0 ≦ j ≦ 1, and 0 ≦ i + j ≦ 1) layers formed on the multilayer film And the third Al e Ga f In 1 in the multilayer film - e - f N x layer and the fourth Al g Ga h In the number of stacked 1-gh N y layer is a semiconductor substrate is disclosed which is characterized in that not more than 160 layers.

また、特許文献2には、シリコン基板上に窒化物半導体領域を設けると、半導体ウエーハに反りが発生するという課題に対して、シリコン基板2の上に窒化物半導体から成るバッファ領域3を介して主半導体領域4を設けるが、その前記バッファ領域3を、複数の多層構造バッファ領域5,5′と、該複数の多層構造バッファ領域5,5′の相互間に配置された第2の単層構造バッファ領域8とで構成すること、そして、複数の多層構造バッファ領域5,5′のそれぞれを、交互に配置された複数の第1及び第2の層から成るサブ多層構造バッファ領域と第2の単層構造バッファ領域8よりも薄い第1の単層構造バッファ領域とで構成する、という技術が開示されている。 Further, in Patent Document 2, the problem that when a nitride semiconductor region is provided on a silicon substrate causes warpage of the semiconductor wafer, a buffer region 3 made of a nitride semiconductor is provided on the silicon substrate 2 via a buffer region 3. A main semiconductor region 4 is provided, and the buffer region 3 includes a plurality of multilayer structure buffer regions 5 and 5 ′ and a second single layer disposed between the plurality of multilayer structure buffer regions 5 and 5 ′. Each of the plurality of multi-layer structure buffer regions 5 and 5 'is divided into a sub-multi-layer structure buffer region composed of a plurality of first and second layers arranged alternately and a second one. A technique is disclosed in which the first single-layer structure buffer region is thinner than the single-layer structure buffer region 8.

さらに、非特許文献1には、Si基板上に、AlN層(〜40nm)、GaN層(160nm)を堆積後、複数の AlN層とGaN層を繰り返し堆積した構造を有する超格子層とこれらの間に配置したGaN層(200nm)をバッファ領域として構成する、という技術が開示されている。 Further, Non-Patent Document 1 discloses a superlattice layer having a structure in which an AlN layer (˜40 nm) and a GaN layer (160 nm) are deposited on a Si substrate, and then a plurality of AlN layers and a GaN layer are repeatedly deposited. A technique is disclosed in which a GaN layer (200 nm) disposed therebetween is configured as a buffer region.

特開2007−258230号公報JP 2007-258230 A 特開2008−205117号公報JP 2008-205117 A

Applied physics letters. Volume79 No.20 November 12 2001 Eric Feltim et.al「Stesscontrol in GaN grown on Si(111) by metalorganic vapor phase epitaxy」Applied physics letters.Volume79 No.20 November 12 2001 Eric Feltim et.al `` Stesscontrol in GaN grown on Si (111) by metalorganic vapor phase epitaxy ''

特許文献1に開示されている技術は、Si基板上に窒化物半導体の多層膜を介して、その上に厚いGaN層を形成することができる、好適な一例である。しかしながら、この技術をもってしても、より反りが低減された窒化物半導体基板を作製するには、必ずしも十分とはいえなかった。 The technique disclosed in Patent Document 1 is a suitable example in which a thick GaN layer can be formed on a Si substrate via a nitride semiconductor multilayer film. However, even with this technique, it has not always been sufficient to produce a nitride semiconductor substrate with reduced warpage.

特許文献2に開示されている技術は、周期構造と他の1層からなる多層膜があり、さらに他の1層を介して、再度この多層膜を形成している点が特徴といえる。しかし、この方法では、層数が膨大になること、製造工程数の増加、基板の設計に対する制約増加、という点も懸念される。 The technique disclosed in Patent Document 2 is characterized in that there is a multilayer film composed of a periodic structure and another layer, and this multilayer film is formed again through another layer. However, with this method, there are concerns that the number of layers will be enormous, the number of manufacturing steps will increase, and the constraints on the substrate design will increase.

非特許文献1に開示されている技術も、Si等の基板上に、窒化物半導体の多層膜を形成することで、転位密度を減少し、結晶性を向上する効果を呈する。しかしながら、この技術でも、反りやクラックが発生する場合があり、結晶性と反り抑制とを両立した窒化半導体基板を作製するには、必ずしも十分とはいえなかった。 The technique disclosed in Non-Patent Document 1 also has the effect of reducing dislocation density and improving crystallinity by forming a nitride semiconductor multilayer film on a substrate such as Si. However, even with this technique, warping and cracks may occur, and it has not always been sufficient to produce a nitride semiconductor substrate that achieves both crystallinity and warpage suppression.

本発明は、これらの課題を鑑みてなされたもので、効果的に転位発生の防止と基板の反りを低減すること、そして、これらの効果を簡易に実現できる、Si単結晶基板を用いた窒化ガリウム系化合物半導体基板を提供するものである。 The present invention has been made in view of these problems, and can effectively prevent the occurrence of dislocation and reduce the warpage of the substrate, and can easily realize these effects by nitriding using a Si single crystal substrate. A gallium compound semiconductor substrate is provided.

本発明に係る窒化ガリウム系化合物半導体基板は、Si単結晶からなる基板と、前記基板上に形成された窒化物半導体からなる中間層と、前記中間層上に形成された窒化ガリウム系化合物半導体からなる活性層で構成される窒化ガリウム系化合物半導体基板であって、前記中間層は、前記基板上に第一層と第二層がこの順で積層された初期バッファ層と、前記初期バッファ層上に第三層と第四層をこの順で複数回繰り返し積層し最後に第五層を積層してなる複合層を複数積層した周期堆積層からなり、前記第五層の膜厚が200nm以上、かつ、前記第三層と前記第四層からなる対の層の厚さの2倍以上20倍以下であることを特徴とする。このような構成をとることで、単純構造でも反りの制御性に優れ、厚膜成膜も可能な、結晶性の良い窒化ガリウム系化合物半導体基板とすることができる。 A gallium nitride compound semiconductor substrate according to the present invention includes a substrate made of Si single crystal, an intermediate layer made of a nitride semiconductor formed on the substrate, and a gallium nitride compound semiconductor formed on the intermediate layer. The intermediate layer includes an initial buffer layer in which a first layer and a second layer are stacked in this order on the substrate, and an initial buffer layer on the initial buffer layer. third layer and Ri Do a plurality of times repeatedly stacked last cycle the deposited layer where the composite layer formed by laminating a fifth layer stacking a plurality of the fourth layer in this order, the thickness of the fifth layer is more than 200nm in and the said third layer wherein 20 times or less der Rukoto least twice the thickness of the fourth made pairs from layers layer. By adopting such a structure, a gallium nitride compound semiconductor substrate with good crystallinity that has excellent warpage controllability and can be formed into a thick film even with a simple structure can be obtained.

本発明に係る窒化ガリウム系化合物半導体基板の製造方法は、Si単結晶からなる基板上に第一層と第二層をこの順で積層する初期バッファ層形成工程と、前記初期バッファ層上に第三層と第四層をこの順に複数回繰り返し積層し最後に第五層を積層してなる複合層を複数積層して周期堆積層を形成する工程と、からなることを特徴とする。このような構成をとることで、少ない積層数で反りの制御性に優れた窒化ガリウム系化合物半導体基板を製造することができる。 The method for manufacturing a gallium nitride-based compound semiconductor substrate according to the present invention includes an initial buffer layer forming step of laminating a first layer and a second layer in this order on a substrate made of Si single crystal, and a first step on the initial buffer layer. A step of forming a periodic deposition layer by repeatedly stacking a plurality of composite layers formed by repeatedly stacking a third layer and a fourth layer in this order a plurality of times and finally stacking a fifth layer. By adopting such a configuration, it is possible to manufacture a gallium nitride compound semiconductor substrate having a small number of stacked layers and excellent warpage controllability.

本発明に係る窒化ガリウム系化合物半導体基板では、中間層を構成する窒化物半導体層の積層数が少なくても、転位発生の防止と基板の反り低減を図ることが出来る。また、異なる材質の薄膜を多数積層することで発生する応力発生を緩和し、塑性変形を抑制することにより、Si基板上に成膜できる総膜厚の増加が可能となる。 In the gallium nitride compound semiconductor substrate according to the present invention, even when the number of stacked nitride semiconductor layers constituting the intermediate layer is small, it is possible to prevent the occurrence of dislocation and reduce the warpage of the substrate. In addition, it is possible to increase the total film thickness that can be formed on the Si substrate by relaxing the generation of stress generated by stacking a large number of thin films of different materials and suppressing plastic deformation.

以下、本発明の実施形態について詳細に説明する。図1は、本発明の一態様に係る窒化ガリウム系化合物半導体基板を、基板の断面方向からみたときの積層構造を示す概念図である。 Hereinafter, embodiments of the present invention will be described in detail. FIG. 1 is a conceptual diagram illustrating a stacked structure when a gallium nitride-based compound semiconductor substrate according to one embodiment of the present invention is viewed from the cross-sectional direction of the substrate.

本発明の一態様に係る窒化ガリウム系化合物半導体基板を、基板の断面方向からみたときの積層構造を示す概念図。1 is a conceptual diagram illustrating a stacked structure when a gallium nitride-based compound semiconductor substrate according to one embodiment of the present invention is viewed from a cross-sectional direction of the substrate.

本発明に係る窒化ガリウム系化合物半導体基板100は、Si単結晶からなる基板1と、前記基板1上に形成された窒化物半導体からなる中間層2と、前記中間層上に形成された窒化ガリウム系化合物半導体からなる活性層3で構成される。 A gallium nitride compound semiconductor substrate 100 according to the present invention includes a substrate 1 made of Si single crystal, an intermediate layer 2 made of a nitride semiconductor formed on the substrate 1, and a gallium nitride formed on the intermediate layer. The active layer 3 is made of a compound semiconductor.

基板1に用いられるSi単結晶は、化合物半導体を形成する下地としての役割を有するが、基本的な製法や結晶構造は特に限定されるものではなく、公知の半導体デバイス用Si単結晶基板を広く用いることができる。例えば、Si単結晶育成方法は、CZ法でもFZ法でもよい。さらには、基板加工処理として各種熱処理を施したSi単結晶基板も適用できる。また、Si単結晶基板の面方位やベベル形状、化合物半導体が形成される主面および裏面の面粗さ等の仕上げ状態についても、設計する窒化ガリウム系化合物半導体基板100の仕様に合わせて適時選択できる。 The Si single crystal used for the substrate 1 has a role as a base for forming a compound semiconductor, but the basic manufacturing method and crystal structure are not particularly limited, and a wide variety of known Si single crystal substrates for semiconductor devices can be used. Can be used. For example, the Si single crystal growth method may be the CZ method or the FZ method. Furthermore, a Si single crystal substrate subjected to various heat treatments as a substrate processing can be applied. In addition, finish conditions such as the surface orientation and bevel shape of the Si single crystal substrate, and the surface roughness of the main surface and the back surface on which the compound semiconductor is formed are selected as appropriate according to the specifications of the gallium nitride compound semiconductor substrate 100 to be designed. it can.

基板1上に形成された窒化物半導体からなる中間層2は、Si単結晶と活性層に用いられる窒化物半導体との格子定数の違いによる不整合や、熱膨張係数の違いにより発生する応力を、効果的に緩和する働きをもつ。中間層2としては、任意の厚さと組成をもつ窒化物半導体を積層した多層構造が、好適に用いられる。 The intermediate layer 2 made of a nitride semiconductor formed on the substrate 1 is subject to a mismatch caused by a difference in lattice constant between the Si single crystal and the nitride semiconductor used for the active layer, or stress generated due to a difference in thermal expansion coefficient. It has the function of effectively mitigating. As the intermediate layer 2, a multilayer structure in which nitride semiconductors having arbitrary thicknesses and compositions are stacked is preferably used.

中間層2上には、窒化物半導体からなる活性層3が形成される。ここには、窒化ガリウム系化合物半導体基板として各種の材料が適用でき、例えばAlGaN、GaN等の窒化物半導体結晶が用いられる。 An active layer 3 made of a nitride semiconductor is formed on the intermediate layer 2. Here, various materials can be applied as the gallium nitride-based compound semiconductor substrate, and for example, nitride semiconductor crystals such as AlGaN and GaN are used.

そして、本発明に係る窒化ガリウム系化合物半導体基板100においては、前記初期バッファ層200上に、第三層23と第四層24をこの順で複数回繰り返し積層し最後に第五層25を積層してなる複合層202を複数積層した周期堆積層203と、周期堆積層203上に活性層3が積層された構造からなる。 In the gallium nitride compound semiconductor substrate 100 according to the present invention, the third layer 23 and the fourth layer 24 are repeatedly stacked in this order on the initial buffer layer 200, and finally the fifth layer 25 is stacked. A periodic deposition layer 203 in which a plurality of composite layers 202 are laminated, and a structure in which the active layer 3 is laminated on the periodic deposition layer 203.

基板1上に中間層2を直接形成する前に、初期バッファ層200を介在させることで、初期バッファ層200がない場合と比べて、周期堆積層の積層数を増やすことなく積層界面が平坦化され、また、基板100全体の反り低減、クラック発生の抑制の効果が増す。 Before the intermediate layer 2 is directly formed on the substrate 1, by interposing the initial buffer layer 200, the stack interface is flattened without increasing the number of stacks of the periodic deposition layers compared to the case where the initial buffer layer 200 is not provided. In addition, the effect of reducing the warpage of the entire substrate 100 and suppressing the generation of cracks is increased.

さらに、本発明においては、初期バッファ層200が、異なる組成の窒化物半導体からなる2層構造をとる。このような構成をとると、1層のみで単に基板のSiとGaの反応を抑制するだけではなく、応力制御バッファ層203に移る前の格子不整合緩衝層として成膜表面平坦化に特化することも可能となる。よって、この上に形成される多層構造の領域における反り低減、転位密度低減効果が、より効果的に発揮される。さらに、中間層2における多層構造の層数が、必要以上に増大することも抑制できる。 Further, in the present invention, the initial buffer layer 200 has a two-layer structure made of nitride semiconductors having different compositions. With such a configuration, not only suppressing the reaction of Si and Ga on the substrate with only one layer, but also specializing in planarizing the deposition surface as a lattice mismatch buffer layer before moving to the stress control buffer layer 203 It is also possible to do. Therefore, the effect of reducing warpage and dislocation density in the region of the multilayer structure formed thereon is more effectively exhibited. Furthermore, it is possible to suppress an increase in the number of layers of the multilayer structure in the intermediate layer 2 more than necessary.

初期バッファ層200は、窒化ガリウム系化合物半導体基板100の要求仕様に応じて、その組成や膜厚は適時選択されるが、その組成は、AlGaN系が好ましい。また、その膜厚は、この上に形成される多層構造で用いられる各層の膜厚に対して、5倍から100倍の厚さを有していることが好ましい。このような構成をとることで、初期バッファ層200における第一層にて基板を保護するだけでなく、第二層にて最も大きな基板との格子不整合による欠陥多発にともなう第一層の成膜表面荒れ(段差、凹凸等)を緩和でき、成膜表面の平坦化が可能となるからである。 The composition and film thickness of the initial buffer layer 200 are appropriately selected according to the required specifications of the gallium nitride compound semiconductor substrate 100, but the composition is preferably AlGaN. Moreover, it is preferable that the film thickness has 5 to 100 times the film thickness of each layer used by the multilayer structure formed on this. By adopting such a configuration, not only the substrate is protected by the first layer in the initial buffer layer 200, but also the formation of the first layer due to frequent occurrence of defects due to lattice mismatch with the largest substrate in the second layer. This is because roughness of the film surface (steps, unevenness, etc.) can be alleviated and the film formation surface can be flattened.

初期バッファ層200のより好ましい例としては、第一層21が50nmから200nmの厚さのAlN、第二層22が100nmから300nmの厚さのAlGaNで構成される。初期バッファ層としては、Si、GaNとの親和性が高く、メルトバックエッチング反応を起こさないAlN単結晶が適しており、また、AlN単結晶層表面の段差を早期に平坦化するためには、下地に近いAlが含まれるGaNとAlNの混晶であるAlGaN単結晶層も挿入しておくことが好ましいためである。 As a more preferable example of the initial buffer layer 200, the first layer 21 is made of AlN having a thickness of 50 nm to 200 nm, and the second layer 22 is made of AlGaN having a thickness of 100 nm to 300 nm. As the initial buffer layer, an AlN single crystal having high affinity with Si and GaN and not causing a meltback etching reaction is suitable, and in order to flatten the step on the surface of the AlN single crystal layer at an early stage, This is because it is preferable to insert an AlGaN single crystal layer which is a mixed crystal of GaN and AlN containing Al close to the base.

次に、この初期バッファ層200上に、窒化物半導体からなる第三層23と第四層24をこの順で積層した対の層201を複数回繰り返し積層する。公知の技術にもあるように、異なる2つの組成、膜厚の層から形成される対の層を繰り返し形成することで、窒化ガリウム系化合物半導体基板100の反りを緩和できる。 Next, a pair of layers 201 in which the third layer 23 and the fourth layer 24 made of a nitride semiconductor are stacked in this order are repeatedly stacked on the initial buffer layer 200 a plurality of times. As known in the art, warping of the gallium nitride compound semiconductor substrate 100 can be alleviated by repeatedly forming a pair of layers formed of layers having two different compositions and film thicknesses.

なお、第三層23と第四層24の組成や膜厚は、設計される窒化ガリウム系化合物半導体基板100の仕様に応じて任意に設定できる。本発明に係る窒化ガリウム系化合物半導体基板100では、第三層23と第四層24がAlGaN系の窒化物半導体であることが好ましい。第三層23と第四層24のAlの比率が大きく離れていると、格子歪みが大きくなり、応力制御および結晶性向上の効果を薄い膜厚から発揮する)ので、より好ましい。好適な一例として、第三層23がGaN、第四層24がAlNで構成される。 The composition and film thickness of the third layer 23 and the fourth layer 24 can be arbitrarily set according to the specifications of the gallium nitride compound semiconductor substrate 100 to be designed. In the gallium nitride compound semiconductor substrate 100 according to the present invention, the third layer 23 and the fourth layer 24 are preferably AlGaN nitride semiconductors. It is more preferable that the ratio of Al between the third layer 23 and the fourth layer 24 is far apart because the lattice distortion increases and the effects of stress control and crystallinity improvement are exhibited from a thin film thickness). As a preferred example, the third layer 23 is made of GaN and the fourth layer 24 is made of AlN.

第三層23と第四層24の膜厚は、繰り返し積層する観点から、あまり厚く形成しないほうが好ましい。好適には、それぞれ1〜50nmである。また、第三層23がと第四層24の繰り返し回数は、設計される窒化ガリウム系化合物半導体基板100の仕様に応じて任意に設定できるが、5回以上20回以下であることが好ましい。少なすぎると、反りや転位の低減効果が十分得られず、多すぎると、成膜中の応力発生により基板の塑性変形を誘発し、成膜後の反りへの影響が懸念されるからである。 The film thicknesses of the third layer 23 and the fourth layer 24 are preferably not so thick from the viewpoint of repeated lamination. Preferably, it is 1-50 nm respectively. The number of repetitions of the third layer 23 and the fourth layer 24 can be arbitrarily set according to the specifications of the gallium nitride compound semiconductor substrate 100 to be designed, but is preferably 5 times or more and 20 times or less. If the amount is too small, the effect of reducing warpage and dislocation cannot be sufficiently obtained. If the amount is too large, plastic deformation of the substrate is induced by the generation of stress during film formation, and there is a concern about the influence on the warp after film formation. .

そして、本発明においては、対の層201を複数回繰り返し積層した上に、さらに第五層25を1層積層して、複合層202とする。第五層25の組成や膜厚も、設計される窒化ガリウム系化合物半導体基板100の仕様に応じて任意に設定できるが、AlGaN系の窒化物半導体であることが好ましい。好適な一例として、第三層23がGaN、第四層24がAlNで構成される場合に、第五層25がGaNで構成される。 In the present invention, the pair of layers 201 is repeatedly stacked a plurality of times, and then the fifth layer 25 is further stacked to form a composite layer 202. The composition and film thickness of the fifth layer 25 can also be arbitrarily set according to the specifications of the gallium nitride compound semiconductor substrate 100 to be designed, but it is preferably an AlGaN nitride semiconductor. As a preferred example, when the third layer 23 is made of GaN and the fourth layer 24 is made of AlN, the fifth layer 25 is made of GaN.

中間層2の多層構造は、反り、転位密度、熱導電性、高抵抗化、その他の特性への影響度に応じて、任意に設計できる。対の層201の繰り返しのみで中間層2を形成することは、反りや転位の低減には有効である。しかし、基板1と中間層2との格子不整合による積層界面平坦性劣化、すなわち面荒れは、対の層201の繰り返しの早期段階において緩和することができない。このため、従来は、対の層201の繰り返し数をかなり多くとる必要があった。また、この場合、中間層2が必要以上に厚膜化して反り量増加の影響が大きくなり、窒化ガリウム系化合物半導体基板100全体の反りを低減することが、困難になるおそれがあった。 The multilayer structure of the intermediate layer 2 can be arbitrarily designed according to the degree of influence on warpage, dislocation density, thermal conductivity, high resistance, and other characteristics. Forming the intermediate layer 2 only by repeating the pair of layers 201 is effective in reducing warpage and dislocation. However, the degradation of the flatness of the laminated interface due to the lattice mismatch between the substrate 1 and the intermediate layer 2, that is, the surface roughness cannot be mitigated at an early stage of repetition of the pair of layers 201. For this reason, conventionally, it has been necessary to increase the number of repetitions of the pair of layers 201. Further, in this case, the intermediate layer 2 is made thicker than necessary, and the influence of the increase in the amount of warpage is increased, which may make it difficult to reduce the warpage of the entire gallium nitride compound semiconductor substrate 100.

ここで、対の層201を複数回繰り返し積層した上に、さらに第五層25を1層積層することで、少ない層数で、効果的に反り低減効果が得られる。これは、転位の消滅を考えず圧縮応力の発生のみを考えるのであれば、格子定数の小さい材料の上に、格子定数の大きい材料を数100nm以上コヒーレント成長させるのが、応力発生効果においては最も好ましいと考えられるが、より低転位な結晶であるほどその効果が向上するためである。このような構成とすることで、応力発生と転位消滅の両効果を発揮し、最も効果的な反りの低減が可能となる。 Here, by repeatedly laminating the pair of layers 201 a plurality of times and further laminating one fifth layer 25, the warp reduction effect can be effectively obtained with a small number of layers. If we consider only the generation of compressive stress without considering the disappearance of dislocations, the most effective stress generation effect is to coherently grow a material with a large lattice constant over several hundreds of nanometers on a material with a small lattice constant. Although it is considered preferable, it is because the lower the dislocation crystal, the better the effect. By adopting such a configuration, both the effects of stress generation and dislocation disappearance are exhibited, and the most effective reduction of warpage is possible.

なお、第五層25の膜厚は、対の層201の厚さの2倍以上20倍以下であることが、より好ましい。第五層25は、対の層201を伝播して基板上方に進展してきた転位を、基板主面に対して水平方向に屈曲させる作用を有する。このとき、第五層25の膜厚を対の層201に対して十分な厚さを持たせることで、効果的にこの作用を発揮させることが出来る。しかしながら、あまり厚すぎると、本発明の効果がほとんど変わらない一方で、膜厚が大きいことによる反り増大の影響が懸念されるので、好ましいものではない。 The film thickness of the fifth layer 25 is more preferably not less than 2 times and not more than 20 times the thickness of the pair of layers 201. The fifth layer 25 has a function of bending the dislocations propagating through the pair of layers 201 and progressing above the substrate in the horizontal direction with respect to the main surface of the substrate. At this time, by providing the fifth layer 25 with a sufficient thickness with respect to the pair of layers 201, this function can be effectively exhibited. However, if the thickness is too large, the effect of the present invention is hardly changed. On the other hand, the influence of an increase in warping due to the large film thickness is a concern, and therefore it is not preferable.

この複合層202がさらに複数回繰り返して積層され、周期堆積層203が構成される。複合層202単体でも反り低減効果が見られるが、活性層3の厚膜化に伴う反り増加をより効果的に低減するために、複合層202を繰り返し積層する。 This composite layer 202 is further repeatedly laminated to form a periodic deposition layer 203. Although the composite layer 202 alone has an effect of reducing warpage, the composite layer 202 is repeatedly laminated in order to more effectively reduce the increase in warpage accompanying the increase in the thickness of the active layer 3.

複合層202の繰り返し回数は、3回以上10回以下が好ましい。繰り返し回数が増えるに従い、中間層2の厚膜化による反り量増加の影響が大きくなるので、この範囲内で設計することで、より適切な反り制御が可能となる。 The number of repetitions of the composite layer 202 is preferably 3 to 10 times. As the number of repetitions increases, the influence of the amount of warpage due to the thickening of the intermediate layer 2 becomes larger. Therefore, more appropriate warpage control can be performed by designing within this range.

そして、周期堆積層203上には、活性層3が積層される。HEMT構造の場合、活性層3は、電子供給層として成膜される。活性層3は、窒化ガリウム系化合物半導体で形成され、電子走行層,チャネル層としての役割をもつ。なお、活性層3の組成や膜厚は、設計する窒化ガリウム系化合物半導体基板100の仕様に基づき、任意に設定できる。一例として、組成としては、好適にはAlGaNが、より好適にはGaNが適用される。また、その膜厚は、好適には500nm以上3000nm、より好適には1000nm以上2000nm以下である。 Then, the active layer 3 is laminated on the periodic deposition layer 203. In the case of the HEMT structure, the active layer 3 is formed as an electron supply layer. The active layer 3 is made of a gallium nitride compound semiconductor and has a role as an electron transit layer and a channel layer. The composition and thickness of the active layer 3 can be arbitrarily set based on the specifications of the gallium nitride compound semiconductor substrate 100 to be designed. As an example, the composition is preferably AlGaN, more preferably GaN. The film thickness is preferably 500 nm to 3000 nm, and more preferably 1000 nm to 2000 nm.

このように、本発明の中間層2は、初期バッファ層200と、第一層から第五層を適切に組み合わせた複合層202の繰返し積層からなる周期堆積層203という構成をとる。特に、薄い対の層201の繰り返し積層のみでは、積層数を数多くする必要があったのに対して、繰り返し積層の下には2層を、上には単層を介在させ、これに合わせて繰り返し積層を最適化したことで、中間層2全体の層数を抑制することが可能となった。 As described above, the intermediate layer 2 of the present invention has a configuration of the initial buffer layer 200 and the periodic deposition layer 203 formed by repeated lamination of the composite layer 202 in which the first to fifth layers are appropriately combined. In particular, it was necessary to increase the number of stacked layers only in the repeated stacking of the thin pair of layers 201, whereas two layers were interposed below the repeated stacking, and a single layer was interposed on the top. By optimizing the repeated lamination, it was possible to suppress the total number of intermediate layers 2.

以上のとおり、本発明に係る窒化ガリウム系化合物半導体基板では、転位発生の防止と基板の反り低減を、中間層を構成する窒化物半導体層の積層数を少なくして実現できる。 As described above, in the gallium nitride-based compound semiconductor substrate according to the present invention, it is possible to prevent the occurrence of dislocation and reduce the warpage of the substrate by reducing the number of stacked nitride semiconductor layers constituting the intermediate layer.

以下、本発明の好ましい実施形態を実施例に基づき説明するが、本発明はこの実施例により限定されるものではない。 Hereinafter, preferred embodiments of the present invention will be described based on examples, but the present invention is not limited to these examples.

面方位(111)、直径4インチ、厚さ625μm、CZ法により引上げたSi単結晶基板1を、MOCVD装置にセットし、原料としてトリメチルアルミニウム(TMA)、およびNH3を用い、1100℃での気相成長により、厚さ100nmのAlN単結晶層21を形成した。さらにその上に、原料としてトリメチルガリウム(TMG)、TMAおよびNH3を用い、1000℃での気相成長により厚さ200nmのAl0.1Ga0.9N単結晶層22を積層させ、この2層を初期バッファ層200とした。 A Si single crystal substrate 1 having a plane orientation (111), a diameter of 4 inches, a thickness of 625 μm, and pulled by a CZ method is set in an MOCVD apparatus, and trimethylaluminum (TMA) and NH 3 are used as raw materials at 1100 ° C. An AlN single crystal layer 21 having a thickness of 100 nm was formed by vapor phase growth. Further thereon, trimethylgallium (TMG), TMA and NH 3 are used as raw materials, and an Al 0.1 Ga 0.9 N single crystal layer 22 having a thickness of 200 nm is laminated by vapor phase growth at 1000 ° C. Two layers were used as the initial buffer layer 200.

次に、前記初期バッファ層200上に、原料としてTMAおよびNH3を用い、1000℃での気相成長により、それぞれ厚さを、25nm(実施例1)、20nm(実施例2)、15nm(実施例3)のGaN単結晶層23を積層させ、続けて、厚さ5nmのAlN単結晶層24を積層させ、対の層201を形成した。この対の層201を同様の工程にて繰り返し積層して、それぞれ積層数を、6回(実施例1)、8回(実施例2),10回(実施例3)とした。さらにこの上に、第五層25として、それぞれGaN層を、220nm(実施例1)、200nm(実施例2)、400nm(実施例3)の厚さで形成し、これを複合層202とした。この複合層202を、それぞれ積層数を、6層(実施例1)、5層(実施例2)、4層(実施例3)として、周期堆積層203とした。以上のようにして、中間層2を形成した。 Next, TMA and NH 3 are used as raw materials on the initial buffer layer 200, and the thicknesses are 25 nm (Example 1), 20 nm (Example 2), and 15 nm by vapor phase growth at 1000 ° C. ( The GaN single crystal layer 23 of Example 3) was laminated, and then the AlN single crystal layer 24 having a thickness of 5 nm was laminated to form a pair of layers 201. This pair of layers 201 was repeatedly laminated in the same process, and the number of laminations was 6 times (Example 1), 8 times (Example 2), and 10 times (Example 3), respectively. Furthermore, as the fifth layer 25, a GaN layer is formed with a thickness of 220 nm (Example 1), 200 nm (Example 2), and 400 nm (Example 3) as the fifth layer 25, and this is used as the composite layer 202. . The composite layer 202 was formed as a periodic deposition layer 203 with the number of layers being 6 (Example 1), 5 (Example 2), and 4 (Example 3). As described above, the intermediate layer 2 was formed.

前記中間層2上に、原料としてTMGおよびNH3を用い、1000℃での気相成長により、厚さ1500nmのGaN単結晶層を形成してこれを活性層3とした。さらに、前記活性層3の上に、原料としてTMG、TMA、およびNH3を用い、1000℃での気相成長により、厚さ50nmのAlGaN単結晶層を積層させて、電子供給層を形成した。以上の工程を経て、実施例1から実施例3の評価用窒化物半導体基板を得た。なお、気相成長で形成した各層の厚さは、原料供給流量および原料供給時間の調整により行った。加えて、実施例1の中間層2上に活性層3を3500nm積層したものを実施例4,中間層2の複合周期数を8周期とし、活性層3を3000nm積層したものを実施例5とした。 A GaN single crystal layer having a thickness of 1500 nm was formed on the intermediate layer 2 by vapor phase growth at 1000 ° C. using TMG and NH 3 as raw materials, and this was used as the active layer 3. Further, an electron supply layer was formed on the active layer 3 by stacking an AlGaN single crystal layer having a thickness of 50 nm by vapor phase growth at 1000 ° C. using TMG, TMA, and NH 3 as raw materials. . The nitride semiconductor substrate for evaluation of Example 1 to Example 3 was obtained through the above steps. The thickness of each layer formed by vapor phase growth was adjusted by adjusting the raw material supply flow rate and the raw material supply time. In addition, the active layer 3 of 3500 nm laminated on the intermediate layer 2 of Example 1 is Example 4 and the composite layer number of the intermediate layer 2 is 8 periods, and the active layer 3 is 3000 nm laminated as in Example 5. did.

次に、初期バッファ層200を省略した構造となるようにして、比較例1の評価用窒化物半導体基板を得た。 Next, an evaluation nitride semiconductor substrate of Comparative Example 1 was obtained so as to have a structure in which the initial buffer layer 200 was omitted.

また、実施例1における初期バッファ層200のうち、第二層22のみ省略し、それ以外は実施例1と同様の構造となるようにして、比較例2の評価用窒化物半導体基板を得た。 Further, in the initial buffer layer 200 in Example 1, only the second layer 22 was omitted, and other than that, the nitride semiconductor substrate for evaluation of Comparative Example 2 was obtained in the same structure as in Example 1. .

さらに、複合層202から第三層を除いた構造を比較例3、比較例3から複合周期数と活性層厚さを増加した構造を比較例4、実施例2において、第二層の厚さを薄く、第五層を除いた構造を比較例5,6、第三層と第四層の厚さを好ましい範囲より薄くしたものを比較例7として、それぞれ評価用窒化物半導体基板を得た。 Further, the structure obtained by removing the third layer from the composite layer 202 is the comparative example 3, the structure in which the composite period number and the active layer thickness are increased from the comparative example 3 is the comparative example 4 and the thickness of the second layer in the example 2. Nitride semiconductor substrates for evaluation were obtained respectively as Comparative Examples 5 and 6, except that the thickness of the third layer and the fourth layer were made thinner than the preferred ranges. .

作製した実施例および比較例の評価用窒化物半導体基板について、活性層として用いられるGaN単結晶層の基板面中心部における転位密度を、AFM観察により評価した。また、反りおよびクラックの発生(基板外周を除く)についても、レーザー変位計および光学顕微鏡の暗視野像により評価した。なお、反りは、エピタキシャル成長前の基板裏面が基板厚さ方向に変位した距離の最大値と最小値の差により評価した。表1に、成膜後の外観、AFM観察による転位密度、XRDによる結晶性(半値幅)、レーザー変位計による反り評価結果を示す。 For the nitride semiconductor substrates for evaluation of the produced examples and comparative examples, the dislocation density at the center of the substrate surface of the GaN single crystal layer used as the active layer was evaluated by AFM observation. Further, the occurrence of warpage and cracks (excluding the outer periphery of the substrate) was also evaluated by a dark field image of a laser displacement meter and an optical microscope. The warpage was evaluated based on the difference between the maximum value and the minimum value of the distance that the back surface of the substrate before epitaxial growth was displaced in the substrate thickness direction. Table 1 shows the appearance after film formation, dislocation density by AFM observation, crystallinity by XRD (half-value width), and warpage evaluation results by a laser displacement meter.

これらの結果から、周期堆積層203の下に位置する初期バッファ層200の有無や、本発明の好ましい構成を有する周期堆積層の有無によって、転位密度や反りの点で優位差がみられ、本発明の構成による効果が確認された。 From these results, there is a significant difference in dislocation density and warpage depending on the presence or absence of the initial buffer layer 200 located under the periodic deposition layer 203 and the presence or absence of the periodic deposition layer having a preferred configuration of the present invention. The effect of the configuration of the invention was confirmed.

本発明は、発光ダイオード、レーザー発光素子、また、高速・高温での動作可能な電子素子等に好適に用いられるHEMT(High Electron Mobility Transistor;高電子移動度トランジスタ)構造を有する窒化ガリウム系化合物半導体基板として、好適に適用することができる。 The present invention relates to a gallium nitride-based compound semiconductor having a HEMT (High Electron Mobility Transistor) structure suitably used for a light-emitting diode, a laser light-emitting element, and an electronic element capable of operating at high speed and high temperature. It can be suitably applied as a substrate.

1…Si単結晶基板、2…中間層、3…活性層、21…第一層、22…第二層、23…第三層、24…第四層、25…第五層、200…初期バッファ層、201…対の層、202…複合層、203…周期堆積層 1 ... Si single crystal substrate, 2 ... intermediate layer, 3 ... active layer, 21 ... first layer, 22 ... second layer, 23 ... third layer, 24 ... fourth layer, 25 ... fifth layer, 200 ... initial stage Buffer layer, 201 ... pair layer, 202 ... composite layer, 203 ... periodic deposition layer

Claims (2)

Si単結晶からなる基板と、前記基板上に形成された窒化物半導体からなる中間層と、前記中間層上に形成された窒化ガリウム系化合物半導体からなる活性層で構成される窒化ガリウム系化合物半導体基板であって、前記中間層は、前記基板上に第一層と第二層がこの順で積層された初期バッファ層と、前記初期バッファ層上に第三層と第四層をこの順で複数回繰り返し積層し最後に第五層を積層してなる複合層を複数積層した周期堆積層からなり、前記第五層の膜厚が200nm以上、かつ、前記第三層と前記第四層からなる対の層の厚さの2倍以上20倍以下であることを特徴とする窒化ガリウム系化合物半導体基板。 A gallium nitride compound semiconductor comprising a substrate made of Si single crystal, an intermediate layer made of nitride semiconductor formed on the substrate, and an active layer made of gallium nitride compound semiconductor formed on the intermediate layer The intermediate layer includes an initial buffer layer in which a first layer and a second layer are laminated in this order on the substrate, and a third layer and a fourth layer in this order on the initial buffer layer. multiple iterations laminated composite layer formed by the last stacked fifth layer Ri Do plurality stacked periodically deposited layer, the film thickness of the fifth layer is 200nm or more, and said fourth layer and said third layer gallium nitride and wherein the 20-fold less der Rukoto least twice the thickness of the layer pairs consisting of compound semiconductor substrate. 請求項1に記載の窒化ガリウム系化合物半導体基板の製造方法であって、Si単結晶からなる基板上に第一層と第二層をこの順で積層する初期バッファ層形成工程と、前記初期バッファ層上に第三層と第四層をこの順に複数回繰り返し積層し最後に第五層を積層してなる複合層を複数積層して周期堆積層を形成する工程と、からなることを特徴とする窒化ガリウム系化合物半導体基板の製造方法。 2. The method for manufacturing a gallium nitride compound semiconductor substrate according to claim 1, wherein an initial buffer layer forming step of laminating a first layer and a second layer in this order on a substrate made of Si single crystal, and the initial buffer. A step of forming a periodic deposition layer by laminating a plurality of composite layers formed by repeatedly laminating a third layer and a fourth layer multiple times in this order on the layer and finally laminating a fifth layer. A method for manufacturing a gallium nitride compound semiconductor substrate.
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