WO2016166949A1 - Semiconductor wafer and semiconductor device - Google Patents

Semiconductor wafer and semiconductor device Download PDF

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WO2016166949A1
WO2016166949A1 PCT/JP2016/001896 JP2016001896W WO2016166949A1 WO 2016166949 A1 WO2016166949 A1 WO 2016166949A1 JP 2016001896 W JP2016001896 W JP 2016001896W WO 2016166949 A1 WO2016166949 A1 WO 2016166949A1
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buffer layer
layer
group iii
nitride semiconductor
iii nitride
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French (fr)
Japanese (ja)
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紘子 井口
哲生 成田
伊藤 健治
嘉代 近藤
伸幸 大竹
真一 星
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株式会社デンソー
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02381Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02455Group 13/15 materials
    • H01L21/02458Nitrides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02494Structure
    • H01L21/02496Layer structure
    • H01L21/02505Layer structure consisting of more than two layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02516Crystal orientation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02538Group 13/15 materials
    • H01L21/0254Nitrides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/80Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/812Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes
    • H01L29/872Schottky diodes

Definitions

  • the present disclosure relates to a semiconductor wafer and a semiconductor device.
  • Patent Document 1 discloses a technique for growing a multilayer buffer layer on a silicon substrate and growing a group III nitride semiconductor layer (functional layer) on the multilayer buffer layer.
  • Patent Document 1 discloses a composition modulation layer in which a first unit layer and a second unit layer having different compositions are repeatedly laminated, a termination layer grown on the composition modulation layer, and an intermediate layer (strain strengthening) grown on the termination layer.
  • a multilayer buffer layer having a unit laminated structure and having a plurality of unit laminated structures.
  • the group III nitride semiconductor When a material with a smaller coefficient of thermal expansion than the group III nitride semiconductor is used as the substrate for growing the group III nitride semiconductor layer, the group III nitride semiconductor is cooled from a high temperature (during vapor phase growth) to a low temperature (typically room temperature). When it is done, tensile strain occurs inside.
  • the multilayer buffer layer has a compressive strain.
  • an intermediate layer strain strengthening layer is provided at a portion in contact with the group III nitride semiconductor layer, thereby strengthening the compressive strain of the multilayer buffer layer and canceling the tensile strain of the group III nitride semiconductor layer.
  • the group III nitride semiconductor layer grows while maintaining the compressive strain.
  • strain-induced step bunching is likely to occur in the group III nitride semiconductor layer, and the surface of the group III nitride semiconductor layer cannot be smoothed.
  • An object of the present disclosure is to provide a semiconductor wafer and a semiconductor device in which the surface of the group III nitride semiconductor layer is smooth.
  • a semiconductor wafer in the first aspect of the present disclosure, includes a substrate and a group III nitride semiconductor layer provided on the substrate via a multilayer buffer layer.
  • the multilayer buffer layer includes at least a first buffer layer and a second buffer layer.
  • the first buffer layer is in contact with the group III nitride semiconductor layer.
  • the second buffer layer is in contact with the first buffer layer and has a composition different from that of the first buffer layer.
  • the multilayer buffer layer has an average lattice constant smaller than that of the group III nitride semiconductor layer.
  • Interfacial lattice distortion of the group III nitride semiconductor layer at the interface between the group III nitride semiconductor layer and the first buffer layer is caused by the first buffer layer at the interface between the first buffer layer and the second buffer layer. Less than interfacial lattice distortion.
  • the interfacial lattice strain of the group III nitride semiconductor layer at the interface between the group III nitride semiconductor layer and the first buffer layer (hereinafter referred to as the interfacial lattice strain of the group III nitride semiconductor layer) is the first buffer. It is smaller than the interface lattice strain of the first buffer layer at the interface between the layer and the second buffer layer (hereinafter referred to as the interface lattice strain of the first buffer layer). Therefore, the group III nitride semiconductor layer is suppressed from growing while having the compressive strain of the first buffer layer.
  • the interface lattice strain of the group III nitride semiconductor layer smaller than the interface lattice strain of the first buffer layer, it is possible to suppress the occurrence of strain-induced step bunching in the group III nitride semiconductor layer.
  • the semiconductor wafer described above can smooth the surface of the group III nitride semiconductor layer.
  • a semiconductor device in a second aspect of the present disclosure, includes a substrate and a group III nitride semiconductor layer provided on the substrate via a multilayer buffer layer.
  • a semiconductor element is formed on the surface side of the group III nitride semiconductor layer.
  • the multilayer buffer layer includes at least a first buffer layer and a second buffer layer.
  • the first buffer layer is in contact with the group III nitride semiconductor layer.
  • the second buffer layer is in contact with the first buffer layer and has a composition different from that of the first buffer layer.
  • the multilayer buffer layer has an average lattice constant smaller than that of the group III nitride semiconductor layer.
  • Interfacial lattice distortion of the group III nitride semiconductor layer at the interface between the group III nitride semiconductor layer and the first buffer layer is caused by the first buffer layer at the interface between the first buffer layer and the second buffer layer. Less than interfacial lattice distortion.
  • the interfacial lattice strain of the group III nitride semiconductor layer (hereinafter referred to as the interfacial lattice strain of the group III nitride semiconductor layer) at the interface between the group III nitride semiconductor layer and the first buffer layer is the first buffer. It is smaller than the interface lattice strain of the first buffer layer at the interface between the layer and the second buffer layer (hereinafter referred to as the interface lattice strain of the first buffer layer). Therefore, the group III nitride semiconductor layer is suppressed from growing while having the compressive strain of the first buffer layer.
  • the interface lattice strain of the group III nitride semiconductor layer smaller than the interface lattice strain of the first buffer layer, it is possible to suppress the occurrence of strain-induced step bunching in the group III nitride semiconductor layer.
  • the semiconductor wafer described above can smooth the surface of the group III nitride semiconductor layer.
  • FIG. 1 schematically shows a cross-sectional view of the semiconductor wafer of the first embodiment
  • FIG. 2 shows the characteristics of the semiconductor wafer of the first embodiment
  • FIG. 3 schematically shows a cross-sectional view of the semiconductor wafer of the second embodiment
  • FIG. 4 shows the characteristics of the semiconductor wafer of the second embodiment
  • FIG. 5 shows the characteristics of the semiconductor wafer of the third embodiment
  • FIG. 6 shows the characteristics of the semiconductor wafer of Comparative Example 1.
  • FIG. 7 shows the characteristics of the semiconductor wafer of Comparative Example 2
  • FIG. 8 shows the results of the surface roughness of the semiconductor wafer for the examples and comparative examples.
  • a group III nitride semiconductor layer is provided on a substrate via a multilayer buffer layer.
  • the multilayer buffer layer has an average lattice constant smaller than that of the group III nitride semiconductor layer.
  • the multilayer buffer layer includes at least a first buffer layer and a second buffer layer.
  • the first buffer layer is in contact with the group III nitride semiconductor layer.
  • the second buffer layer is in contact with the first buffer layer.
  • the first buffer layer and the second buffer layer have different compositions.
  • the interfacial lattice strain of the group III nitride semiconductor layer at the interface between the group III nitride semiconductor layer and the first buffer layer is the first at the interface between the first buffer layer and the second buffer layer. It is smaller than the interfacial lattice distortion of one buffer layer.
  • the interfacial lattice strain of the group III nitride semiconductor layer at the interface between the group III nitride semiconductor layer and the first buffer layer (hereinafter referred to as the interfacial lattice strain of the group III nitride semiconductor layer) is the first buffer. It is smaller than the interface lattice strain of the first buffer layer at the interface between the layer and the second buffer layer (hereinafter referred to as the interface lattice strain of the first buffer layer). Therefore, the group III nitride semiconductor layer is suppressed from growing while having the compressive strain of the first buffer layer.
  • the interface lattice strain of the group III nitride semiconductor layer smaller than the interface lattice strain of the first buffer layer, it is possible to suppress the occurrence of strain-induced step bunching in the group III nitride semiconductor layer.
  • the semiconductor wafer described above can smooth the surface of the group III nitride semiconductor layer.
  • multilayer buffer layer does not mean a so-called “low temperature buffer layer” for reducing the lattice constant difference between the substrate and the semiconductor element layer, but a group III nitride semiconductor layer.
  • a group III nitride semiconductor layer In order to relieve the thermal strain generated in the group III nitride semiconductor layer when the group III nitride semiconductor layer changes from a high temperature to a low temperature after film formation.
  • strain-induced step bunching is a mechanism of step bunching occurrence discovered and proposed by Tersoff et al. And disclosed in “Physical Review Letters Volume 75 2730 (1995)”.
  • the mechanism is that when a strain is generated on a semiconductor surface formed by periodic step terraces, an attractive force between steps is proportional to the square of the strain and inversely proportional to the distance between steps.
  • the attractive force between steps forms a bundle of steps (step bunching) one after another, and a step is formed on the surface of the semiconductor wafer, so that the surface smoothness of the semiconductor wafer is lowered. Therefore, generation of step bunching can be suppressed by reducing the distortion of the semiconductor surface.
  • the strain-induced step bunching becomes more prominent in a wafer (so-called wafer having an off angle) whose main axis is slightly inclined with respect to the normal of the growth surface.
  • the c-axis is generally the main axis. Therefore, in the case of a group III nitride semiconductor, it can be said that the state where the c-axis is inclined with respect to the normal of the growth surface has an off-angle.
  • the growth surface has a periodic structure in which step terraces are regularly repeated, and the flatness of the wafer surface can be improved.
  • the strain-induced step bunching in the nitride semiconductor layer is more remarkable in the group III nitride semiconductor whose main component is gallium as the group III element.
  • Step bunching occurs in the process where group III atomic species on the terrace are diffused into the step edge. Therefore, step bunching is likely to occur in an environment that satisfies the condition of “average distance between steps ⁇ (1/2) ⁇ surface diffusion length of group III atomic species”.
  • gallium is known to have a longer surface diffusion length than aluminum and indium. Therefore, strain-induced step bunching is likely to occur in a group III nitride semiconductor mainly containing gallium, particularly gallium nitride.
  • gallium nitride includes gallium nitride containing less than 1% impurities (B, Al, In, C, Si, Ge, Mg, S, Fe, As, Sb, etc.). Is also included.
  • the multilayer buffer layer has a smaller lattice constant than the group III nitride semiconductor layer
  • the lattice constant of the multilayer buffer layer Mean lattice constant
  • the lattice constant of a portion of the multilayer buffer layer may be larger than the lattice constant of a portion of the group III nitride semiconductor layer.
  • the terms “average lattice strain” and “interface lattice strain” are used.
  • the ideal lattice constant (theoretical lattice constant) in the plane direction of the first layer (direction perpendicular to the crystal growth direction) is a 1
  • the actual lattice constant is a 1 ′
  • the ideal lattice in the plane direction of the second layer is a 2
  • the actual lattice constant is a 2 ′.
  • the rate R 1 is expressed by the following equation.
  • a group III nitride semiconductor layer is provided over a substrate via a multilayer buffer layer, and a semiconductor element is formed on the surface side of the group III nitride semiconductor layer.
  • the multilayer buffer layer includes at least a first buffer layer and a second buffer layer. The first buffer layer is in contact with the group III nitride semiconductor layer.
  • the second buffer layer is in contact with the first buffer layer.
  • the first buffer layer and the second buffer layer have different compositions.
  • the multilayer buffer layer has an average lattice constant smaller than that of the group III nitride semiconductor layer.
  • the interface lattice strain of the group III nitride semiconductor layer at the interface between the group III nitride semiconductor layer and the first buffer layer is smaller than the interface lattice strain of the first buffer layer at the interface between the first buffer layer and the second buffer layer.
  • the semiconductor wafer includes a substrate, a multilayer buffer layer provided on the substrate, and a group III nitride semiconductor layer provided on the multilayer buffer layer.
  • the substrate has a smaller coefficient of thermal expansion than the group III nitride semiconductor layer.
  • the temperature integral value of the linear expansion coefficient of 300 to 1300K is smaller than the temperature integral value of the linear expansion coefficient of 300 to 1300K in the a-axis direction of the material constituting the group III nitride semiconductor layer.
  • the material of the substrate is silicon (Si) or silicon carbide (SiC).
  • the thickness of the substrate is 0.1 to 2 mm.
  • an interface layer and an aluminum nitride (AlN) layer are provided between the substrate and the multilayer buffer layer.
  • Al 2 O 3 , AlON, or the like can be used as the material for the interface layer.
  • the interface layer can be omitted.
  • the thickness of the aluminum nitride layer is 10 to 500 nm.
  • the aluminum nitride layer preferably has a thickness of 50 to 500 nm.
  • the thickness of the aluminum nitride layer is preferably 10 to 100 nm.
  • Aluminum nitride has the smallest lattice constant among group III nitride semiconductors. Therefore, by providing the aluminum nitride layer, a necessary amount of compressive strain can be applied to the multilayer buffer layer described later. In addition, as described above, the interface layer and the aluminum nitride layer can be omitted, and the multilayer buffer layer can be formed directly on the surface of the substrate.
  • the multilayer buffer layer includes at least a first buffer layer in contact with the group III nitride semiconductor layer and a second buffer layer in contact with the first buffer layer.
  • the multilayer buffer layer may include a third buffer layer in contact with the second buffer layer, a fourth buffer layer in contact with the third buffer layer, and the like. That is, the multilayer buffer layer has a multilayer structure including two or more layers.
  • the first buffer layer is a layer located on the most surface side (group III nitride semiconductor layer side) among the layers constituting the multilayer buffer layer.
  • the first buffer layer and the second buffer layer have different compositions. Also, the first buffer layer is not coherent with respect to the second buffer layer.
  • the strain relaxation rate (R 1 ) of the first buffer layer with respect to the second buffer layer is 0.8 or more. By setting the strain relaxation rate (R 1 ) to 0.8 or more, sufficient strain relaxation occurs in the first buffer layer, and the strain of the group III nitride semiconductor layer can be effectively reduced.
  • the first buffer layer By setting the thickness of the first buffer layer to 0.05 ⁇ m or more, the first buffer layer can be prevented from growing coherently with respect to the second buffer layer. More preferably, the thickness of the first buffer layer is 0.2 ⁇ m or more. By setting the thickness of the first buffer layer to 0.2 ⁇ m or more, the first buffer layer is more reliably connected to the second buffer regardless of the size of the interfacial lattice strain of the first buffer layer and the growth conditions of the first buffer layer. It is possible to prevent coherent growth with respect to the layer.
  • the average lattice constant of the multilayer buffer layer is smaller than the average lattice constant of the group III nitride semiconductor layer. Further, when the entire multilayer buffer layer and aluminum nitride are compared, the average lattice constant of the multilayer buffer layer is larger than the lattice constant of aluminum nitride.
  • the multilayer buffer layer preferably has a compressive strain as a whole. Due to the compressive strain of the multilayer buffer layer, it occurs in the group III nitride semiconductor layer when the temperature of the group III nitride semiconductor layer changes from the growth temperature (high temperature) to room temperature (low temperature) after film formation.
  • Tensile strain can be offset. It is preferable that no tensile strain remains in the first buffer layer. In other words, in the first buffer layer, no strain remains or compressive strain remains. More preferably, the first buffer layer has a compressive strain remaining. Note that “the compressive strain remains in the first buffer layer” corresponds to the average lattice strain of the first buffer layer being a negative value.
  • the layer having the largest absolute value of the average lattice strain among the layers of the multilayer structure constituting the multilayer buffer layer is a layer other than the first buffer layer. In other words, the absolute value of the average lattice strain of the first buffer layer is not the maximum among the layers of the multilayer structure constituting the multilayer buffer layer.
  • a nitride semiconductor represented by Al x Ga 1-x N (0 ⁇ x ⁇ 1) can be used as the material of the multilayer buffer layer.
  • the first buffer layer is preferably a nitride semiconductor represented by Al x Ga 1-x N (0 ⁇ x ⁇ 0.5). More preferably, the first buffer layer is a nitride semiconductor represented by Al x Ga 1-x N (0 ⁇ x ⁇ 0.2). Since the average lattice constant of the first buffer layer is closer to GaN (nitride semiconductor) than to AlN, the difference in average lattice constant between the group III nitride semiconductor layer and the first buffer layer is reduced, and the group III nitride semiconductor layer is reduced. It is possible to reduce the interfacial lattice distortion.
  • each layer of the multilayer buffer layer may have a different “x” value.
  • the value of “x” becomes smaller toward the surface (the group III nitride semiconductor layer side). That is, the multilayer buffer layer preferably has a multilayer structure in which the Al composition becomes smaller toward the surface.
  • the multilayer buffer layer may have a structure in which different materials are repeatedly stacked.
  • the multilayer buffer layer can have a structure in which a laminated structure of AlN and GaN is repeatedly provided.
  • the multilayer buffer layer may have a structure in which a laminated structure of AlN and AlGaN is repeatedly provided.
  • the thickness of the multilayer buffer layer can be 0.5 to 10 ⁇ m.
  • the group III nitride semiconductor layer may be a single layer or multiple layers.
  • the single-layer group III nitride semiconductor layer means that the composition from the front surface to the back surface of the group III nitride semiconductor layer is the same.
  • the multiple group III nitride semiconductor layer means that the group III nitride semiconductor layer includes a plurality of layers having different compositions of group III elements.
  • the group III nitride semiconductor layer is preferably a group III nitride semiconductor mainly composed of gallium (Ga).
  • group III nitride semiconductor mainly composed of gallium typically means gallium nitride (GaN), and B, Al, In on the order of atomic percent of less than 1% with respect to GaN as impurities.
  • gallium nitride containing elements such as C, Si, Ge, Mg, S, Fe, As, and Sb is also included.
  • the group III nitride semiconductor layer preferably contains carbon. When the group III nitride semiconductor layer contains carbon, leakage current can be prevented from flowing when the semiconductor device is in the off state.
  • the group III nitride semiconductor layer can be used as a functional layer (a layer constituting a semiconductor element). A single group III nitride semiconductor layer can also be used as a functional layer.
  • a group III nitride semiconductor layer provided on the surface side of the layer in contact with the first buffer layer can also be used as a functional layer.
  • the interface lattice strain of the nitride semiconductor element (interface lattice strain of the nitride semiconductor element) at the interface between the group III nitride semiconductor layer and the first buffer layer is less than that of the first buffer layer. It is smaller than the interface lattice strain of the first buffer layer at the interface of the second buffer layer (interface lattice strain of the first buffer layer). Since the interfacial lattice strain of the nitride semiconductor element is smaller than the interfacial lattice strain of the first buffer layer, it is possible to suppress the occurrence of strain-induced step bunching in the group III nitride semiconductor layer.
  • the semiconductor wafer 1 includes a silicon substrate 2, an interface layer 4 formed on the silicon substrate 2, an AlN layer 6 formed on the interface layer 4, a multilayer buffer layer 8 formed on the AlN layer 6, A group III nitride semiconductor layer 10 formed on the multilayer buffer layer 8 and a nitride semiconductor functional layer 12 formed on the group III nitride semiconductor layer 10 are provided.
  • the thickness T2 of the silicon substrate 2 is 675 ⁇ m.
  • the material of the interface layer 4 is Al 2 O 3 .
  • the thickness T4 of the interface layer 4 is adjusted to be less than 3 nm.
  • the thickness T6 of the AlN layer 6 is adjusted to 0.3 ⁇ m.
  • the material of the multilayer buffer layer 8 is Al x Ga 1-x N.
  • the thickness T8 of the multilayer buffer layer 8 is adjusted to 2.5 ⁇ m.
  • the multilayer buffer layer 8 has a four-layer structure including a first buffer layer 8a, a second buffer layer 8b, a third buffer layer 8c, and a fourth buffer layer 8d.
  • the first buffer layer 8 a is in contact with the group III nitride semiconductor layer 10
  • the fourth buffer layer 8 d is in contact with the AlN layer 6. Note that the value of “x” of Al x Ga 1-x N increases from the first buffer layer 8a toward the fourth buffer layer 8d.
  • the thickness of the first buffer layer 8a is adjusted to 0.8 ⁇ m
  • the thickness of the second buffer layer 8b is adjusted to 0.2 ⁇ m
  • the thickness of the third buffer layer 8c is adjusted to 0.5 ⁇ m.
  • the thickness of the fourth buffer layer 8d is adjusted to 1.0 ⁇ m.
  • the interface layer 4 is formed by using an atomic layer deposition method (ALD method).
  • ALD method atomic layer deposition method
  • trimethylaluminum is used as the Al raw material
  • ozone is used as the O raw material.
  • the AlN layer 6 and the multilayer buffer layer 8 are formed using a metal organic chemical vapor deposition method (MOCVD method).
  • MOCVD method metal organic chemical vapor deposition method
  • the growth temperature is about 1000 ° C.
  • the material of the group III nitride semiconductor layer 10 is gallium nitride (GaN).
  • the thickness of group III nitride semiconductor layer 10 is adjusted to 0.6 ⁇ m, and the thickness of nitride semiconductor functional layer 12 is adjusted to 0.4 ⁇ m.
  • the group III nitride semiconductor layer 10 contains 2 ⁇ 10 18 cm ⁇ 3 of carbon.
  • the carbon introduced into the group III nitride semiconductor layer 10 prevents leakage current from flowing between the semiconductor element formed in the nitride semiconductor functional layer 12 and the silicon substrate 2.
  • the nitride semiconductor functional layer 12 is i-type that does not contain impurities (it may contain unavoidable carbon).
  • a semiconductor element can be formed using the nitride semiconductor functional layer 12.
  • FIG. 2 shows the characteristics of the AlN layer 6, the multilayer buffer layer 8, and the group III nitride semiconductor layer 10 for the semiconductor wafer 1.
  • the Al composition (x) corresponds to the value of “x” when each layer is represented by Al x Ga 1-x N.
  • the group III nitride semiconductor layer 10 is denoted by GaN
  • the first buffer layer 8a is denoted by TOP
  • the “i” th buffer layer from the first buffer layer 8a is denoted by i.
  • the average lattice constant a ′ j in the a-axis direction and the average lattice constant c ′ j in the c-axis direction were calculated from the following formulas (1) and (2) using the face spacings d 114j and d 004j .
  • Formula (2): c ′ j 4 ⁇ d 004j
  • the Al composition (x) is obtained by using the interplanar spacings d 114j and d 004j obtained by the X-ray reciprocal mapping and the results obtained by the above formulas (1) and (2), using “x” in the following formula (3). ”Was calculated.
  • a AlN is the ideal lattice constant of the a-axis of AlN
  • c AlN is the ideal lattice constant of the c-axis of AlN.
  • 0.38 was used as the Poisson's ratio.
  • the Poisson's ratio is disclosed in “T.
  • the ideal lattice constant a j of each layer (TOP, i) of the buffer layer was calculated from the following formula (4) using the value of “x” of each layer as a variable when each layer was represented by Al x Ga 1-x N.
  • the average lattice strain and the interface lattice strain are positive strains when they are positive values, and compressive strains when they are negative values. Therefore, the magnitude relation of the lattice distortion does not compare actual numerical values but compares absolute values.
  • j GaN
  • j + 1 corresponds to TOP.
  • the semiconductor wafer 1 the interface lattice distortion of the group III nitride semiconductor layer 10 ( ⁇ If_GaN) is the interface lattice distortion ( ⁇ If_TOP) of the first buffer layer 8a smaller.
  • the average lattice strain epsilon '1 of the second buffer layer 8b is the maximum among the average lattice strain of the buffer layer 8a ⁇ 8d. That is, the average lattice strain ( ⁇ TOP ) of the first buffer layer 8 a is not the maximum among the average lattice strains ( ⁇ 1 to 3 ) of the layers constituting the multilayer buffer layer 8.
  • the semiconductor wafer 11 will be described with reference to FIG.
  • the semiconductor wafer 11 is a modification of the semiconductor wafer 1.
  • the semiconductor wafer 11 has a larger number of layers constituting the multilayer buffer layer 18 than the semiconductor wafer 1.
  • the multilayer buffer layer 18 has a five-layer structure including a first buffer layer 18a, a second buffer layer 18b, a third buffer layer 18c, a fourth buffer layer 18d, and a fifth buffer layer 18e.
  • the first buffer layer 18a is a composition gradient layer having an Al composition (x) of 0.08 to 0.03.
  • the average Al composition (x) of the first buffer layer 18a is 0.033.
  • the multilayer buffer layer 18 has a thickness T18 of 2.43 ⁇ m.
  • the thickness T18a of the first buffer layer 18a is adjusted to 0.63 ⁇ m.
  • the thicknesses T18b to T18e of the second to fifth buffer layers 18b to 18e are adjusted to 0.1, 0.2, 0.5, and 1.0 ⁇ m, respectively.
  • FIG. 4 shows the characteristics of the AlN layer 6, the multilayer buffer layer 18, and the group III nitride semiconductor layer 10 for the semiconductor wafer 11.
  • the interface lattice distortion of the group III nitride semiconductor layer 10 ⁇ If_GaN
  • interface lattice distortion of the first buffer layer 18a ⁇ If_TOP
  • the average lattice strain epsilon '1 of the second buffer layer 18b is the largest among the average lattice strain of the buffer layer 18a ⁇ 18e (absolute value).
  • the average lattice strain ( ⁇ TOP ) of the first buffer layer 18 a is not the maximum among the average lattice strains ( ⁇ 1 to 4 ) of the layers constituting the multilayer buffer layer 18.
  • the group III nitride semiconductor layer 10 has a thickness adjusted to 0.75 ⁇ m and contains 4 ⁇ 10 19 cm ⁇ 3 of carbon.
  • the nitride semiconductor functional layer 12 is adjusted to a thickness of 0.48 ⁇ m and is i-type.
  • an AlGaN barrier layer 20 nm and a GaN cap layer 5 nm are formed on the surface of the nitride semiconductor functional layer 12.
  • a field effect transistor can be manufactured by forming a gate electrode, a source electrode, and a drain electrode on the surfaces of the semiconductor wafers 1 and 11.
  • the gate electrode is opposed to the nitride semiconductor functional layer 12 through the insulating film.
  • the source electrode and the drain electrode are in ohmic contact with the nitride semiconductor functional layer 12.
  • the nitride semiconductor functional layer 12 functions as a channel layer of the field effect transistor.
  • a Schottky electrode and an ohmic electrode can be formed on the surfaces of the semiconductor wafers 1 and 11 to manufacture a Schottky diode.
  • the nitride semiconductor functional layer 12 functions as a current-carrying layer for the Schottky diode.
  • a semiconductor wafer according to a third embodiment will be described.
  • the structure of the semiconductor wafer of this embodiment is substantially the same as that of the semiconductor wafer 1 of the first embodiment.
  • the semiconductor wafer of this example has different characteristics of each layer.
  • differences from the semiconductor wafer 1 will be described with reference to FIG.
  • the average lattice strain ⁇ ′ TOP of the first buffer layer 8a is the largest among the average lattice strains (absolute values) of the buffer layers 8a to 8d. Different from wafer 1. That is, the portion of the buffer layer in contact with the group III nitride semiconductor layer 10 has the highest compressive strain. This difference can be caused by adjusting the manufacturing conditions (buffer layer growth conditions). Also in the semiconductor wafer of the present embodiment, the interface lattice distortion of the group III nitride semiconductor layer 10 ( ⁇ If_GaN) is in that the interface lattice distortion ( ⁇ If_TOP) is smaller than the first buffer layer 8a, the first embodiment The semiconductor wafer 1 has common characteristics.
  • Example 2 The surface roughness of the semiconductor wafers of Examples 1 to 3 was measured. The results are shown in FIG. The surface roughness is a root mean square roughness (RMS) of an atomic force microscope in an area of 50 ⁇ m square. In addition, the surface roughness of the semiconductor wafers of Comparative Examples 1 and 2 was also measured. First, the characteristics of the semiconductor wafers of Comparative Examples 1 and 2 will be described.
  • RMS root mean square roughness
  • the characteristics of the semiconductor wafer of Comparative Example 1 are shown in FIG.
  • the semiconductor wafer of Comparative Example 1 includes four buffer layers having different Al compositions (x).
  • the thickness of the first buffer layer is 0.5 ⁇ m.
  • the group III nitride semiconductor layer contains 4 ⁇ 10 18 cm ⁇ 3 of carbon and has a thickness of 0.4 ⁇ m.
  • an i-type nitride semiconductor functional layer is laminated on the surface of the group III nitride semiconductor layer.
  • the nitride semiconductor functional layer has a thickness of 0.6 ⁇ m.
  • the average lattice strain ⁇ ′ TOP of the first buffer layer is the largest among the average lattice strains (absolute values) of the first to fourth buffer layers. Further, the interfacial lattice strain ( ⁇ If_GaN ) of the group III nitride semiconductor layer is larger than the interfacial lattice strain ( ⁇ If_TOP ) of the first buffer layer.
  • the semiconductor wafer of Comparative Example 1 includes four buffer layers having different Al compositions (x).
  • the thickness of the first buffer layer is 0.44 ⁇ m.
  • the group III nitride semiconductor layer contains 1.5 ⁇ 10 18 cm ⁇ 3 of carbon and has a thickness of 0.66 ⁇ m.
  • an i-type nitride semiconductor functional layer is laminated on the surface of the group III nitride semiconductor layer.
  • the nitride semiconductor functional layer has a thickness of 0.33 ⁇ m.
  • an AlGaN barrier layer of 20 nm and a GaN cap layer of 5 nm are formed on the surface of the i-type nitride semiconductor functional layer.
  • the average lattice strain ⁇ ′ TOP of the first buffer layer is the largest among the average lattice strains (absolute values) of the first to fourth buffer layers. Further, the interfacial lattice strain ( ⁇ If_GaN ) of the group III nitride semiconductor layer is larger than the interfacial lattice strain ( ⁇ If_TOP ) of the first buffer layer.
  • the inclination angle of the group III nitride semiconductor layer with respect to the c-axis growth surface was measured by X-ray diffraction.
  • the c-axes of the group III nitride semiconductor layers of Examples 1 to 3 were inclined 0.22 degrees, 0.31 degrees, and 0.30 degrees in the m-axis direction with respect to the normal to the growth surface, respectively.
  • the c-axes of the group III nitride semiconductor layers of Comparative Examples 1 and 2 were inclined by 0.26 degrees and 0.33 degrees in the m-axis direction with respect to the normal to the growth surface, respectively.
  • the interface lattice distortion of the group III nitride semiconductor layer (epsilon If_GaN) is marked with ⁇ in experimental examples that satisfy the interface lattice distortion of the first buffer layer a ( ⁇ If_TOP) condition that is less than (condition 1) In the experiment example which is not satisfied, x is marked.
  • condition 1 In the experiment example which is not satisfied, x is marked.
  • Condition 2 that the average lattice strain (absolute value,
  • is marked and not satisfied X is described in the experimental example.
  • “ ⁇ ” is marked for an experimental example having an RMS value of 5.0 or less
  • “ ⁇ ” is marked for an experimental example of 10.0 or less
  • x” is marked for an experimental example of 10.0 or more.
  • the average lattice strain (absolute value) of the group III nitride semiconductor layer is 3.97 ⁇ 10 ⁇ 4 to 1.03 ⁇ 10 ⁇ 3
  • the group III nitride semiconductor of the comparative example It is less than half of the average lattice strain (2.44 ⁇ 10 ⁇ 3 , 2.04 ⁇ 10 ⁇ 3 ) of the layer.
  • the strain relaxation rates (R TOP ) of the first buffer layer with respect to the second buffer layer are 0.974, 0.863, and 0.837, respectively (FIGS. 2 and 4). And 5). That is, the semiconductor wafers of Examples 1 to 3 have a strain relaxation rate (R TOP ) of 0.8 or more. In contrast, the semiconductor wafers of Comparative Examples 1 and 2 have strain relaxation rates (R TOP ) of 0.464 and 0.431, respectively, which are smaller than those of the semiconductor wafers of Examples 1 to 3 (see FIG. 6 and 7).
  • the average lattice strain (3.97 ⁇ 10 ⁇ 4 , 4.96 ⁇ 10 ⁇ 4 ) of the group III nitride semiconductor layers of Examples 1 and 2 satisfies both Condition 1 and Condition 2, It is one quarter or less of the average lattice strain of the Group III nitride semiconductor layer of the comparative example.
  • Examples 1 and 3 have the same structure in the upper layer than the group III nitride semiconductor layer.
  • Example 1 and 3 differ in whether condition 2 is satisfied.
  • the 004 diffraction half widths related to the helical component dislocation were 390 sec (Example 1) and 470 sec (Example 3), respectively.
  • the 114 diffraction half widths including information on the edge component dislocations were 540 sec (Example 1) and 740 sec (Example 3), respectively.
  • both conditions 1 and 2 are satisfied, the X-ray half width is narrow and the crystallinity is improved.
  • the edge dislocation density was suppressed to about 1 ⁇ 2 to 3 of Example 3 in Example 1. This is because, when both conditions 1 and 2 are satisfied, a first buffer layer having a large interface lattice strain but a small average lattice strain is formed, and a large strain relaxation occurs in the first buffer layer. This is probably because the edge dislocations having the Burgers vector of opposite polarity disappeared. It was also shown that there is an effect of reducing the dislocation density by satisfying both conditions 1 and 2. When dislocation pair annihilation having a reverse polarity Burgers vector occurs, the first buffer layer is compressive strain at the growth temperature, and the strain remaining at room temperature is either compression or no strain. That is, at least a tensile strain does not remain in the first buffer layer at room temperature.
  • the warpage of the semiconductor wafer changes according to the product of the “strain” and the “film thickness” of the group III nitride semiconductor layer. That is, when the strain of the group III nitride semiconductor layer is large, the amount of warpage of the semiconductor wafer greatly changes due to a slight change in film thickness. Therefore, when the group III nitride semiconductor layer grows with inherent strain, it becomes difficult to control the amount of warpage of the semiconductor wafer. According to the technology disclosed in this specification, the group III nitride semiconductor layer is prevented from growing with inherent strain, so even if an error occurs in the film thickness, variation in the amount of warpage between batches is suppressed. be able to.
  • the semiconductor wafer 1 can also improve the robustness of warpage control.
  • the Al composition (x) of each layer of the multilayer buffer layer was calculated using Equations 2 and 3.
  • the cathodoluminescence measurement (CL measurement) is performed on the cross section of the buffer layer, and the band edge emission peak EGap is measured. It can also be obtained optically from (eV). That is, the Al composition (x) can be obtained by measuring the band edge emission peak EGap (eV) and calculating “x” in the following formula (8).
  • the bowing parameters are disclosed in (T. Onuma et.al., J. Appl. Phys.
  • EGap (X) 3.4 ⁇ (1 ⁇ x) + 6.2 ⁇ x ⁇ b ⁇ xx ⁇ (1 ⁇ x)
  • the average composition x when a multilayer periodic structure such as AlN / GaN is used for the multilayer buffer layer can be calculated by obtaining the AlN / GaN film thickness ratio by a cross-sectional TEM (Transmission Electron Microscope) or the like.
  • AlN / AlGaN the case of a multilayer periodic structure comprising Al x Ga 1-x N / Al y Ga 1-y N, and calculates the respective layers of the Al composition (x) by CL measurement, the film thickness measurement by cross-sectional TEM By combining, it can be converted into an average Al composition (x).
  • the multilayer buffer layer may be present in at least two layers (a first buffer layer in contact with the group III nitride semiconductor layer and a second buffer layer in contact with the first buffer layer). Further, a structure having six or more multilayer buffer layers may be taken.
  • a multilayer periodic structure such as AlN / GaN
  • the layer period / film thickness ratio is different in the multilayer buffer layer
  • the i-type semiconductor functional layer is provided on the surface of the group III nitride semiconductor layer.
  • a layer containing an n-type or p-type impurity can also be provided.
  • a heterojunction is formed, a structure including a heterojunction of a mixed crystal with InN can be taken.

Abstract

A semiconductor wafer is provided with a substrate and a group III nitride semiconductor layer provided on the substrate with a multilayer buffer layer interposed therebetween. The multilayer buffer layer includes at least a first buffer layer and a second buffer layer. The first buffer layer is in contact with the group III nitride semiconductor layer. The second buffer layer is in contact with the first buffer layer, and has a different composition from the first buffer layer. The average lattice constant of the multilayer buffer layer is lower than that of the group III nitride semiconductor layer, and the interface lattice distortion of the group III nitride semiconductor layer at the interface between the group III nitride semiconductor layer and the first buffer layer is lower than the interface lattice distortion of the first buffer layer at the interface between the first buffer layer and the second buffer layer.

Description

半導体ウエハ及び半導体装置Semiconductor wafer and semiconductor device 関連出願の相互参照Cross-reference of related applications
 本出願は、2015年4月16日に出願された日本特許出願番号2015-84187号に基づくもので、ここにその記載内容を援用する。 This application is based on Japanese Patent Application No. 2015-84187 filed on April 16, 2015, the contents of which are incorporated herein by reference.
 本開示は、半導体ウエハ及び半導体装置に関するものである。 The present disclosure relates to a semiconductor wafer and a semiconductor device.
 基板上にIII族窒化物半導体層を気相成長させて半導体ウエハを製造する技術の研究が行われている。特許文献1には、シリコン基板上に多層バッファ層を成長させ、多層バッファ層上にIII族窒化物半導体層(機能層)を成長する技術が開示されている。特許文献1は、組成が異なる第1単位層と第2単位層を繰り返し積層した組成変調層と、組成変調層上に成長させた終端層と、終端層上に成長させた中間層(歪強化層)とを単位積層構造とし、複数の単位積層構造を備える多層バッファ層を開示している。III族窒化物半導体層を成長させる基板としてIII族窒化物半導体より熱膨張係数が小さい材料を用いると、III族窒化物半導体が高温(気相成長中)から低温(典型的に室温)に冷却されるときに、内部に引張歪みが生じる。多層バッファ層は、圧縮歪みを有している。特許文献1は、III族窒化物半導体層と接する部分に中間層(歪強化層)を設けることにより、多層バッファ層の圧縮歪みを強め、III族窒化物半導体層の引張歪みを相殺している。 Research is being conducted on techniques for producing semiconductor wafers by vapor-phase growth of group III nitride semiconductor layers on a substrate. Patent Document 1 discloses a technique for growing a multilayer buffer layer on a silicon substrate and growing a group III nitride semiconductor layer (functional layer) on the multilayer buffer layer. Patent Document 1 discloses a composition modulation layer in which a first unit layer and a second unit layer having different compositions are repeatedly laminated, a termination layer grown on the composition modulation layer, and an intermediate layer (strain strengthening) grown on the termination layer. A multilayer buffer layer having a unit laminated structure and having a plurality of unit laminated structures. When a material with a smaller coefficient of thermal expansion than the group III nitride semiconductor is used as the substrate for growing the group III nitride semiconductor layer, the group III nitride semiconductor is cooled from a high temperature (during vapor phase growth) to a low temperature (typically room temperature). When it is done, tensile strain occurs inside. The multilayer buffer layer has a compressive strain. In Patent Document 1, an intermediate layer (strain strengthening layer) is provided at a portion in contact with the group III nitride semiconductor layer, thereby strengthening the compressive strain of the multilayer buffer layer and canceling the tensile strain of the group III nitride semiconductor layer. .
 しかしながら、III族窒化物半導体層と接する部分において多層バッファ層の圧縮歪みが強いと、III族窒化物半導体層は、圧縮歪みを内在したまま成長する。その結果、III族窒化物半導体層に歪み誘因ステップバンチングが発生しやすくなり、III族窒化物半導体層の表面を平滑にすることができない。 However, when the compressive strain of the multilayer buffer layer is strong at the portion in contact with the group III nitride semiconductor layer, the group III nitride semiconductor layer grows while maintaining the compressive strain. As a result, strain-induced step bunching is likely to occur in the group III nitride semiconductor layer, and the surface of the group III nitride semiconductor layer cannot be smoothed.
特表2011-155496号公報Special table 2011-155498 gazette
 本開示は、III族窒化物半導体層の表面が平滑な半導体ウエハ及び半導体装置を提供することを目的とする。 An object of the present disclosure is to provide a semiconductor wafer and a semiconductor device in which the surface of the group III nitride semiconductor layer is smooth.
 本開示の第一の態様において、半導体ウエハは、基板と、基板上に多層バッファ層を介して設けられたIII族窒化物半導体層とを備える。前記多層バッファ層は、少なくとも第1バッファ層と第2バッファ層を含んでいる。前記第1バッファ層は、前記III族窒化物半導体層に接している。前記第2バッファ層は、前記第1バッファ層に接しており、前記第1バッファ層とは組成が異なる。前記多層バッファ層の平均格子定数が、前記III族窒化物半導体層より小さい。前記III族窒化物半導体層と前記第1バッファ層との界面における前記III族窒化物半導体層の界面格子歪みが、前記第1バッファ層と前記第2バッファ層の界面における前記第1バッファ層の界面格子歪みより小さい。 In the first aspect of the present disclosure, a semiconductor wafer includes a substrate and a group III nitride semiconductor layer provided on the substrate via a multilayer buffer layer. The multilayer buffer layer includes at least a first buffer layer and a second buffer layer. The first buffer layer is in contact with the group III nitride semiconductor layer. The second buffer layer is in contact with the first buffer layer and has a composition different from that of the first buffer layer. The multilayer buffer layer has an average lattice constant smaller than that of the group III nitride semiconductor layer. Interfacial lattice distortion of the group III nitride semiconductor layer at the interface between the group III nitride semiconductor layer and the first buffer layer is caused by the first buffer layer at the interface between the first buffer layer and the second buffer layer. Less than interfacial lattice distortion.
 上記半導体ウエハでは、III族窒化物半導体層と第1バッファ層との界面におけるIII族窒化物半導体層の界面格子歪み(以下、III族窒化物半導体層の界面格子歪みという)が、第1バッファ層と第2バッファ層の界面における第1バッファ層の界面格子歪み(以下、第1バッファ層の界面格子歪みという)より小さい。そのため、III族窒化物半導体層は、第1バッファ層の圧縮歪みを内在したまま成長することが抑制される。III族窒化物半導体層の界面格子歪みを第1バッファ層の界面格子歪みより小さくすることにより、III族窒化物半導体層に歪み誘因ステップバンチングが発生することを抑制することができる。上記の半導体ウエハは、III族窒化物半導体層の表面を平滑にすることができる。 In the semiconductor wafer, the interfacial lattice strain of the group III nitride semiconductor layer at the interface between the group III nitride semiconductor layer and the first buffer layer (hereinafter referred to as the interfacial lattice strain of the group III nitride semiconductor layer) is the first buffer. It is smaller than the interface lattice strain of the first buffer layer at the interface between the layer and the second buffer layer (hereinafter referred to as the interface lattice strain of the first buffer layer). Therefore, the group III nitride semiconductor layer is suppressed from growing while having the compressive strain of the first buffer layer. By making the interface lattice strain of the group III nitride semiconductor layer smaller than the interface lattice strain of the first buffer layer, it is possible to suppress the occurrence of strain-induced step bunching in the group III nitride semiconductor layer. The semiconductor wafer described above can smooth the surface of the group III nitride semiconductor layer.
 本開示の第二の態様において、半導体装置は、基板と、基板上に多層バッファ層を介して設けられたIII族窒化物半導体層とを備える。そのIII族窒化物半導体層の表面側に半導体素子が形成されている。前記多層バッファ層は、少なくとも第1バッファ層と第2バッファ層を含んでいる。前記第1バッファ層は、前記III族窒化物半導体層に接している。前記第2バッファ層は、前記第1バッファ層に接しており、前記第1バッファ層とは組成が異なる。前記多層バッファ層の平均格子定数が、前記III族窒化物半導体層より小さい。前記III族窒化物半導体層と前記第1バッファ層との界面における前記III族窒化物半導体層の界面格子歪みが、前記第1バッファ層と前記第2バッファ層の界面における前記第1バッファ層の界面格子歪みより小さい。 In a second aspect of the present disclosure, a semiconductor device includes a substrate and a group III nitride semiconductor layer provided on the substrate via a multilayer buffer layer. A semiconductor element is formed on the surface side of the group III nitride semiconductor layer. The multilayer buffer layer includes at least a first buffer layer and a second buffer layer. The first buffer layer is in contact with the group III nitride semiconductor layer. The second buffer layer is in contact with the first buffer layer and has a composition different from that of the first buffer layer. The multilayer buffer layer has an average lattice constant smaller than that of the group III nitride semiconductor layer. Interfacial lattice distortion of the group III nitride semiconductor layer at the interface between the group III nitride semiconductor layer and the first buffer layer is caused by the first buffer layer at the interface between the first buffer layer and the second buffer layer. Less than interfacial lattice distortion.
 上記半導体装置では、III族窒化物半導体層と第1バッファ層との界面におけるIII族窒化物半導体層の界面格子歪み(以下、III族窒化物半導体層の界面格子歪みという)が、第1バッファ層と第2バッファ層の界面における第1バッファ層の界面格子歪み(以下、第1バッファ層の界面格子歪みという)より小さい。そのため、III族窒化物半導体層は、第1バッファ層の圧縮歪みを内在したまま成長することが抑制される。III族窒化物半導体層の界面格子歪みを第1バッファ層の界面格子歪みより小さくすることにより、III族窒化物半導体層に歪み誘因ステップバンチングが発生することを抑制することができる。上記の半導体ウエハは、III族窒化物半導体層の表面を平滑にすることができる。 In the semiconductor device, the interfacial lattice strain of the group III nitride semiconductor layer (hereinafter referred to as the interfacial lattice strain of the group III nitride semiconductor layer) at the interface between the group III nitride semiconductor layer and the first buffer layer is the first buffer. It is smaller than the interface lattice strain of the first buffer layer at the interface between the layer and the second buffer layer (hereinafter referred to as the interface lattice strain of the first buffer layer). Therefore, the group III nitride semiconductor layer is suppressed from growing while having the compressive strain of the first buffer layer. By making the interface lattice strain of the group III nitride semiconductor layer smaller than the interface lattice strain of the first buffer layer, it is possible to suppress the occurrence of strain-induced step bunching in the group III nitride semiconductor layer. The semiconductor wafer described above can smooth the surface of the group III nitride semiconductor layer.
 本開示についての上記目的およびその他の目的、特徴や利点は、添付の図面を参照しながら下記の詳細な記述により、より明確になる。その図面は、
図1は、第1実施例の半導体ウエハの断面図を模式的に示し、 図2は、第1実施例の半導体ウエハの特性を示し、 図3は、第2実施例の半導体ウエハの断面図を模式的に示し、 図4は、第2実施例の半導体ウエハの特性を示し、 図5は、第3実施例の半導体ウエハの特性を示し、 図6は、比較例1の半導体ウエハの特性を示し、 図7は、比較例2の半導体ウエハの特性を示し、 図8は、実施例及び比較例について、半導体ウエハの表面粗さの結果を示す。
The above and other objects, features, and advantages of the present disclosure will become more apparent from the following detailed description with reference to the accompanying drawings. The drawing
FIG. 1 schematically shows a cross-sectional view of the semiconductor wafer of the first embodiment, FIG. 2 shows the characteristics of the semiconductor wafer of the first embodiment. FIG. 3 schematically shows a cross-sectional view of the semiconductor wafer of the second embodiment, FIG. 4 shows the characteristics of the semiconductor wafer of the second embodiment. FIG. 5 shows the characteristics of the semiconductor wafer of the third embodiment. FIG. 6 shows the characteristics of the semiconductor wafer of Comparative Example 1. FIG. 7 shows the characteristics of the semiconductor wafer of Comparative Example 2, FIG. 8 shows the results of the surface roughness of the semiconductor wafer for the examples and comparative examples.
 本明細書で開示する半導体ウエハは、基板上に多層バッファ層を介してIII族窒化物半導体層が設けられている。多層バッファ層は、平均格子定数がIII族窒化物半導体層より小さい。多層バッファ層は、少なくとも第1バッファ層と第2バッファ層を含んでいる。第1バッファ層は、III族窒化物半導体層に接している。第2バッファ層は、第1バッファ層に接している。第1バッファ層と第2バッファ層は組成が異なる。本明細書で開示する半導体ウエハでは、III族窒化物半導体層と第1バッファ層との界面におけるIII族窒化物半導体層の界面格子歪みが、第1バッファ層と第2バッファ層の界面における第1バッファ層の界面格子歪みより小さい。 In the semiconductor wafer disclosed in this specification, a group III nitride semiconductor layer is provided on a substrate via a multilayer buffer layer. The multilayer buffer layer has an average lattice constant smaller than that of the group III nitride semiconductor layer. The multilayer buffer layer includes at least a first buffer layer and a second buffer layer. The first buffer layer is in contact with the group III nitride semiconductor layer. The second buffer layer is in contact with the first buffer layer. The first buffer layer and the second buffer layer have different compositions. In the semiconductor wafer disclosed in the present specification, the interfacial lattice strain of the group III nitride semiconductor layer at the interface between the group III nitride semiconductor layer and the first buffer layer is the first at the interface between the first buffer layer and the second buffer layer. It is smaller than the interfacial lattice distortion of one buffer layer.
 上記半導体ウエハでは、III族窒化物半導体層と第1バッファ層との界面におけるIII族窒化物半導体層の界面格子歪み(以下、III族窒化物半導体層の界面格子歪みという)が、第1バッファ層と第2バッファ層の界面における第1バッファ層の界面格子歪み(以下、第1バッファ層の界面格子歪みという)より小さい。そのため、III族窒化物半導体層は、第1バッファ層の圧縮歪みを内在したまま成長することが抑制される。III族窒化物半導体層の界面格子歪みを第1バッファ層の界面格子歪みより小さくすることにより、III族窒化物半導体層に歪み誘因ステップバンチングが発生することを抑制することができる。上記の半導体ウエハは、III族窒化物半導体層の表面を平滑にすることができる。 In the semiconductor wafer, the interfacial lattice strain of the group III nitride semiconductor layer at the interface between the group III nitride semiconductor layer and the first buffer layer (hereinafter referred to as the interfacial lattice strain of the group III nitride semiconductor layer) is the first buffer. It is smaller than the interface lattice strain of the first buffer layer at the interface between the layer and the second buffer layer (hereinafter referred to as the interface lattice strain of the first buffer layer). Therefore, the group III nitride semiconductor layer is suppressed from growing while having the compressive strain of the first buffer layer. By making the interface lattice strain of the group III nitride semiconductor layer smaller than the interface lattice strain of the first buffer layer, it is possible to suppress the occurrence of strain-induced step bunching in the group III nitride semiconductor layer. The semiconductor wafer described above can smooth the surface of the group III nitride semiconductor layer.
 なお、本明細書でいう「多層バッファ層」とは、基板と半導体素子層の間の格子定数差を緩和するための所謂「低温バッファ層」を意味するものではなく、III族窒化物半導体層に面方向の力を加え、III族窒化物半導体層が成膜後に高温から低温に変化するときにIII族窒化物半導体層に生じる熱歪みを緩和するためのものである。また、「歪み誘因ステップバンチング」とは、Tersoffらが発見し、提唱したステップバンチング発生のメカニズムであり、「Physical Review Letters Volume 75 2730(1995)」に開示されている。そのメカニズムは、周期的なステップ・テラスで形成される半導体表面に歪みが発生すると、歪みの2乗に比例し、ステップ間の距離に反比例したステップ間引力が働くというものである。ステップ間引力がステップの束(ステップバンチング)を次々と形成し、半導体ウエハの表面に段差が形成され、半導体ウエハの表面平滑性が低下する。そのため、半導体表面の歪みを小さくすることにより、ステップバンチングの発生を抑制することができる。 As used herein, the term “multilayer buffer layer” does not mean a so-called “low temperature buffer layer” for reducing the lattice constant difference between the substrate and the semiconductor element layer, but a group III nitride semiconductor layer. In order to relieve the thermal strain generated in the group III nitride semiconductor layer when the group III nitride semiconductor layer changes from a high temperature to a low temperature after film formation. “Strain-induced step bunching” is a mechanism of step bunching occurrence discovered and proposed by Tersoff et al. And disclosed in “Physical Review Letters Volume 75 2730 (1995)”. The mechanism is that when a strain is generated on a semiconductor surface formed by periodic step terraces, an attractive force between steps is proportional to the square of the strain and inversely proportional to the distance between steps. The attractive force between steps forms a bundle of steps (step bunching) one after another, and a step is formed on the surface of the semiconductor wafer, so that the surface smoothness of the semiconductor wafer is lowered. Therefore, generation of step bunching can be suppressed by reducing the distortion of the semiconductor surface.
 また、歪み誘因ステップバンチングは、成長面の垂線に対して主軸が微傾斜したウエハ(所謂オフ角を有するウエハ)において、より顕著となる。例えばIII族窒化物半導体の場合、一般的にc軸が主軸となる。そのため、III族窒化物半導体の場合、c軸が成長面の垂線に対して傾斜している状態がオフ角を有するといえる。典型的に、オフ角を設けることにより、成長表面をステップ・テラスが規則的に繰り返す周期構造となり、ウエハ表面の平坦性を向上させることができる。また、オフ角を設けることにより、急峻なヘテロ接合を実現したり、ウエハ上に形成する半導体素子の界面特性が向上するといった利点も得られる。しかしながら、歪み誘因ステップ間引力が働く状況下では、オフ角を有するウエハ表面のステップ間距離が小さい。よって、オフ角を有するウエハにおいては、ステップ間引力が無視できない働きをする。そのため、歪み誘因ステップ間引力が働く状況下では、半導体ウエハの表面にステップバンチングが発生しやすい。 Further, the strain-induced step bunching becomes more prominent in a wafer (so-called wafer having an off angle) whose main axis is slightly inclined with respect to the normal of the growth surface. For example, in the case of a group III nitride semiconductor, the c-axis is generally the main axis. Therefore, in the case of a group III nitride semiconductor, it can be said that the state where the c-axis is inclined with respect to the normal of the growth surface has an off-angle. Typically, by providing an off-angle, the growth surface has a periodic structure in which step terraces are regularly repeated, and the flatness of the wafer surface can be improved. In addition, by providing an off-angle, it is possible to obtain advantages such as realizing a steep heterojunction and improving the interface characteristics of a semiconductor element formed on a wafer. However, the distance between steps on the wafer surface having an off angle is small under a situation where a strain-induced step attractive force is applied. Therefore, in the wafer having an off-angle, the inter-step attractive force cannot be ignored. For this reason, step bunching is likely to occur on the surface of the semiconductor wafer under a situation in which a strain-induced attraction between steps works.
 また、窒化物半導体層における歪み誘因ステップバンチングは、III族元素としてガリウムを主成分とするIII族窒化物半導体でより顕著である。ステップバンチングは、テラス上のIII族原子種が表面拡散してステップ端に取り込まれる過程で起こる。そのため、ステップバンチングは、「ステップ間平均距離×(1/2)≦III族原子種の表面拡散長」の条件を満足する環境下で起こりやすい。III族原子種において、ガリウムは、アルミニウムやインジウムと比較して表面拡散長が長いことが知られている。そのため、歪み誘因ステップバンチングは、ガリウムを主成分とするIII族窒化物半導体、特に窒化ガリウムで発生しやすい。なお、本明細書でいう「窒化ガリウム」には、1%未満の不純物(B,Al,In,C,Si,Ge,Mg,S,Fe,As,Sb等)を含有している窒化ガリウムも含まれる。 Further, the strain-induced step bunching in the nitride semiconductor layer is more remarkable in the group III nitride semiconductor whose main component is gallium as the group III element. Step bunching occurs in the process where group III atomic species on the terrace are diffused into the step edge. Therefore, step bunching is likely to occur in an environment that satisfies the condition of “average distance between steps × (1/2) ≦ surface diffusion length of group III atomic species”. In group III atomic species, gallium is known to have a longer surface diffusion length than aluminum and indium. Therefore, strain-induced step bunching is likely to occur in a group III nitride semiconductor mainly containing gallium, particularly gallium nitride. As used herein, “gallium nitride” includes gallium nitride containing less than 1% impurities (B, Al, In, C, Si, Ge, Mg, S, Fe, As, Sb, etc.). Is also included.
 また、「多層バッファ層は、III族窒化物半導体層より格子定数が小さい」とは、多層バッファ層の全体とIII族窒化物半導体層の全体を比較したときに、多層バッファ層の格子定数(平均格子定数)が、III族窒化物半導体層の格子定数(平均格子定数)より小さいことを意味する。そのため、多層バッファ層の一部分とIII族窒化物半導体層の一部分とを比較したときに、多層バッファ層の一部分の格子定数が、III族窒化物半導体層の一部分の格子定数より大きくなることもある。 In addition, “the multilayer buffer layer has a smaller lattice constant than the group III nitride semiconductor layer” means that when comparing the entire multilayer buffer layer and the entire group III nitride semiconductor layer, the lattice constant of the multilayer buffer layer ( Mean lattice constant) is smaller than the lattice constant (average lattice constant) of the group III nitride semiconductor layer. Therefore, when a portion of the multilayer buffer layer is compared with a portion of the group III nitride semiconductor layer, the lattice constant of a portion of the multilayer buffer layer may be larger than the lattice constant of a portion of the group III nitride semiconductor layer. .
 なお、本明細書では、「平均格子歪み」と「界面格子歪み」という用語が用いられている。ここで、「平均格子歪み」と「界面格子歪み」について、第1層が第2層の表面に積層されている場合について説明する。第1層の面方向(結晶成長する方向と直交する方向)の理想格子定数(理論上の格子定数)をa、実際の格子定数をa’とし、第2層の面方向の理想格子定数をa、実際の格子定数をa’とする。第1層の平均格子歪みε、第2層の平均格子歪みε、第1層と第2層の界面における第1層の界面格子歪みεIf1、第1層の第2層に対する歪み緩和率Rは、以下の式で示される。 In the present specification, the terms “average lattice strain” and “interface lattice strain” are used. Here, a case where the first layer is laminated on the surface of the second layer will be described with respect to “average lattice strain” and “interface lattice strain”. The ideal lattice constant (theoretical lattice constant) in the plane direction of the first layer (direction perpendicular to the crystal growth direction) is a 1 , the actual lattice constant is a 1 ′, and the ideal lattice in the plane direction of the second layer The constant is a 2 , and the actual lattice constant is a 2 ′. Average lattice strain ε 1 of the first layer, average lattice strain ε 2 of the second layer, interface lattice strain ε If1 of the first layer at the interface between the first layer and the second layer, strain relaxation of the first layer with respect to the second layer The rate R 1 is expressed by the following equation.
  ε=(a’-a)/a
  ε=(a’-a)/a
  εIf1=(a’-a)/a
  R=(a’-a’)/(a-a’)
 本明細書で開示する半導体装置は、基板上に多層バッファ層を介してIII族窒化物半導体層が設けられており、そのIII族窒化物半導体層の表面側に半導体素子が形成されている。多層バッファ層は、少なくとも第1バッファ層と第2バッファ層を含んでいる。第1バッファ層は、III族窒化物半導体層に接している。第2バッファ層は、第1バッファ層に接している。第1バッファ層と第2バッファ層は組成が異なる。多層バッファ層は、平均格子定数がIII族窒化物半導体層より小さい。III族窒化物半導体層と第1バッファ層との界面におけるIII族窒化物半導体層の界面格子歪みが、第1バッファ層と第2バッファ層の界面における第1バッファ層の界面格子歪みより小さい。
ε 1 = (a 1 '−a 1 ) / a 1
ε 2 = (a 2 '-a 2 ) / a 2
ε If1 = (a 2 '-a 1 ) / a 1
R 1 = (a 1 ′ −a 2 ′) / (a 1 −a 2 ′)
In the semiconductor device disclosed in this specification, a group III nitride semiconductor layer is provided over a substrate via a multilayer buffer layer, and a semiconductor element is formed on the surface side of the group III nitride semiconductor layer. The multilayer buffer layer includes at least a first buffer layer and a second buffer layer. The first buffer layer is in contact with the group III nitride semiconductor layer. The second buffer layer is in contact with the first buffer layer. The first buffer layer and the second buffer layer have different compositions. The multilayer buffer layer has an average lattice constant smaller than that of the group III nitride semiconductor layer. The interface lattice strain of the group III nitride semiconductor layer at the interface between the group III nitride semiconductor layer and the first buffer layer is smaller than the interface lattice strain of the first buffer layer at the interface between the first buffer layer and the second buffer layer.
 以下、本明細書で開示される技術の特徴を整理する。なお、以下に記す事項は、各々単独で技術的な有用性を有している。 The following summarizes the features of the technology disclosed in this specification. The items described below have technical usefulness independently.
 半導体ウエハは、基板と、基板上に設けられている多層バッファ層と、多層バッファ層上に設けられているIII族窒化物半導体層を備えている。基板は、III族窒化物半導体層より熱膨張係数が小さい。具体的には、基板は、300~1300Kの線膨張係数の温度積分値が、III族窒化物半導体層を構成する材料のa軸方向の300~1300Kの線膨張係数の温度積分値より小さい。より具体的には、基板の材料は、シリコン(Si)、シリコンカーバード(SiC)である。基板の厚みは0.1~2mmである。好ましくは、基板と多層バッファ層の間に、界面層、窒化アルミニウム(AlN)層を設ける。界面層の材料は、Al,AlON等を用いることができる。界面層を設けることにより、窒化アルミニウム層の配向性が向上し、多層バッファ層,III族窒化物半導体層の結晶性を向上させることができる。なお、界面層は省略することもできる。窒化アルミニウム層の厚みは10~500nmである。なお、基板がシリコンの場合、窒化アルミニウム層の厚みは50~500nmであることが好ましい。基板がシリコンカーバイドの場合、窒化アルミニウム層の厚みは10~100nmであることが好ましい。窒化アルミニウムは、III族窒化物半導体の中で最も格子定数が小さい。そのため、窒化アルミニウム層を設けることにより、後述する多層バッファ層に必要な量の圧縮歪みを与えることができる。なお、上記したように、界面層,窒化アルミニウム層を省略し、基板の表面に直接多層バッファ層を形成することもできる。 The semiconductor wafer includes a substrate, a multilayer buffer layer provided on the substrate, and a group III nitride semiconductor layer provided on the multilayer buffer layer. The substrate has a smaller coefficient of thermal expansion than the group III nitride semiconductor layer. Specifically, in the substrate, the temperature integral value of the linear expansion coefficient of 300 to 1300K is smaller than the temperature integral value of the linear expansion coefficient of 300 to 1300K in the a-axis direction of the material constituting the group III nitride semiconductor layer. More specifically, the material of the substrate is silicon (Si) or silicon carbide (SiC). The thickness of the substrate is 0.1 to 2 mm. Preferably, an interface layer and an aluminum nitride (AlN) layer are provided between the substrate and the multilayer buffer layer. As the material for the interface layer, Al 2 O 3 , AlON, or the like can be used. By providing the interface layer, the orientation of the aluminum nitride layer is improved, and the crystallinity of the multilayer buffer layer and the group III nitride semiconductor layer can be improved. The interface layer can be omitted. The thickness of the aluminum nitride layer is 10 to 500 nm. When the substrate is silicon, the aluminum nitride layer preferably has a thickness of 50 to 500 nm. When the substrate is silicon carbide, the thickness of the aluminum nitride layer is preferably 10 to 100 nm. Aluminum nitride has the smallest lattice constant among group III nitride semiconductors. Therefore, by providing the aluminum nitride layer, a necessary amount of compressive strain can be applied to the multilayer buffer layer described later. In addition, as described above, the interface layer and the aluminum nitride layer can be omitted, and the multilayer buffer layer can be formed directly on the surface of the substrate.
 多層バッファ層は、少なくとも、III族窒化物半導体層に接する第1バッファ層と、第1バッファ層に接する第2バッファ層を含んでいる。なお、多層バッファ層は、第2バッファ層に接する第3バッファ層、第3バッファ層に接する第4バッファ層等を含むこともある。すなわち、多層バッファ層は、2層以上の層を備える多層構造である。第1バッファ層は、多層バッファ層を構成する層のうち、最も表面側(III族窒化物半導体層側)に位置する層である。第1バッファ層と第2バッファ層は組成が異なっている。また、第1バッファ層は、第2バッファ層に対してコヒーレントではない。具体的には、第1バッファ層の平均格子定数と第2バッファ層の平均格子定数とをオングストローム単位で小数点以下3桁まで比較したときに、両者が異なっている。第1バッファ層が第2バッファ層に対してコヒーレントでないことにより、第1バッファ層内で歪み緩和が起こる。そのため、第2バッファ層の歪みがIII族窒化物半導体層にそのまま引き継がれることを防止することができる。すなわち、第1バッファ層が第2バッファ層に対してコヒーレントでないことにより、III族窒化物半導体層の歪みを低減し、歪み誘因ステップバンチングを抑制することができる。好ましくは、第1バッファ層の第2バッファ層に対する歪み緩和率(R)は0.8以上である。歪み緩和率(R)を0.8以上とすることにより、第1バッファ層で十分な歪み緩和が起こり、III族窒化物半導体層の歪みを効果的に低減することができる。 The multilayer buffer layer includes at least a first buffer layer in contact with the group III nitride semiconductor layer and a second buffer layer in contact with the first buffer layer. The multilayer buffer layer may include a third buffer layer in contact with the second buffer layer, a fourth buffer layer in contact with the third buffer layer, and the like. That is, the multilayer buffer layer has a multilayer structure including two or more layers. The first buffer layer is a layer located on the most surface side (group III nitride semiconductor layer side) among the layers constituting the multilayer buffer layer. The first buffer layer and the second buffer layer have different compositions. Also, the first buffer layer is not coherent with respect to the second buffer layer. Specifically, when the average lattice constant of the first buffer layer and the average lattice constant of the second buffer layer are compared to 3 digits after the decimal point in angstrom units, they are different. Since the first buffer layer is not coherent with the second buffer layer, strain relaxation occurs in the first buffer layer. Therefore, it is possible to prevent the distortion of the second buffer layer from being directly transferred to the group III nitride semiconductor layer. That is, since the first buffer layer is not coherent with respect to the second buffer layer, the strain of the group III nitride semiconductor layer can be reduced and the strain-induced step bunching can be suppressed. Preferably, the strain relaxation rate (R 1 ) of the first buffer layer with respect to the second buffer layer is 0.8 or more. By setting the strain relaxation rate (R 1 ) to 0.8 or more, sufficient strain relaxation occurs in the first buffer layer, and the strain of the group III nitride semiconductor layer can be effectively reduced.
 第1バッファ層の厚みは、0.05μm以上とすることにより、第1バッファ層が第2バッファ層に対してコヒーレントに成長することを防止することができる。より好ましくは、第1バッファ層の厚みは、0.2μm以上である。第1バッファ層の厚みを0.2μm以上とすることにより、第1バッファ層の界面格子歪みの大きさ、第1バッファ層の成長条件に係らず、より確実に第1バッファ層が第2バッファ層に対してコヒーレントに成長することを防止することができる。 By setting the thickness of the first buffer layer to 0.05 μm or more, the first buffer layer can be prevented from growing coherently with respect to the second buffer layer. More preferably, the thickness of the first buffer layer is 0.2 μm or more. By setting the thickness of the first buffer layer to 0.2 μm or more, the first buffer layer is more reliably connected to the second buffer regardless of the size of the interfacial lattice strain of the first buffer layer and the growth conditions of the first buffer layer. It is possible to prevent coherent growth with respect to the layer.
 多層バッファ層の全体とIII族窒化物半導体層の全体を比較したときに、多層バッファ層の平均格子定数が、III族窒化物半導体層の平均格子定数より小さい。また、多層バッファ層の全体と窒化アルミニウムを比較したときに、多層バッファ層の平均格子定数が、窒化アルミニウムの格子定数より大きい。なお、多層バッファ層は、全体として、圧縮歪みを有していることが好ましい。多層バッファ層が圧縮歪みを有していることにより、III族窒化物半導体層の温度が成膜後に成長温度(高温)から室温(低温)に変化するときに、III族窒化物半導体層に生じる引張歪みを相殺することができる。第1バッファ層には、引張歪みが残留していないことが好ましい。換言すると、第1バッファ層は、歪みが残留していないか、圧縮歪みが残留している。より好ましくは、第1バッファ層は、圧縮歪みが残留している。なお、「第1バッファ層に圧縮歪みが残留している」とは、第1バッファ層の平均格子歪みが負の値であることに相当する。本明細書で開示する半導体ウエハでは、多層バッファ層を構成している多層構造の各層において、平均格子歪みの絶対値が最も大きい層は、第1バッファ層以外の層である。すなわち、第1バッファ層の平均格子歪みの絶対値は、多層バッファ層を構成している多層構造の各層のうち、最大ではない。 When comparing the entire multilayer buffer layer and the entire group III nitride semiconductor layer, the average lattice constant of the multilayer buffer layer is smaller than the average lattice constant of the group III nitride semiconductor layer. Further, when the entire multilayer buffer layer and aluminum nitride are compared, the average lattice constant of the multilayer buffer layer is larger than the lattice constant of aluminum nitride. The multilayer buffer layer preferably has a compressive strain as a whole. Due to the compressive strain of the multilayer buffer layer, it occurs in the group III nitride semiconductor layer when the temperature of the group III nitride semiconductor layer changes from the growth temperature (high temperature) to room temperature (low temperature) after film formation. Tensile strain can be offset. It is preferable that no tensile strain remains in the first buffer layer. In other words, in the first buffer layer, no strain remains or compressive strain remains. More preferably, the first buffer layer has a compressive strain remaining. Note that “the compressive strain remains in the first buffer layer” corresponds to the average lattice strain of the first buffer layer being a negative value. In the semiconductor wafer disclosed in this specification, the layer having the largest absolute value of the average lattice strain among the layers of the multilayer structure constituting the multilayer buffer layer is a layer other than the first buffer layer. In other words, the absolute value of the average lattice strain of the first buffer layer is not the maximum among the layers of the multilayer structure constituting the multilayer buffer layer.
 多層バッファ層の材料は、AlGa1-xN(0<x<1)で示される窒化物半導体を用いることができる。また、第1バッファ層は、AlGa1-xN(0<x<0.5)で示される窒化物半導体であることが好ましい。より好ましくは、第1バッファ層は、AlGa1-xN(0<x<0.2)で示される窒化物半導体である。第1バッファ層の平均格子定数がAlNよりもGaN(窒化物半導体)に近くなるので、III族窒化物半導体層と第1バッファ層の平均格子定数の差が小さくなり、III族窒化物半導体層の界面格子歪みを小さくすることができる。 As the material of the multilayer buffer layer, a nitride semiconductor represented by Al x Ga 1-x N (0 <x <1) can be used. The first buffer layer is preferably a nitride semiconductor represented by Al x Ga 1-x N (0 <x <0.5). More preferably, the first buffer layer is a nitride semiconductor represented by Al x Ga 1-x N (0 <x <0.2). Since the average lattice constant of the first buffer layer is closer to GaN (nitride semiconductor) than to AlN, the difference in average lattice constant between the group III nitride semiconductor layer and the first buffer layer is reduced, and the group III nitride semiconductor layer is reduced. It is possible to reduce the interfacial lattice distortion.
 多層バッファ層がAlGa1-xN(0<x<1)で示される窒化物半導体の場合、多層バッファ層の各層は「x」の値が異なることがある。なお、「x」の値は、表面(III族窒化物半導体層側)に向かうに従って小さくなっていることが好ましい。すなわち、多層バッファ層は、表面に向かうに従ってAl組成が小さくなる多層構造であることが好ましい。あるいは、多層バッファ層は、異なる材料を繰り返し積層した構造とすることもできる。例えば、多層バッファ層は、AlNとGaNの積層構造が繰り返し設けられている構造とすることができる。あるいは、多層バッファ層は、AlNとAlGaNの積層構造が繰り返し設けられている構造とすることもできる。多層バッファ層の厚みは0.5~10μmとすることができる。 When the multilayer buffer layer is a nitride semiconductor represented by Al x Ga 1-x N (0 <x <1), each layer of the multilayer buffer layer may have a different “x” value. In addition, it is preferable that the value of “x” becomes smaller toward the surface (the group III nitride semiconductor layer side). That is, the multilayer buffer layer preferably has a multilayer structure in which the Al composition becomes smaller toward the surface. Alternatively, the multilayer buffer layer may have a structure in which different materials are repeatedly stacked. For example, the multilayer buffer layer can have a structure in which a laminated structure of AlN and GaN is repeatedly provided. Alternatively, the multilayer buffer layer may have a structure in which a laminated structure of AlN and AlGaN is repeatedly provided. The thickness of the multilayer buffer layer can be 0.5 to 10 μm.
 III族窒化物半導体層は、単層であってもよいし、複層であってもよい。なお、単層のIII族窒化物半導体層とは、III族窒化物半導体層の表面から裏面までの組成が同一であることを意味する。また、複層のIII族窒化物半導体層とは、III族窒化物半導体層がIII族元素の組成が異なる複数の層を備えていることを意味する。単層のIII族窒化物半導体層の場合、III族窒化物半導体層の材料は、ガリウム(Ga)を主体とするIII族窒化物半導体であることが好ましい。また、複層のIII族窒化物半導体層の場合、複数の層のうち、少なくとも第1バッファ層に接する層の材料がガリウムを主体とするIII族窒化物半導体であることが好ましい。なお、「ガリウムを主体とするIII族窒化物半導体」とは、典型的には窒化ガリウム(GaN)を意味し、不純物としてGaNに対して1%未満の原子%のオーダーでB,Al,In,C,Si,Ge,Mg,S,Fe,As,Sb等の元素を含有している窒化ガリウムも含まれる。 The group III nitride semiconductor layer may be a single layer or multiple layers. Note that the single-layer group III nitride semiconductor layer means that the composition from the front surface to the back surface of the group III nitride semiconductor layer is the same. In addition, the multiple group III nitride semiconductor layer means that the group III nitride semiconductor layer includes a plurality of layers having different compositions of group III elements. In the case of a single-layer group III nitride semiconductor layer, the group III nitride semiconductor layer is preferably a group III nitride semiconductor mainly composed of gallium (Ga). Further, in the case of a multi-layer group III nitride semiconductor layer, it is preferable that at least a layer material in contact with the first buffer layer among the plurality of layers is a group III nitride semiconductor mainly composed of gallium. The “group III nitride semiconductor mainly composed of gallium” typically means gallium nitride (GaN), and B, Al, In on the order of atomic percent of less than 1% with respect to GaN as impurities. Further, gallium nitride containing elements such as C, Si, Ge, Mg, S, Fe, As, and Sb is also included.
 III族窒化物半導体層は、炭素を含んでいることが好ましい。III族窒化物半導体層が炭素を含むことにより、半導体装置がオフ状態のときにリーク電流が流れることを抑制することができる。III族窒化物半導体層は、機能層(半導体素子を構成する層)として利用することができる。単層のIII族窒化物半導体層を機能層として利用することもできる。また、複層のIII族窒化物半導体層のうちの、第1バッファ層に接する層より表面側に設けられたIII族窒化物半導体層を機能層として利用することもできる。本明細書で開示する半導体ウエハでは、III族窒化物半導体層と第1バッファ層との界面における窒化物半導体素子の界面格子歪み(窒化物半導体素子の界面格子歪み)が、第1バッファ層と第2バッファ層の界面における第1バッファ層の界面格子歪み(第1バッファ層の界面格子歪み)より小さい。窒化物半導体素子の界面格子歪みが第1バッファ層の界面格子歪みより小さいことにより、III族窒化物半導体層に歪み誘因ステップバンチングが発生することを抑制することができる。
(第1実施例)
 図1を参照し、半導体ウエハ1について説明する。半導体ウエハ1は、シリコン基板2と、シリコン基板2上に形成された界面層4と、界面層4上に形成されたAlN層6と、AlN層6上に形成された多層バッファ層8と、多層バッファ層8上に形成されたIII族窒化物半導体層10と、III族窒化物半導体層10に形成された窒化物半導体機能層12を備えている。シリコン基板2の厚みT2は675μmである。界面層4の材料はAlである。界面層4の厚みT4は3nm未満になるように調整されている。AlN層6の厚みT6は0.3μmに調整されている。多層バッファ層8の材料はAlGa1-xNである。多層バッファ層8の厚みT8は2.5μmに調整されている。
The group III nitride semiconductor layer preferably contains carbon. When the group III nitride semiconductor layer contains carbon, leakage current can be prevented from flowing when the semiconductor device is in the off state. The group III nitride semiconductor layer can be used as a functional layer (a layer constituting a semiconductor element). A single group III nitride semiconductor layer can also be used as a functional layer. In addition, among the multiple group III nitride semiconductor layers, a group III nitride semiconductor layer provided on the surface side of the layer in contact with the first buffer layer can also be used as a functional layer. In the semiconductor wafer disclosed in this specification, the interface lattice strain of the nitride semiconductor element (interface lattice strain of the nitride semiconductor element) at the interface between the group III nitride semiconductor layer and the first buffer layer is less than that of the first buffer layer. It is smaller than the interface lattice strain of the first buffer layer at the interface of the second buffer layer (interface lattice strain of the first buffer layer). Since the interfacial lattice strain of the nitride semiconductor element is smaller than the interfacial lattice strain of the first buffer layer, it is possible to suppress the occurrence of strain-induced step bunching in the group III nitride semiconductor layer.
(First embodiment)
The semiconductor wafer 1 will be described with reference to FIG. The semiconductor wafer 1 includes a silicon substrate 2, an interface layer 4 formed on the silicon substrate 2, an AlN layer 6 formed on the interface layer 4, a multilayer buffer layer 8 formed on the AlN layer 6, A group III nitride semiconductor layer 10 formed on the multilayer buffer layer 8 and a nitride semiconductor functional layer 12 formed on the group III nitride semiconductor layer 10 are provided. The thickness T2 of the silicon substrate 2 is 675 μm. The material of the interface layer 4 is Al 2 O 3 . The thickness T4 of the interface layer 4 is adjusted to be less than 3 nm. The thickness T6 of the AlN layer 6 is adjusted to 0.3 μm. The material of the multilayer buffer layer 8 is Al x Ga 1-x N. The thickness T8 of the multilayer buffer layer 8 is adjusted to 2.5 μm.
 多層バッファ層8は、第1バッファ層8a,第2バッファ層8b,第3バッファ層8c及び第4バッファ層8dを備えた4層構造である。第1バッファ層8aがIII族窒化物半導体層10に接しており、第4バッファ層8dがAlN層6に接している。なお、第1バッファ層8aから第4バッファ層8dに向かうに従ってAlGa1-xNの「x」の値が大きくなっている。第1バッファ層8aの厚みは0.8μmに調整されており、第2バッファ層8bの厚みは0.2μmに調整されており、第3バッファ層8cの厚みは0.5μmに調整されており、第4バッファ層8dの厚みは1.0μmに調整されている。なお、界面層4は、原子層堆積法(ALD法)を用いて形成されている。界面層4の原料として、Al原料はトリメチルアルミニウム、O原料はオゾンが用いられている。また、AlN層6及び多層バッファ層8は、有機金属気相成長法(MOCVD法)を用いて形成されている。AlN層6及び多層バッファ層8の原料として、Al原料はトリメチルアルミニウム、Ga原料はトリメチルガリウム、N原料はアンモニアが用いられている。なお、成長温度はおよそ1000℃である。 The multilayer buffer layer 8 has a four-layer structure including a first buffer layer 8a, a second buffer layer 8b, a third buffer layer 8c, and a fourth buffer layer 8d. The first buffer layer 8 a is in contact with the group III nitride semiconductor layer 10, and the fourth buffer layer 8 d is in contact with the AlN layer 6. Note that the value of “x” of Al x Ga 1-x N increases from the first buffer layer 8a toward the fourth buffer layer 8d. The thickness of the first buffer layer 8a is adjusted to 0.8 μm, the thickness of the second buffer layer 8b is adjusted to 0.2 μm, and the thickness of the third buffer layer 8c is adjusted to 0.5 μm. The thickness of the fourth buffer layer 8d is adjusted to 1.0 μm. The interface layer 4 is formed by using an atomic layer deposition method (ALD method). As the raw material of the interface layer 4, trimethylaluminum is used as the Al raw material, and ozone is used as the O raw material. The AlN layer 6 and the multilayer buffer layer 8 are formed using a metal organic chemical vapor deposition method (MOCVD method). As raw materials for the AlN layer 6 and the multilayer buffer layer 8, trimethylaluminum is used as the Al raw material, trimethylgallium is used as the Ga raw material, and ammonia is used as the N raw material. The growth temperature is about 1000 ° C.
 III族窒化物半導体層10の材料は、窒化ガリウム(GaN)である。III族窒化物半導体層10の厚みは0.6μmに調整されており、窒化物半導体機能層12の厚みは0.4μmに調整されている。III族窒化物半導体層10は、炭素を2×1018cm-3含んでいる。III族窒化物半導体層10に導入されている炭素は、窒化物半導体機能層12に作りこまれた半導体素子とシリコン基板2の間にリーク電流が流れることを防止する。窒化物半導体機能層12は、不純物を含まないi型である(不可避の炭素を含んでいることはある)。窒化物半導体機能層12を用いて半導体素子を形成することができる。 The material of the group III nitride semiconductor layer 10 is gallium nitride (GaN). The thickness of group III nitride semiconductor layer 10 is adjusted to 0.6 μm, and the thickness of nitride semiconductor functional layer 12 is adjusted to 0.4 μm. The group III nitride semiconductor layer 10 contains 2 × 10 18 cm −3 of carbon. The carbon introduced into the group III nitride semiconductor layer 10 prevents leakage current from flowing between the semiconductor element formed in the nitride semiconductor functional layer 12 and the silicon substrate 2. The nitride semiconductor functional layer 12 is i-type that does not contain impurities (it may contain unavoidable carbon). A semiconductor element can be formed using the nitride semiconductor functional layer 12.
 図2は、半導体ウエハ1について、AlN層6,多層バッファ層8及びIII族窒化物半導体層10の特性を示している。なお、Al組成(x)は、各層をAlGa1-xNで示したときの「x」の値に相当する。以下、各層の特性の算出方法について説明する。なお、以下の計算式では、III族窒化物半導体層10をGaNと示し、第1バッファ層8aをTOPと示し、第1バッファ層8aから「i」番目のバッファ層をiと示す。例えば、第2バッファ層8bは「i=1」であり、第3バッファ層8cは「i=2」である。 FIG. 2 shows the characteristics of the AlN layer 6, the multilayer buffer layer 8, and the group III nitride semiconductor layer 10 for the semiconductor wafer 1. The Al composition (x) corresponds to the value of “x” when each layer is represented by Al x Ga 1-x N. Hereinafter, a method for calculating the characteristics of each layer will be described. In the following calculation formula, the group III nitride semiconductor layer 10 is denoted by GaN, the first buffer layer 8a is denoted by TOP, and the “i” th buffer layer from the first buffer layer 8a is denoted by i. For example, the second buffer layer 8b is “i = 1”, and the third buffer layer 8c is “i = 2”.
 各層の平均格子定数は、X線逆格子マッピングによって測定した。具体的には、114回折と004回折の逆格子マッピングのピークから、GaN,TOP,「i」の114面の面間隔d114jと004面の面間隔d004jを求めた(j=GaN,TOP,i)。面間隔d114jとd004jを用いて、a軸方向の平均格子定数a’とc軸方向の平均格子定数c’を下記式(1),(2)より算出した。図2には、下記式(1)により算出した平均格子定数a’を示している。
式(1):a’=2×d110j=2×{(1/d114j )-(1/d004j )}-0.5
式(2):c’=4×d004j
 次に、Al組成(x)について説明する。Al組成(x)は、X線逆格子マッピングによって得られた面間隔d114j,d004j,上記式(1),(2)で得られた結果を用いて、下記式(3)の「x」を求めることにより算出した。なお、aAlNはAlNのa軸の理想格子定数であり、cAlNはAlNのc軸の理想格子定数である。AlNの理想格子定数aAlN,cAlNは、各々3.112Å(=0.3112nm),4.980Å(=0.4980nm)である。また、GaNの理想格子定数aGaN,cGaNは、各々3.189Å(=0.0.3189nm),5.185Å(=0.5185nm)である。なお、ポアソン比としてσ=0.38を用いた。ポアソン比については、「T.Detchprohm et.al., Jpn.J.Appl.phys.31, L454(1992)」に開示されている。
式(3):(1+σ)×(aGaN-aAlN)×(cGaN-cAlN)×x-{[(1+σ)×cGaN]-c’}×(aGaN-aAlN)+[(1+σ)×aGaN-σ×a’]×(cGaN-cAlN)}×x+σ×cGaN×(aGaN-a’)+aGaN×(cGaN-c’)=0
 次に、バッファ層のa軸の理想格子定数の算出方法について説明する。上記したように、GaNの理想格子定数aGaNは、3.189Å(=0.3189nm)であり、AlNの理想格子定数aAlNは、3.112Å(=0.3112nm)である。バッファ層の各層(TOP,i)の理想格子定数aは、各層をAlGa1-xNで示したときの各層の「x」の値を変数として下記式(4)より算出した。
式(4):a=3.112×x+3.189×(1-x)
 次に、平均格子歪みε(j=GaN,TOP,i)と、III族窒化物半導体層の界面格子歪みεIf_GaNと、第1バッファ層の界面格子歪みεIf_TOPと、歪み緩和率R(j=GaN,TOP,i)について説明する。ε,εIf_GaN,εIf_TOP,Rは、上記式(1)~(4)で得られた結果を用いて、下記式(5)~(8)より算出した。なお、平均格子歪み,界面格子歪みは、正の値の場合は引張歪みであり、負の値の場合は圧縮歪みである。そのため、格子歪みの大小関係は、実際の数値を比較するのではなく、絶対値を比較する。また、下記式(8)において、j=GaNの場合、j+1はTOPに相当する。同様に、j=TOPの場合、j+1はi=1に相当する。
式(5):ε(j=GaN,TOP,i)=(a’-a)/a
式(6):εIf_GaN=(a’TOP-aGaN)/aGaN
式(7):εIf_TOP=(a’-aTOP)/aTOP
式(8):R(j=GaN,TOP,i)=(a’-aj+1’)/(a-aj+1’)
 図2に示すように、半導体ウエハ1では、III族窒化物半導体層10の界面格子歪み(εIf_GaN)が、第1バッファ層8aの界面格子歪み(εIf_TOP)より小さい。また、第2バッファ層8bの平均格子歪みε’が、バッファ層8a~8dの平均格子歪みのなかで最大である。すなわち、第1バッファ層8aの平均格子歪み(εTOP)は、多層バッファ層8を構成する層の平均格子歪み(ε1~3)のなかで最大ではない。なお、第1バッファ層8aの平均格子定数が3.1815Å(=0.31815nm)であり、第2バッファ層8bの平均格子定数が3.1378Å(=0.31378nm)である。そのため、第1バッファ層8aは、第2バッファ層8bに対してコヒーレントではないといえる。なお、X線逆格子マッピング測定における誤差(X線逆格子マッピング測定の精度)によって、第1バッファ層と第2バッファ層がコヒーレントな状態であっても、両者の平均格子定数が異なることもある。しかしながら、X線逆格子マッピング測定の精度を考慮しても、オングストローム(Å)の単位で平均格子定数の小数点以下3桁までを比較したときに第1バッファ層と第2バッファ層の平均格子定数に相違が見られれば、第1バッファ層と第2バッファ層はコヒーレントではないといえる。
(第2実施例)
 図3を参照し、半導体ウエハ11について説明する。半導体ウエハ11は、半導体ウエハ1の変形例である。半導体ウエハ11は、多層バッファ層18を構成する層の数が半導体ウエハ1よりも多い。半導体ウエハ11について、半導体ウエハ1と実質的に同じ構造については、半導体ウエハ1と同じ参照番号を付すことにより説明を省略することがある。
The average lattice constant of each layer was measured by X-ray reciprocal lattice mapping. Specifically, the peak of the reciprocal lattice mapping 114 diffraction and 004 diffraction, GaN, TOP, was determined 114 side of the plane spacing d 114j and 004 face the surface interval d 004J "i" (j = GaN, TOP , I). The average lattice constant a ′ j in the a-axis direction and the average lattice constant c ′ j in the c-axis direction were calculated from the following formulas (1) and (2) using the face spacings d 114j and d 004j . FIG. 2 shows an average lattice constant a ′ j calculated by the following equation (1).
Expression (1): a ′ j = 2 × d 110j = 2 × {(1 / d 114j 2 ) − (1 / d 004j 2 )} − 0.5
Formula (2): c ′ j = 4 × d 004j
Next, the Al composition (x) will be described. The Al composition (x) is obtained by using the interplanar spacings d 114j and d 004j obtained by the X-ray reciprocal mapping and the results obtained by the above formulas (1) and (2), using “x” in the following formula (3). ”Was calculated. Note that a AlN is the ideal lattice constant of the a-axis of AlN, and c AlN is the ideal lattice constant of the c-axis of AlN. The ideal lattice constants a AlN and c AlN of AlN are 3.112Å (= 0.3112 nm) and 4.980Å (= 0.4980 nm), respectively. The ideal lattice constants a GaN and c GaN of GaN are 3.189 で (= 0.0.3189 nm) and 5.185Å (= 0.5185 nm), respectively. Note that σ = 0.38 was used as the Poisson's ratio. The Poisson's ratio is disclosed in “T. Detchprohm et.al., Jpn.J.Appl.phys.31, L454 (1992)”.
Formula (3): (1 + σ) × (a GaN −a AlN ) × (c GaN −c AlN ) × x 2 − {[(1 + σ) × c GaN ] −c ′ j } × (a GaN −a AlN ) + [(1 + σ) × a GaN −σ × a ′ j ] × (c GaN −c AlN )} × x + σ × c GaN × (a GaN −a ′ j ) + a GaN × (c GaN −c ′ j ) = 0
Next, a method for calculating the ideal lattice constant of the a axis of the buffer layer will be described. As described above, the ideal lattice constant a GaN of GaN is 3.189 Å (= 0.3189 nm), and the ideal lattice constant a AlN of AlN is 3.112 Å (= 0.3112 nm). The ideal lattice constant a j of each layer (TOP, i) of the buffer layer was calculated from the following formula (4) using the value of “x” of each layer as a variable when each layer was represented by Al x Ga 1-x N.
Formula (4): a j = 3.112 × x + 3.189 × (1−x)
Then, the average lattice strain ε j (j = GaN, TOP , i) and the interface lattice distortion epsilon If_GaN group III nitride semiconductor layer, and the interface lattice distortion epsilon If_TOP the first buffer layer, the strain relaxation rate R j (J = GaN, TOP, i) will be described. ε j , ε If_GaN , ε If_TOP , and R j were calculated from the following equations (5) to (8) using the results obtained from the above equations (1) to (4). The average lattice strain and the interface lattice strain are positive strains when they are positive values, and compressive strains when they are negative values. Therefore, the magnitude relation of the lattice distortion does not compare actual numerical values but compares absolute values. In the following formula (8), when j = GaN, j + 1 corresponds to TOP. Similarly, when j = TOP, j + 1 corresponds to i = 1.
Expression (5): ε j (j = GaN, TOP, i) = (a ′ j −a j ) / a j
Formula (6): ε IfGaN = (a ′ TOP −a GaN ) / a GaN
Expression (7): ε IfTOP = (a ′ 1 −a TOP ) / a TOP
Formula (8): R j (j = GaN, TOP, i) = (a j '−a j + 1 ′) / (a j −a j + 1 ′)
As shown in FIG. 2, the semiconductor wafer 1, the interface lattice distortion of the group III nitride semiconductor layer 10 (ε If_GaN) is the interface lattice distortion (ε If_TOP) of the first buffer layer 8a smaller. The average lattice strain epsilon '1 of the second buffer layer 8b is the maximum among the average lattice strain of the buffer layer 8a ~ 8d. That is, the average lattice strain (ε TOP ) of the first buffer layer 8 a is not the maximum among the average lattice strains (ε 1 to 3 ) of the layers constituting the multilayer buffer layer 8. The average lattice constant of the first buffer layer 8a is 3.18153 (= 0.31815 nm), and the average lattice constant of the second buffer layer 8b is 3.1378Å (= 0.31378 nm). Therefore, it can be said that the first buffer layer 8a is not coherent with respect to the second buffer layer 8b. Note that due to an error in the X-ray reciprocal lattice mapping measurement (accuracy of the X-ray reciprocal lattice mapping measurement), even if the first buffer layer and the second buffer layer are in a coherent state, the average lattice constants of both may be different. . However, even if the accuracy of the X-ray reciprocal lattice mapping measurement is taken into consideration, the average lattice constant of the first buffer layer and the second buffer layer is compared when the average lattice constant is compared to the third decimal place in units of angstroms (Å). If there is a difference, it can be said that the first buffer layer and the second buffer layer are not coherent.
(Second embodiment)
The semiconductor wafer 11 will be described with reference to FIG. The semiconductor wafer 11 is a modification of the semiconductor wafer 1. The semiconductor wafer 11 has a larger number of layers constituting the multilayer buffer layer 18 than the semiconductor wafer 1. About the semiconductor wafer 11, about the substantially same structure as the semiconductor wafer 1, description may be abbreviate | omitted by attaching | subjecting the same reference number as the semiconductor wafer 1. FIG.
 半導体ウエハ11では、多層バッファ層18が、第1バッファ層18a,第2バッファ層18b,第3バッファ層18c,第4バッファ層18d及び第5バッファ層18eを備えた5層構造である。なお、第1バッファ層18aは、Al組成(x)が0.08~0.03の組成傾斜層である。第1バッファ層18aの平均Al組成(x)は、0.033である。なお、図4では、小数点第3以下を四捨五入した値(すなわち、x=0.03)を示している。多層バッファ層18の厚みT18は、2.43μmである。第1バッファ層18aの厚みT18aは0.63μmに調整されている。第2~第5バッファ層18b~18eの厚みT18b~T18eは、各々0.1,0.2,0.5,1.0μmに調整されている。 In the semiconductor wafer 11, the multilayer buffer layer 18 has a five-layer structure including a first buffer layer 18a, a second buffer layer 18b, a third buffer layer 18c, a fourth buffer layer 18d, and a fifth buffer layer 18e. The first buffer layer 18a is a composition gradient layer having an Al composition (x) of 0.08 to 0.03. The average Al composition (x) of the first buffer layer 18a is 0.033. In FIG. 4, a value obtained by rounding off the third decimal place (ie, x = 0.03) is shown. The multilayer buffer layer 18 has a thickness T18 of 2.43 μm. The thickness T18a of the first buffer layer 18a is adjusted to 0.63 μm. The thicknesses T18b to T18e of the second to fifth buffer layers 18b to 18e are adjusted to 0.1, 0.2, 0.5, and 1.0 μm, respectively.
 図4に、半導体ウエハ11について、AlN層6,多層バッファ層18及びIII族窒化物半導体層10の特性を示す。図4に示すように、III族窒化物半導体層10の界面格子歪み(εIf_GaN)が、第1バッファ層18aの界面格子歪み(εIf_TOP)より小さい。また、第2バッファ層18bの平均格子歪みε’が、バッファ層18a~18eの平均格子歪み(絶対値)のなかで最大である。すなわち、第1バッファ層18aの平均格子歪み(εTOP)は、多層バッファ層18を構成する層の平均格子歪み(ε1~4)のなかで最大ではない。なお、第1バッファ層18aの平均格子定数が3.1804Å(=0.31804nm)であり、第2バッファ層18bの平均格子定数が3.1421Å(=0.31421nm)である。そのため、第1バッファ層18aは、第2バッファ層18bに対してコヒーレントではないといえる。 FIG. 4 shows the characteristics of the AlN layer 6, the multilayer buffer layer 18, and the group III nitride semiconductor layer 10 for the semiconductor wafer 11. As shown in FIG. 4, the interface lattice distortion of the group III nitride semiconductor layer 10 (ε If_GaN) is, interface lattice distortion of the first buffer layer 18a (ε If_TOP) smaller. The average lattice strain epsilon '1 of the second buffer layer 18b is the largest among the average lattice strain of the buffer layer 18a ~ 18e (absolute value). That is, the average lattice strain (ε TOP ) of the first buffer layer 18 a is not the maximum among the average lattice strains (ε 1 to 4 ) of the layers constituting the multilayer buffer layer 18. The average lattice constant of the first buffer layer 18a is 3.18043 (= 0.31804 nm), and the average lattice constant of the second buffer layer 18b is 3.1421Å (= 0.42121 nm). Therefore, it can be said that the first buffer layer 18a is not coherent with respect to the second buffer layer 18b.
 なお、半導体ウエハ11では、III族窒化物半導体層10は、厚みが0.75μmに調整されており、炭素を4×1019cm-3含んでいる。窒化物半導体機能層12は、厚みが0.48μmに調整されており、i型である。一例として、半導体ウエハ11では、窒化物半導体機能層12の表面に、AlGaN障壁層20nm、GaNキャップ層5nmが形成される。それにより、ヘテロ接合の2次元電子ガスとチャネルとして動作するHEMT構造を備える半導体装置を製造することができる。 In the semiconductor wafer 11, the group III nitride semiconductor layer 10 has a thickness adjusted to 0.75 μm and contains 4 × 10 19 cm −3 of carbon. The nitride semiconductor functional layer 12 is adjusted to a thickness of 0.48 μm and is i-type. As an example, in the semiconductor wafer 11, an AlGaN barrier layer 20 nm and a GaN cap layer 5 nm are formed on the surface of the nitride semiconductor functional layer 12. Thereby, a semiconductor device having a HEMT structure that operates as a heterojunction two-dimensional electron gas and a channel can be manufactured.
 なお、上記した半導体ウエハ1,11を用いて種々の半導体装置を製造することができる。一例として、半導体ウエハ1,11の表面にゲート電極,ソース電極及びドレイン電極を形成し、電界効果トランジスタを製造することができる。この場合、ゲート電極は、絶縁膜を介して窒化物半導体機能層12に対向させる。また、ソース電極及びドレイン電極は、窒化物半導体機能層12にオーミック接触させる。窒化物半導体機能層12は、電界効果トランジスタのチャネル層として機能する。また、他の一例として、半導体ウエハ1,11の表面にショットキー電極とオーミック電極を形成し、ショットキーダイオードを製造することもできる。この場合、窒化物半導体機能層12は、ショットキーダイオードの通電層として機能する。
(第3実施例)
 第3実施例の半導体ウエハについて説明する。本実施例の半導体ウエハの構造は、第1実施例の半導体ウエハ1と実質的に同じである。しかしながら、本実施例の半導体ウエハは、各層の特性が異なる。以下、図5を参照し、半導体ウエハ1との相違点を説明する。
Various semiconductor devices can be manufactured using the semiconductor wafers 1 and 11 described above. As an example, a field effect transistor can be manufactured by forming a gate electrode, a source electrode, and a drain electrode on the surfaces of the semiconductor wafers 1 and 11. In this case, the gate electrode is opposed to the nitride semiconductor functional layer 12 through the insulating film. The source electrode and the drain electrode are in ohmic contact with the nitride semiconductor functional layer 12. The nitride semiconductor functional layer 12 functions as a channel layer of the field effect transistor. As another example, a Schottky electrode and an ohmic electrode can be formed on the surfaces of the semiconductor wafers 1 and 11 to manufacture a Schottky diode. In this case, the nitride semiconductor functional layer 12 functions as a current-carrying layer for the Schottky diode.
(Third embodiment)
A semiconductor wafer according to a third embodiment will be described. The structure of the semiconductor wafer of this embodiment is substantially the same as that of the semiconductor wafer 1 of the first embodiment. However, the semiconductor wafer of this example has different characteristics of each layer. Hereinafter, differences from the semiconductor wafer 1 will be described with reference to FIG.
 本実施例の半導体ウエハは、第1バッファ層8aの平均格子歪みε’TOPが、バッファ層8a~8dの平均格子歪み(絶対値)のなかで最大である点が、第1実施例の半導体ウエハ1と異なる。すなわち、バッファ層のIII族窒化物半導体層10と接する部分が、最も高い圧縮歪みを有している。この相違は、製造条件(バッファ層の成長条件)を調整することで生じさせることができる。なお、本実施例の半導体ウエハにおいても、III族窒化物半導体層10の界面格子歪み(εIf_GaN)が第1バッファ層8aの界面格子歪み(εIf_TOP)より小さいという点において、第1実施例の半導体ウエハ1と共通の特性を有している。
(実験例)
 実施例1から3の半導体ウエハについて、表面粗さの測定を実施した。結果を、図8に示す。表面粗さは、50μm角領域における原子間力顕微鏡(Atomic Force Microscope)の二乗平均面粗さ(RMS)である。併せて、比較例1,2の半導体ウエハの表面粗さの測定も実施した。まず、比較例1,2の半導体ウエハの特徴を説明する。
In the semiconductor wafer of this embodiment, the average lattice strain ε ′ TOP of the first buffer layer 8a is the largest among the average lattice strains (absolute values) of the buffer layers 8a to 8d. Different from wafer 1. That is, the portion of the buffer layer in contact with the group III nitride semiconductor layer 10 has the highest compressive strain. This difference can be caused by adjusting the manufacturing conditions (buffer layer growth conditions). Also in the semiconductor wafer of the present embodiment, the interface lattice distortion of the group III nitride semiconductor layer 10 (ε If_GaN) is in that the interface lattice distortion (ε If_TOP) is smaller than the first buffer layer 8a, the first embodiment The semiconductor wafer 1 has common characteristics.
(Experimental example)
The surface roughness of the semiconductor wafers of Examples 1 to 3 was measured. The results are shown in FIG. The surface roughness is a root mean square roughness (RMS) of an atomic force microscope in an area of 50 μm square. In addition, the surface roughness of the semiconductor wafers of Comparative Examples 1 and 2 was also measured. First, the characteristics of the semiconductor wafers of Comparative Examples 1 and 2 will be described.
 比較例1の半導体ウエハの特性を図6に示す。比較例1の半導体ウエハは、Al組成(x)が異なる4層のバッファ層を備えている。第1バッファ層の厚みは、0.5μmである。III族窒化物半導体層は、炭素が4×1018cm-3含まれており、厚みは0.4μmである。比較例1では、III族窒化物半導体層の表面にi型の窒化物半導体機能層が積層されている。窒化物半導体機能層の厚みは0.6μmである。比較例1の半導体ウエハは、第1バッファ層の平均格子歪みε’TOPが、第1~第4バッファ層の平均格子歪み(絶対値)のなかで最大である。また、III族窒化物半導体層の界面格子歪み(εIf_GaN)が、第1バッファ層の界面格子歪み(εIf_TOP)より大きい。 The characteristics of the semiconductor wafer of Comparative Example 1 are shown in FIG. The semiconductor wafer of Comparative Example 1 includes four buffer layers having different Al compositions (x). The thickness of the first buffer layer is 0.5 μm. The group III nitride semiconductor layer contains 4 × 10 18 cm −3 of carbon and has a thickness of 0.4 μm. In Comparative Example 1, an i-type nitride semiconductor functional layer is laminated on the surface of the group III nitride semiconductor layer. The nitride semiconductor functional layer has a thickness of 0.6 μm. In the semiconductor wafer of Comparative Example 1, the average lattice strain ε ′ TOP of the first buffer layer is the largest among the average lattice strains (absolute values) of the first to fourth buffer layers. Further, the interfacial lattice strain (ε If_GaN ) of the group III nitride semiconductor layer is larger than the interfacial lattice strain (ε If_TOP ) of the first buffer layer.
 比較例2の半導体ウエハの特性を図7に示す。比較例1の半導体ウエハは、Al組成(x)が異なる4層のバッファ層を備えている。第1バッファ層の厚みは、0.44μmである。III族窒化物半導体層は、炭素が1.5×1018cm-3含まれており、厚みは0.66μmである。比較例2では、III族窒化物半導体層の表面にi型の窒化物半導体機能層が積層されている。窒化物半導体機能層の厚みは0.33μmである。また、比較例2では、i型の窒化物半導体機能層の表面に、AlGaN障壁層20nm、GaNキャップ層5nmが形成されている。比較例2の半導体ウエハは、第1バッファ層の平均格子歪みε’TOPが、第1~第4バッファ層の平均格子歪み(絶対値)のなかで最大である。また、III族窒化物半導体層の界面格子歪み(εIf_GaN)が、第1バッファ層の界面格子歪み(εIf_TOP)より大きい。 The characteristics of the semiconductor wafer of Comparative Example 2 are shown in FIG. The semiconductor wafer of Comparative Example 1 includes four buffer layers having different Al compositions (x). The thickness of the first buffer layer is 0.44 μm. The group III nitride semiconductor layer contains 1.5 × 10 18 cm −3 of carbon and has a thickness of 0.66 μm. In Comparative Example 2, an i-type nitride semiconductor functional layer is laminated on the surface of the group III nitride semiconductor layer. The nitride semiconductor functional layer has a thickness of 0.33 μm. In Comparative Example 2, an AlGaN barrier layer of 20 nm and a GaN cap layer of 5 nm are formed on the surface of the i-type nitride semiconductor functional layer. In the semiconductor wafer of Comparative Example 2, the average lattice strain ε ′ TOP of the first buffer layer is the largest among the average lattice strains (absolute values) of the first to fourth buffer layers. Further, the interfacial lattice strain (ε If_GaN ) of the group III nitride semiconductor layer is larger than the interfacial lattice strain (ε If_TOP ) of the first buffer layer.
 実施例1から3,比較例1及び2について、X線回折によりIII族窒化物半導体層のc軸の成長面に対する傾斜角を測定した。実施例1から3のIII族窒化物半導体層のc軸は、成長面の垂線に対してm軸方向に各々0.22度、0.31度、0.30度傾斜していた。また、比較例1及び2のIII族窒化物半導体層のc軸は、成長面の垂線に対してm軸方向に各々0.26度、0.33度傾斜していた。 For Examples 1 to 3 and Comparative Examples 1 and 2, the inclination angle of the group III nitride semiconductor layer with respect to the c-axis growth surface was measured by X-ray diffraction. The c-axes of the group III nitride semiconductor layers of Examples 1 to 3 were inclined 0.22 degrees, 0.31 degrees, and 0.30 degrees in the m-axis direction with respect to the normal to the growth surface, respectively. Further, the c-axes of the group III nitride semiconductor layers of Comparative Examples 1 and 2 were inclined by 0.26 degrees and 0.33 degrees in the m-axis direction with respect to the normal to the growth surface, respectively.
 図8では、III族窒化物半導体層の界面格子歪み(εIf_GaN)が、第1バッファ層aの界面格子歪み(εIf_TOP)より小さいという条件(条件1)を満足する実験例に○を記し、満足しない実験例に×を記している。また、第1バッファ層の平均格子歪み(絶対値,|εTOP|)が多層バッファ層を構成する層のなかで最大でないという条件(条件2)を満足する実験例に○を記し、満足しない実験例に×を記している。また、RMSの値が5.0以下の実験例に◎を記し、10.0以下の実験例に○を記し、10.0以上の実験例に×を記している。 In Figure 8, the interface lattice distortion of the group III nitride semiconductor layer (epsilon If_GaN) is marked with ○ in experimental examples that satisfy the interface lattice distortion of the first buffer layer a (ε If_TOP) condition that is less than (condition 1) In the experiment example which is not satisfied, x is marked. In addition, in the experimental example that satisfies the condition (Condition 2) that the average lattice strain (absolute value, | ε TOP |) of the first buffer layer is not the maximum among the layers constituting the multilayer buffer layer, ○ is marked and not satisfied X is described in the experimental example. In addition, “◎” is marked for an experimental example having an RMS value of 5.0 or less, “◯” is marked for an experimental example of 10.0 or less, and “x” is marked for an experimental example of 10.0 or more.
 図8に示すように、条件1を満足すると、RMS値が小さくなり、表面が平滑な半導体ウエハが得られることが確認できる(実施例1~3)。特に、条件1と条件2の双方を満足すると、RMS値が5.0以下となり、半導体ウエハの表面が極めて平滑であることが確認できる。なお、実施例の半導体ウエハは、III族窒化物半導体層の平均格子歪み(絶対値)が3.97×10-4~1.03×10-3であり、比較例のIII族窒化物半導体層の平均格子歪み(2.44×10-3,2.04×10-3)の半分以下である。III族窒化物半導体層の界面格子歪み(εIf_GaN)を第1バッファ層aの界面格子歪み(εIf_TOP)より小さくすることにより、III族窒化物半導体層の歪が低減され、歪み誘因ステップバンチングが抑制されることを示している。なお、実施例1~3の半導体ウエハは、第1バッファ層の第2バッファ層に対する歪み緩和率(RTOP)が、各々0.974,0.863,0.837である(図2,4及び5を参照)。すなわち、実施例1~3の半導体ウエハは、歪み緩和率(RTOP)が0.8以上である。それに対して、比較例1及び2の半導体ウエハは、歪み緩和率(RTOP)が、各々0.464,0.431であり、実施例1~3の半導ウエハと比較して小さい(図6及び7を参照)。 As shown in FIG. 8, when the condition 1 is satisfied, it can be confirmed that the RMS value becomes small and a semiconductor wafer having a smooth surface can be obtained (Examples 1 to 3). In particular, when both condition 1 and condition 2 are satisfied, the RMS value is 5.0 or less, and it can be confirmed that the surface of the semiconductor wafer is extremely smooth. In the semiconductor wafer of the example, the average lattice strain (absolute value) of the group III nitride semiconductor layer is 3.97 × 10 −4 to 1.03 × 10 −3 , and the group III nitride semiconductor of the comparative example It is less than half of the average lattice strain (2.44 × 10 −3 , 2.04 × 10 −3 ) of the layer. By smaller than interface lattice distortion of the group III nitride semiconductor layer (ε If_GaN) interface lattice distortion of the first buffer layer a (ε If_TOP), distortion of the group III nitride semiconductor layer is reduced, distortion inducement step bunching Is suppressed. In the semiconductor wafers of Examples 1 to 3, the strain relaxation rates (R TOP ) of the first buffer layer with respect to the second buffer layer are 0.974, 0.863, and 0.837, respectively (FIGS. 2 and 4). And 5). That is, the semiconductor wafers of Examples 1 to 3 have a strain relaxation rate (R TOP ) of 0.8 or more. In contrast, the semiconductor wafers of Comparative Examples 1 and 2 have strain relaxation rates (R TOP ) of 0.464 and 0.431, respectively, which are smaller than those of the semiconductor wafers of Examples 1 to 3 (see FIG. 6 and 7).
 また、実施例1及び2のIII族窒化物半導体層の平均格子歪み(3.97×10-4,4.96×10-4)は、条件1と条件2の双方を満足することにより、比較例のIII族窒化物半導体層の平均格子歪みの4分の1以下である。このことは、第1バッファ層の平均格子歪みを小さくすることにより、III族窒化物半導体層が歪みを内在したまま成長することを抑制し、歪み誘因ステップバンチングの発生を抑制することができることを示している。すなわち、第1バッファ層の平均格子歪みが多層バッファ層のなかで最大であると、III族窒化物半導体層が歪みを引き継いだ状態で成長し易くなる。 In addition, the average lattice strain (3.97 × 10 −4 , 4.96 × 10 −4 ) of the group III nitride semiconductor layers of Examples 1 and 2 satisfies both Condition 1 and Condition 2, It is one quarter or less of the average lattice strain of the Group III nitride semiconductor layer of the comparative example. This means that by reducing the average lattice strain of the first buffer layer, the group III nitride semiconductor layer can be prevented from growing with inherent strain, and the occurrence of strain-induced step bunching can be suppressed. Show. That is, when the average lattice strain of the first buffer layer is the largest among the multilayer buffer layers, the group III nitride semiconductor layer is likely to grow in a state where the strain is inherited.
 上記したように、実施例1と3は、III族窒化物半導体層より上層の構造が等しい。実施例1と3は、条件2を満足するか否かが相違している。実施例1と3についてX線半値幅の比較を行ったところ、螺旋成分転位に関係する004回折半値幅は、各々390sec(実施例1),470sec(実施例3)であった。また、刃状成分転位の情報を含む114回折半値幅は、各々540sec(実施例1)、740sec(実施例3)であった。条件1と2の双方を満足することにより、X線半値幅が狭く、結晶性が良くなることを示している。特に、刃状転位密度は、実施例1は実施例3の1/2~1/3程度に抑制されていた。このことは、条件1と2の双方を満足することにより、界面格子歪みは大きいが、平均格子歪みの小さい第1バッファ層が形成され、第1バッファ層内で大きな歪み緩和が起こり、その過程で逆極性のバーガースベクトルを有する刃状転位が対消滅したためと考えられる。条件1と2の双方を満足することにより、転位密度の低減効果があることも示された。なお、逆極性のバーガースベクトルを有する転位の対消滅が起こる場合、第1バッファ層は成長温度で圧縮歪みであり、室温において残留する歪みは圧縮または無歪みである。すなわち、室温において、第1バッファ層には、少なくとも引っ張り歪みは残留していない。 As described above, Examples 1 and 3 have the same structure in the upper layer than the group III nitride semiconductor layer. Example 1 and 3 differ in whether condition 2 is satisfied. When the X-ray half widths of Examples 1 and 3 were compared, the 004 diffraction half widths related to the helical component dislocation were 390 sec (Example 1) and 470 sec (Example 3), respectively. In addition, the 114 diffraction half widths including information on the edge component dislocations were 540 sec (Example 1) and 740 sec (Example 3), respectively. When both conditions 1 and 2 are satisfied, the X-ray half width is narrow and the crystallinity is improved. In particular, the edge dislocation density was suppressed to about ½ to 3 of Example 3 in Example 1. This is because, when both conditions 1 and 2 are satisfied, a first buffer layer having a large interface lattice strain but a small average lattice strain is formed, and a large strain relaxation occurs in the first buffer layer. This is probably because the edge dislocations having the Burgers vector of opposite polarity disappeared. It was also shown that there is an effect of reducing the dislocation density by satisfying both conditions 1 and 2. When dislocation pair annihilation having a reverse polarity Burgers vector occurs, the first buffer layer is compressive strain at the growth temperature, and the strain remaining at room temperature is either compression or no strain. That is, at least a tensile strain does not remain in the first buffer layer at room temperature.
 半導体ウエハの反りは、III族窒化物半導体層の「歪み」と「膜厚」の積に応じて変化する。すなわち、III族窒化物半導体層の歪みが大きいと、僅かな膜厚の変化によって半導体ウエハの反り量が大きく変化する。そのため、III族窒化物半導体層が歪みを内在したまま成長すると、半導体ウエハの反り量を制御することが困難になる。本明細書で開示する技術によると、III族窒化物半導体層が歪みを内在したまま成長することを抑制されるので、膜厚に誤差が生じても、バッチ間の反り量のばらつきを抑制することができる。半導体ウエハ1は、反り量の制御のロバスト性を向上させることもできる。 The warpage of the semiconductor wafer changes according to the product of the “strain” and the “film thickness” of the group III nitride semiconductor layer. That is, when the strain of the group III nitride semiconductor layer is large, the amount of warpage of the semiconductor wafer greatly changes due to a slight change in film thickness. Therefore, when the group III nitride semiconductor layer grows with inherent strain, it becomes difficult to control the amount of warpage of the semiconductor wafer. According to the technology disclosed in this specification, the group III nitride semiconductor layer is prevented from growing with inherent strain, so even if an error occurs in the film thickness, variation in the amount of warpage between batches is suppressed. be able to. The semiconductor wafer 1 can also improve the robustness of warpage control.
 なお、上記実施例では、式2及び式3を用いて多層バッファ層の各層のAl組成(x)を算出した。しかしながら、Al組成(x)は、バッファ層の断面についてカソードルミネッセンス測定(CL測定)を行い、バンド端発光ピークEGap (eV)から光学的に求めることもできる。すなわち、バンド端発光ピークEGap(eV)を測定し、下記式(8)の「x」を算出することにより、Al組成(x)を求めることができる。なお、下記式の「b」は、ボーイングパラメータと呼ばれ、例えばb=0.82eVが用いられる。ボーイングパラメータについては、(T.Onuma et.al., J.Appl.Phys.95, 2495 (2004))に開示されている。
式(8):EGap (x)=3.4×(1-x)+6.2×x-b×x×(1-x)
 また、多層バッファ層にAlN/GaN等の多層周期構造を用いる場合の平均組成xは、AlN/GaNの膜厚比を断面TEM(Transmission Electron Microscope)等で求めることによって算出することができる。また、AlN/AlGaN、AlGa1-xN/AlGa1-yNを含む多層周期構造の場合、CL測定により各層のAl組成(x)を算出し、断面TEMによる膜厚測定を組み合わせることにより平均Al組成(x)に換算することができる。
In the above example, the Al composition (x) of each layer of the multilayer buffer layer was calculated using Equations 2 and 3. However, for the Al composition (x), the cathodoluminescence measurement (CL measurement) is performed on the cross section of the buffer layer, and the band edge emission peak EGap is measured.   It can also be obtained optically from (eV). That is, the Al composition (x) can be obtained by measuring the band edge emission peak EGap (eV) and calculating “x” in the following formula (8). In addition, “b” in the following formula is called a bowing parameter, and for example, b = 0.82 eV is used. The bowing parameters are disclosed in (T. Onuma et.al., J. Appl. Phys. 95, 2495 (2004)).
Formula (8): EGap   (X) = 3.4 × (1−x) + 6.2 × x−b × xx × (1−x)
The average composition x when a multilayer periodic structure such as AlN / GaN is used for the multilayer buffer layer can be calculated by obtaining the AlN / GaN film thickness ratio by a cross-sectional TEM (Transmission Electron Microscope) or the like. Further, AlN / AlGaN, the case of a multilayer periodic structure comprising Al x Ga 1-x N / Al y Ga 1-y N, and calculates the respective layers of the Al composition (x) by CL measurement, the film thickness measurement by cross-sectional TEM By combining, it can be converted into an average Al composition (x).
 また、上記実施例では、多層バッファ層が4層又は5層の半導体ウエハについて説明した。しかしながら、多層バッファ層は、少なくとも2層(III族窒化物半導体層に接する第1バッファ層と、第1バッファ層に接する第2バッファ層)存在すればよい。また、多層バッファ層が6層以上である構造も取り得る。なお、多層バッファ層にAlN/GaN等の多層周期構造が用いられている場合であって、多層バッファ層内において層の周期・膜厚比が異なる場合、周期・膜厚比が一定の領域ごとに多層バッファ層を仮想的に分割し、仮想的に分割した層における平均格子定数a’(j=TOP,i)を各バッファ層j(j=TOP,i)とすることができる。また、上記したように、バッファ層内の一部の層が組成傾斜層である場合、その組成傾斜層内の平均格子定数でa’(j=TOP,i)を決定することができる。 In the above embodiment, a semiconductor wafer having four or five multilayer buffer layers has been described. However, the multilayer buffer layer may be present in at least two layers (a first buffer layer in contact with the group III nitride semiconductor layer and a second buffer layer in contact with the first buffer layer). Further, a structure having six or more multilayer buffer layers may be taken. In addition, when a multilayer periodic structure such as AlN / GaN is used for the multilayer buffer layer, and the layer period / film thickness ratio is different in the multilayer buffer layer, for each region where the period / film thickness ratio is constant The multilayer buffer layer is virtually divided, and the average lattice constant a ′ j (j = TOP, i) in the virtually divided layer can be defined as each buffer layer j (j = TOP, i). Further, as described above, when a part of the buffer layer is a composition gradient layer, a ′ j (j = TOP, i) can be determined by the average lattice constant in the composition gradient layer.
 上記実施例では、III族窒化物半導体層の表面にi型の半導体機能層を設ける例について説明したが、さらに、n型又はp型の不純物を含む層を設けることもできる。また、ヘテロ接合を構成する場合、InNとの混晶のヘテロ接合が含まれる構造も取り得る。 In the above embodiment, the example in which the i-type semiconductor functional layer is provided on the surface of the group III nitride semiconductor layer has been described. However, a layer containing an n-type or p-type impurity can also be provided. Further, when a heterojunction is formed, a structure including a heterojunction of a mixed crystal with InN can be taken.
 本開示は、実施例に準拠して記述されたが、本開示は当該実施例や構造に限定されるものではないと理解される。本開示は、様々な変形例や均等範囲内の変形をも包含する。加えて、様々な組み合わせや形態、さらには、それらに一要素のみ、それ以上、あるいはそれ以下、を含む他の組み合わせや形態をも、本開示の範疇や思想範囲に入るものである。 Although the present disclosure has been described based on the embodiments, it is understood that the present disclosure is not limited to the embodiments and structures. The present disclosure includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, as well as other combinations and forms including only one element, more or less, are within the scope and spirit of the present disclosure.

Claims (10)

  1.  基板と、
     基板上に多層バッファ層を介して設けられたIII族窒化物半導体層とを備え、
     前記多層バッファ層は、少なくとも第1バッファ層と第2バッファ層を含んでおり、
     前記第1バッファ層は、前記III族窒化物半導体層に接しており、
     前記第2バッファ層は、前記第1バッファ層に接しており、前記第1バッファ層とは組成が異なり、
     前記多層バッファ層の平均格子定数が、前記III族窒化物半導体層より小さく、
     前記III族窒化物半導体層と前記第1バッファ層との界面における前記III族窒化物半導体層の界面格子歪みが、前記第1バッファ層と前記第2バッファ層の界面における前記第1バッファ層の界面格子歪みより小さい半導体ウエハ。
    A substrate,
    A group III nitride semiconductor layer provided on the substrate via a multilayer buffer layer,
    The multilayer buffer layer includes at least a first buffer layer and a second buffer layer;
    The first buffer layer is in contact with the group III nitride semiconductor layer;
    The second buffer layer is in contact with the first buffer layer and has a composition different from that of the first buffer layer.
    The multilayer lattice layer has an average lattice constant smaller than that of the group III nitride semiconductor layer,
    Interfacial lattice distortion of the group III nitride semiconductor layer at the interface between the group III nitride semiconductor layer and the first buffer layer is caused by the first buffer layer at the interface between the first buffer layer and the second buffer layer. A semiconductor wafer smaller than the interfacial lattice strain.
  2.  前記多層バッファ層の各層において、平均格子歪みが最も大きい層が前記第1バッファ層以外の層である請求項1に記載の半導体ウエハ。 2. The semiconductor wafer according to claim 1, wherein, in each of the multilayer buffer layers, the layer having the largest average lattice strain is a layer other than the first buffer layer.
  3.  前記第1バッファ層は、前記第2バッファ層に対してコヒーレントではない状態である請求項1又は2に記載の半導体ウエハ。 The semiconductor wafer according to claim 1 or 2, wherein the first buffer layer is not coherent with the second buffer layer.
  4.  前記第1バッファ層の前記第2バッファ層に対する歪み緩和率が、0.8以上である請
    求項3に記載の半導体ウエハ。
    The semiconductor wafer according to claim 3, wherein a strain relaxation rate of the first buffer layer with respect to the second buffer layer is 0.8 or more.
  5.  前記第1バッファ層は、AlGa1-xN(0<x<0.2)で示される窒化物半導体である請求項1から4のいずれか一項に記載の半導体ウエハ。 5. The semiconductor wafer according to claim 1, wherein the first buffer layer is a nitride semiconductor represented by Al x Ga 1-x N (0 <x <0.2).
  6.  前記III族窒化物半導体層のc軸が、成長面の垂線に対して傾斜している請求項1から5のいずれか一項に記載の半導体ウエハ。 The semiconductor wafer according to claim 1, wherein a c-axis of the group III nitride semiconductor layer is inclined with respect to a normal to the growth surface.
  7.  前記III族窒化物半導体層は単層であり、その材料が窒化ガリウムである請求項1から6のいずれか一項に記載の半導体ウエハ。 The semiconductor wafer according to claim 1, wherein the group III nitride semiconductor layer is a single layer and the material thereof is gallium nitride.
  8.  前記III族窒化物半導体層は、III族元素の組成が異なる複数の層を備えており、
     前記複数の層のうち、前記第1バッファ層に接する層の材料が窒化ガリウムである請求項1から6のいずれか一項に記載の半導体ウエハ。
    The group III nitride semiconductor layer includes a plurality of layers having different compositions of group III elements,
    The semiconductor wafer according to any one of claims 1 to 6, wherein a material of a layer in contact with the first buffer layer among the plurality of layers is gallium nitride.
  9.  前記基板の材料が、シリコンである請求項1から8のいずれか一項に記載の半導体ウエハ。 The semiconductor wafer according to any one of claims 1 to 8, wherein a material of the substrate is silicon.
  10.  基板と、
     基板上に多層バッファ層を介して設けられたIII族窒化物半導体層とを備え、
     そのIII族窒化物半導体層の表面側に半導体素子が形成されており、
     前記多層バッファ層は、少なくとも第1バッファ層と第2バッファ層を含んでおり、
     前記第1バッファ層は、前記III族窒化物半導体層に接しており、
     前記第2バッファ層は、前記第1バッファ層に接しており、前記第1バッファ層とは組成が異なり、
     前記多層バッファ層の平均格子定数が、前記III族窒化物半導体層より小さく、
     前記III族窒化物半導体層と前記第1バッファ層との界面における前記III族窒化物半導体層の界面格子歪みが、前記第1バッファ層と前記第2バッファ層の界面における前記第1バッファ層の界面格子歪みより小さい半導体装置。
     
    A substrate,
    A group III nitride semiconductor layer provided on the substrate via a multilayer buffer layer,
    A semiconductor element is formed on the surface side of the group III nitride semiconductor layer,
    The multilayer buffer layer includes at least a first buffer layer and a second buffer layer;
    The first buffer layer is in contact with the group III nitride semiconductor layer;
    The second buffer layer is in contact with the first buffer layer and has a composition different from that of the first buffer layer.
    The multilayer lattice layer has an average lattice constant smaller than that of the group III nitride semiconductor layer,
    Interfacial lattice distortion of the group III nitride semiconductor layer at the interface between the group III nitride semiconductor layer and the first buffer layer is caused by the first buffer layer at the interface between the first buffer layer and the second buffer layer. A semiconductor device smaller than the interfacial lattice strain.
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