JP2004235473A - Compound semiconductor element and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a compound semiconductor element structure wherein crystal defects are reluctant to occur along the boundary between a buffer zone and a semiconductor element layer and wherein high-quality element layers are realized with stability, and to provide a method for manufacturing the same. <P>SOLUTION: For the heteroepitaxial growth of a semiconductor element layer 50 constituted of In<SB>x</SB>Ga<SB>y</SB>Al<SB>1-x-y</SB>N on a single crystal substrate 1 of SiC, sapphire, or silicon, an Al<SB>1-a</SB>In<SB>a</SB>N layer is used as a buffer layer 2 wherein the mixed crystal ratio a of InN is higher on the side of the boundary with the semiconductor layer 50 than on the side of the boundary with the single crystal substrate 1. By adjusting the mixed crystal ratio a of InN whose lattice constant is larger than that of GaN, the lattice constant of the buffer layer 2 is made to be nearer to the lattice constant of the semiconductor element layer 50 on the side of the boundary with the semiconductor element layer 50, as compared with a conventional buffer layer constituted of GaN, AlN, or their combination. On the side of the boundary with the single crystal substrate 1, difference in lattice constant from that of the single crystal substrate 1 is effectively reduced by lowering the mixed crystal ratio a of InN. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a compound semiconductor device and a method for manufacturing the same.
[0002]
[Prior art]
[Patent Document 1]
JP-A-5-110138 [Patent Document 2]
JP-A-5-206513
As is well known, a multi-layer structure of a compound semiconductor is applied to ultra-high-speed transistors such as MESFET (Metal-Semiconductor Field Transistor) and HEMT (High Electron Mobility Transistor), and light-emitting elements such as light-emitting diodes and lasers. Has been earned. As a semiconductor multilayer structure that has been receiving attention in recent years, there is a heterojunction structure using a GaN-based compound semiconductor. GaN-based compound semiconductors can be changed in bandgap at room temperature from 2.0 eV to 6.2 eV and are chemically stable, so that they are applied to light-emitting elements such as blue light and are becoming popular. In addition, the GaN-based compound-based semiconductor has a wide band gap, high electron mobility, and easy heterojunction formation, so that it can be operated in a high-temperature environment, and has a higher speed and higher output. Its application to next-generation ultra-high-speed transistors has also attracted attention and has been studied.
[0004]
Unlike a GaAs-based compound, it is difficult to manufacture a semi-insulating single-crystal substrate that enables homoepitaxial growth of a GaN-based compound-based semiconductor. Single crystal substrates and sapphire (single crystal alumina) substrates are used. At this time, GaN (Patent Document 1) or AlN is grown as a buffer layer on a single crystal substrate, and then the element layer is heteroepitaxially grown to improve the quality of the element layer.
[0005]
[Problems to be solved by the invention]
In heteroepitaxial growth of a GaN-based compound semiconductor, the lattice constant difference between GaN and SiC or sapphire used as a single crystal substrate is very large (about 5% for SiC and about 15% for sapphire). Therefore, a high-quality device layer cannot be stably manufactured unless the buffer layer used for growth can absorb or reduce the lattice constant difference. In addition, since the difference in linear expansion coefficient between the single crystal substrate and the compound semiconductor layer is large (especially when an insulating sapphire substrate is used), the generation and growth of crystal defects are further promoted by the thermal stress derived from this. Care must be taken, as they tend to be susceptible.
[0006]
Conventionally, GaN, which has been used as a material for the buffer layer, has a large lattice constant difference from the substrate, so that crystal defects tend to occur near the boundary between the buffer layer and the substrate. On the other hand, although the lattice constant difference between AlN and the substrate is smaller than that of GaN, the lattice mismatch ratio between the AlN and the element layer made of a GaN-based compound semiconductor increases. Crystal defects easily occur in the layer. As disclosed in Patent Document 2, a method using a buffer layer in which a GaN layer and an AlN layer are alternately stacked or a buffer layer made of a mixed crystal of GaN and AlN is also conceivable. As long as the combination with AlN is used, generation of crystal defects due to lattice mismatch between the buffer layer and the element layer is inevitable.
[0007]
An object of the present invention is to provide a semiconductor device structure and a method of manufacturing the same, which are less likely to generate crystal defects at the boundary between the buffer layer and the device layer, and can stably realize a high-quality device layer.
[0008]
[Means for Solving the Problems and Functions / Effects]
In order to solve the above problems, a compound semiconductor device of the present _invention, from the _{In x Ga y Al 1-x} -y N ( However, 0 ≦ x <1,0 ≦ y ≦ 1,0 <x + y ≦ 1) comprising a semiconductor element layer is at least partially interval _Al 1-a _in a N layer thickness direction (a is InN mixed crystal ratio, 0 <a <1) via a buffer layer and AlInN layer made of a single It is characterized by being epitaxially grown on a crystal substrate. By growing a semiconductor element layer using such a buffer layer, a high-quality element layer having a low crystal defect density can be stably realized.
[0009]
The AlInN layer in the buffer layer can be formed so that the InN mixed crystal ratio a is larger at the boundary side with the semiconductor element layer than at the boundary side with the single crystal substrate, and the semiconductor layer is formed via the buffer layer. The element layer can be epitaxially grown on a single crystal substrate made of any of SiC, sapphire, and silicon.
[0010]
According to the above configuration, SiC, when to hetero-epitaxially growing a semiconductor element layer formed of sapphire and an In x _Ga either become more single crystal substrate of silicon _{y Al 1-x-y N} , the boundary between the semiconductor element layer The Al _1-a In _a N layer formed so that the InN mixed crystal ratio a is higher on the side than on the boundary side with the single crystal substrate is used as a buffer layer. InN has a larger lattice constant than GaN, and the InN mixed crystal ratio a is adjusted to make the buffer at the boundary side with the semiconductor element layer, as compared with the conventional buffer layer of GaN, AlN, or a combination thereof. The lattice constant of the layer can be made closer to the lattice constant of the semiconductor element layer. As a result, crystal defects hardly occur at the boundary between the buffer layer and the element layer, and a high-quality element layer can be stably realized. In particular, when a SiC single crystal substrate is used, the difference in lattice constant between the buffer layer and the single crystal substrate can be effectively reduced by reducing the substrate side InN mixed crystal ratio a.
[0011]
_{In x Ga y Al 1-x} -y N semiconductor device layer of the, InN mixed crystal ratio x, by adjusting the GaN mole fraction y and AlN mixed crystal ratio 1-x-y, the lattice constant and band gap energy Can be adjusted to a desired value. For example, in a HEMT structure using a GaN-based compound, many attempts have been made to form a two-dimensional electron gas layer by hetero-junctioning a GaN channel layer with an n-type doped GaAlN electron supply layer. Further, the electron supply layer may be formed as an InGaAlN layer in order to further improve lattice matching with the GaN channel layer.
[0012]
In the case where the semiconductor element layer has an InN mixed crystal ratio x, a GaN mixed crystal ratio y, and an AlN mixed crystal ratio 1-xy adjusted such that the lattice constant difference from GaN is within ± 1%. (For example, in the case of a GaN channel layer, y = 1 and x = 0). In the AlInN layer in the buffer layer, the portion including the boundary with the semiconductor element layer has an InN mixed crystal ratio a of 0.1 or more and 0 or less. By using Al _1-a In _a N adjusted to be .25 or less, the semiconductor element layer and the lattice constant can be substantially matched at the boundary. As a result, generation of crystal defects near the boundary between the buffer layer and the semiconductor element layer can be more effectively prevented.
[0013]
The AlInN layer in the buffer layer is formed such that the InN mixed crystal ratio a increases stepwise (preferably three or more steps) or continuously from the boundary on the single crystal substrate side to the boundary on the semiconductor element layer side. It is desirable. By doing so, the lattice constant of the buffer layer gradually increases from the single crystal substrate side to the semiconductor element layer side in the layer thickness direction, and the lattice constant does not increase discontinuously largely in the middle. As a result, stress based on a change in lattice constant hardly concentrates at a specific position in the thickness direction of the buffer layer, and the occurrence of crystal defects can be more effectively prevented.
[0014]
In the present invention, a buffer layer having an AlInN layer can be used to improve the crystallinity of the semiconductor element layer. In this case, the AlInN layer may be amorphous.
[0015]
Further, the method of manufacturing a compound semiconductor device of the present invention,
Epitaxially growing a buffer layer on the single crystal substrate, the buffer layer being an AlInN layer in which at least a part of the layer thickness direction is Al _1-a In _a N (a is an InN mixed crystal ratio, 0 <a <1). ,
_{In x Ga y Al 1-x} -y N ( However, 0 ≦ x <1,0 ≦ y ≦ 1,0 <x + y ≦ 1) semiconductor element layer consisting of the steps of epitaxially grown on the buffer layer,
It is characterized by including. By growing a semiconductor element layer using such a buffer layer, a compound semiconductor element having a high-quality element layer with a low crystal defect density can be easily and stably manufactured.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 shows an example in which the semiconductor device of the present invention is configured as a HEMT. In the HEMT 200, a semiconductor element layer 103 is formed on a single crystal substrate 101 made of SiC via a buffer layer 102 by a heteroepitaxial growth method using a MOVPE method. Note that the single crystal substrate 101 may be a sapphire substrate or a silicon substrate instead of the SiC substrate.
[0017]
The semiconductor element layer 103 functions as a non-doped GaN channel layer 119, a non-doped GaAlN spacer layer 105, a GaAlN electron supply layer 110 doped n-type with Si or the like, and a contact layer with an electrode from the side close to the buffer layer 102. The n-type GaN layers 111 are stacked in this order. Then, a drain electrode 106 and a source electrode 107 are formed on the n-type GaN layer 111, and a gate electrode 108 is formed on the n-type GaAlN layer 110 exposed in a region where the n-type GaN layer 111 is not formed. The drain electrode 106 and the source electrode 107 are made of a metal (for example, Ti / Al) that forms an ohmic junction with the n-type GaN layer 111, and the gate electrode 108 is Schottky-connected to the n-type GaAlN electron supply layer 110. (Schottky) junctions are formed of a metal (for example, Pd / Au). The GaAlN spacer layer 105 is for preventing impurities such as Si, which is an n-type dopant, from diffusing into the GaN channel layer 119 that has already been formed when the n-type GaAlN electron supply layer 110 is grown. .
[0018]
A two-dimensional electron gas (2DEG) layer having high electron mobility is formed between the GaAlN spacer layer 105 and the GaN channel layer 119. Then, a voltage is applied between the drain electrode 106 and the source electrode 107, and while the current value is controlled by the gate electrode 108, a current is applied between the drain electrode 106 and the source electrode 107 via the GaN channel layer 119. Can do it.
[0019]
Next, in the buffer layer 102, at least a portion including a boundary with the semiconductor element layer 103 is set to Al _1−a In _a N (a is an InN mixed crystal ratio, 0 <a <1), and the semiconductor element layer 103 is formed. Is formed such that the InN mixed crystal ratio a is larger at the boundary side with the SiC single crystal substrate 101 than at the boundary side with the SiC single crystal substrate 101. In the present embodiment, as shown in FIG. 2, the InN mixed crystal ratio a is composed of Al _1-a In _a N with a1, a2, ‥, and an (where a1 <a2 <‥ <an). The unit layers 2-1, 2-2,..., 2-n are stacked in this order from the substrate 101 side. Thereby, as shown in FIG. 3, for example, the buffer layer 102 has a semiconductor element layer whose InN mixed crystal ratio a in the layer thickness direction changes from a value a1 (0 in the present embodiment) on the boundary side with the substrate 101. The distribution has a stepwise increasing distribution toward the value an (0.17 in the present embodiment) on the 103 side. The number n of the unit layers is 3 or more, and the thickness of each unit layer is appropriately determined according to the number of the unit layers so that the buffer layer 102 has a thickness of 50 nm to 200 nm, for example.
[0020]
Hereinafter, a method for manufacturing the HEMT 200 will be described. The formation of the buffer layer 102 and the semiconductor element layer 103 can be performed by a known MOVPE method or a vapor phase growth method using an MBE (Molecular Beam Epitaxy) method. When the MOVPE method is employed, the following can be used as a source gas. Ga source: trimethyl gallium (TMGa), triethyl gallium (TEGa), etc. In source: trimethyl indium (TMIn), triethyl indium (TEIn), etc.
-Al source; trimethyl aluminum (TMAl), triethyl aluminum (TEAl), etc .;
· N source: ammonia (NH _3), such as.
The following can be used as the dopant gas serving as the p-type dopant source and the n-type dopant source.
· Mg source: such as biscyclopentadienyl magnesium _(Cp 2 Mg).
-Si source: silicon hydride such as silane;
In this embodiment, Si and Mg are employed as dopant elements, but a group IV element such as C, Ge, and Sn is used as an n-type dopant, and a group II element such as Ca, Sr, and Zn is used as a p-type dopant. Elements can be used.
Each of the above-mentioned source gases is supplied to the inside of the reaction vessel in which the substrate 101 is arranged in a form appropriately diluted with a carrier gas (for example, nitrogen gas).
[0021]
Specifically, buffer layer 102 shown in FIG. 2 is grown on the main surface of SiC single crystal substrate (having a crystal main axis of [0001]) 1 by using the MOVPE method described above. Each of the unit layers 2-1, 2-2,..., 2-n of the buffer layer 102 has a flow rate ratio of an organometallic gas serving as an In source and an Al source for each layer according to the difference in the InN mixed crystal ratio a. , Is controlled by a mass flow controller or the like so as to change stepwise. Note that at least the first one or more layers of the buffer layer 102 may be a polycrystalline layer or an amorphous layer. It is desirable that the last one or more unit layers of the buffer layer 102 be a single crystal suitable for epitaxial growth of the semiconductor element layer 103 (the crystallinity of the unit layer is sequentially improved each time the formation is repeated). Do).
[0022]
From the viewpoint of improving crystallinity, InN is preferably grown at a relatively low temperature (eg, 400 ° C. or more and 900 ° C. or less), and AlN is preferably grown at a relatively high temperature (eg, 900 ° C. or more and 1100 ° C. or less). It has been. Therefore, it is desirable that the buffer layer 2 made of a mixed crystal of the two grows at an intermediate temperature range of 500 ° C. or more and 1000 ° C. or less.
[0023]
Next, when the formation of the buffer layer 102 is completed, the GaN channel layer 119 and the GaAlN spacer layer are continuously adjusted in the reaction vessel by adjusting the flow rate ratio of the source gas and the organic metal gas serving as the dopant gas for each layer. 105, a GaAlN electron supply layer 110 and an n-type GaN layer 111 are sequentially epitaxially grown. Thereafter, part of the n-type GaN layer 111 is partially removed by photolithography or the like, and the gate electrode 108 is formed on the exposed GaAlN electron supply layer 110, and the drain electrode 106 and the source electrode are formed on the remaining n-type GaN layer 111. 107 is formed. Thereafter, dicing is performed with the substrate 101 to form a chip, and resin molding is performed together with a lead frame that is electrically connected to each electrode, thereby forming the final HEMT 200.
[0024]
HEMT200 obtained by the above process, the semiconductor element layer 103, the lattice constant difference between GaN is composed of _{In x Ga y Al 1-x} -y N within 1% ±. Then, the buffer layer 102, the semiconductor element layer 103 and the contact unit layer 2-n (FIG. 2) is, InN mixed crystal ratio a is from 0.1 to 0.25 of _{Al 1-a} In a N. The unit layer 2-n has a lattice constant substantially equal to that of the semiconductor element layer 103, and can effectively prevent generation of crystal defects near a boundary between the buffer layer 102 and the semiconductor element layer 103. Also, the unit layer 2-1 (FIG. 2) of the buffer layer 102 which is in contact with the SiC single crystal substrate 101 is made of Al _1-a In _a N having an InN mixed crystal ratio a of 0, that is, an AlN layer. The difference in lattice constant from the crystal substrate 101 is reduced, and the generation of crystal defects near the boundary with the SiC single crystal substrate 101 can be effectively suppressed.
[0025]
Hereinafter, various modifications of the present invention will be described.
As shown in FIG. 4, the InN mixed crystal ratio a of the buffer layer 102 may change continuously in the layer thickness direction. In order to form such a buffer layer 102, the flow ratio of the organometallic gas serving as an In source and an Al source during growth by MOVPE may be controlled by a mass flow controller or the like so as to be continuously changed.
[0026]
As shown in FIG. 5, the buffer layer 102 has an InN mixed crystal ratio near the boundary with the substrate (single crystal substrate) a1 and an InN mixed crystal ratio near the boundary with the semiconductor element layer an (where As an> a1), the distribution of the InN mixed crystal ratio a in the layer thickness direction increases and decreases from the single crystal substrate side toward the semiconductor element layer side while repeatedly increasing and decreasing with a fluctuation width smaller than an-a1. It can also be formed so as to show a tendency. When a layer having a higher InN mixed crystal ratio is formed on the preceding layer toward the semiconductor element layer side, the lattice constant is increased by the increment of the InN mixed crystal ratio. Stress acts. If the tensile stress level is high, crystal defects such as cracks and peeling are likely to occur between adjacent layers. Therefore, after a layer having a high InN mixed crystal ratio is formed, a layer having a reduced lattice constant and a low InN mixed crystal ratio is grown on the layer. The tensile stress due to the layers is offset, and the generation of crystal defects between the layers can be made more difficult. Specifically, the buffer layer in FIG. 5 has a structure in which a plurality of unit layers each having a constant InN mixed crystal ratio are stacked in such a manner that the InN mixed crystal ratio alternately increases and decreases toward the semiconductor element layer side. It has become.
[0027]
In the above embodiment, almost all of the buffer layer 2 is configured as an AlInN layer except that the vicinity of the boundary with the substrate 101 is AlN, and the buffer layer 2 is in contact with the semiconductor element layer. Although arranged, as shown in FIG. 6, the buffer layer should be formed as having an auxiliary layer in which a GaN layer and an InGaAlN layer are alternately stacked between an AlInN layer and a semiconductor element layer. You can also. Thereby, it is possible to more effectively prevent a defect that a crystal defect due to lattice mismatch with the substrate occurs in the semiconductor element layer.
[0028]
In the embodiment described above, the compound semiconductor element is configured as a HEMT. However, the present invention can be applied to other ultra-high-speed transistors, such as a MESFET (Metal-Semiconductor Field Effect Transistor) and an HBT (Hetero Bipolar Transistor). You can also. Further, the compound semiconductor element can be configured as a light emitting element as shown in FIG. The light emitting element 1 (shown in schematic cross-section of a main portion) of a sapphire substrate as a single crystal substrate (hereinafter, simply referred to as a substrate) via a buffer layer 2 on the _{1, In x Ga y Al 1} -x- _A semiconductor element layer 50 of yN (where 0 ≦ x <1, 0 ≦ y ≦ 1, 0 <x + y ≦ 1) is formed. This buffer layer 2 has the same configuration as the buffer layer 102 shown in FIG. 2, FIG. 3, FIG. 4 or FIG. The forms the main part of the semiconductor element layer _{50, In a Ga b Al 1-} a-b N active layer (non-doped) 5, p-type _{In x Ga y Al 1-x} -y N cladding layer (p-type dopant for example Mg: hereinafter also referred to as p-type cladding layer) 6 and n-type _{in x Ga y Al 1-x} -y n layer (n-type dopant, for example Si: hereinafter also referred to as n-type cladding layer) sandwich at 4 The light emitting layer portion 24 has a double hetero structure. The p-type cladding layer 6 and the n-type cladding layer 4 are assumed to contain AlN in the present embodiment, and form a potential barrier for the GaN active layer 5 that advantageously acts to confine carriers in the active layer 5. ing.
[0029]
In the present embodiment, light is extracted from the p-type cladding layer 6 side. On the p-type cladding layer 6, a current diffusion layer having a higher p-type dopant concentration than the p-type cladding layer 6 is formed. For example, it is made of GaN: it is regarded as forming a part of the semiconductor element layer 50), and an electrode 9 for driving light emission is provided on the current diffusion layer. On the other hand, between the buffer layer 2 and the n-type cladding layer 4, a backside low-resistance layer having a higher n-type dopant concentration than the n-type cladding layer 4 (for example, made of GaN: a part of the semiconductor element layer 50) 3) are arranged. The back surface low resistance layer 3 extends outward in the in-plane direction of the light emitting layer portion 24 on the main surface of the substrate 1, and a light emitting drive electrode 15 is provided in the extended region.
[0030]
Further, in the light emitting element 100 of FIG. 7, the sapphire substrate 1 is taken in as a part of the element structure. However, the insulating sapphire substrate 1 is peeled off, and an electrode is provided on the peeling surface side of the light emitting layer portion. The formed element structure can also be used.
[0031]
Further, instead of the sapphire substrate 1, a SiC substrate may be used. Since the SiC substrate has high conductivity, the backside low-resistance layer 3 is omitted, while the electrode 15 is provided on the backside of the SiC substrate, and the conduction for light emission drive is performed in such a manner that a conduction path is formed in the thickness direction of the SiC substrate. It is possible to do.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view schematically showing a HEMT which is an example of a compound semiconductor device of the present invention.
FIG. 2 is a schematic cross-sectional view showing details of a buffer layer of the HEMT of FIG. 1;
FIG. 3 is a schematic diagram showing the distribution of the InN mixed crystal ratio in the thickness direction of the buffer layer of FIG. 2;
FIG. 4 is a schematic diagram showing a first modification of the distribution of the InN mixed crystal ratio of the buffer layer in the layer thickness direction.
FIG. 5 is a schematic diagram showing a second modification of the distribution of the InN mixed crystal ratio in the buffer layer in the thickness direction of the buffer layer.
FIG. 6 is a schematic view showing still another modified example of the buffer layer.
FIG. 7 is a cross-sectional view schematically showing a light-emitting element which is another example of the compound semiconductor element of the present invention.
[Explanation of symbols]
1 Sapphire substrate (single crystal substrate)
2 Buffer layers 50 and 103 Semiconductor element layer 100 Light emitting element (compound semiconductor element)
101 SiC single crystal substrate 200 HEMT (compound semiconductor device)

Claims (6)

_{In x Ga y Al 1-x} -y N ( However, 0 ≦ x <1,0 ≦ y ≦ 1,0 <x + y ≦ 1) semiconductor element layer of the at least some sections of the layer thickness direction Al _{1 -A} In _a N (a is an InN mixed crystal ratio, 0 <a <1) A compound semiconductor element which is epitaxially grown on a single crystal substrate via a buffer layer which is an AlInN layer. The AlInN layer in the buffer layer is formed such that the InN mixed crystal ratio a is larger on the boundary side with the semiconductor element layer than on the boundary side with the single crystal substrate, and through the buffer layer. 2. The compound semiconductor device according to claim 1, wherein said semiconductor device layer is epitaxially grown on said single crystal substrate made of one of SiC, sapphire and silicon. The semiconductor element layer has an InN mixed crystal ratio x, a GaN mixed crystal ratio y, and an AlN mixed crystal ratio 1-xy adjusted so that a lattice constant difference from GaN is within ± 1%. ,
In the AlInN layer in the buffer layer, a portion including a boundary with the semiconductor element layer is made of Al _1-a In _a N in which the InN mixed crystal ratio a is adjusted to 0.1 or more and 0.25 or less. The compound semiconductor device according to claim 2, wherein: 3. The AlInN layer in the buffer layer, wherein the InN mixed crystal ratio a increases stepwise or continuously from the boundary on the single crystal substrate side to the boundary on the semiconductor element layer side. Or the compound semiconductor device according to 3. The AlInN layer in the buffer layer has an InN mixed crystal ratio near the boundary on the single crystal substrate side as an, and an InN mixed crystal ratio near the boundary on the semiconductor element layer side as a1 (where an> a1). The distribution of the InN mixed crystal ratio a in the layer thickness direction shows an increasing tendency from the single crystal substrate side to the semiconductor element layer side while repeatedly increasing and decreasing with a fluctuation width smaller than an-a1. The compound semiconductor device according to any one of claims 2 to 4, wherein Epitaxially growing a buffer layer on the single crystal substrate, wherein at least a part of the layer in the layer thickness direction is an AlInN layer in which Al _1-a In _a N (a is an InN mixed crystal ratio, 0 <a <1). ,
_{In x Ga y Al 1-x} -y N ( However, 0 ≦ x <1,0 ≦ y ≦ 1,0 <x + y ≦ 1) and the step of the semiconductor element layer made of epitaxially grown on the buffer layer,
A method for manufacturing a compound semiconductor device, comprising:

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