JP2006347786A - Group iii nitride semiconductor substrate and manufacturing method of group iii nitride semiconductor substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a group III nitride semiconductor substrate capable of reducing the generation of crack at an Al<SB>b</SB>Ga<SB>1-b</SB>N (0<b≤1)layer on the substrate surface and reducing a dislocation density and to provide a manufacturing method of the group III nitride semiconductor substrate. <P>SOLUTION: The group III nitride semiconductor substrate 1 is provided with a mask 19 formed on a ground substrate 10, a first layer 11 composed of Al<SB>a</SB>Ga<SB>1-a</SB>N (0≤a<1) and having a constant composition (a), a second layer 12 formed on the first layer 11 and a third layer 13 composed of Al<SB>b</SB>Ga<SB>1-b</SB>N (0<b≤1) having a constant composition (b). The first layer 11 fills the inside of an opening part 191 of the mask 19 and also covers the upper surface of a coated part 192. The second layer 12 is composed of Al<SB>x</SB>Ga<SB>1-x</SB>N (0<x<1), and a composition (x) changes along the thickness direction of the layer, and a composition (x) of the surface in contact with the third layer 13 has a composition distribution in which the composition (x) of the surface side contacting with the third layer 13 is higher than the composition (x) of the surface side contacting with the first layer 11. The relation (a)<(x)<(b) is established between the compositions (a), (b) and (x). <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a group III nitride semiconductor substrate and a method for manufacturing a group III nitride semiconductor substrate.

In recent years, group III nitride semiconductor substrates have been used for blue LEDs, short wavelength LDs, ultraviolet LEDs, white LEDs, and the like, and the market is on an expanding trend.
Conventionally, a GaN substrate has been used as a group III nitride semiconductor substrate. However, when an element structure including an AlGaN layer is formed on the GaN substrate, distortion may occur in the AlGaN layer due to the difference between the lattice constant of the GaN substrate and the lattice constant of the AlGaN layer. For example, when a laser structure is formed on a GaN substrate, an AlGaN layer having a high Al composition may be used as the cladding layer. This is because the light confinement effect can be improved by using an AlGaN layer having a high Al composition as the cladding layer.
In this case, the difference in lattice constant between the AlGaN layer and the GaN substrate becomes large, and there is a high possibility that a large strain will occur in the AlGaN layer.
Therefore, it is desired to use an AlGaN substrate containing Al instead of the conventional GaN substrate.

Here, a conventional typical AlGaN substrate manufacturing method will be described with reference to FIG. A GaN buffer layer 21 of about 1 μm is grown on the sapphire substrate 20 by metal organic vapor phase epitaxy (hereinafter referred to as MOCVD) or molecular beam epitaxy (MBE), and an AlGaN layer 22 of about 0.1 to 2 μm is formed thereon. Growing directly (see Patent Document 1). The AlN composition of the AlGaN layer 22 is in the range of 0.3 to 0.5, and the AlN composition in the AlGaN layer 22 is constant.
JP 2003-192896 A

However, it has been clarified that the following problems arise when the present inventors produce an AlGaN substrate by the conventional method of directly forming the AlGaN layer 22 on the GaN buffer layer 21.
That is, it has been found that when the AlGaN layer of the AlGaN substrate has a thickness of 2 μm or more, array-like cracks are generated at a high density on the surface. It was also revealed that array-like cracks are likely to occur even when the AlN composition exceeds 0.1. Note that the array-like cracks generated in the AlGaN substrate are different from the cracks in the GaN substrate.
Furthermore, it has also been clarified that the AlGaN layer of the AlGaN substrate manufactured by the conventional method has a high dislocation density.
It is considered that good device characteristics cannot be obtained when a laser structure or the like is formed on a substrate having an AlGaN layer with many cracks and a high dislocation density.

The present invention has been made in view of the above circumstances, and its object is to reduce the occurrence of cracks in the Al _b Ga _1-b N (0 <b ≦ 1) layer on the substrate surface, Furthermore, it is possible to provide a group III nitride semiconductor substrate and a method for manufacturing a group III nitride semiconductor substrate that can reduce the dislocation density in the Al _b Ga _1-b N (0 <b ≦ 1) layer on the substrate surface. It is in.

As a result of intensive studies, the inventor has greatly influenced the occurrence of array-like cracks in the AlGaN layer of the conventional AlGaN substrate by the difference in the thermal expansion coefficient and the lattice constant between the GaN buffer layer and the AlGaN layer. I guessed that.
Tensile stress is generated due to the difference in thermal expansion coefficient between the GaN buffer layer and the AlGaN layer. It is considered that this tensile stress greatly affects the generation of array-like cracks in the AlGaN layer.
Further, it is considered that a large strain is generated in the AlGaN layer due to a difference in lattice constant between the GaN buffer layer and the AlGaN layer, and this strain is also considered to have a great influence on the generation of array-like cracks.
Furthermore, as a result of intensive studies, the present inventor has presumed that the dislocation density of the AlGaN layer of the AlGaN substrate is increased due to threading dislocations.
The present invention is based on such knowledge estimation.

According to the present invention, the insulating film in which the opening is formed, and Al _a Ga _1-a N (0 ≦ a <1) having a constant composition a are embedded in the opening of the insulating film, A first layer covering the insulating film, a second layer formed on the first layer, and Al _b Ga _1-b N (0 <b) having a constant composition b formed on the second layer. A third layer constituted by ≦ 1);
The second layer is composed of an Al _x Ga _1-x N (0 <x <1) layer, the composition x changes in the layer thickness direction, and the composition x of the surface in contact with the third layer is A group III nitride having a composition distribution higher than the composition x of the surface in contact with the first layer, and a relation of a <x <b is established in the compositions a, b, and x A physical semiconductor substrate is provided.

  Here, in the second layer of the present invention, the composition x on the surface in contact with the third layer only needs to be higher than the composition x on the surface in contact with the first layer. That is, in the second layer of the present invention, the composition x may have a composition distribution in which the value of the composition x simply increases from the first layer side toward the third layer side. The composition distribution may be such that after increasing toward the third layer side, it decreases once and then increases again.

Furthermore, in the present invention, the first layer composed of Al _a Ga _1-a N (0 ≦ a <1) may be a buffer layer grown at a low temperature, and is a base substrate of a group III nitride semiconductor substrate. There may be.
Further, in the present invention, the composition a of the first layer is assumed to be constant, but the term “constant” referred to here is a concept including fluctuation within a range of −10% to + 10% with respect to the composition a, − Any variation within the range of 10% to + 10% is considered constant. Similarly, in the third layer, the fact that the composition b is constant is a concept including fluctuation within a range of −10% to + 10% with respect to the composition b.

In the present invention, the second layer is provided between the first layer and the third layer. Since this second layer is composed of Al _x Ga _1-x N (0 <x <1) in which the composition x changes in the layer thickness direction, the thermal expansion between the first layer and the third layer The difference in coefficients can be reduced. Thereby, the tensile stress applied to the third layer can be reduced, and the occurrence of array-like cracks in the third layer can be reduced.

In addition, since the second layer is composed of Al _x Ga _1-x N (0 <x <1) in which the composition x changes in the layer thickness direction, the second layer is between the first layer and the third layer. The difference in lattice constant can also be reduced. Since distortion based on the difference in lattice constant is less likely to occur in the third layer, the occurrence of array-like cracks in the third layer can be reliably reduced.

Further, when manufacturing the group III nitride semiconductor substrate of the present invention, an insulating film is formed on the base substrate, and the first layer is grown from the opening of the insulating film. By forming the insulating film on the base substrate, threading dislocations do not propagate to at least a portion of the first layer formed on the insulating film. Thereby, propagation of threading dislocations to the second layer and the third layer formed above the first layer can be reduced, and the dislocation density of the third layer can be reduced.
Here, the growth method of the first layer is not particularly limited. For example, the first layer may be grown by an ELO (epitaxial lateral overgrowth) method, or may be grown by a FIELO (facet-initiated epitaxial lateral overgrowth) method. Also good.
When the first layer is grown by the FIELO method, the first layer grows while forming a structure having a facet surface inclined with respect to the base substrate. And the propagation of threading dislocations to the upper second layer and third layer can be effectively suppressed.
Thereby, it is possible to reliably reduce the dislocation density of the third layer.

According to the present invention, there is also provided a method for producing a group III nitride semiconductor substrate, the step of forming an insulating film having an opening formed on a base substrate, and a composition a constant from the opening of the insulating film. Forming a first layer by growing an Al _a Ga _1-a N (0 ≦ a <1) layer, and Al _x Ga _{1− having} a composition x larger than the composition a on the first layer. growing a second layer composed of _{x N (0 <x <1} ), the second layer on, the composition b is constant and the composition b is larger than the composition x Al _b Ga _{1 -B} N (0 <b ≦ 1) is grown, and in the step of growing the second layer, the composition x changes in the layer thickness direction and contacts the third layer. It is characterized by growing a second layer having a composition distribution in which the surface composition x is higher than the surface composition x in contact with the first layer. A method for producing a group III nitride semiconductor substrate can also be provided.

According to the present invention, generation of cracks in the Al _b Ga _1-b N (0 <b ≦ 1) layer on the substrate surface can be reduced, and further, Al _b Ga _1-b N (0 < A group III nitride semiconductor substrate capable of reducing the dislocation density in the b ≦ 1) layer and a method for manufacturing the group III nitride semiconductor substrate are provided.

The group III nitride semiconductor substrate of the present invention may include a base substrate.
The insulating film may be directly formed on the base substrate, a buffer layer may be formed on the base substrate, and the insulating film may be formed on the buffer layer.
By forming the buffer layer on the base substrate, the crystallinity of the first to third layers formed on the buffer layer can be further enhanced.

In the present invention, the insulating film includes a plurality of insulating film portions arranged in a dot shape at a predetermined arrangement pitch, or a plurality of insulating film portions arranged in a stripe shape at a predetermined arrangement pitch. May be from 2 to 15 μm.
Here, the arrangement pitch of the insulating film portions refers to the distance between the midpoints of the widths of the pair of insulating film portions adjacent along the arrangement direction. Note that the width of the insulating film portion is the width in the arrangement direction of the plurality of insulating film portions.
By setting the arrangement pitch of the insulating film portions to 2 to 15 μm, the first layer with high crystallinity can be formed.

Furthermore, in the present invention, the insulating film is preferably made of silicon oxide or silicon nitride.
Among them, the insulating film is preferably composed of a workable SiO _2.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

FIG. 1 shows a cross-sectional view of a group III nitride semiconductor substrate 1 of the present embodiment.
The group III nitride semiconductor substrate 1 includes a base substrate 10, a GaN buffer layer B formed on the base substrate 10, a mask (insulating film) 19 formed on the GaN buffer layer B, and Al _a Ga _{1 -A} N (0 ≦ a <1), the first layer 11 having a constant composition a, the second layer 12 formed on the first layer 11, and the second layer 12 formed. And a third layer 13 composed of Al _b Ga _1-b N (0 <b ≦ 1) having a constant composition b.

The first layer 11 grows from the opening 191 of the mask 19 and fills the inside of the opening 191 of the mask 19 and covers the upper surface of the covering portion 192 of the mask 19.
The second layer 12 is made of Al _x Ga _1-x N (0 <x <1), the composition x changes in the layer thickness direction, and the composition x on the surface in contact with the third layer 13 is the first layer 11. The composition distribution is higher than the composition x of the surface in contact with the surface. In the compositions a, b, and x, the relationship a <x <b is established.

Hereinafter, the configuration of the group III nitride semiconductor substrate 1 will be described in more detail.
The base substrate 10 is preferably a single crystal substrate, for example, a sapphire substrate, a silicon carbide (SiC) substrate, a silicon (Si) substrate, a gallium arsenide (GaAs) substrate, or a gallium phosphide (GaP) substrate.

Among these, it is preferable to use a sapphire substrate as the base substrate 10. This is because the sapphire substrate is inexpensive and has good quality. Moreover, it is preferable to use a sapphire substrate also on the point that a good quality nitride epitaxial layer (the 1st layer 11-the 3rd layer 13) can be formed on a sapphire substrate. When the first layer 11 or the like is formed on such a sapphire substrate, the off-angle is on the (0001) c plane, (11-20) a plane, or (10-10) m plane of the sapphire substrate. A plane that is 0-10 ° is selected. Of these, a (0001) c plane with an off angle of 0.1 to 1 ° is more preferable.
Further, a GaN substrate may be used as the base substrate 10.

  The GaN buffer layer B is formed by metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), HVPE, or the like. The GaN buffer layer B is grown at a low temperature of 400 to 650 ° C. A GaN layer grown at a high temperature of 1000 to 1200 ° C. may be formed on the GaN buffer layer B. The layer thickness of the GaN buffer layer B may be 0.01 μm to 50 μm, and preferably 0.05 to 20 μm. Considering the growth time, it is particularly preferably 0.05 to 3 μm.

The mask 19 is formed on the GaN buffer layer B. As shown in FIG. 2, the mask 19 is formed between a plurality of covering portions (insulating film portions) 192 that cover the GaN buffer layer B and the covering portion 192. And an opening 191.
FIG. 2 is a plan view showing a state in which the mask 19 is formed on the GaN buffer layer B. FIG.
The thickness of the mask 19 is 0.01 to 5 μm. The mask 19 is an insulating film containing Si as a constituent element. The mask 19 is preferably made of SiO ₂ or SiN _x . In particular, the mask 19 is particularly preferably made of SiO ₂ from the viewpoint of ease of processing.
The mask 19 may have a single layer configuration or a multilayer configuration.

Each covering portion 192 has a substantially rectangular shape in plan and has the same size and shape. The covering portions 192 are arranged in the form of dots at predetermined intervals along the <10-10> direction of the sapphire substrate as the base substrate 10 and the direction orthogonal to the <10-10> direction of the sapphire substrate. Yes.
Two opposing sides of the covering portion 192 are along the <10-10> direction of the sapphire substrate, and the other two opposing sides of the covering portion 192 are in a direction orthogonal to the <10-10> direction of the sapphire substrate. Along.
The arrangement pitches P1 and P2 of the covering portion 192 are 2 to 15 μm, and preferably 3 to 11 μm. The crystallinity of the first layer 11 can be improved by setting the arrangement pitches P1 and P2 to 3 to 11 μm.
The width W1 of the covering portion 192 with respect to the arrangement pitch P1 is preferably 30 to 70% of the arrangement pitch. Further, the width W2 of the covering portion 192 with respect to the arrangement pitch P2 is preferably 30 to 70% of the arrangement pitch P2. The first layer 11 with good crystallinity can be formed by setting the widths W1 and W2 of the covering portion 192 to 30 to 70% of the arrangement pitches P1 and P2.
Here, the arrangement pitch P1 refers to the distance between the midpoints of the width W1 of the adjacent covering portions 192, and the arrangement pitch P2 refers to the distance between the midpoints of the width W2 of the adjacent covering portions 192.
Further, the cross-sectional shape in the <10-10> direction of the sapphire substrate of the covering portion 192 and the cross-sectional shape in the direction orthogonal to the <10-10> direction of the sapphire substrate are not particularly limited, but are rectangular. Examples include a trapezoidal shape.

  The openings 191 extend in a direction perpendicular to the <10-10> direction of the sapphire substrate and the <10-10> direction of the sapphire substrate, and are formed in a lattice shape. The GaN buffer layer B is exposed from the opening 191.

With reference to FIG. 1 again, the first layer 11 to the third layer 13 will be described.
The first layer 11 is composed of Al _a Ga _1-a N (0 ≦ a <1), and the composition a is constant. The first layer 11 is an epitaxial growth layer.
Here, the first layer 11 is preferably a GaN layer with a = 0. This is because the initial growth of the GaN layer is stable. In general, since the substrate on which a GaN layer of 0.01 to 10 μm is grown on the surface is often used as the base substrate 10, the first layer 11 is preferably a GaN layer.

  The layer thickness of the first layer 11 is 0.01 to 100 μm. Especially, it is preferable that it is 1 micrometer or more. This is because, in the epitaxial growth, crystallinity is improved when grown to 1 μm or more. Moreover, it is preferable that the 1st layer 11 is 20 micrometers or less. This is because if the first layer 11 exceeds 20 μm, the cost is increased and cracks may occur in the first layer 11.

The second layer 12 is an epitaxially grown layer and is Al _x Ga _1-x N (0 <x <1). In the second layer 12, an array-like crack is generated.
The second layer 12 has a composition distribution in which the composition x changes in the layer thickness direction, and the composition x on the surface in contact with the third layer 13 is higher than the composition x on the surface in contact with the first layer 11.
In the present embodiment, the composition x of the second layer 12 increases stepwise from the first layer 11 toward the third layer 13 over five steps. In the present embodiment, the second layer 12 has a five-layer configuration (layers 121 to 125). For example, it is possible to adopt a configuration in which the composition x of each of the layers 121 to 125 increases from the first layer 11 side to the third layer 13 side by 0.1. The layer 121 on the first layer 11 side is Al _0.2 Ga _0.8 N, the layer 122 is Al _0.3 Ga _0.7 N, the layer 123 is Al _0.4 Ga _0.6 N, and the layer 124 is Al _{0. .5} Ga _0.5 N, the layer 125 can be Al _0.6 Ga _0.4 N.
The composition x of the layer 125 in contact with the third layer 13 is preferably 30% or more of the composition b of Al _b Ga _1-b N (0 <b ≦ 1) of the third layer 13.

Here, in order to increase the composition x stepwise, when the second layer 12 is formed, the ratio of the Al source gas supply amount and the Ga source gas supply amount may be changed.
In addition, when the composition x of the second layer 12 is increased stepwise, the second layer 12 has a multilayer structure, and the second layer 12 is preferably 2 layers or more and 30 layers or less. In consideration of the quality and cost of the crystal, it is more preferably 2 layers or more and 15 layers or less.
Moreover, it is preferable that the thickness of each layer which comprises the 2nd layer 12 is 0.2-50 micrometers.
The layer thickness of the entire second layer 12 is preferably 2 to 100 μm, but considering costs and the like, it is more preferably 3 to 50 μm, and particularly preferably 3 to 25 μm.
By setting the layer thickness of the second layer 12 to 3 μm or more, array-like cracks on the surface of the third layer 13 can be reliably reduced.

The third layer 13 is a layer formed by epitaxial growth, and is an Al _b Ga _1-b N (0 <b ≦ 1) layer having a constant composition b.
The composition b of Al _b Ga _1-b N in the third layer 13 is preferably 0.1 ≦ b ≦ 1. Therefore, the third layer 13 may be AlN.
Furthermore, it is more preferable that 0.3 ≦ b ≦ 1, and it is particularly preferable that 0.5 ≦ b ≦ 1.

The layer thickness of the third layer 13 is preferably more than 3 μm. Even if misfit dislocation occurs at the interface between the third layer 13 and the second layer 12, if the layer thickness of the third layer 13 exceeds 3 μm, the misfit reaches the surface of the third layer 13. Defects resulting from dislocations can be reduced.
Furthermore, the crack of the second layer 12 can be prevented from propagating to the surface of the third layer 13 by making the layer thickness of the third layer 13 exceed 3 μm.
In addition, the crack of the second layer 12 is more reliably prevented from propagating to the surface of the third layer 13, and further, defects caused by misfit dislocations reaching the surface of the third layer 13 are reliably reduced. For this purpose, the thickness of the third layer 13 is preferably 5 μm or more. Considering the growth stability and cost of the third layer 13, the layer thickness of the third layer 13 is 5 to 300 μm, more preferably 5 to 50 μm.

  The group III nitride semiconductor substrate 1 as described above can be used as a substrate for a light emitting diode or a semiconductor laser. For example, a laser structure such as an n-type cladding layer, an active layer, a p-type cladding layer, and an electrode can be formed on the group III nitride semiconductor substrate 1 to constitute a semiconductor laser.

Such a group III nitride semiconductor substrate 1 can be manufactured as follows.
First, the GaN buffer layer B is formed on the base substrate 10 at 400 to 700 ° C. (more preferably 450 to 600 ° C.) by HVPE (Hydride Vapor Phase Epitaxy) method.
In order to form a high-quality GaN buffer layer B, the surface of the base substrate 10 may be cleaned at 900 to 1200 ° C. before the GaN buffer layer B is formed. Although the temperature at the time of cleaning should just be 900-1200 degreeC, if it is 1000 degreeC or more, cleaning can be aimed at reliably.

Next, a mask 19 is formed on the GaN buffer layer B. Specifically, an SiO ₂ film that covers the upper surface of the GaN buffer layer B is formed, and a resist mask is formed on the SiO ₂ film. This resist mask has the same pattern as the mask 19. When the base substrate 10 on which the resist mask is formed is immersed in an etching solution, the SiO ₂ film exposed from the opening of the resist mask is removed, and a mask 19 is formed.

Next, gallium chloride (GaCl) and ammonia (NH ₃ ), or gallium chloride (GaCl), aluminum chloride (AlCl ₃ ), and ammonia (NH ₃ ) are used as raw materials, and the opening 191 of the mask 19 is formed by the HVPE method. The first layer 11 is grown. The first layer 11 grows laterally so as to cover the covering portion 192, and unites on the covering portion 192. Then, the mask 19 is completely embedded by the first layer 11.

Next, the second layer 12 is formed by adjusting the supply amount of GaCl and AlCl ₃ . Further, the third layer 13 is formed by adjusting the supply amount of GaCl and AlCl ₃ .
The GaN buffer layer B and the first layer 11 to the third layer 13 are not necessarily manufactured by the HVPE method. For example, the GaN buffer layer B is formed on the base substrate 10 by the MOCVD method, and further, the HVPE method is used. Thus, the first layer 11 to the third layer 13 may be formed.
In addition, if each layer 11-13 is formed by HVPE method, it is possible to increase the layer thickness of each layer 11-13.

Below, the effect of the group III nitride semiconductor substrate 1 is demonstrated.
In the present embodiment, the second layer 12 is provided between the first layer 11 and the third layer 13. Second layer 12, the composition x is changed in the layer thickness direction, the third layer 13 composition x of the surface in contact with the first layer of composition distribution is higher than the amount x of the surface in contact with the 11 Al _x Ga _{1 -X} N (0 <x <1). The second layer 12 can alleviate the difference in thermal expansion coefficient between the first layer 11 and the third layer 13. Therefore, the tensile stress applied to the third layer 13 can be reduced, and the occurrence of array-like cracks in the third layer 13 can be reduced.
In addition to this, by providing the second layer 12, the difference in lattice constant between the first layer 11 and the third layer 13 can be reduced. Since distortion based on the difference in lattice constant is less likely to occur in the third layer 13, the generation of array-like cracks in the third layer 13 can be reliably reduced.

In the group III nitride semiconductor substrate 1 of the present embodiment, the second layer 12 reduces the difference in thermal expansion coefficient and the difference in lattice constant between the first layer 11 and the third layer 13, and the second layer 12. The occurrence of cracks in the third layer 13 can be reduced due to the defects generated therein.
That is, in the second layer 12, since the composition x of Al _x Ga _1-x N (0 <x <1) changes in the layer thickness direction, some defects may occur due to misfit dislocations. . In particular, in the present embodiment, since the composition distribution is such that the composition x increases stepwise, in the second layer 12, a composition discontinuous surface in which the composition x changes rapidly can be formed. It becomes possible to cause defects.
When stress is applied to the second layer 12 due to a difference in thermal expansion coefficient between the first layer 11 to the third layer 13 and a difference in lattice constant, a large number of cracks are formed on the composition discontinuous surface due to the defects of the second layer 12. appear. Due to the presence of cracks in the second layer 12, the tensile stress applied to the third layer 13 is reduced, and the generation of array-like cracks on the surface of the third layer 13 can be further reduced.
Moreover, since defects and cracks occur on the composition discontinuous surface of the second layer 12, even if misfit dislocation occurs between the first layer 11 and the second layer 12, the composition discontinuous surface of the second layer 12. The propagation of misfit dislocations is hindered by defects and cracks. Thereby, generation | occurrence | production of the array-like crack in the 3rd layer surface can be reduced reliably.

When the composition b of Al _b Ga _1-b N in the third layer 13 is 0.1 or more, if the third layer 13 is formed directly on the first layer 11 as in the prior art, the third layer 13 In this embodiment, since the second layer 12 is provided, even if the composition b of the third layer 13 is 0.1 or more, the third layer 13 has an array of cracks. Almost never occurs.

Furthermore, in this embodiment, since the value of the composition x of the layer 125 in contact with the third layer 13 of the second layer 12 is 30% or more of the composition b of the third layer 13, the second layer 12 and the third layer Thus, the difference in lattice constant and the difference in thermal expansion coefficient generated with respect to 13 can be reduced.
Thereby, generation | occurrence | production of the array-shaped crack by the 3rd layer 13 by the difference in the lattice constant of the 2nd layer 12 and the 3rd layer 13 can be reduced. Moreover, the tensile stress produced by the difference of the thermal expansion coefficient of the 2nd layer 12 and the 3rd layer 13 can be made small, and generation | occurrence | production of the array-like crack in the 3rd layer 13 can be reduced.

  In the present embodiment, the first layer is grown from the opening 191 of the mask 19. By forming the mask 19 on the base substrate 10, the propagation of threading dislocations generated at the interface between the base substrate 10 and the GaN buffer layer B is inhibited by the covering portion 192 of the mask 19. Thereby, the threading dislocations propagated to the second layer 12 and further to the third layer 13 formed above the first layer 11 can be reduced, and the third layer 13 having a low dislocation density can be formed. It becomes possible.

As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable.
For example, in the above-described embodiment, the GaN buffer layer B is formed between the base substrate 10 and the first layer 11. However, the present invention is not limited thereto, and for example, an AlN buffer layer may be formed.
Alternatively, the first layer 11 may be formed directly on the base substrate 10 without forming the GaN buffer layer B. Furthermore, the first layer may be grown at a low temperature to form a buffer layer.

  In the embodiment, the first layer 11 to the third layer 13 are formed on the base substrate 10. However, a GaN substrate is used as the first layer 11, and the second layer and the third layer are formed on the GaN substrate. It may be formed.

In the above embodiment, the second layer 12 has a multilayer structure, and the composition x of Al _x Ga _1-x N (0 <x <1) extends from the first layer 11 to the third layer 13 over two or more stages. Although it is assumed to increase stepwise, it is not limited to this.
For example, as shown in FIGS. 3A and 3B, the second layer 12 may have a single-layer configuration, and the composition x may gradually increase from the first layer 11 toward the third layer 13.
Furthermore, the composition x may increase linearly from the first layer 11 toward the third layer 13.

Moreover, as shown in FIG. 4, after the composition x increases from the first layer side toward the third layer side, the composition x may once decrease and then increase again.
Furthermore, in the said embodiment, although the group III nitride semiconductor substrate 1 shall be provided with the base substrate 10, it is good not only as this but the structure which does not have the base substrate 10. FIG. For example, the first to third layers may be formed on the base substrate, and the base substrate may be separated from the interface between the first layer and the base substrate by etching or the like.

Moreover, in the said embodiment, although the 1st layer 11 grew from the opening part 191 of the mask 19 and was grown in the horizontal direction so that the coating | coated part 192 was covered, the growth aspect of the 1st layer 11 is not restricted to this. Absent.
When the planar polygonal covering portions are arranged in a dot shape, the first layer may grow as follows by adjusting various conditions.
When forming the first layer, various conditions are adjusted (for example, the first layer is formed by the HVPE method, and the V / III ratio, which is the ratio between the supply amount of NH ₃ gas and the supply amount of HCl gas, is adjusted. By setting it to 30 or more, the three-dimensional nucleus of the first layer can be formed at the corner of the covering portion. Using this three-dimensional nucleus as a reference, a first layer extends in the opening and covering of the mask, and a structure having a facet surface inclined with respect to the substrate surface of the base substrate is formed.
When the growth of the first layer is continued, the structures grown from the corners of the covering portion of the mask are united at substantially the center of the upper surface of the covering portion of the mask. Further, the structures are united at substantially the center of the portion surrounded by the covering portion of the opening.
Furthermore, if the growth of the first layer is continued, the first layer completely fills the opening and the covering portion of the mask.

  Thus, when the first layer grows while the first layer forms a structure having a facet surface that is inclined with respect to the base substrate, the threading dislocation that has passed through the opening of the mask is the facet surface. Bending and propagation of threading dislocations to the upper second layer and third layer can be effectively suppressed. Thereby, generation | occurrence | production of the crystal defect in a 3rd layer can be prevented reliably.

  Furthermore, in the said embodiment, two opposing sides of the covering part 192 of the mask 19 are along the <10-10> direction of the sapphire substrate which is the base substrate 10, and the other two opposing sides of the covering part 192 are Although the direction is perpendicular to the <10-10> direction of the sapphire substrate, the direction of the sides of the covering portion 192 of the mask 19 is not limited to this. For example, the two opposing sides of the covering portion 192 may be along the <1-100> direction of the sapphire substrate, and the other two opposing sides may be along the <11-20> direction of the sapphire substrate. In this case, the opening 191 extends along the <1-100> direction of the sapphire substrate and the <11-20> direction of the sapphire substrate.

  As described above, when the two opposing sides of the covering portion 192 are along the <1-100> direction of the sapphire substrate, and the other two opposite sides are along the <11-20> direction of the sapphire substrate. The first layer 11 may grow as follows.

A structure having a facet surface {1-101} inclined with respect to the substrate surface of the sapphire substrate is formed from a portion of the opening 191 along the <1-100> direction of the sapphire substrate, and the first layer 11 is formed. Grow.
On the other hand, the first layer 11 grows laterally from the portion of the opening 191 along the <11-20> direction of the sapphire substrate, and the cross-sectional shape along the <1-100> direction of the sapphire substrate is T. A letter-shaped first layer 11 grows. These first layers 11 are combined on the covering portion 192, and the mask 19 is completely embedded by the first layer 11.
Also in this case, the first layer 11 grows while forming a structure having a facet surface inclined with respect to the base substrate 10, so that threading dislocations that have passed through the opening 191 of the mask 19 are bent at the facet surface. The propagation of threading dislocations to the upper second layer 12 and third layer 13 can be effectively suppressed. Thereby, generation | occurrence | production of the crystal defect in the 3rd layer 13 can be prevented reliably.

Furthermore, in the embodiment, the shape of the covering portion 192 is a planar rectangular shape, but the shape of the covering portion is not limited to this, and for example, a planar triangular shape, a planar hexagonal shape, and a planar circular shape Also good.
Moreover, in the said embodiment, although the mask 19 in which the coating | coated part 192 was arrange | positioned at dot shape was used, it is not restricted to this, For example, as shown in FIG. 5, the mask 39 by which the coating | coated part 392 was arrange | positioned at stripe form is used. May be used. The mask 39 is formed by alternately arranging planar rectangular covering portions 392 and planar rectangular opening portions 391. The longitudinal direction of the covering portion 392 is preferably a direction along the <1-100> direction of the base substrate (sapphire substrate). By disposing the covering portion 392 in this manner, the first layer 11 can be grown while forming a structure having a facet surface.
The arrangement pitch of the covering portions 392 of the mask 39 is preferably 2 to 15 μm.

(Example)
In this example, the group III nitride semiconductor substrate having the structure shown in FIG. 1 was manufactured by the HVPE method.
First, high purity gallium (Ga) was filled in a quartz Ga source boat of an HVPE apparatus, and high purity aluminum (Al) was filled in an Al source boat made of alumina. Then, a Ga source boat and an Al source boat were respectively arranged in a predetermined arrangement in a horizontal quartz reactor.

  A sapphire substrate was used as the base substrate. As the sapphire substrate, a sapphire substrate having a diameter of 2 inches and having a (0001) c plane and a surface displaced by 0.25 ° in the (10-10) direction was used. A GaN buffer layer having a thickness of 2 μm is previously formed on the sapphire substrate by metal organic vapor phase epitaxy.

A mask similar to that of the above embodiment was formed on the GaN buffer layer on the sapphire substrate. The mask is a SiO ₂ film, and a plurality of covering portions are arranged in a dot shape in the direction perpendicular to the <10-10> direction of the sapphire substrate and the <10-10> direction of the sapphire substrate, as in the above embodiment. Yes.
The arrangement pitch of the covering portions in the <10-10> direction of the sapphire substrate is 7 μm, and the arrangement pitch in the direction orthogonal to the <10-10> direction of the sapphire substrate is also 7 μm. Further, the width of the opening in the <10-10> direction of the sapphire substrate and the width of the sapphire substrate in the direction orthogonal to the <10-10> direction were both 4 μm.
Furthermore, the coating | coated part is a planar substantially rectangular shape, and the 2 sides which oppose are along the <10-10> direction of a sapphire substrate. Further, the other two sides facing the covering portion are along a direction orthogonal to the <10-10> direction of the sapphire substrate.

  Next, the sapphire substrate on which the mask was formed was placed on the holder of the HVPE apparatus and rotated.

In the following description, SCCM, which is a unit converted to a standard state, is used as a unit of gas supply amount.
Nitrogen (N ₂ ) gas was supplied into the reactor to replace the air in the reactor, and then N ₂ gas was supplied at 10,000 SCCM. And the inside of a reactor was heated with the heater. The heating method here is a so-called hot wall method in which the outer wall of the reactor is heated by a heater.
NH ₃ gas was introduced at 3000 SCCM to prevent dissociation of GaN on the surface of the GaN buffer layer. After confirming that the temperatures of the Al source boat, Ga source boat, and sapphire substrate were maintained at 500 ° C., 800 ° C., and 1050 ° C., respectively, vapor phase growth of the first layer was started.

First, NH ₃ gas was supplied onto the sapphire substrate at 1500 SCCM. Next, without changing the flow rate of NH ₃ , HCl gas was supplied to the Ga source boat at 50 SCCM to generate GaCl at 50 SCCM. This GaCl was supplied onto the sapphire substrate on which the mask was formed. GaCl was supplied for 10 minutes. Thereby, the 1st layer which is a GaN layer was formed. The first layer is an epitaxially grown layer.

Next, without changing the supply amounts of NH ₃ gas and GaCl gas, HCl gas is supplied to the Al source boat to generate AlCl ₃ , and this AlCl ₃ is supplied onto the sapphire substrate on which the first layer is formed. did. The supply amount of AlCl ₃ was increased stepwise to grow the second layer.
Specifically, the supply amount of HCl gas was 30 SCCM (AlCl ₃ supply amount 10 SCCM), and the supply was performed for 2 minutes.
Next, the supply amount of HCl gas was set to 60 SCCM (AlCl ₃ supply amount 20 SCCM), and the supply was performed for 2 minutes.

Further, the supply amount of HCl gas was 90 SCCM (AlCl ₃ supply amount 30 SCCM), and the supply was performed for 2 minutes.
Next, the supply amount of HCl gas was set to 120 SCCM (AlCl ₃ supply amount 40 SCCM), and the supply was performed for 2 minutes.
Further, the supply amount of HCl gas was 150 SCCM (AlCl ₃ supply amount 50 SCCM), and the supply was continued for 2 minutes.
From the above, a second layer consisting of five layers was formed.

Next, without changing the supply amount of NH ₃ gas and the supply amount of GaCl gas, the supply amount of HCl gas supplied to the Al source boat is 180 SCCM (AlCl ₃ supply amount 60 SCCM), and is supplied for 30 minutes. A layer was formed.
The layer thicknesses of the first layer, the second layer, and the third layer thus formed were 17 μm, 8 μm, and 28 μm, respectively.

  The diffraction peak angle of each layer was determined by 2θ-ω measurement using a Philips X-ray diffractometer Xpert-MRD, and the composition of the first to third layers was determined from the lattice constant.

In general, the lattice constant d (c) of Al _c Ga _1-c N having the composition c can be obtained based on the difference between the lattice constant of AlN of 0.4981 nm and the lattice constant of GaN of 0.5185 nm. The following relationship holds between the lattice constant d (c), the lattice constant of AlN, and the lattice constant of GaN.
d (c) = 0.4981 + (0.5185-0.4981) × (1-c) (Formula 1)
When the composition b of the third layer was determined based on this formula 1, b = 0.72.
Moreover, when the composition of each layer of the second layer was determined based on Formula 1, Al _0.06 Ga _0.94 N, Al _0.15 Ga _0.85 N, Al _{0. 23} Ga _0.77 N, Al _0.29 Ga _0.71 N, and Al _0.38 Ga _0.62 N.

When the surface of the third layer of the manufactured group III nitride semiconductor substrate was observed with an optical microscope, it was confirmed that there was no occurrence of array-like cracks as shown in FIG.
Since the base substrate of the group III nitride semiconductor substrate is a colorless and transparent sapphire substrate, the first layer is observed from the back side of the group III nitride semiconductor substrate with an optical microscope as shown in FIG. It was also confirmed that array-like cracks occurred in the second layer.
It was confirmed that array-like cracks occurred in the first layer and the second layer, but did not reach the surface of the third layer.
Further, the dislocation density of the group III nitride semiconductor substrate was determined by counting the dark spots from the cathode luminescence (CL) image having an emission wavelength of 220 or 360 nm at an electron beam acceleration voltage of 5 kV and an observation magnification of 10,000 times. The dislocation density of the group III nitride semiconductor substrate was 8 × 10 ⁸ cm ⁻² .

(Comparative example)
A GaN buffer layer, a first layer, and a third layer were formed on a sapphire substrate having the GaN layer formed on the surface (the same sapphire substrate used in the examples).
The method for forming the GaN buffer layer, the first layer, and the third layer is the same as in the example. The comparative example is different from the example in that the second layer is not formed between the first layer and the third layer and the mask is not formed.
In the comparative example, the layer thickness of the first layer was 18 μm, and the layer thickness of the third layer was 29 μm.

The diffraction peak angle of each layer was determined by 2θ-ω measurement using a Philips X-ray diffractometer Xpert-MRD, and the composition was calculated from the lattice constant in the same manner as in the example. The composition b of the third layer was 0.7. It was.
When the surface of the third layer was observed with a microscope, it was confirmed that an array of cracks had occurred as shown in FIG. This crack was generated at a high density on the surface of the third layer.
Moreover, when the dislocation density was calculated | required by the method similar to an Example, the dislocation density in a comparative example was 5 * 10 ^{< 9} > cm ^<-2> .

It is a figure which shows the structure of the group III nitride semiconductor substrate concerning embodiment of this invention, and the ratio of Al composition of a group III nitride semiconductor substrate. It is a top view which shows the mask of the group III nitride semiconductor substrate of the said embodiment. (A) is a figure which shows the structure of the group III nitride semiconductor substrate concerning the modification of this invention, and the ratio of Al composition of a group III nitride semiconductor substrate. (B) is a figure which shows the structure of the group III nitride semiconductor substrate concerning the other modification of this invention, and the ratio of Al composition of a group III nitride semiconductor substrate. It is a figure which shows the structure of the group III nitride semiconductor substrate concerning the modification of this invention, and the ratio of Al composition of a group III nitride semiconductor substrate. It is a top view which shows the mask of the modification of this invention. It is a figure which shows the microscope picture (observation magnification 200 times) of the 3rd layer surface in an Example. It is a figure which shows the micrograph (observation magnification 200 times) of the 1st layer and the 2nd layer in which the crack generate | occur | produced in the Example. It is a figure which shows the microscope picture (observation magnification 200 times) of the surface of the 3rd layer of a comparative example. It is a figure which shows the structure of the conventional AlGaN substrate.

Explanation of symbols

1 Group III Nitride Semiconductor Substrate 10 Base Substrate 11 First Layer 12 Second Layer 13 Third Layer 19 Mask 20 Sapphire Substrate 21 Buffer Layer 22 AlGaN Layer 39 Mask 121 Layer 122 Layer 123 Layer 124 Layer 125 Layer 191 Opening 192 Covering Portion 391 Opening 392 Covering portion B Buffer layer W1 Width W2 Width P1 Arrangement pitch P2 Arrangement pitch

Claims (6)

An insulating film having an opening formed therein;
A first layer composed of Al _a Ga _1-a N (0 ≦ a <1) having a constant composition a, filling the inside of the opening of the insulating film and covering the insulating film;
A second layer formed on the first layer;
A third layer formed on the second layer and composed of Al _b Ga _1-b N (0 <b ≦ 1) having a constant composition b;
With
The second layer is composed of an Al _x Ga _1-x N (0 <x <1) layer, the composition x changes in the layer thickness direction, and the composition x of the surface in contact with the third layer is the first Having a composition distribution that is higher than the composition x of the surface in contact with the layer;
A group III nitride semiconductor substrate, wherein a relation of a <x <b is established in the compositions a, b, and x. In the group III nitride semiconductor substrate according to claim 1,
With a base substrate,
A group III nitride semiconductor substrate, wherein the insulating film is formed on the base substrate. In the group III nitride semiconductor substrate according to claim 2,
A buffer layer formed on the base substrate;
A group III nitride semiconductor substrate, wherein the insulating film is formed on the buffer layer. In the group III nitride semiconductor substrate according to any one of claims 1 to 3,
The insulating film includes a plurality of insulating film portions arranged in a dot shape at a predetermined arrangement pitch, or a plurality of insulating film portions arranged in a stripe shape at a predetermined arrangement pitch,
The group pitch of the group III nitride semiconductor substrate, wherein the array pitch is 2 to 15 μm. In the group III nitride semiconductor substrate according to any one of claims 1 to 4,
The group III nitride semiconductor substrate, wherein the insulating film is made of silicon oxide or silicon nitride. A method for manufacturing a group III nitride semiconductor substrate, comprising:
Forming an insulating film having an opening formed on a base substrate;
A step of growing an Al _a Ga _1-a N (0 ≦ a <1) layer having a constant composition a from the opening of the insulating film to form a first layer;
Growing a second layer composed of Al _x Ga _1-x N (0 <x <1) having a composition x larger than the composition a on the first layer;
Growing a third layer composed of Al _b Ga _1-b N (0 <b ≦ 1) having a constant composition b and a composition b larger than the composition x on the second layer; Including
In the step of growing the second layer, the composition x changes in the layer thickness direction, and the composition x on the surface in contact with the third layer has a composition distribution that is higher than the composition x on the surface in contact with the first layer. A method of manufacturing a group III nitride semiconductor substrate, comprising growing two layers.