JP4055763B2 - Gallium nitride compound semiconductor and semiconductor substrate - Google Patents
Gallium nitride compound semiconductor and semiconductor substrate Download PDFInfo
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本発明は、新規な製造方法により製造される一般式Alx Gay In1-x-y N(0 ≦x ≦1,0 ≦y ≦1,0 ≦x+y ≦1)の窒化ガリウム系化合物半導体及び窒化ガリウム系化合物半導体基板に関する。特に、基板上に横方向エピタキシャル成長（ＥＬＯ）を用いて成長させた窒化ガリウム系化合物半導体及び窒化ガリウム系化合物半導体基板に関する。 The present invention relates to a gallium nitride-based compound semiconductor having a general formula of Al x Ga y In 1-xy N (0 ≦ x ≦ 1,0 ≦ y ≦ 1,0 ≦ x + y ≦ 1) manufactured by a novel manufacturing method And a gallium nitride compound semiconductor substrate. In particular, the present invention relates to a gallium nitride compound semiconductor and a gallium nitride compound semiconductor substrate grown by lateral epitaxial growth (ELO) on the substrate.
窒化ガリウム系化合物半導体は、発光スペクトルが紫外から赤色の広範囲に渡る直接遷移型の半導体であり、発光ダイオード(LED) やレーザダイオード(LD)等の発光素子に応用されている。この窒化ガリウム系化合物半導体では、通常、サファイア上に形成している。 Gallium nitride compound semiconductors are direct-transition semiconductors whose emission spectrum covers a wide range from ultraviolet to red, and are applied to light-emitting elements such as light-emitting diodes (LEDs) and laser diodes (LDs). The gallium nitride compound semiconductor is usually formed on sapphire.
しかしながら、上記従来技術では、サファイア基板上に窒化ガリウム系化合物半導体を形成すると、サファイアと窒化ガリウム系化合物半導体との熱膨張係数差により、半導体層にクラック、そりが発生し、ミスフットにより転位が発生し、このため素子特性が良くないという問題がある。 However, in the above prior art, when a gallium nitride compound semiconductor is formed on a sapphire substrate, cracks and warpage occur in the semiconductor layer due to a difference in thermal expansion coefficient between sapphire and the gallium nitride compound semiconductor, and dislocation occurs due to a misfoot. For this reason, there is a problem that the device characteristics are not good.
従って、本発明の目的は、上記課題に鑑み、クラック、転位のない窒化ガリウム系半導体層を形成することで、素子特性を向上させると共に、効率のよい製造方法を実現することである。 Accordingly, an object of the present invention is to realize an efficient manufacturing method while improving element characteristics by forming a gallium nitride-based semiconductor layer free from cracks and dislocations in view of the above problems.
上記の課題を解決するために、請求項１に記載の発明は、基板と、基板上に形成され、基板の露出部の幅を１μｍ〜１０μｍとし、幅が１μｍ〜１０μｍのストライプ状又は格子状の島状態に形成された第１の窒化ガリウム系化合物半導体と、第１の窒化ガリウム系化合物半導体の上に形成され、第１の窒化ガリウム系化合物半導体と同一パターンの第２の窒化ガリウム系化合物半導体とから成る２層構造と、島状態の第２の窒化ガリウム系化合物半導体を核として成長した、基板の露出部を核としてはエピタキシャル成長しておらず且つ基板の露出面とは化学的に接合していない、基板の露出面上に横方向成長した第３の窒化ガリウム系化合物半導体とから成ることを特徴とする窒化ガリウム系化合物半導体である。 In order to solve the above-described problems, the invention according to claim 1 is a stripe or grid having a substrate and a width of an exposed portion of the substrate of 1 μm to 10 μm formed on the substrate, and a width of 1 μm to 10 μm. The first gallium nitride compound semiconductor formed in the island state and the second gallium nitride compound formed on the first gallium nitride compound semiconductor and having the same pattern as the first gallium nitride compound semiconductor A two-layer structure composed of a semiconductor and an island-like second gallium nitride compound semiconductor grown as a nucleus, not epitaxially grown using an exposed portion of the substrate as a nucleus, and chemically bonded to the exposed surface of the substrate to not a lateral grown third gallium nitride-based compound semiconductor, characterized in that it consists of a gallium nitride-based compound semiconductor on the exposed surface of the substrate.
尚、ここでいう横方向とは、基板の面方向を意味する。これにより、第３の窒化ガリウム系化合物半導体は、基板の露出部には成長せず、第２の窒化ガリウム系化合物半導体上に３次元的、即、面方向にも成長し、基板の上方向では一様に成長される。この結果、基板と窒化ガリウム系化合物半導体との間のミスフィットに基づく転位は縦方向に成長し、横方向へは成長しない。よって、基板の露出部上の第３の窒化ガリウム系化合物半導体の縦方向の貫通転位はなくなり、第２の窒化ガリウム系化合物半導体の上の部分だけ縦方向の貫通転位が残る。この結果、第３の窒化ガリウム系化合物半導体の縦方向の貫通転位の面密度が極めて減少する。従って、第３の窒化ガリウム系化合物半導体の結晶性が向上する。また、基板の露出部とその上の第３の窒化ガリウム系化合物半導体とは化学的に接合していないので、第３の窒化ガリウム系化合物半導体のそりが防止されると共に応力歪みがその半導体に入ることが抑制される。 Here, the horizontal direction means the surface direction of the substrate. As a result, the third gallium nitride compound semiconductor does not grow on the exposed portion of the substrate, but grows three-dimensionally on the second gallium nitride compound semiconductor in the plane direction, and the upper direction of the substrate. Then it grows uniformly. As a result, dislocations based on misfit between the substrate and the gallium nitride compound semiconductor grow in the vertical direction and do not grow in the horizontal direction. Therefore, the threading dislocations in the vertical direction of the third gallium nitride compound semiconductor on the exposed portion of the substrate disappear, and the threading dislocations in the vertical direction remain only in the portion above the second gallium nitride compound semiconductor. As a result, the surface density of the threading dislocations in the vertical direction of the third gallium nitride compound semiconductor is extremely reduced. Accordingly, the crystallinity of the third gallium nitride compound semiconductor is improved. In addition, since the exposed portion of the substrate and the third gallium nitride compound semiconductor on the substrate are not chemically bonded, warpage of the third gallium nitride compound semiconductor is prevented and stress strain is applied to the semiconductor. Entering is suppressed.
また、請求項２に記載の発明は、第３の窒化ガリウム系化合物半導体と第２の窒化ガリウム系化合物半導体とは同一組成であることを特徴とする請求項１に記載の窒化ガリウム系化合物半導体である。 The invention according to claim 2 is characterized in that the third gallium nitride compound semiconductor and the second gallium nitride compound semiconductor have the same composition. It is.
また、請求項３に記載の発明は、第３の窒化ガリウム系化合物半導体と第２の窒化ガリウム系化合物半導体は、共に、窒化ガリウムであることを特徴とする請求項１に記載の窒化ガリウム系化合物半導体である。 According to a third aspect of the present invention, the third gallium nitride compound semiconductor and the second gallium nitride compound semiconductor are both gallium nitride. It is a compound semiconductor.
また、請求項４に記載の発明は、第３の窒化ガリウム系化合物半導体の上に形成された窒化ガリウム系化合物半導体から成る素子層を有することを特徴とする請求項１乃至請求項３の何れか１項に記載の窒化ガリウム系化合物半導体である。
また、請求項５に記載の発明は、基板は、サファイア、シリコン、又は、炭化珪素であることを特徴とする請求項１乃至請求項４の何れか１項に記載の窒化ガリウム系化合物半導体である。
The invention described in claim 4 has an element layer made of a gallium nitride compound semiconductor formed on the third gallium nitride compound semiconductor. 2. The gallium nitride compound semiconductor according to claim 1.
The invention according to claim 5 is the gallium nitride compound semiconductor according to any one of claims 1 to 4, wherein the substrate is sapphire, silicon, or silicon carbide. is there.
また、請求項６に記載の発明は、基板はシリコンであり、島状態に形成される第１の窒化ガリウム系化合物半導体は、アルミニウムを含む窒化ガリウム系化合物半導体であり、第３の窒化ガリウム系化合物半導体はアルミニウムを含まない窒化ガリウム系化合物半導体であることを特徴とする請求項１乃至請求項５に記載の窒化ガリウム系化合物半導体である。
アルミニウムを含む窒化ガリウム系化合物半導体はシリコン上にエピタキシャル成長するが、アルミニウムを含まない窒化ガリウム系化合物半導体はシリコン上にエピタキシャル成長しない。よって、シリコン基板上に島状態の第１の窒化ガリウム系化合物半導体と第２の窒化ガリウム系化合物半導体を形成し、その後、その第２の窒化ガリウム系化合物半導体上にはエピタキシャル成長するが、シリコン基板の露出部にはエピタキシャル成長しない第３の窒化ガリウム系化合物半導体を形成することができる。これにより、シリコン基板の露出部上は、第２の窒化ガリウム系化合物半導体を核として、第３の窒化ガリウム系化合物半導体が横方向にエピタキシャル成長することになり、結晶性の高い窒化ガリウム系化合物半導体を得ることができる。
According to a sixth aspect of the present invention, the substrate is silicon, the first gallium nitride compound semiconductor formed in an island state is a gallium nitride compound semiconductor containing aluminum, and the third gallium nitride compound 6. The gallium nitride compound semiconductor according to claim 1, wherein the compound semiconductor is a gallium nitride compound semiconductor containing no aluminum.
A gallium nitride compound semiconductor containing aluminum is epitaxially grown on silicon, but a gallium nitride compound semiconductor containing no aluminum is not epitaxially grown on silicon. Therefore, the first gallium nitride compound semiconductor and the second gallium nitride compound semiconductor in an island state are formed on the silicon substrate, and then epitaxially grown on the second gallium nitride compound semiconductor. A third gallium nitride-based compound semiconductor that does not grow epitaxially can be formed on the exposed portion. As a result, the third gallium nitride compound semiconductor is epitaxially grown in the lateral direction on the exposed portion of the silicon substrate with the second gallium nitride compound semiconductor as a nucleus, and the gallium nitride compound semiconductor having high crystallinity. Can be obtained.
また、請求項７に記載の発明は、基板と第１の窒化ガリウム系化合物半導体との間に、その第１の窒化ガリウム系化合物半導体と同一形状のバッファ層を有することを特徴とする請求項１乃至請求項４の何れか１項に記載の窒化ガリウム系化合物半導体である。 The invention according to claim 7 is characterized in that a buffer layer having the same shape as that of the first gallium nitride compound semiconductor is provided between the substrate and the first gallium nitride compound semiconductor. The gallium nitride compound semiconductor according to any one of claims 1 to 4.
また、請求項８に記載の発明は、請求項１乃至請求項５の何れかの窒化ガリウム系化合物半導体において、基板、又は基板から第２の窒化ガリウム系化合物半導体までを除去して得られる半導体基板である。 According to an eighth aspect of the present invention, in the gallium nitride compound semiconductor according to any one of the first to fifth aspects, the substrate or a semiconductor obtained by removing the substrate to the second gallium nitride compound semiconductor. It is a substrate.
以下、本発明を具体的な実施例に基づいて説明する。
（第１実施例）
図１は、本発明の第１実施例に係わる窒化ガリウム系化合物半導体の断面構成を示した模式図である。シリコン基板１の上には膜厚約1000ÅのAl0.15Ga0.85N 層（第１の窒化ガリウム系化合物半導体）２がストライプ状（図１（ｂ））又は格子状（図１（ｃ））に形成されている。又、シリコン基板１上の層２を除いた露出領域Ａ及び層２の上面領域Ｂには膜厚約10μｍのGaN 層（第２の窒化ガリウム系化合物半導体）３が形成されている。
Hereinafter, the present invention will be described based on specific examples.
(First embodiment)
FIG. 1 is a schematic diagram showing a cross-sectional structure of a gallium nitride compound semiconductor according to the first embodiment of the present invention. On the silicon substrate 1, an Al 0.15 Ga 0.85 N layer (first gallium nitride compound semiconductor) 2 having a thickness of about 1000 mm is formed in a stripe shape (FIG. 1B) or a lattice shape (FIG. 1C). Is formed. A GaN layer (second gallium nitride compound semiconductor) 3 having a thickness of about 10 μm is formed in the exposed region A excluding the layer 2 on the silicon substrate 1 and the upper surface region B of the layer 2.
次に、このGaN 系化合物半導体の製造方法について説明する。
この半導体は、スパッタリング法及び有機金属気相成長法（以下「MOVPE 」と略す）により製造された。MOVPE で用いられたガスは、アンモニア(NH3) 、キャリアガス(H2,N2) 、トリメチルガリウム(Ga(CH3)3)（以下「TMG 」と記す）、トリメチルアルミニウム(Al(CH3)3)（以下「TMA 」と記す）である。
Next, a method for manufacturing this GaN-based compound semiconductor will be described.
This semiconductor was manufactured by sputtering and metal organic vapor phase epitaxy (hereinafter abbreviated as “MOVPE”). The gases used in MOVPE are ammonia (NH 3 ), carrier gas (H 2 , N 2 ), trimethyl gallium (Ga (CH 3 ) 3 ) (hereinafter referred to as “TMG”), trimethyl aluminum (Al (CH 3 3 ) (hereinafter referred to as “TMA”).
まず、フッ酸系溶液(HF:H2O=1:1)を用いて洗浄した (111)面、 (100)面、又は、(110) 面を主面としたｎ−シリコン基板１をＭＯＶＰＥ装置の反応室に載置されたサセプタに装着する。次に、常圧でH2を流速2 liter/分で約10分間反応室に流しながら温度1150℃で基板１をベーキングした。 First, an n-silicon substrate 1 having a (111) plane, a (100) plane, or a (110) plane as a principal plane cleaned with a hydrofluoric acid solution (HF: H 2 O = 1: 1) is converted into MOVPE. It is attached to a susceptor placed in the reaction chamber of the apparatus. Next, the substrate 1 was baked at a temperature of 1150 ° C. while flowing H 2 at normal pressure at a flow rate of 2 liter / min for about 10 minutes in the reaction chamber.
この後、基板１の温度を1150℃に保持し、N2又はH2を10liter/分、NH3 を10liter/分、TMG を1.0 ×10-4モル／分、トリメチルアルミニウム(Al(CH3)3)（以下「TMA 」と記す）を1.0 ×10-5モル／分、H2ガスにより0.86ppm に希釈されたシランを20×10-8モル／分で供給し、膜厚約1000Å、Si濃度1.0 ×1018/cm3のAl0.15Ga0.85N 層２を形成した。 Thereafter, the temperature of the substrate 1 is maintained at 1150 ° C., N 2 or H 2 is 10 liter / min, NH 3 is 10 liter / min, TMG is 1.0 × 10 −4 mol / min, trimethylaluminum (Al (CH 3 ) 3 ) (hereinafter referred to as “TMA”) is supplied at 1.0 × 10 −5 mol / min and silane diluted to 0.86 ppm with H 2 gas at 20 × 10 −8 mol / min. An Al 0.15 Ga 0.85 N layer 2 having a concentration of 1.0 × 10 18 / cm 3 was formed.
次に、この層２の上に、一様に、SiO2層をスパッタリングにより膜厚約2000Åに形成し、レジストを塗布して、フォトリソグラフィによりSiO2層を所定形状にエッチングした。次に、この所定形状のSiO2層をマスクとして、Al0.15Ga0.85N 層２をドライエッチングした。このようにして、層２の上部領域Ｂの幅ｂが約５μｍ、基板１の露出領域Ａの間隔ａが約５μｍのストライプ状（図１（ｂ））又は格子状（図１（ｃ））に形成した。 Next, an SiO 2 layer was uniformly formed on the layer 2 to a thickness of about 2000 mm by sputtering, a resist was applied, and the SiO 2 layer was etched into a predetermined shape by photolithography. Next, the Al 0.15 Ga 0.85 N layer 2 was dry etched using the SiO 2 layer having the predetermined shape as a mask. In this way, a stripe shape (FIG. 1 (b)) or a lattice shape (FIG. 1 (c)) in which the width b of the upper region B of the layer 2 is about 5 μm and the distance a between the exposed regions A of the substrate 1 is about 5 μm. Formed.
次に、MOVPE 法により基板１の温度を1100℃にしてN2又はH2を20liter/分、NH3 を10liter/分、TMG を1.0 ×10-4モル／分、H2ガスにより0.86ppm に希釈されたシランを20×10-8モル／分で供給して、膜厚約10μｍのGaN 層３をエピタキシャル成長させた。このとき、GaN は、Al0.15Ga0.85N 層２の上に、このAl0.15Ga0.85N を核として、エピタキシャル成長する。しかし、シリコン基板１の露出領域Ａの上には、GaN はエピタキシャル成長しない。そして、シリコン基板１の露出領域Ａでは、Al0.15Ga0.85N 層２上に成長したGaN を核として、GaN が横方向、即ち、シリコン基板１の面方向に沿ってエピタキシャル成長する。このGaN 層３は、Al0.15Ga0.85N 層２の上部領域Ｂにだけ縦方向に転位が生じ、シリコン基板１の露出領域Ａでは、横方向のエピタキシャル成長であるために、転位は生じない。シリコン基板１の露出領域Ａの面積をAl0.15Ga0.85N 層２の上部領域Ｂの面積に比べて大きくすることで、広い面積に渡って結晶性の良好なGaN 層３を形成することができる。また、シリコン基板１とその上のGaN は化学的に結合していないために、GaN 層３のそり、応力歪みを極めて大きく減少させることができる。 Next, the temperature of the substrate 1 is set to 1100 ° C. by the MOVPE method, N 2 or H 2 is 20 liter / min, NH 3 is 10 liter / min, TMG is 1.0 × 10 −4 mol / min, and H 2 gas is 0.86 ppm. Diluted silane was supplied at 20 × 10 −8 mol / min to epitaxially grow a GaN layer 3 having a thickness of about 10 μm. At this time, GaN is epitaxially grown on the Al 0.15 Ga 0.85 N layer 2 using the Al 0.15 Ga 0.85 N as a nucleus. However, GaN does not grow epitaxially on the exposed region A of the silicon substrate 1. In the exposed region A of the silicon substrate 1, GaN grows epitaxially in the lateral direction, that is, along the surface direction of the silicon substrate 1 with GaN grown on the Al 0.15 Ga 0.85 N layer 2 as a nucleus. In the GaN layer 3, dislocation occurs in the vertical direction only in the upper region B of the Al 0.15 Ga 0.85 N layer 2, and in the exposed region A of the silicon substrate 1, dislocation does not occur because of lateral epitaxial growth. By making the area of the exposed region A of the silicon substrate 1 larger than the area of the upper region B of the Al 0.15 Ga 0.85 N layer 2, the GaN layer 3 having good crystallinity can be formed over a wide area. . Further, since the silicon substrate 1 and the GaN on the silicon substrate 1 are not chemically bonded, warpage and stress strain of the GaN layer 3 can be greatly reduced.
尚、上記実施例において、ストライプ状又は格子状に形成されたシリコン基板１の露出領域Ａの幅ａを約５μｍとしたが、露出領域Ａの幅ａが10μｍを超えると横方向の成長に長時間必要となり、シリコン基板１の露出領域Ａの幅ａが１μｍ未満になると、良好なGaN 膜の形成が困難となるので、望ましくは１〜10μｍの範囲が良い。また、Al0.15Ga0.85N 層２の上部領域Ｂの幅ｂを５μｍとしたが、Al0.15Ga0.85N 層２の上部領域Ｂの幅ｂが10μｍを超えると転位発生の確率が増大し、上部領域Ｂの幅ｂが１μｍ未満になると横方向の成長のための核形成が良好でできず、したがって、結晶性の良い横方向のエピタキシャル成長が困難となる。よって、望ましくは１〜10μｍの範囲が良い。また、層３の結晶性の観点から、シリコン基板１の露出領域Ａの幅ａのAl0.15Ga0.85N 層２の上部領域Ｂの幅ｂに対する割合ａ／ｂは１〜10が望ましい。 In the above embodiment, the width “a” of the exposed region A of the silicon substrate 1 formed in a stripe shape or a lattice shape is about 5 μm. However, if the width “a” of the exposed region A exceeds 10 μm, the lateral growth is long. Time is required, and if the width a of the exposed region A of the silicon substrate 1 is less than 1 μm, it becomes difficult to form a good GaN film. Therefore, the range of 1 to 10 μm is desirable. The width b of the upper region B of the Al 0.15 Ga 0.85 N layer 2 is 5 μm. However, if the width b of the upper region B of the Al 0.15 Ga 0.85 N layer 2 exceeds 10 μm, the probability of dislocation generation increases. If the width b of the region B is less than 1 μm, nucleation for lateral growth cannot be performed well, and therefore lateral epitaxial growth with good crystallinity becomes difficult. Therefore, the range of 1 to 10 μm is desirable. Further, from the viewpoint of the crystallinity of the layer 3, the ratio a / b of the width a of the exposed region A of the silicon substrate 1 to the width b of the upper region B of the Al 0.15 Ga 0.85 N layer 2 is preferably 1 to 10.
尚、上記実施例では、シリコン基板を用いたが、他の導電性基板、サファイア基板、炭化珪素等を用いることができる。導電性基板を用いた場合には、基板の裏面と基板上に形成された素子層の最上層とに電極を形成して、基板面に垂直に電流を流すことができ、発光ダイオード、レーザ等における電流供給効率が向上する。
本実施例では、層２の組成をAl0.15Ga0.85N としたが、任意組成比の一般式Alx Gay In1-x-y N(0 ≦x ≦1,0 ≦y ≦1,0 ≦x+y ≦1)の窒化ガリウム系化合物半導体を用いることができる。シリコン基板１上にエピタキシャル成長させるには、Alx Ga1-x N(0 ＜x ≦1)（AlN を含む) が望ましい。また、層３は、任意組成比の一般式Alx Gay In1-x-y N(0 ≦x ≦1,0 ≦y ≦1,0 ≦x+y ≦1)の窒化ガリウム系化合物半導体を用いることができ、層２と同一組成比であっても、異なる組成比であっても良いが、基板に対してエピタキシャル成長しない組成比とする必要がある。
又、本実施例では、層２の膜厚を約1000Åとしたが、層２は厚いとクラックが多くなり、薄いと層２を核として層３が成長しない。よって、層２の厚さは、500 Å〜2000Åが望ましい。
In the above embodiment, a silicon substrate is used, but other conductive substrates, sapphire substrates, silicon carbide, and the like can be used. In the case of using a conductive substrate, electrodes can be formed on the back surface of the substrate and the uppermost layer of the element layer formed on the substrate so that a current can flow perpendicularly to the substrate surface. Current supply efficiency is improved.
In this example, the composition of the layer 2 was Al 0.15 Ga 0.85 N, but the general formula Al x Ga y In 1-xy N (0 ≦ x ≦ 1,0 ≦ y ≦ 1,0 ≦ x A gallium nitride compound semiconductor of + y ≦ 1) can be used. In order to perform epitaxial growth on the silicon substrate 1, Al x Ga 1-x N (0 <x ≦ 1) (including AlN) is desirable. The layer 3 uses general formula Al x Ga y In 1-xy N (0 ≦ x ≦ 1,0 ≦ y ≦ 1,0 ≦ x + y ≦ 1) The gallium nitride-based compound semiconductor of any composition ratio The composition ratio may be the same as that of the layer 2 or may be a different composition ratio. However, it is necessary to set the composition ratio so that it does not grow epitaxially with respect to the substrate.
In this embodiment, the thickness of the layer 2 is about 1000 mm. However, if the layer 2 is thick, cracks increase. If the layer 2 is thin, the layer 3 does not grow using the layer 2 as a nucleus. Therefore, the thickness of the layer 2 is desirably 500 mm to 2000 mm.
（第２実施例）
上述の第１実施例では、第１の窒化ガリウム系化合物半導体として、Al0.15Ga0.85N 層２を１層だけ設けられている。本実施例では、第１の窒化ガリウム系化合物半導体として、Al0.15Ga0.85N 層２１とその上のGaN 層２２の２層で形成したことを特徴とする。
(Second embodiment)
In the first embodiment described above, only one Al 0.15 Ga 0.85 N layer 2 is provided as the first gallium nitride compound semiconductor. The present embodiment is characterized in that the first gallium nitride compound semiconductor is formed of two layers of an Al 0.15 Ga 0.85 N layer 21 and a GaN layer 22 thereon.
図２は、本発明の第２実施例に係わる窒化ガリウム系化合物半導体の断面構成を示した模式図である。シリコン基板１の上には膜厚約1000ÅのAl0.15Ga0.85N 層２１が形成され、この層２１上に、膜厚約1000ÅのGaN 層２２が形成されている。層２１と層２２とで第１の窒化ガリウム系化合物半導体が構成される。これらの層２１と層２２層は、第１実施例と同様にストライプ状又は格子状に形成されている。層２２及びシリコン基板１の露出領域Ａ上には、膜厚約10μｍのGaN 層３が形成されている。 FIG. 2 is a schematic diagram showing a cross-sectional structure of a gallium nitride compound semiconductor according to the second embodiment of the present invention. An Al 0.15 Ga 0.85 N layer 21 having a thickness of about 1000 mm is formed on the silicon substrate 1, and a GaN layer 22 having a thickness of about 1000 mm is formed on the layer 21. The layer 21 and the layer 22 constitute a first gallium nitride compound semiconductor. These layers 21 and 22 are formed in a stripe shape or a lattice shape as in the first embodiment. A GaN layer 3 having a thickness of about 10 μm is formed on the layer 22 and the exposed region A of the silicon substrate 1.
この第２実施例の窒化ガリウム系化合物半導体は、第１実施例において、層２１、層２２をシリコン基板１上に一様に形成した後、所定パターンのSiO2層をマスクにして、層２１、層２２をドライエッチングで図１（ｂ）又は（ｃ）に示すように、ストライプ状又は格子状にする。その後のGaN 層３の形成は第１実施例と同一である。 In the gallium nitride compound semiconductor of the second embodiment, the layer 21 and the layer 22 are uniformly formed on the silicon substrate 1 in the first embodiment, and then the SiO 2 layer having a predetermined pattern is used as a mask. As shown in FIG. 1B or 1C, the layer 22 is formed into a stripe shape or a lattice shape by dry etching. Subsequent formation of the GaN layer 3 is the same as in the first embodiment.
膜厚約10μｍのGaN 層３の成長過程は以下の通りである。GaN は、GaN 層２２の上部領域ＢのGaN を核として、面に垂直方向に成長する。そして、シリコン基板１の露出領域Ａでは、層２２の露出領域Ｂ上に成長したGaN を核として、GaN が横方向にエピタキシャル成長する。このようにして、本実施例では、GaN がGaN を核として縦方向にも横方向にもエピタキシャル成長するので、第１実施例よりも、さらに、結晶性の高いGaN が得られる。 The growth process of the GaN layer 3 having a thickness of about 10 μm is as follows. GaN grows in a direction perpendicular to the surface with GaN in the upper region B of the GaN layer 22 as a nucleus. In the exposed region A of the silicon substrate 1, GaN grows epitaxially in the lateral direction with GaN grown on the exposed region B of the layer 22 as a nucleus. Thus, in this embodiment, GaN epitaxially grows in the vertical and horizontal directions with GaN as the nucleus, so that GaN having higher crystallinity than that in the first embodiment can be obtained.
尚、本実施例において、層２２と層３とをGaN としたが、層２２と層３とを同一組成比の一般式Alx Gay In1-x-y N(0 ≦x ≦1,0 ≦y ≦1,0 ≦x+y ≦1)の窒化ガリウム系化合物半導体としても良い。但し、層３は基板に対してエピタキシャル成長しない組成比とする必要がある。基板にシリコンを用いた場合には、Alが含まれない窒化ガリウム系化合物半導体を用いるのが良い。勿論、層２２と層３との組成比を変化させても良い。 In the present embodiment has the GaN and a layer 22 and the layer 3, typically a layer 22 and the layer 3 having the same composition ratio formula Al x Ga y In 1-xy N (0 ≦ x ≦ 1,0 ≦ A gallium nitride compound semiconductor of y ≦ 1,0 ≦ x + y ≦ 1) may be used. However, the layer 3 needs to have a composition ratio that does not grow epitaxially with respect to the substrate. When silicon is used for the substrate, a gallium nitride compound semiconductor that does not contain Al is preferably used. Of course, the composition ratio between the layer 22 and the layer 3 may be changed.
上記の全実施例において、シリコン基板１又は、シリコン基板１から層２又は層２２までの部分Ｃを研磨又はエッチングにより除去することにより、無転位のGaN 基板を得ることができる。上記の全実施例において、層３にGaN を用いたが、任意組成比のInGaN を用いても良い。また、層３の上に、他の材料の半導体層を形成しても良い。特に、窒化ガリウム系化合物半導体をさらに成長させることで、発光ダイオード、レーザ等の特性の良好な素子を得ることができる。
また、上記の全実施例において、基板１と層２、又は層２２の間に、任意組成比のAlGaN のバッファ層や AlGaInNのバッファ層を設けても良い。このバッファ層は層２、層２２の単結晶成長温度よりも低温で形成されるアモルファス状又は微結晶の混在したアモルファス等の結晶構造をしたものである。
In all the above embodiments, the dislocation-free GaN substrate can be obtained by removing the silicon substrate 1 or the portion C from the silicon substrate 1 to the layer 2 or the layer 22 by polishing or etching. In all the above embodiments, GaN is used for the layer 3, but InGaN having an arbitrary composition ratio may be used. Further, a semiconductor layer of another material may be formed on the layer 3. In particular, by further growing a gallium nitride-based compound semiconductor, an element having good characteristics such as a light emitting diode and a laser can be obtained.
In all the embodiments described above, an AlGaN buffer layer or an AlGaInN buffer layer having an arbitrary composition ratio may be provided between the substrate 1 and the layer 2 or the layer 22. This buffer layer has a crystal structure such as an amorphous form formed at a temperature lower than the single crystal growth temperature of the layers 2 and 22 or an amorphous structure in which microcrystals are mixed.
素子層としてＳＱＷ又はＭＱＷ等の量子構造を有した発光ダイオード、レーザを形成することができる。
上記の全実施例において、MOVPE 法は常圧雰囲気中で行われたが、減圧成長下で行っても良い。また、常圧、減圧の組み合わせで行なって良い。
本発明で得られたGaN 系化合物半導体は、ＬＥＤやＬＤの発光素子に利用可能であると共に受光素子及び電子ディバイスにも利用することができる。
As the element layer, a light emitting diode or laser having a quantum structure such as SQW or MQW can be formed.
In all the above examples, the MOVPE method was performed in a normal pressure atmosphere, but may be performed under reduced pressure growth. Moreover, you may carry out by the combination of a normal pressure and pressure reduction.
The GaN-based compound semiconductor obtained in the present invention can be used for a light emitting device such as an LED or LD, and can also be used for a light receiving device and an electronic device.
尚、本件出願には、基板上に第１の窒化ガリウム系化合物半導体を成長させ、その後、その第１の窒化ガリウム系化合物半導体を、基板の露出部が散在するように、点状、ストライプ状又は格子状等の島状態にエッチングし、その後、島状態の第１の窒化ガリウム系化合物半導体を核として成長するが、基板の露出部を核としてはエピタキシャル成長しない第２の窒化ガリウム系化合物半導体を成長させ、基板の露出面上は横方向成長により形成することを特徴とする窒化ガリウム系化合物半導体の製造方法も開示されている。 In the present application, a first gallium nitride compound semiconductor is grown on a substrate, and then the first gallium nitride compound semiconductor is formed in a dot shape or a stripe shape so that exposed portions of the substrate are scattered. Alternatively, the second gallium nitride compound semiconductor is etched into an island state such as a lattice shape, and then grown using the island-state first gallium nitride compound semiconductor as a nucleus, but not epitaxially grown using the exposed portion of the substrate as a nucleus. Also disclosed is a method for producing a gallium nitride compound semiconductor, which is grown and formed on the exposed surface of the substrate by lateral growth.
本発明は、素子特性を向上させる半導体として用いることができる。 The present invention can be used as a semiconductor that improves device characteristics.
１ シリコン基板
２ Al0.15Ga0.85N 層
３ GaN 層（第３の窒化ガリウム系化合物半導体）
２１ Al0.15Ga0.85N 層（第１の窒化ガリウム系化合物半導体）
２２ GaN 層（第２の窒化ガリウム系化合物半導体）
1 Silicon substrate 2 Al 0.15 Ga 0.85 N layer 3 GaN layer (third gallium nitride compound semiconductor)
21 Al 0.15 Ga 0.85 N layer (first gallium nitride compound semiconductor)
22 GaN layer (second gallium nitride compound semiconductor)
Claims (8)
基板と、
前記基板上に形成され、前記基板の露出部の幅を１μｍ〜１０μｍとし、幅が１μｍ〜１０μｍのストライプ状又は格子状の島状態に形成された第１の窒化ガリウム系化合物半導体と、前記第１の窒化ガリウム系化合物半導体の上に形成され、前記第１の窒化ガリウム系化合物半導体と同一パターンの第２の窒化ガリウム系化合物半導体とから成る２層構造と、
前記島状態の前記第２の窒化ガリウム系化合物半導体を核として成長した、前記基板の露出部を核としてはエピタキシャル成長しておらず且つ前記基板の露出面とは化学的に接合していない、前記基板の露出面上に横方向成長した第３の窒化ガリウム系化合物半導体と
から成ることを特徴とする窒化ガリウム系化合物半導体。 In gallium nitride compound semiconductors,
A substrate,
A first gallium nitride-based compound semiconductor formed on the substrate, the exposed portion of the substrate having a width of 1 μm to 10 μm, and having a width of 1 μm to 10 μm in a striped or grid-like island state; A two-layer structure formed on one gallium nitride compound semiconductor and comprising a second gallium nitride compound semiconductor having the same pattern as the first gallium nitride compound semiconductor ;
Growing using the second gallium nitride compound semiconductor in the island state as a nucleus, not growing epitaxially using the exposed portion of the substrate as a nucleus, and not chemically bonding to the exposed surface of the substrate, And a third gallium nitride compound semiconductor grown laterally on the exposed surface of the substrate.
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