JP2014022685A - Semiconductor laminate structure and semiconductor element using the same - Google Patents
Semiconductor laminate structure and semiconductor element using the same Download PDFInfo
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本発明は、電界効果トランジスタ(FET)、発光ダイオード(LED)等の半導体素子に用いられる半導体積層構造であって、特に反りおよびクラックの発生を抑制した、結晶品質の優れたSi基板を用いた半導体積層構造およびこれを用いた半導体素子に関するものである。 The present invention is a semiconductor multilayer structure used for semiconductor elements such as field effect transistors (FETs), light emitting diodes (LEDs), etc., and particularly uses a Si substrate with excellent crystal quality that suppresses the occurrence of warpage and cracks. The present invention relates to a semiconductor laminated structure and a semiconductor element using the same.
窒化物半導体は、電界効果トランジスタ等の電子デバイス、あるいは、可視光領域から紫外光領域の短波長帯における受発光デバイスの活性材料として、近年盛んに研究開発が行われている。 BACKGROUND ART Nitride semiconductors have been actively researched and developed in recent years as active materials for electronic devices such as field effect transistors or light receiving and emitting devices in the short wavelength band from the visible light region to the ultraviolet light region.
一般的に、前記窒化物半導体は、サファイア、SiC又はSi等からなる基板上に形成される。特に、Si単結晶基板(以下、「Si基板」という)は、大面積が低価格で入手でき、結晶性及び放熱性に優れ、さらに、へき開やエッチングが容易で、プロセス技術が成熟しているといった多くの利点を具えている。 Generally, the nitride semiconductor is formed on a substrate made of sapphire, SiC, Si, or the like. In particular, a Si single crystal substrate (hereinafter referred to as “Si substrate”) has a large area and is available at a low price, is excellent in crystallinity and heat dissipation, is easy to cleave and etch, and has a mature process technology. Has many advantages.
しかし、前記窒化物半導体とSi基板とでは、格子定数や熱膨張係数が大きく異なるため、Si基板上に窒化物半導体を成長させた場合、成長した窒化物半導体は、ウェーハとして反る、あるいはクラックやピット(点状欠陥)が発生するという問題があった。特に反りが大きいと、デバイス加工としてプロセスが困難となり、また素子として耐圧が低いなど大きな課題となっている。 However, since the nitride semiconductor and the Si substrate have greatly different lattice constants and thermal expansion coefficients, when the nitride semiconductor is grown on the Si substrate, the grown nitride semiconductor warps as a wafer or cracks. And pits (point defects) occur. In particular, when the warpage is large, the process becomes difficult as device processing, and the breakdown voltage as an element is low, which is a big problem.
上記問題を解決するための手段としては、前記Si基板と窒化物半導体層との間にバッファ層を形成することで、反りあるいはクラックを抑制する技術が知られている。例えば、特許文献1では、Si基板の上に、窒化物半導体からなり、組成的に勾配を付けたAlxGa1−XN等からなる転移層(バッファ層)を形成し、該転移層の上に窒化ガリウムを形成してなる半導体材料が開示されている。 As a means for solving the above problem, a technique for suppressing warpage or cracking by forming a buffer layer between the Si substrate and the nitride semiconductor layer is known. For example, in Patent Document 1, a transition layer (buffer layer) made of a nitride semiconductor and made of compositionally graded Al x Ga 1-X N or the like is formed on a Si substrate. A semiconductor material having gallium nitride formed thereon is disclosed.
また、特許文献2では、Si基板上に、高Al含有層と、低Al含有層とを交互に複数層積層してなるAlN系超格子複合層を形成し、該AlN系超格子複合バッファ層上に窒化物半導体層を形成してなる窒化物半導体素子が開示されている。 In Patent Document 2, an AlN-based superlattice composite layer formed by alternately laminating a plurality of high Al-containing layers and low Al-containing layers on a Si substrate is formed, and the AlN-based superlattice composite buffer layer is formed. A nitride semiconductor device having a nitride semiconductor layer formed thereon is disclosed.
しかしながら、特許文献1及び2に記載の半導体材料では、いずれも前記窒化物半導体層に発生する反りあるいはクラックの抑制については十分でなかった。 However, none of the semiconductor materials described in Patent Documents 1 and 2 is sufficient for suppressing warpage or cracks generated in the nitride semiconductor layer.
一方、特許文献3および4では、反りの少ない半導体積層基板を得るため、2インチ径で330μm厚のサファイア基板上に、30nm厚のGaNバッファ層を設けた後、GaN層とGaの一部をInで置換したInGaN層からなる中間層を設け、さらにAlGaN系の膜を20〜30nmの厚みで形成した半導体積層構造の反りが10〜25μmであることが開示されている。 On the other hand, in Patent Documents 3 and 4, a GaN buffer layer having a thickness of 30 nm is provided on a sapphire substrate having a diameter of 2 inches and a thickness of 330 μm in order to obtain a semiconductor multilayer substrate with little warpage. It is disclosed that the warp of a semiconductor multilayer structure in which an intermediate layer composed of an InGaN layer substituted with In is provided and an AlGaN-based film is formed with a thickness of 20 to 30 nm is 10 to 25 μm.
しかし、特許文献3および4で用いたサファイア基板のヤング率はSi基板のヤング率の2〜3倍であり、相対的に反りが小さくなること、また、基板の径を2インチから4インチへと大きくすれば反りは4倍程度大きくなることが予想され、さらに歪緩和のための中間層上のAlGaNの膜厚が小さく、中間層の歪緩和効果が十分には確認されていない。 However, the Young's modulus of the sapphire substrate used in Patent Documents 3 and 4 is 2 to 3 times the Young's modulus of the Si substrate, so that the warpage is relatively small, and the diameter of the substrate is changed from 2 inches to 4 inches. If it is larger, the warpage is expected to be about 4 times larger. Further, the film thickness of AlGaN on the intermediate layer for strain relaxation is small, and the strain relaxation effect of the intermediate layer has not been sufficiently confirmed.
本発明の課題は、Si基板上にバッファ層を設け、このバッファ層上に、歪超格子層あるいは組成傾斜層を設け、さらにGaN系のデバイス層を設けた半導体積層構造であって、反りを低減した半導体積層構造およびこれを用いた半導体素子を提供することにある。 An object of the present invention is a semiconductor laminated structure in which a buffer layer is provided on a Si substrate, a strained superlattice layer or a composition gradient layer is provided on the buffer layer, and a GaN-based device layer is further provided. It is an object of the present invention to provide a reduced semiconductor multilayer structure and a semiconductor element using the same.
本発明者らは、前記半導体積層構造において、歪超格子層の膜厚と半導体層の総膜厚との関係、あるいは組成傾斜層の膜厚と半導体層の総膜厚とが特定の関係にあることが、上記課題が解決しうることを見出した。すなわち、本発明によれば、以下の半導体積層構造およびこれを用いた半導体素子が提供される。 In the semiconductor stacked structure, the inventors have a specific relationship between the thickness of the strained superlattice layer and the total thickness of the semiconductor layer, or the thickness of the composition gradient layer and the total thickness of the semiconductor layer. It has been found that the above problems can be solved. That is, according to the present invention, the following semiconductor multilayer structure and a semiconductor element using the same are provided.
[1] 基板上にバッファ層、歪超格子層、チャネル層、およびバリア層なるAlGaN系半導体層を順次設けた半導体積層構造であって、室温〜1200℃における前記基板の熱膨張係数が前記半導体層のいずれの熱膨張係数より小さく、歪超格子層の膜厚(tSL)、チャネル層の膜厚(tCH)、および半導体層の総厚(tTOTAL)との関係が、0.75≦tSL/tTOTAL≦0.90 、または0.75≦tSL/(tSL+tCH)≦0.90である半導体積層構造。 [1] A semiconductor laminated structure in which an AlGaN-based semiconductor layer as a buffer layer, a strained superlattice layer, a channel layer, and a barrier layer is sequentially provided on a substrate, and the thermal expansion coefficient of the substrate at room temperature to 1200 ° C. The relationship between the thermal expansion coefficient smaller than any of the layers, the thickness of the strained superlattice layer (t SL ), the thickness of the channel layer (t CH ), and the total thickness of the semiconductor layer (t TOTAL ) is 0.75 ≦ t SL / t TOTAL ≦ 0.90 or 0.75 ≦ t SL / (t SL + t CH ) ≦ 0.90
[2] 前記歪超格子層がAlX1Ga1−X1NとAlX2Ga1−X2Nの組み合わせを交互に繰り返した層であり、その合計の厚みが1.0μm〜6.0μmである前記[1]に記載の半導体積層構造。 [2] The strained superlattice layer is a layer in which a combination of Al X1 Ga 1-X1 N and Al X2 Ga 1-X2 N is alternately repeated, and the total thickness is 1.0 μm to 6.0 μm The semiconductor multilayer structure according to [1].
[3] 前記歪超格子層の対組成が、0.9≦X1≦1.0、X2+0.65≦X1≦X2+0.75である前記[2]に記載の半導体積層構造。 [3] The semiconductor multilayer structure according to [2], wherein the pair composition of the strained superlattice layer is 0.9 ≦ X1 ≦ 1.0 and X2 + 0.65 ≦ X1 ≦ X2 + 0.75.
[4] 基板上にバッファ層、歪超格子層、および発光層なるAlGaN系半導体層を順次設けた半導体積層構造であって、室温〜1200℃における前記基板の熱膨張係数が前記半導体層のいずれの熱膨張係数より小さく、歪超格子層の膜厚(tSL)、発光層の膜厚(tLE)、および半導体層の総厚(tTOTAL)との関係が、0.75≦tSL/tTOTAL≦0.90 、または0.75≦tSL/(tSL+tLE)≦0.90である半導体積層構造。 [4] A semiconductor laminated structure in which a buffer layer, a strained superlattice layer, and an AlGaN-based semiconductor layer as a light-emitting layer are sequentially provided on a substrate, and the thermal expansion coefficient of the substrate at room temperature to 1200 ° C. is any of the semiconductor layers. The relationship between the thickness of the strained superlattice layer (t SL ), the thickness of the light emitting layer (t LE ), and the total thickness of the semiconductor layer (t TOTAL ) is 0.75 ≦ t SL. / T TOTAL ≦ 0.90, or 0.75 ≦ t SL / (t SL + t LE ) ≦ 0.90.
[5] 前記発光層が第1の導電型半導体層、活性層、および第1の導電型と反対の第2の導電型半導体層を順次積層してなる前記[4]に記載の半導体積層構造。 [5] The semiconductor stacked structure according to [4], wherein the light emitting layer is formed by sequentially stacking a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer opposite to the first conductive type. .
[6] 前記歪超格子層がAlX1Ga1−X1NとAlX2Ga1−X2Nの組み合わせを交互に繰り返した層であり、その合計の厚みが1.0μm〜6.0μmである前記[4]または[5]に記載の半導体積層構造。 [6] The strained superlattice layer is a layer in which a combination of Al X1 Ga 1-X1 N and Al X2 Ga 1-X2 N is alternately repeated, and the total thickness thereof is 1.0 μm to 6.0 μm. The semiconductor multilayer structure according to [4] or [5].
[7] 前記歪超格子層の対組成が、0.9≦X1≦1.0、X2+0.65≦X1≦X2+0.75である前記[6]に記載の半導体積層構造 [7] The semiconductor multilayer structure according to [6], wherein a pair composition of the strained superlattice layer is 0.9 ≦ X1 ≦ 1.0 and X2 + 0.65 ≦ X1 ≦ X2 + 0.75.
[8] 前記歪超格子層の厚み(tSL)と基板(tSUB)の厚みの比(tSL/tSUB)が、0.001〜0.014である前記[1]〜[7]のいずれかに記載の半導体積層構造。 [8] The above [1] to [7], wherein the ratio of the thickness (t SL ) of the strained superlattice layer to the thickness of the substrate (t SUB ) (t SL / t SUB ) is 0.001 to 0.014. The semiconductor laminated structure in any one of.
[9] 基板上にバッファ層、組成傾斜層、チャネル層、およびバリア層なるAlGaN系半導体層を順次設けた半導体積層構造であって、室温〜1200℃における前記基板の熱膨張係数が前記AlGaN系半導体層のいずれの熱膨張係数より小さく、組成傾斜層のAl組成が膜成長方向に減少し、組成傾斜層の膜厚(tCG)、チャネル層の膜厚(tCH)、および半導体層の総厚(tTOTAL)との関係が、0.75≦tCG/tTOTAL≦0.90、または0.75≦tCG/tCG+tCH≦0.90、である半導体積層構造。 [9] A semiconductor multilayer structure in which a buffer layer, a composition gradient layer, a channel layer, and a barrier layer are sequentially provided on a substrate, and the substrate has a thermal expansion coefficient of room temperature to 1200 ° C. Less than any thermal expansion coefficient of the semiconductor layer, the Al composition of the composition gradient layer decreases in the film growth direction, the film thickness of the composition gradient layer (t CG ), the film thickness of the channel layer (t CH ), and the semiconductor layer A semiconductor stacked structure in which the relationship with the total thickness (t TOTAL ) is 0.75 ≦ t CG / t TOTAL ≦ 0.90 or 0.75 ≦ t CG / t CG + t CH ≦ 0.90.
[10] 前記組成傾斜層の厚みが0.7μm〜2.5μmである前記[9]に記載の半導体積層構造。 [10] The semiconductor multilayer structure according to [9], wherein the composition gradient layer has a thickness of 0.7 μm to 2.5 μm.
[11] 前記組成傾斜層はAlX3Ga1−X3Nなる組成であり、膜厚10nm〜100nm毎にX3が膜成長方向に階段状に減少する前記[9]または[10]に記載の半導体積層構造。 [11] The semiconductor according to [9] or [10], wherein the composition gradient layer has a composition of Al X3 Ga 1-X3 N, and X3 decreases stepwise in the film growth direction every 10 nm to 100 nm in film thickness. Laminated structure.
[12] 基板上にバッファ層、組成傾斜層、および発光層なるAlGaN系半導体層を順次設けた半導体積層構造であって、室温〜1200℃における前記基板の熱膨張係数が前記半導体層のいずれの熱膨張係数より小さく、組成傾斜層の膜厚(tCG)、発光層の膜厚(tLE)、および半導体層の総厚(tTOTAL)との関係が、0.75≦tCG/tTOTAL≦0.90 、または0.75≦tCG/(tCG+tLE)≦0.90である半導体積層構造。 [12] A semiconductor laminated structure in which a buffer layer, a composition gradient layer, and an AlGaN-based semiconductor layer as a light emitting layer are sequentially provided on a substrate, and the thermal expansion coefficient of the substrate at room temperature to 1200 ° C. is any of the semiconductor layers. The relationship between the thickness of the composition gradient layer (t CG ), the thickness of the light emitting layer (t LE ), and the total thickness of the semiconductor layer (t TOTAL ), which is smaller than the thermal expansion coefficient, is 0.75 ≦ t CG / t A semiconductor stacked structure in which TOTAL ≦ 0.90 or 0.75 ≦ t CG / (t CG + t LE ) ≦ 0.90.
[13] 前記発光層が第1の導電型半導体層、活性層、および第1の導電型と反対の第2の導電型半導体層を順次積層してなる前記[12]に記載の半導体積層構造。 [13] The semiconductor stacked structure according to [12], wherein the light emitting layer is formed by sequentially stacking a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer opposite to the first conductive type. .
[14] 前記組成傾斜層の厚みが0.7μm〜2.5μmである前記[12]または[13]に記載の半導体積層構造。 [14] The semiconductor multilayer structure according to [12] or [13], wherein the thickness of the composition gradient layer is 0.7 μm to 2.5 μm.
[15] 前記組成傾斜層はAlX3Ga1−X3Nなる組成であり、膜厚10nm〜100nm毎にX3が膜成長方向に階段状に減少する前記[12]〜[14]のいずれかに記載の半導体積層構造。 [15] The composition gradient layer has a composition of Al X3 Ga 1-X3 N, and X3 decreases stepwise in the film growth direction every 10 nm to 100 nm in film thickness. The semiconductor laminated structure as described.
[16] 前記組成傾斜層の厚み(tCG)と基板(tSUB)の厚みの比(tCG/tSUB)が、0.0007〜0.0060である前記[9]〜[15]のいずれかに記載の半導体積層構造。 [16] In the above [9] to [15], the ratio of the thickness (t CG ) of the composition gradient layer to the thickness of the substrate (t SUB ) (t CG / t SUB ) is 0.0007 to 0.0060. The semiconductor laminated structure in any one.
[17] 前記チャネル層が厚み0.2μm〜5.0μmのAlX4Ga1−X4N(0≦X4≦0.1)からなる層である前記[1]〜[3]、[8]、[9]〜[11]、および[16]のいずれかに記載の半導体積層構造。 [17] The [1] to [3], [8], wherein the channel layer is a layer made of Al X4 Ga 1-X4 N (0 ≦ X4 ≦ 0.1) having a thickness of 0.2 μm to 5.0 μm. [9] to [11], and a semiconductor multilayer structure according to any one of [16].
[18] 前記基板がSi基板である前記[1]〜[17]のいずれかに記載の半導体積層構造。 [18] The semiconductor multilayer structure according to any one of [1] to [17], wherein the substrate is a Si substrate.
[19] 前記[1]〜[3]、[8]、[9]〜[11]、および[16]のいずれかに記載の半導体積層構造を用いたHEMT素子。 [19] A HEMT device using the semiconductor multilayer structure according to any one of [1] to [3], [8], [9] to [11], and [16].
[20] 前記[4]〜[8]、および[12]〜[16]のいずれかに記載の半導体積層構造を用いた発光素子。 [20] A light emitting device using the semiconductor multilayer structure according to any one of [4] to [8] and [12] to [16].
以下、図面を参照しつつ本発明の実施の形態について説明する。本発明は、以下の実施形態に限定されるものではなく、発明の範囲を逸脱しない限りにおいて、変更、修正、改良を加え得るものである。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. The present invention is not limited to the following embodiments, and changes, modifications, and improvements can be added without departing from the scope of the invention.
図1は本発明実施例1の半導体積層構造の概念図である。なお、図示の都合上、図1における各層の厚みの比率は実際の比率を反映していない。図1に示す半導体積層構造1は、Si基板2の上に、バッファ層としてAlN層3およびAlGaN層4を形成し、次に歪超格子層5、さらにデバイス層としてGaN層6およびAlxGa1−XN層7を順次積層したものである。この半導体積層構造1は、基板上2に、バッファ層3および4、歪超格子層5、さらにデバイス層6および7を順次エピタキシャル成長させることにより形成されるので、当該半導体積層構造は半導体エピタキシャル基板(あるいは半導体エピ基板)と称する場合がある。 FIG. 1 is a conceptual diagram of a semiconductor laminated structure of Example 1 of the present invention. For convenience of illustration, the ratio of the thickness of each layer in FIG. 1 does not reflect the actual ratio. In the semiconductor multilayer structure 1 shown in FIG. 1, an AlN layer 3 and an AlGaN layer 4 are formed as a buffer layer on a Si substrate 2, and then a strained superlattice layer 5, and further a GaN layer 6 and Al x Ga as a device layer. The 1- XN layer 7 is sequentially laminated. Since the semiconductor multilayer structure 1 is formed by epitaxially growing the buffer layers 3 and 4, the strained superlattice layer 5, and the device layers 6 and 7 on the substrate 2 in order, the semiconductor multilayer structure is a semiconductor epitaxial substrate ( Alternatively, it may be referred to as a semiconductor epi substrate.
本半導体積層構造に、たとえば、ソース電極、ゲート電極、およびドレイン電極を形成することにより、HEMT素子を形成することができる。 For example, a HEMT element can be formed by forming a source electrode, a gate electrode, and a drain electrode in the semiconductor multilayer structure.
基板は、その上に形成するバッファ層、歪超格子、デバイス層の組成や構造、あるいは各層の形成手法に応じて適宜に選択される。例えば、基板としては、シリコン、ゲルマニウム、サファイア、炭化ケイ素、酸化物(ZnO、LiAlO2,LiGaO2,MgAl2O4,(LaSr)(AlTa)O3,NdGaO3,MgOなど)、Si-Ge合金、周期律表の第3族−第5族化合物(GaAs,AlN,GaN,AlGaN、AlInN)、ホウ化物(ZrB2など)、などを用いることができる。ただし、室温〜1200℃における前記基板の熱膨張係数が基板上に形成するAlXGa1−XNからなる膜の熱膨張係数より小さいことが好ましく、なかでもSi基板が品質およびコストの点で好ましく、Si基板の厚みとしては0.42〜1.00mmが好適である。 The substrate is appropriately selected according to the buffer layer, strained superlattice, device layer composition and structure formed thereon, and the formation method of each layer. For example, as a substrate, silicon, germanium, sapphire, silicon carbide, oxide (ZnO, LiAlO 2 , LiGaO 2 , MgAl 2 O 4 , (LaSr) (AlTa) O 3 , NdGaO 3 , MgO, etc.), Si—Ge An alloy, a Group 3 to Group 5 compound of the periodic table (GaAs, AlN, GaN, AlGaN, AlInN), boride (such as ZrB2), and the like can be used. However, the thermal expansion coefficient of the substrate at room temperature to 1200 ° C. is preferably smaller than the thermal expansion coefficient of the film made of Al X Ga 1-X N formed on the substrate, and in particular, the Si substrate is in terms of quality and cost. Preferably, the thickness of the Si substrate is 0.42 to 1.00 mm.
バッファ層は、その上に形成する歪超格子、デバイス層の組成や構造、あるいは各層の形成手法に応じて、様々な第3族窒化物半導体からなる単一層または複数層から形成される。本発明では、バッファ層はAlXGa1−XNからなり、X≧0.2の1層または2層からなり,合計の厚みとして30〜500nmが好ましい。このバッファ層は、例えばMOCVD法やMBE法などの公知の成膜手法にて形成される。歪や転位密度ができるだけ少ない膜構造とすることが好ましく、後に形成される膜の品質に影響するため、転位密度は1×1011/cm3以下に形成することが好ましい。 The buffer layer is formed from a single layer or a plurality of layers made of various Group III nitride semiconductors depending on the strained superlattice formed thereon, the composition and structure of the device layer, or the formation method of each layer. In the present invention, the buffer layer is made of Al X Ga 1-X N, consists of one or two layers of X ≧ 0.2, 30 to 500 nm is preferred as the thickness of the total. This buffer layer is formed by a known film formation method such as MOCVD method or MBE method. It is preferable that the film structure has as little strain and dislocation density as possible, and the dislocation density is preferably 1 × 10 11 / cm 3 or less in order to affect the quality of a film to be formed later.
バッファ層の次に歪超格子層が形成される。歪超格子層は一方のAlX1Ga1−X1Nと他方のAlX2Ga1−X2Nの組み合わせ(対)を交互に繰り返した層であり、一方の厚みが2nm〜10nm,他方の厚みが5nm〜50nmであり、この歪超格子層の対組成が、0.9≦X1≦1.0、X2+0.65≦X1≦X2+0.75、そしてこの対を20〜200周期繰り返すことが好ましい。歪超格子層の合計の厚みとしては、1.0μm〜6.0μmが特に好ましい。上記対の組成差は、各歪超格子層の臨界膜厚の関係から選択される。すなわち、各歪超格子層の厚みを大きくする場合は対の組成差は大きくないことが好ましい。さらに、歪超格子層の厚み(tSL)と基板(tSUB)との厚みの比(tSL/tSUB)が、0.001〜0.014であることが好ましい。歪超格子層も例えばMOCVD法やMBE法などの公知の成膜手法にて形成される。 A strained superlattice layer is formed next to the buffer layer. The strained superlattice layer is a layer in which a combination (pair) of one Al X1 Ga 1-X1 N and the other Al X2 Ga 1-X2 N is alternately repeated, one having a thickness of 2 nm to 10 nm and the other having a thickness of It is preferable that the pair composition of this strained superlattice layer is 0.9 ≦ X1 ≦ 1.0, X2 + 0.65 ≦ X1 ≦ X2 + 0.75, and this pair is repeated 20 to 200 cycles. The total thickness of the strained superlattice layer is particularly preferably 1.0 μm to 6.0 μm. The composition difference of the pair is selected from the relationship of the critical film thickness of each strained superlattice layer. That is, when the thickness of each strained superlattice layer is increased, it is preferable that the difference in the composition of the pair is not large. Furthermore, the thickness ratio (t SL / t SUB ) between the thickness (t SL ) of the strained superlattice layer and the substrate (t SUB ) is preferably 0.001 to 0.014. The strained superlattice layer is also formed by a known film formation method such as MOCVD method or MBE method.
なお、歪超格子層の代わりに膜成長方向に連続または不連続に組成が変化する組成傾斜層でもよい。組成傾斜層を用いた本発明実施例2の半導体積層構造の概念図を図2に示す。この組成傾斜層はAlX3Ga1−X3Nなる組成であり、膜厚10nm〜100nm毎にX3が階段状に変化して膜成長方向に小さくなり、合計の膜厚は0.7μm〜2.5μmが好ましく、1.5μm〜2.5μmがより好ましい。そして、組成傾斜層の厚み(tCG)と基板(tSUB)の厚みの(比tCG/tSUB)が、0.0007〜0.0060が好ましい。なお、組成傾斜層も例えばMOCVD法やMBE法などの公知の成膜手法にて形成される。 Instead of the strained superlattice layer, a composition gradient layer whose composition changes continuously or discontinuously in the film growth direction may be used. FIG. 2 shows a conceptual diagram of the semiconductor laminated structure of Example 2 of the present invention using the composition gradient layer. The composition gradient layer is Al X3 Ga 1-X3 N having a composition, decreases in the direction of film growth for each film thickness 10 nm to 100 nm X3 is changed stepwise, the total thickness 0.7Myuemu~2. 5 micrometers is preferable and 1.5 micrometers-2.5 micrometers are more preferable. The thickness (t CG ) of the composition gradient layer and the thickness (ratio CG / t SUB ) of the substrate (t SUB ) are preferably 0.0007 to 0.0060. The composition gradient layer is also formed by a known film forming method such as MOCVD method or MBE method.
前記歪格子層または組成傾斜層に引続きデバイス層を形成する。例えば本発明の半導体積層構造をHEMT素子に利用する場合は、このデバイス層はチャネル層が厚み0.2μm〜5.0μmのAlX4Ga1−X4N(0≦X4≦0.1)からなるチャネル層とAlX5Ga1−X5N(0<X5<1)からなるバリア層からなる。ここで、チャネル層とバリア層との組成差は、X4+0.2≦X5≦X4+0.4、を満たすことが好ましい。チャネル層はGaN(X4=0)であることが特に好ましい。チャネル層の厚みは0.2μm〜5.0μmであることが好ましく、バリア層は10〜100nmであることが好ましい。チャネル層とバリア層の界面近傍に電子供給層が形成される。このデバイス層も例えばMOCVD法やMBE法などの公知の成膜手法にて形成される。 A device layer is formed subsequently to the strained lattice layer or the composition gradient layer. For example, when the semiconductor laminated structure of the present invention is used for a HEMT element, this device layer is made of Al X4 Ga 1-X4 N (0 ≦ X4 ≦ 0.1) having a channel layer thickness of 0.2 μm to 5.0 μm. It consists of a channel layer and a barrier layer made of Al X5 Ga 1-X5 N (0 <X5 <1). Here, the composition difference between the channel layer and the barrier layer preferably satisfies X4 + 0.2 ≦ X5 ≦ X4 + 0.4. The channel layer is particularly preferably GaN (X4 = 0). The thickness of the channel layer is preferably 0.2 μm to 5.0 μm, and the barrier layer is preferably 10 to 100 nm. An electron supply layer is formed in the vicinity of the interface between the channel layer and the barrier layer. This device layer is also formed by a known film formation method such as MOCVD or MBE.
上記のように、本発明の半導体積層構造は、基板上にバッファ層、歪超格子層、チャネル層、およびバリア層なるAlGaN系半導体層を順次設けた半導体積層構造であって、歪超格子層の膜厚(tSL)、チャネル層の膜厚(tCH)、および半導体層の総厚(tTOTAL)との関係が、0.75≦tSL/tTOTAL≦0.90、または0.75≦tSL/tSL+tCH≦0.90、であることが好ましく、この関係により本半導体積層構造の反りを小さくすることができる。そして、本半導体積層構造にソース、ゲート、およびドレインの電極を設けて、HEMT素子を作製することができる。 As described above, the semiconductor multilayer structure of the present invention is a semiconductor multilayer structure in which a buffer layer, a strained superlattice layer, a channel layer, and an AlGaN-based semiconductor layer as a barrier layer are sequentially provided on a substrate. The relationship between the film thickness (t SL ), the channel layer thickness (t CH ), and the total thickness (t TOTAL ) of the semiconductor layer is 0.75 ≦ t SL / t TOTAL ≦ 0.90, or It is preferable that 75 ≦ t SL / t SL + t CH ≦ 0.90, and this relationship can reduce the warpage of the semiconductor stacked structure. Then, the HEMT device can be manufactured by providing source, gate, and drain electrodes in the semiconductor stacked structure.
また同様に、本発明の半導体積層構造は、基板上にバッファ層、組成傾斜層、チャネル層、およびバリア層なるAlGaN系半導体層を順次設けた半導体積層構造であって、組成傾斜層のAl組成が膜成長方向に減少し、組成傾斜層の膜厚(tCG)、チャネル層の膜厚(tCH)、および半導体層の総厚(tTOTAL)との関係が、0.75≦tCG/tTOTAL≦0.90、または0.75≦tCG/tCG+tCH≦0.90、であることが好ましく、この関係により本半導体積層構造の反りを小さくすることができる。そして本半導体積層構造にソース、ゲート、およびドレインの電極を設けて、HEMT素子を作製することができる。 Similarly, the semiconductor multilayer structure of the present invention is a semiconductor multilayer structure in which an AlGaN-based semiconductor layer as a buffer layer, a composition gradient layer, a channel layer, and a barrier layer is sequentially provided on a substrate, and the Al composition of the composition gradient layer is Decreases in the film growth direction, and the relationship between the thickness of the composition gradient layer (t CG ), the thickness of the channel layer (t CH ), and the total thickness of the semiconductor layer (t TOTAL ) is 0.75 ≦ t CG It is preferable that / t TOTAL ≦ 0.90 or 0.75 ≦ t CG / t CG + t CH ≦ 0.90, and this relationship can reduce the warp of the present semiconductor stacked structure. The HEMT device can be manufactured by providing source, gate, and drain electrodes in the semiconductor multilayer structure.
一方、本発明の半導体積層構造において、基板上にバッファ層、歪超格子層あるいは組成傾斜層を設けた後、チャネル層とバリア層との代わりに、発光層を設けて、反りの小さい発光素子用の半導体積層構造を作製することができる。この場合、発光層は第1の導電型半導体層、活性層、および第1の導電型と反対の第2の導電型半導体層からなる。例えば、膜厚0.1μm〜1.0μmのn型半導体層、膜厚2nm〜20nmの活性層、および膜厚0.1μm〜1.0μmのp型半導体層を順次形成する。そして、好適にはn型半導体層およびp型半導体層としてGaN、活性層としてInGaNを用いることができる。この後、発光層上にカソード電極およびアノード電極を設ける、あるいは一方の電極を基板の他方の面(積層膜とは反対)に形成して発光素子を作製することができる。 On the other hand, in the semiconductor laminated structure of the present invention, after providing a buffer layer, a strained superlattice layer or a composition gradient layer on a substrate, a light emitting layer is provided instead of a channel layer and a barrier layer, and a light emitting element with small warpage A semiconductor laminated structure can be produced. In this case, the light emitting layer includes a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer opposite to the first conductive type. For example, an n-type semiconductor layer having a thickness of 0.1 μm to 1.0 μm, an active layer having a thickness of 2 nm to 20 nm, and a p-type semiconductor layer having a thickness of 0.1 μm to 1.0 μm are sequentially formed. Preferably, GaN can be used as the n-type semiconductor layer and p-type semiconductor layer, and InGaN can be used as the active layer. Thereafter, a cathode electrode and an anode electrode are provided on the light emitting layer, or one electrode is formed on the other surface of the substrate (opposite to the laminated film), whereby a light emitting element can be manufactured.
(実施例1:歪超格子層を用いた半導体積層構造)
本実施例においては、上述の実施形態に係る半導体積層構造を作製してウェーハの反りを測定した。まず、4インチ径の厚み525μmの(111)面シリコン(Si)単結晶を用い、これを所定のMOCVD装置の反応菅内に設置した。MOCVD装置は、キャリアガスあるいは反応ガスとして、少なくともH2、N2、TMG(トリメチルガリウム)、TMA(トリメチルアルミニウム)、およびNH3が、反応管内に供給可能とされている。キャリアガスとして水素を流量20SLM及び窒素を流量10SLMで流しながら、反応管内の圧力を100Torrに保ちつつ、基板を1210℃まで昇温した後、10分間保持し、基板のサーマルクリーニングを実施した。
(Example 1: Semiconductor laminated structure using strained superlattice layer)
In this example, the semiconductor multilayer structure according to the above-described embodiment was produced, and the warpage of the wafer was measured. First, a (111) plane silicon (Si) single crystal having a 4 inch diameter and a thickness of 525 μm was used and placed in a reaction vessel of a predetermined MOCVD apparatus. In the MOCVD apparatus, at least H 2 , N 2 , TMG (trimethyl gallium), TMA (trimethyl aluminum), and NH 3 can be supplied into the reaction tube as a carrier gas or a reaction gas. While flowing hydrogen as a carrier gas at a flow rate of 20 SLM and nitrogen at a flow rate of 10 SLM, while maintaining the pressure in the reaction tube at 100 Torr, the substrate was heated to 1210 ° C. and held for 10 minutes to perform thermal cleaning of the substrate.
その後、基板温度を下げて1030℃に保ちつつ、TMAとそのキャリアガスである水素を供給するとともに、NH3とそのキャリアガスである水素とを供給することにより、バッファ層として膜厚100nmのAlN層を最初に形成した。供給反応ガスのモル比、すなわち、第5族ガス/第3族ガス(NH3/TMA)の比は5600とし、反応管内の圧力は100Torrとした。 Thereafter, while the substrate temperature is lowered and maintained at 1030 ° C., TMA and hydrogen as its carrier gas are supplied, and NH 3 and hydrogen as its carrier gas are supplied to thereby form AlN having a film thickness of 100 nm as a buffer layer. A layer was first formed. The molar ratio of the supplied reaction gas, that is, the ratio of Group 5 gas / Group 3 gas (NH 3 / TMA) was 5600, and the pressure in the reaction tube was 100 Torr.
そして基板温度を1130℃にし、供給する反応ガスモル比(第5族ガス/第3族ガス)を4,000にして膜厚40nmのAl0.30Ga0.70Nを形成した。以上により、AlN層およびAl0.3Ga0.7Nからなるバッファ層を形成した。 Then, the substrate temperature was set to 1130 ° C., and the reaction gas molar ratio (Group 5 gas / Group 3 gas) to be supplied was set to 4,000 to form Al 0.30 Ga 0.70 N having a thickness of 40 nm. As described above, an AlN layer and a buffer layer made of Al 0.3 Ga 0.7 N were formed.
次に、基板温度を1130℃に維持したまま、歪超格子層を形成した。バッファ層同様に供給ガスとしてTMA、TMG、およびNH3の供給量を調整して、AlNとAl0.26Ga0.74Nをそれぞれ6nm、15nmの膜厚で交互に積層し、この一対を50周期、160周期、200周期の3種類を形成した。 Next, a strained superlattice layer was formed while maintaining the substrate temperature at 1130 ° C. As with the buffer layer, the supply amounts of TMA, TMG, and NH 3 are adjusted as supply gases, and AlN and Al 0.26 Ga 0.74 N are alternately stacked with a thickness of 6 nm and 15 nm, respectively. Three types of 50 cycles, 160 cycles, and 200 cycles were formed.
さらに、基板温度を1130℃維持したまま、圧力を100Torr、供給する反応ガスモル比(第5族ガス/第3族ガス)が2800となるように供給して、チャネル層として膜厚0〜2.13μm(膜厚6種類)のGaN層を形成した。 Further, while maintaining the substrate temperature at 1130 ° C., the pressure is 100 Torr, the reaction gas molar ratio (Group 5 gas / Group 3 gas) to be supplied is 2800, and the channel layer has a thickness of 0 to 2. A GaN layer having a thickness of 13 μm (6 kinds of film thickness) was formed.
チャネル層としてのGaN層の形成後、基板温度を1130℃維持したまま、供給する反応ガスモル比(第5族ガス/第3族ガス)を歪超格子層と同じように供給して、Al0.26Ga0.74Nなるバリア層を膜厚25nm形成した。以上により、半導体積層構造(実施例1)を得た。 After the formation of the GaN layer as the channel layer, while maintaining the substrate temperature 1130 ° C., and supplies for supplying reaction gas molar ratio (group 5 gas / Group 3 gas) like Ibitsucho grating layer, Al 0 A barrier layer of .26 Ga 0.74 N was formed to a thickness of 25 nm. Thus, a semiconductor multilayer structure (Example 1) was obtained.
上記のように、歪超格子層の合計膜厚(周期数)およびチャネル層の膜厚をそれぞれ変えて、半導体積層構造の反り量を測定した。その結果を表1に示す。半導体積層構造の反り量の測定は図3のように行い、基板のオリフラ方向とこれに直角方向の平均とした。 As described above, the amount of warpage of the semiconductor multilayer structure was measured by changing the total thickness (number of periods) of the strained superlattice layer and the thickness of the channel layer. The results are shown in Table 1. The amount of warpage of the semiconductor laminated structure was measured as shown in FIG. 3, and the average of the orientation flat direction of the substrate and the direction perpendicular thereto was taken.
(実施例2:組成傾斜層を用いた半導体積層構造)
本実施例においては、実施例1の歪超格子層に代えて、組成傾斜層を形成した。組成傾斜層としてAlX3Ga1−X3Nなる層は、基板温度を1130℃に維持し、圧力を100Torr、供給する反応ガスモル比(第5族ガス/第3族ガス)を5600から2800へと階段状に減少させながら、Al組成比のX3を1から0へと減少させ、膜厚2.1μmの組成傾斜層を形成した。膜厚50nm毎の階段状にAl組成を減少させた。またこの組成傾斜層下地のバッファ層としてAlN層140nmを基板温度1130℃で形成し、チャネル層としてGaN層を膜厚0〜1.7μmの6種類を形成すること以外は、基板含めて実施例1と同様の膜形成条件で半導体積層構造を形成した。
(Example 2: Semiconductor laminated structure using composition gradient layer)
In this example, a composition gradient layer was formed in place of the strained superlattice layer of Example 1. The layer composed of Al X3 Ga 1-X3 N as the composition gradient layer maintains the substrate temperature at 1130 ° C., the pressure is 100 Torr, and the reaction gas molar ratio (Group 5 gas / Group 3 gas) is increased from 5600 to 2800. While decreasing stepwise, the Al composition ratio X3 was decreased from 1 to 0 to form a composition gradient layer having a thickness of 2.1 μm. The Al composition was decreased stepwise every 50 nm. In addition, the substrate including the substrate is formed except that an AlN layer of 140 nm is formed at a substrate temperature of 1130 ° C. as a buffer layer under the composition gradient layer, and six types of GaN layers having a film thickness of 0 to 1.7 μm are formed as a channel layer. A semiconductor multilayer structure was formed under the same film formation conditions as in No. 1.
上記のように、チャネル層の膜厚を変えて半導体積層構造の反り量を測定した。その結果を表2に示す。 As described above, the warpage amount of the semiconductor multilayer structure was measured by changing the thickness of the channel layer. The results are shown in Table 2.
表1および表2の結果に基づき、歪超格子層の膜厚(tSL)の半導体層の総厚(tTOTAL)に対する比、および、組成傾斜層の膜厚(tCG)の半導体層の総厚(tTOTAL)に対する比と反り量との関係を図4に示す。 Based on the results of Table 1 and Table 2, the ratio of the thickness of the strained superlattice layer (t SL ) to the total thickness (t TOTAL ) of the semiconductor layer, and the thickness of the composition gradient layer (t CG ) of the semiconductor layer FIG. 4 shows the relationship between the ratio of the total thickness (t TOTAL ) and the amount of warpage.
表1および表2の結果に基づき、歪超格子層の膜厚(tSL)の、歪超格子層の膜厚(tSL)とチャネル層(tCH)の膜厚との合計に対する比、および組成傾斜層の膜厚(tCG)の、組成傾斜層の膜厚(tCG)とチャネル層(tCH)の膜厚との合計に対する比を求め、これらの比と反り量との関係を図5に示す。 Based on the results of Table 1 and Table 2, the thickness of the strained superlattice layer (t SL), the ratio to the sum of the thickness of the film thickness of the strained superlattice layer (t SL) and the channel layer (t CH), and the thickness of the composition gradient layer (t CG), obtains the ratio of the sum of the thickness of the film thickness of the composition gradient layer (t CG) and channel layer (t CH), relationship between these ratios and warpage Is shown in FIG.
図4より、0.75≦tSL/tTOTAL≦0.90、0.75≦tCG/tTOTAL≦0.90の場合に反り量が小さくなることが分かる。一方、図5より、0.75≦tSL/(tSL+tCH)≦0.90、0.75≦tCG/(tCG+tCH)≦0.90の場合に反り量が小さくなることが分かる。すなわち、歪超格子層あるいは組成傾斜層がその上に形成するデバイス層に対して相対的に膜厚が大きいと反りが小さいことが分かる。 Than 4, it can be seen that the warp amount is small in the case of 0.75 ≦ t SL / t TOTAL ≦ 0.90,0.75 ≦ t CG / t TOTAL ≦ 0.90. On the other hand, as shown in FIG. 5, the amount of warpage decreases when 0.75 ≦ t SL / (t SL + t CH ) ≦ 0.90 and 0.75 ≦ t CG / (t CG + t CH ) ≦ 0.90. I understand. That is, it can be seen that the warp is small when the strained superlattice layer or the composition gradient layer is relatively thick with respect to the device layer formed thereon.
次に、表1に記載の実施例1−12、1−13、および1−14の半導体エピタキシャル基板を用いてHEMT素子を試作し、ストレス印加前後でのしきい値電圧の変化を調べた。作製した素子寸法は、ゲート長が1.5μm、ゲート幅が200μm、ソース‐ドレイン間隔が9.5μm、ゲート‐ドレイン間隔が4.0μmである。ゲート電極にはPb(40nm)/Ti(20nm)/Au(60nm)を用いた。ソース電極およびドレイン電極にはTi(15nm)/Al(80nm)/Ni(12nm)/Au(40nm)を用いた。ストレスの印加条件は、ソース‐ゲート電極間に−10Vの一定電圧を印加し、ソース‐ドレイン間には5Vから40Vの電圧を5Vステップで印加し各状態を600秒間保持し、ストレスを印加した。ストレス印加前後でのしきい値電圧(Vth)および相互コンダクタンス(gm)の変化を表3に示す。各しきい値電圧および相互コンダクタンスの値はそれぞれ5個の素子の平均値を示す。 Next, HEMT devices were prototyped using the semiconductor epitaxial substrates of Examples 1-12, 1-13, and 1-14 shown in Table 1, and changes in threshold voltage before and after stress application were examined. The dimensions of the fabricated device are a gate length of 1.5 μm, a gate width of 200 μm, a source-drain distance of 9.5 μm, and a gate-drain distance of 4.0 μm. Pb (40 nm) / Ti (20 nm) / Au (60 nm) was used for the gate electrode. Ti (15 nm) / Al (80 nm) / Ni (12 nm) / Au (40 nm) were used for the source electrode and the drain electrode. The stress was applied by applying a constant voltage of -10V between the source and gate electrodes, applying a voltage of 5V to 40V in 5V steps between the source and drain, and holding each state for 600 seconds, and applying stress. . Table 3 shows changes in threshold voltage (V th ) and transconductance (g m ) before and after stress application. Each threshold voltage and transconductance value represents an average value of five elements.
反り量の大きい実施例1−12と実施例1−14のエピタキシャル基板では、ストレス印加前後でしきい値電圧および相互コンダクタンスが変動する。一方、反り量が他の実施例より小さな実施例1−13のエピタキシャル基板では、ストレス印加前後でのしきい値電圧および相互コンダクタンスの変化はない。 In the epitaxial substrates of Examples 1-12 and 1-14 with a large amount of warpage, the threshold voltage and the mutual conductance fluctuate before and after stress application. On the other hand, in the epitaxial substrate of Example 1-13 whose warpage amount is smaller than that of the other examples, there is no change in the threshold voltage and the mutual conductance before and after the stress application.
なお、実施例2の膜厚2.1μmの組成傾斜層の代わりに膜厚1.1μmの組成傾斜層とした場合の半導体積層構造の反り量は、図4および図5における歪超格子層の反り量の曲線と近似しており、総膜厚1.05μmの歪超格子層の場合の反り量に対して±10μm以下の差異であった。 In addition, the amount of warpage of the semiconductor multilayer structure in the case of using a composition gradient layer with a film thickness of 1.1 μm instead of the composition gradient layer with a film thickness of 2.1 μm in Example 2 is the same as that of the strained superlattice layer in FIGS. The curve approximates the curve of the warp amount, and the difference is ± 10 μm or less with respect to the warp amount in the case of a strained superlattice layer having a total film thickness of 1.05 μm.
実施例1および実施例2では、4インチ径の厚み525μmの(111)面Si単結晶を基板に用いたが、同じ4インチ径で厚みを900μmの(111)面Si単結晶を基板とし、歪超格子層を用いた半導体積層構造の反りを調べた。厚み525μmのSi単結晶基板に比べて相対的に反りは小さくなったが、歪超格子層の膜厚の半導体層の総厚(tTOTALに対する比、さらに、歪超格子層の膜厚の、歪超格子層の膜厚とチャネル層の膜厚との合計に対する比、が実施例1と同様の関係であると反りが小さく、したがって歪超格子層の膜厚の基板の厚みに対する比も実施例1と同様に0.001〜0.014であるとよいことが分かった。 In Example 1 and Example 2, a (111) plane Si single crystal having a 4 inch diameter and a thickness of 525 μm was used as the substrate, but the same 4 inch diameter and a (111) plane Si single crystal having a thickness of 900 μm was used as the substrate. The warpage of the semiconductor multilayer structure using the strained superlattice layer was investigated. Although the warpage was relatively small as compared with the Si single crystal substrate having a thickness of 525 μm, the total thickness of the semiconductor layer of the strained superlattice layer (ratio to t TOTAL , and further the thickness of the strained superlattice layer, The warp is small when the ratio of the film thickness of the strained superlattice layer and the film thickness of the channel layer is the same as in Example 1, so the ratio of the film thickness of the strained superlattice layer to the thickness of the substrate is also implemented. It turned out that it is good to be 0.001-0.014 similarly to Example 1.
本発明の半導体積層構造は、電界効果トランジスタ(FET、HEMT)あるいは発光素子等の半導体素子に用いられる。
The semiconductor laminated structure of the present invention is used for a semiconductor element such as a field effect transistor (FET, HEMT) or a light emitting element.
Claims (20)
The light emitting element using the semiconductor laminated structure in any one of Claims 4-8 and 12-16.
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Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015192004A (en) * | 2014-03-28 | 2015-11-02 | 国立大学法人 名古屋工業大学 | Mis type normally-off hemt element of recess structure having drain current density/transconductance improved greatly |
JP2016031961A (en) * | 2014-07-28 | 2016-03-07 | 国立大学法人 名古屋工業大学 | Large-current and high-withstand voltage nitride semiconductor vertical schottky barrier diode |
JP2016149410A (en) * | 2015-02-10 | 2016-08-18 | Dowaエレクトロニクス株式会社 | Epitaxial substrate for electronic device and high electron mobility transistor, and methods of manufacturing them |
JP2016195248A (en) * | 2015-04-01 | 2016-11-17 | 環球晶圓股▲ふん▼有限公司 | Semiconductor device |
JP2022533787A (en) * | 2019-05-24 | 2022-07-25 | プレッシー・セミコンダクターズ・リミテッド | Light-emitting diode precursor containing passivation layer |
WO2023120143A1 (en) * | 2021-12-23 | 2023-06-29 | 信越半導体株式会社 | Nitride semiconductor substrate and method for manufacturing same |
Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000277441A (en) * | 1999-03-26 | 2000-10-06 | Nagoya Kogyo Univ | Semiconductor structure, semiconductor element comprising the same and crystal growth method |
JP2001230447A (en) * | 2000-02-16 | 2001-08-24 | Toyoda Gosei Co Ltd | Manufacture method for iii nitride-based compound semiconductor element |
JP2003059948A (en) * | 2001-08-20 | 2003-02-28 | Sanken Electric Co Ltd | Semiconductor device and production method therefor |
JP2003060234A (en) * | 2001-08-20 | 2003-02-28 | Sanken Electric Co Ltd | Semiconductor light-emitting element and manufacturing method therefor |
JP2005536873A (en) * | 2002-07-19 | 2005-12-02 | クリー インコーポレイテッド | Strain-compensating semiconductor structure and method of fabricating a strain-compensating semiconductor structure |
JP2007067077A (en) * | 2005-08-30 | 2007-03-15 | Nippon Telegr & Teleph Corp <Ntt> | Nitride semiconductor device and method of manufacturing same |
JP2009158804A (en) * | 2007-12-27 | 2009-07-16 | Dowa Electronics Materials Co Ltd | Semiconductor material, method for manufacturing semiconductor material, and semiconductor element |
JP2009188252A (en) * | 2008-02-07 | 2009-08-20 | Furukawa Electric Co Ltd:The | Semiconductor electronic device |
JP2011100772A (en) * | 2009-11-04 | 2011-05-19 | Dowa Electronics Materials Co Ltd | Group iii nitride laminated substrate |
JP2011187654A (en) * | 2010-03-08 | 2011-09-22 | Toyoda Gosei Co Ltd | Hemt composed of group-iii nitride semiconductor, and method of manufacturing the same |
-
2012
- 2012-07-23 JP JP2012162720A patent/JP2014022685A/en active Pending
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000277441A (en) * | 1999-03-26 | 2000-10-06 | Nagoya Kogyo Univ | Semiconductor structure, semiconductor element comprising the same and crystal growth method |
JP2001230447A (en) * | 2000-02-16 | 2001-08-24 | Toyoda Gosei Co Ltd | Manufacture method for iii nitride-based compound semiconductor element |
JP2003059948A (en) * | 2001-08-20 | 2003-02-28 | Sanken Electric Co Ltd | Semiconductor device and production method therefor |
JP2003060234A (en) * | 2001-08-20 | 2003-02-28 | Sanken Electric Co Ltd | Semiconductor light-emitting element and manufacturing method therefor |
JP2005536873A (en) * | 2002-07-19 | 2005-12-02 | クリー インコーポレイテッド | Strain-compensating semiconductor structure and method of fabricating a strain-compensating semiconductor structure |
JP2007067077A (en) * | 2005-08-30 | 2007-03-15 | Nippon Telegr & Teleph Corp <Ntt> | Nitride semiconductor device and method of manufacturing same |
JP2009158804A (en) * | 2007-12-27 | 2009-07-16 | Dowa Electronics Materials Co Ltd | Semiconductor material, method for manufacturing semiconductor material, and semiconductor element |
JP2009188252A (en) * | 2008-02-07 | 2009-08-20 | Furukawa Electric Co Ltd:The | Semiconductor electronic device |
JP2011100772A (en) * | 2009-11-04 | 2011-05-19 | Dowa Electronics Materials Co Ltd | Group iii nitride laminated substrate |
JP2011187654A (en) * | 2010-03-08 | 2011-09-22 | Toyoda Gosei Co Ltd | Hemt composed of group-iii nitride semiconductor, and method of manufacturing the same |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015192004A (en) * | 2014-03-28 | 2015-11-02 | 国立大学法人 名古屋工業大学 | Mis type normally-off hemt element of recess structure having drain current density/transconductance improved greatly |
JP2016031961A (en) * | 2014-07-28 | 2016-03-07 | 国立大学法人 名古屋工業大学 | Large-current and high-withstand voltage nitride semiconductor vertical schottky barrier diode |
JP2016149410A (en) * | 2015-02-10 | 2016-08-18 | Dowaエレクトロニクス株式会社 | Epitaxial substrate for electronic device and high electron mobility transistor, and methods of manufacturing them |
JP2016195248A (en) * | 2015-04-01 | 2016-11-17 | 環球晶圓股▲ふん▼有限公司 | Semiconductor device |
JP2022533787A (en) * | 2019-05-24 | 2022-07-25 | プレッシー・セミコンダクターズ・リミテッド | Light-emitting diode precursor containing passivation layer |
JP7447151B2 (en) | 2019-05-24 | 2024-03-11 | プレッシー・セミコンダクターズ・リミテッド | Light emitting diode precursor including passivation layer |
WO2023120143A1 (en) * | 2021-12-23 | 2023-06-29 | 信越半導体株式会社 | Nitride semiconductor substrate and method for manufacturing same |
JP2023094473A (en) * | 2021-12-23 | 2023-07-05 | 信越半導体株式会社 | Nitride semiconductor substrate and production method thereof |
JP7388422B2 (en) | 2021-12-23 | 2023-11-29 | 信越半導体株式会社 | Method for manufacturing nitride semiconductor substrate |
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