JP2016031961A - Large-current and high-withstand voltage nitride semiconductor vertical schottky barrier diode - Google Patents
Large-current and high-withstand voltage nitride semiconductor vertical schottky barrier diode Download PDFInfo
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本発明は、ショットキーバリアダイオード、特にＳｉ基板を用いたショットキーバリアダイオードに係る。 The present invention relates to a Schottky barrier diode, and more particularly to a Schottky barrier diode using a Si substrate.
ＧａＮ等窒化物半導体をパワーデバイスに用いる場合、大電流化、高耐圧化、小型化等が求められる。Ｓｉ基板上のＧａＮ系デバイスとして、ショットキーバリアダイオード構造（図１および図２参照、非特許文献１および非特許文献２参照）、またＡｌＧａＮ/ＧａＮ ＨＥＭＴ構造（図３参照）が知られているが、これらの構造はオーミック電極、ショットキー電極ともに素子表面側に設けており、また電流の流れは横方向（基板面に平行方向）である。そのため、どの構造も製造プロセスが複雑であり、また電流パスが制限され、大きな電流が得られないという問題がある。 When a nitride semiconductor such as GaN is used for a power device, a large current, a high breakdown voltage, miniaturization, etc. are required. Known GaN-based devices on a Si substrate include a Schottky barrier diode structure (see FIGS. 1 and 2, Non-Patent Document 1 and Non-Patent Document 2), and an AlGaN / GaN HEMT structure (see FIG. 3). However, in these structures, both the ohmic electrode and the Schottky electrode are provided on the element surface side, and the current flow is in the lateral direction (parallel to the substrate surface). For this reason, the manufacturing process is complicated in any structure, and the current path is limited, and a large current cannot be obtained.
本発明の課題は、Ｓｉ基板上の窒化物半導体により構成されたショットキーバリアダイオードにおいて、大電流化、高耐圧化、小型化を図ることである。 An object of the present invention is to increase the current, increase the breakdown voltage, and reduce the size of a Schottky barrier diode formed of a nitride semiconductor on a Si substrate.
本発明者らは、基板面に垂直方向に電流を流す構造を創案した。すなわち、本発明によれば、以下のショットキーバリアダイオードが提供される。 The inventors of the present invention have invented a structure in which current flows in a direction perpendicular to the substrate surface. That is, according to the present invention, the following Schottky barrier diode is provided.
［１］ｎ＋-Ｓｉ基板上に少なくともＡｌＸＧａ１−ＸＮバッファ層およびｎ−‐ＧａＮ層を含む積層構造のショットキーバリアダイオードであって、積層構造の表面にショットキー電極、前記Ｓｉ基板裏面にオーミック電極が形成され、電流を積層方向に流すショットキーバリアダイオード。 [1] A Schottky barrier diode having a laminated structure including at least an Al X Ga 1-X N buffer layer and an n − -GaN layer on an n + -Si substrate, the Schottky electrode on the surface of the laminated structure, the Si A Schottky barrier diode in which an ohmic electrode is formed on the backside of the substrate and current flows in the stacking direction.
［２］ＡｌＸＧａ１−ＸＮバッファ層およびｎ−‐ＧａＮ層との間に超格子層が形成され、超格子層の一方の組成がＡｌＮであり、他方の組成がＡｌＹＧａ１−ＹＮであり、Ｙ：０〜０．３０である前記［１］請求項１に記載のショットキーバリアダイオード。 [2] A superlattice layer is formed between the Al X Ga 1- XN buffer layer and the n − -GaN layer, and one composition of the superlattice layer is AlN, and the other composition is Al Y Ga 1− The Schottky barrier diode according to claim 1, wherein Y is N, and Y is 0 to 0.30.
［３］前記ＡｌＸＧａ１−ＸＮバッファ層において、Ｘ≧０．３０、膜厚が１ｎｍ〜１０ｎｍである前記［１］または［２］に記載のショットキーバリアダイオード。 [3] The Schottky barrier diode according to the above [1] or [2], wherein the Al X Ga 1-X N buffer layer has X ≧ 0.30 and a film thickness of 1 nm to 10 nm.
［４］前記ＡｌＸＧａ１−ＸＮバッファ層および歪超格子層にＳｉがドープされた前記［１］〜［３］のいずれかに記載のショットキーバリアダイオード。 [4] The Schottky barrier diode according to any one of [1] to [3], wherein the Al X Ga 1-X N buffer layer and the strained superlattice layer are doped with Si.
［５］前記ｎ−‐ＧａＮ層のキャリア密度が５×１０１５〜２×１０１７ｃｍ−３である前記［１］〜［４］のいずれかに記載のショットキーバリアダイオード。 [5] The Schottky barrier diode according to any one of [1] to [4], wherein the n − -GaN layer has a carrier density of 5 × 10 15 to 2 × 10 17 cm −3 .
［６］前記積層構造表面に絶縁膜またはｐ‐ＧａＮ層が形成され、その一部が前記ショットキー電極と重なる前記［１］〜［５］のいずれかに記載のショットキーバリアダイオード。 [6] The Schottky barrier diode according to any one of [1] to [5], wherein an insulating film or a p-GaN layer is formed on the surface of the stacked structure, and a part thereof overlaps the Schottky electrode.
以下、図面を参照しつつ本発明の実施の形態について説明する。本発明は、以下の実施形態に限定されるものではなく、発明の範囲を逸脱しない限りにおいて、変更、修正、改良を加え得るものである。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. The present invention is not limited to the following embodiments, and changes, modifications, and improvements can be added without departing from the scope of the invention.
本発明において基板は、その上に形成するバッファ層（緩衝層）、歪超格子層、およびｎ−‐ＧａＮ層の各組成あるいは形成手法に応じて適宜に選択される。例えば、基板としては、シリコン、ゲルマニウム、サファイア、炭化ケイ素、酸化物(ＺｎＯ、ＬｉＡｌＯ２，ＬｉＧａＯ２，ＭｇＡｌ２Ｏ４，（ＬａＳｒ）（ＡｌＴａ）Ｏ３，ＮｄＧａＯ３，ＭｇＯなど)、Ｓｉ-Ｇｅ合金、周期律表の第３族−第５族化合物(ＧａＡｓ，ＡｌＮ，ＧａＮ，ＡｌＧａＮ、ＡｌＩｎＮ)、ホウ化物(ＺｒＢ２など)、などを用いることができる。ただし、室温〜１２００℃における前記基板の熱膨張係数が基板上に形成するＡｌＸＧａ１−ＸＮからなる膜の熱膨張係数より小さいことが好ましく、なかでもＳｉ基板が品質およびコストの点で好ましく、Ｓｉ単結晶が特に好ましく、基板の厚みとしては０．４２〜１．００ｍｍが好適である。 In the present invention, the substrate is appropriately selected according to each composition or formation method of the buffer layer (buffer layer), strained superlattice layer, and n − -GaN layer formed thereon. For example, as a substrate, silicon, germanium, sapphire, silicon carbide, oxide (ZnO, LiAlO 2 , LiGaO 2 , MgAl 2 O 4 , (LaSr) (AlTa) O 3 , NdGaO 3 , MgO, etc.), Si—Ge An alloy, a Group 3 to Group 5 compound of the periodic table (GaAs, AlN, GaN, AlGaN, AlInN), boride (such as ZrB2), and the like can be used. However, the thermal expansion coefficient of the substrate at room temperature to 1200 ° C. is preferably smaller than the thermal expansion coefficient of the film made of Al X Ga 1-X N formed on the substrate, and the Si substrate is particularly preferable in terms of quality and cost. Preferably, Si single crystal is particularly preferable, and the thickness of the substrate is preferably 0.42 to 1.00 mm.
バッファ層は、その上に形成するデバイス層の組成や構造、あるいは各層の形成手法に応じて、様々な第３族窒化物半導体からなる層から形成される。本発明では、バッファ層はＡｌＸＧａ１−ＸＮからなり、Ｘ≧０．３０であり、Ｘ≧０．７０がより好ましい。Ｘ＝１が特に好ましい。膜厚として１ｎｍ〜３０ｎｍが好ましく、１ｎｍ〜１０ｎｍがより好ましく、３ｎｍ〜１０ｎｍさらに好ましい。このバッファ層は、例えばＭＯＣＶＤ法やＭＢＥ法などの公知の成膜手法にて形成される。歪や転位密度ができるだけ少ない膜構造とすることが好ましく、後に形成される膜の品質に影響するため、転位密度は１×１０１１ｃｍ−２以下に形成することが好ましい。なお、バッファ層とデバイス層のｎ−‐ＧａＮ層との間に、更なる格子歪低減のため、超格子層を形成することが好ましい。超格子層としては、一方の組成がＡｌＮであり、他方の組成がＡｌＹＧａ１−ＹＮであり、Ｙが０〜０．３０であることが好ましい。そして、超格子の一対がＡｌＮとＡｌＹＧａ１−ＹＮの場合、その膜厚比（ＡｌＮ：ＡｌＹＧａ１−ＹＮ）が１：２〜１：５が好ましい。また、ＡｌＮバッファ層および歪超格子層にＳｉがドープされることが、ショットキーバリアダイオードの直列抵抗成分の低減のためにより好ましい。 The buffer layer is formed of various Group 3 nitride semiconductor layers depending on the composition and structure of the device layer formed thereon or the method of forming each layer. In the present invention, the buffer layer is made of Al X Ga 1-X N, and X ≧ 0.30, and more preferably X ≧ 0.70. X = 1 is particularly preferred. The film thickness is preferably 1 nm to 30 nm, more preferably 1 nm to 10 nm, and even more preferably 3 nm to 10 nm. This buffer layer is formed by a known film formation method such as MOCVD method or MBE method. It is preferable that the film structure has as little strain and dislocation density as possible, and the dislocation density is preferably 1 × 10 11 cm −2 or less in order to affect the quality of a film to be formed later. A superlattice layer is preferably formed between the buffer layer and the n − -GaN layer of the device layer in order to further reduce lattice strain. The superlattice layers, where one composition is AlN, other compositions are Al Y Ga 1-Y N, it is preferable Y is from 0 to 0.30. When a pair of superlattice of AlN and Al Y Ga 1-Y N, the film thickness ratio (AlN: Al Y Ga 1- Y N) is 1: 2 to 1: 5 are preferred. Further, it is more preferable that the AlN buffer layer and the strained superlattice layer are doped with Si in order to reduce the series resistance component of the Schottky barrier diode.
本発明の場合は、バッファ層、超格子層に引き続き、膜厚０．５μｍ〜２．０μｍのｎ−‐ＧａＮ層が形成される。ｎ−‐ＧａＮ層は、ＧａＮにＳｉＨ４を用いてキャリア密度が５×１０１５〜２×１０１７ｃｍ−３になるようにＳｉをドープしてｎ型として形成する。 In the present invention, an n − -GaN layer having a thickness of 0.5 μm to 2.0 μm is formed following the buffer layer and the superlattice layer. The n − -GaN layer is formed as n-type by doping Si with GaN using SiH 4 so that the carrier density is 5 × 10 15 to 2 × 10 17 cm −3 .
ｎ−‐ＧａＮ層の表面の素子中央部となる領域以外にはＳｉＯ２等の絶縁層あるいはＰ型ＧａＮ層を形成することが好ましい。ＳｉＯ２等の絶縁層あるいはＰ型ＧａＮ層が形成されない素子中央部の領域にショットキー電極、一方基板裏面にはオーミック電極が形成される。たとえば、ショットキー電極としてはＰｄＴｉＡｕ、オーミック電極としてはＡｕＳｂ／Ａｕが形成される。 An insulating layer such as SiO 2 or a P-type GaN layer is preferably formed in a region other than the central portion of the element on the surface of the n − -GaN layer. A Schottky electrode is formed in a central region of the element where an insulating layer such as SiO 2 or a P-type GaN layer is not formed, and an ohmic electrode is formed on the back surface of the substrate. For example, PdTiAu is formed as the Schottky electrode, and AuSb / Au is formed as the ohmic electrode.
（実施例１：ｎ−‐ＧａＮ層のＳｉドーピング特性）
４インチ径、厚み５２５μｍの（１１１）面のｎ＋‐Ｓｉ基板（抵抗率０.００４Ω・ｃｍ以下）を用い、この基板をＭＯＣＶＤ装置の反応管内に設置した。ＭＯＣＶＤ装置は、キャリアガスとしてＨ２、Ｎ２、反応ガスとして、ＴＭＧ（トリメチルガリウム）、ＴＭＡ（トリメチルアルミニウム）およびＮＨ３が反応管に供給可能とされている。キャリアガスとして水素を流量２０ＳＬＭ、及び窒素を流量１０ＳＬＭで流しながら、反応管内の圧力を１００Ｔｏｒｒに保ちつつ、基板を１２１０℃まで昇温した後、１０分間保持し、基板のサーマルクリーニングを実施した。
その後、基板温度を下げて１０３０℃に保ちつつ、ＴＭＡとそのキャリアガスである水素を供給するとともに、ＮＨ３とそのキャリアガスである水素とを供給することにより、バッファ層として膜厚５ｎｍのＡｌＮ層を最初に形成した。供給反応ガスのモル比、すなわち、第５族ガス／第３族ガス（ＮＨ３／ＴＭＡ）の比は５６００とし、反応管内の圧力は１００Ｔｏｒｒ、ＳｉＨ４の流量は１００ＳＣＣＭとした。なお、同じ条件で、ＡｌＮ層の膜厚５ｎｍ以外に、膜厚２０ｎｍ，８０ｎｍの２種類を準備した。
次に、基板温度を１１３０℃にし、ＧａＮ層／ＡｌＮ層からなる超格子層を形成した。バッファ層同様に、供給ガスとしてＴＭＡ、ＴＭＧ、およびＮＨ３の供給量を調整して、反応管内の圧力は１００Ｔｏｒｒ、ＳｉＨ４の流量は１００ＳＣＣＭとした。ＧａＮ層とＡｌＮ層をそれぞれ２０ｎｍ、５ｎｍの膜厚で交互に積層し、超格子層として３．０μｍ厚とした。
基板温度を１１３０℃維持したまま、圧力を７６０Ｔｏｒｒ、供給する反応ガスモル比（第５族ガス／第３族ガス）が２８００となるように供給して、膜厚１．０μｍのｎ‐ＧａＮ層を形成した。モノシラン(ＳiＨ４)の流量を０．１５ＳＣＣＭ〜８．０ＳＣＣＭと変化させた。
図６に示す積層構造にて、ｎ-ＧａN層へのＳｉＨ４を用いたＳｉのドーピング特性の評価を行った。ＡｌＮ層は、成長温度１０３０℃、圧力１００Ｔｏｒｒ、膜厚５ｎｍ、歪超格子は成長温度１０３０℃、圧力１００Ｔｏｒｒ、その膜構成はＧａＮ（２０ｎｍ）／ＡｌＮ（５ｎｍ）の合計１２０層、ｎ‐ＧａＮ層は１１３０℃、圧力７６０Ｔｏｒｒ、膜厚１μｍとした。
キャリア密度の測定は、容量−電圧（Ｃ−Ｖ）法を用いて行った（図７参照）。ｎ−ＧａＮ層の表層１μｍまではＳiＨ４の流量を増加とともにキャリア密度は増加するが、より深い部位での特定の傾向は見いだせなかった。また転位密度はＸ線の半値幅を用いて求めた。ＡｌＮの膜厚が５ｎｍの場合は、転位密度が１×１０１１ｃｍ−２ 、ＳiＨ４の供給量に対するキャリア密度（５×１０１５〜１×１０１８ｃｍ−３）の制御が容易である。これに対して、ＡｌＮ層の膜厚が２０ｎｍおよび８０ｎｍの場合、転位密度が５×１０１１ｃｍ−２と大きく、またＳiＨ４の供給量に対するキャリア密度変化（１×１０１５〜１×１０１７ｃｍ−３）と変化が大きく、その制御が困難である（図８参照）。
Example 1: Si doping characteristics of n − -GaN layer
A (111) -plane n + -Si substrate (resistivity 0.004 Ω · cm or less) having a diameter of 4 inches and a thickness of 525 μm was used, and this substrate was placed in a reaction tube of an MOCVD apparatus. The MOCVD apparatus can supply H 2 and N 2 as carrier gases and TMG (trimethyl gallium), TMA (trimethyl aluminum) and NH 3 as reaction gases to the reaction tube. While flowing hydrogen as a carrier gas at a flow rate of 20 SLM and nitrogen at a flow rate of 10 SLM, while maintaining the pressure in the reaction tube at 100 Torr, the substrate was heated to 1210 ° C. and then held for 10 minutes to perform thermal cleaning of the substrate.
Thereafter, while the substrate temperature is lowered and maintained at 1030 ° C., TMA and hydrogen as its carrier gas are supplied, and NH 3 and hydrogen as its carrier gas are supplied to thereby form a 5 nm-thick AlN film as a buffer layer. A layer was first formed. The molar ratio of the supplied reaction gas, that is, the ratio of Group 5 gas / Group 3 gas (NH 3 / TMA) was 5600, the pressure in the reaction tube was 100 Torr, and the flow rate of SiH 4 was 100 SCCM. Under the same conditions, two types of film thicknesses of 20 nm and 80 nm were prepared in addition to the film thickness of the AlN layer of 5 nm.
Next, the substrate temperature was set to 1130 ° C. to form a superlattice layer composed of a GaN layer / AlN layer. Similarly to the buffer layer, the supply amounts of TMA, TMG, and NH 3 were adjusted as supply gases, the pressure in the reaction tube was 100 Torr, and the flow rate of SiH 4 was 100 SCCM. A GaN layer and an AlN layer were alternately stacked with a thickness of 20 nm and 5 nm, respectively, to obtain a thickness of 3.0 μm as a superlattice layer.
While maintaining the substrate temperature at 1130 ° C., the pressure was set to 760 Torr, the reaction gas molar ratio (Group 5 gas / Group 3 gas) to be supplied was set to 2800, and an n-GaN layer having a thickness of 1.0 μm was formed. Formed. The flow rate of monosilane (SiH 4 ) was changed from 0.15 SCCM to 8.0 SCCM.
In the laminated structure shown in FIG. 6, the doping characteristics of Si using SiH 4 to the n-GaN layer were evaluated. The AlN layer has a growth temperature of 1030 ° C., a pressure of 100 Torr, a film thickness of 5 nm, the strained superlattice has a growth temperature of 1030 ° C., a pressure of 100 Torr, and the film structure is a total of 120 layers of GaN (20 nm) / AlN (5 nm), n-GaN layer Was 1130 ° C., pressure 760 Torr, and film thickness 1 μm.
The carrier density was measured using a capacitance-voltage (CV) method (see FIG. 7). Although the carrier density increases with an increase in the flow rate of SiH 4 up to the surface layer of 1 μm of the n-GaN layer, a specific tendency in a deeper part was not found. The dislocation density was determined using the half width of X-rays. When the film thickness of AlN is 5 nm, the dislocation density is 1 × 10 11 cm −2 and the carrier density (5 × 10 15 to 1 × 10 18 cm −3 ) with respect to the supply amount of SiH 4 can be easily controlled. On the other hand, when the film thickness of the AlN layer is 20 nm and 80 nm, the dislocation density is as large as 5 × 10 11 cm −2, and the carrier density change (1 × 10 15 to 1 × 10 17 with respect to the SiH 4 supply amount). cm −3 ) and the change is large, and its control is difficult (see FIG. 8).
（実施例２：ＳｉＯ２絶縁膜を有するＧａＮショットキーバリアダイオード）
実施例１の構造（図６）および同じプロセスにおいて、ｎ−ＧａＮ層へのＳｉＨ４の流量を０.４ＳＣＣＭとして結晶成長を行った後、Ｓｉ基板の裏面に電子ビーム蒸着法を用いて、ＡｕＳｂ／Ａｕ（２０ｎｍ／１００ｎｍ) 蒸着し、その後３００℃でアニールし、Ｓｉ基板裏面のオーミック電極を形成した。その後、素子表面側において電子ビーム蒸着法によりＳｉＯ２絶縁膜１００ｎｍを蒸着し、部分的にＳｉＯ２膜を除去した。さらにフォトリソグラフィ技術とリフトオフ法を用いてショットキー電極としてＰｄ／Ｔｉ／Ａｕ (４０ｎｍ／２０ｎｍ／６０ｎｍ)を電子ビーム蒸着法により形成した。チップサイズは１×１ｍｍ２とした。
当ショットキーバリアダイオードの電流−電圧特性を測定したところ、立ち上がり電圧：１．４Ｖ、順方向電圧：２．１Ｖ（@順方向電流：８Ａ）、耐圧：８５０Ｖであった。
(Example 2: GaN Schottky barrier diode having SiO2 insulating film)
In the structure of Example 1 (FIG. 6) and the same process, after crystal growth was performed with the flow rate of SiH 4 to the n-GaN layer being 0.4 SCCM, the back surface of the Si substrate was subjected to electron beam evaporation, and AuSb / Au (20 nm / 100 nm) was deposited, and then annealed at 300 ° C. to form an ohmic electrode on the back surface of the Si substrate. Thereafter, an SiO 2 insulating film of 100 nm was deposited on the element surface side by an electron beam deposition method, and the SiO 2 film was partially removed. Further, Pd / Ti / Au (40 nm / 20 nm / 60 nm) was formed by electron beam evaporation as a Schottky electrode by using a photolithography technique and a lift-off method. The chip size was 1 × 1 mm 2 .
When the current-voltage characteristics of the Schottky barrier diode were measured, the rising voltage was 1.4 V, the forward voltage was 2.1 V (@ forward current: 8 A), and the withstand voltage was 850 V.
（実施例３：ｐ−ＧａＮ層を有するＧａＮショットキーバリアダイオード層）
実施例１の構造（図６）および同じプロセスにおいて、ｎ−ＧａＮ層へのＳｉＨ４の流量を０.４ＳＣＣＭとして結晶成長を行った後、素子側において、ＳｉＯ２（膜厚１００ｎｍ）を全面に成膜した。その後、部分的にＳｉＯ２を除去し、ＳｉＯ２膜以外の部分のｎ−ＧａＮ層をＲＩＥ（ＢＣｌ３, １０ＳＣＣＭ、 ３Ｐａ、５Ｗ、１０分）を用いて選択的に０．１μm除去した。その後、ＳｉＯ２膜をマスクとして、膜厚が０.１μmのｐ−ＧａＮ層の選択再成長を行う。そして、ＳｉＯ２膜を除去した後、７５０℃、２０分間、窒素雰囲気中で活性化アニールを行った。その後、実施例２と同様に、Ｓｉ基板の裏面に電子ビーム蒸着法を用いて、ＡｕＳｂ／Ａｕ（２０ｎｍ／１００ｎｍ) 蒸着し、その後３００℃でアニールし、Ｓｉ基板裏面のオーミック電極を形成し、フォトリソグラフィ技術とリフトオフ法を用いてショットキー電極としてＰｄ／Ｔｉ／Ａｕ (４０ｎｍ／２０ｎｍ／６０ｎｍ)を電子ビーム蒸着法により形成した。
当ショットキーバリアダイオードの電流ー電圧特性を測定したところ、立ち上がり電圧：１．４Ｖ、順方向電圧：１.９Ｖ（@順方向電流：８Ａ）、耐圧：９００Ｖであった。
(Example 3: GaN Schottky barrier diode layer having a p-GaN layer)
In the structure of Example 1 (FIG. 6) and the same process, after crystal growth was performed with the flow rate of SiH 4 to the n-GaN layer being 0.4 SCCM, SiO 2 (film thickness 100 nm) was deposited on the entire surface on the device side. A film was formed. Thereafter, SiO 2 was partially removed, and the n-GaN layer other than the SiO 2 film was selectively removed by 0.1 μm using RIE (BCl 3 , 10SCCM, 3Pa, 5W, 10 minutes). Thereafter, selective regrowth of the p-GaN layer having a film thickness of 0.1 μm is performed using the SiO 2 film as a mask. Then, after removing the SiO 2 film, activation annealing was performed in a nitrogen atmosphere at 750 ° C. for 20 minutes. Thereafter, as in Example 2, using an electron beam evaporation method on the back surface of the Si substrate, AuSb / Au (20 nm / 100 nm) is deposited, and then annealed at 300 ° C. to form an ohmic electrode on the back surface of the Si substrate. Pd / Ti / Au (40 nm / 20 nm / 60 nm) was formed by electron beam evaporation as a Schottky electrode by using a photolithography technique and a lift-off method.
When the current-voltage characteristics of the Schottky barrier diode were measured, the rising voltage was 1.4 V, the forward voltage was 1.9 V (@ forward current: 8 A), and the withstand voltage was 900 V.
本発明は、ショットキーバリアダイオードに用いられる。
The present invention is used for a Schottky barrier diode.
Claims (6)
The Schottky barrier diode according to any one of claims 1 to 5, wherein an insulating film or a p-GaN layer is formed on the surface of the laminated structure, and a part thereof overlaps the Schottky electrode.
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