JP2011100772A - Group iii nitride laminated substrate - Google Patents

Group iii nitride laminated substrate Download PDF

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JP2011100772A
JP2011100772A JP2009252982A JP2009252982A JP2011100772A JP 2011100772 A JP2011100772 A JP 2011100772A JP 2009252982 A JP2009252982 A JP 2009252982A JP 2009252982 A JP2009252982 A JP 2009252982A JP 2011100772 A JP2011100772 A JP 2011100772A
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group iii
iii nitride
superlattice laminate
laminate
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JP5334057B2 (en
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Takashi Egawa
孝志 江川
Ryo Sakamoto
陵 坂本
Tsuneo Ito
統夫 伊藤
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Dowa Electronics Materials Co Ltd
Nagoya Institute of Technology NUC
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Nagoya Institute of Technology NUC
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a group III nitride laminated substrate that suppresses the occurrence of cracking and has improved crystallinity. <P>SOLUTION: The group III nitride laminated substrate includes a silicon substrate, a distorted superlattice laminate formed on the silicon substrate, and a group III nitride laminate grown on the distorted superlattice laminate. The distorted superlattice laminate is provided with at least a first superlattice laminate and a second superlattice laminate in order from the side of the silicon substrate, wherein the first superlattice laminate is formed by piling up an AlN layer and a GaN layer alternately, the second superlattice laminate is formed by piling up an AlN layer and an Al<SB>x</SB>Ga<SB>1-x</SB>N(0<x<1) alternately, and the total thickness of the first superlattice laminate exceeds 1 μm. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、III族窒化物積層基板に関し、特に、電子デバイス等に用いられるIII族窒化物積層基板に関する。   The present invention relates to a group III nitride multilayer substrate, and more particularly to a group III nitride multilayer substrate used for electronic devices and the like.

一般に、Al、Ga、InなどのIII族元素と窒素との化合物であるIII族窒化物半導体は、発光素子やHEMT等の電子デバイスに広く用いられている。このようなデバイスの特性は、III族窒化物半導体の結晶性に大きく影響されるため、結晶性の高いIII族窒化物半導体が求められている。   In general, a group III nitride semiconductor, which is a compound of a group III element such as Al, Ga, and In and nitrogen, is widely used in electronic devices such as light emitting elements and HEMTs. Since the characteristics of such a device are greatly influenced by the crystallinity of the group III nitride semiconductor, a group III nitride semiconductor having high crystallinity is required.

III族窒化物半導体の成長用基板としては、サファイアを用いるのが一般的であったが、近年、安価で比較的放熱性が良い等の理由から、シリコン基板を用いる技術が開発されている。このようなシリコン基板は、上記サファイア基板と比較してIII族窒化物半導体との格子定数差が大きいため、結晶性の高いIII族窒化物半導体を得ることは困難であった。   As a substrate for growing a group III nitride semiconductor, sapphire is generally used. However, in recent years, a technique using a silicon substrate has been developed for reasons such as low cost and relatively good heat dissipation. Since such a silicon substrate has a larger lattice constant difference from the group III nitride semiconductor than the sapphire substrate, it is difficult to obtain a group III nitride semiconductor having high crystallinity.

特許文献１には、シリコン基板とIII族窒化物半導体との間にAl組成の低いAlGaN層とAl組成の高いAlGaN層とを交互に積層した超格子積層体を設けることにより、表面が平坦で割れのないIII族窒化物半導体を得る技術が開示されているが、このIII族窒化物半導体の結晶性については、何ら考慮されていなかった。   In Patent Document 1, a superlattice laminate in which an AlGaN layer having a low Al composition and an AlGaN layer having a high Al composition are alternately laminated between a silicon substrate and a group III nitride semiconductor is provided, so that the surface is flat. Although a technique for obtaining a group III nitride semiconductor without cracks has been disclosed, no consideration has been given to the crystallinity of the group III nitride semiconductor.

特開２００７−６７０７７号公報JP 2007-67077 A

本発明の目的は、III族窒化物半導体の割れの発生を抑制し、かつ結晶性の高いIII族窒化物積層基板を提供することにある。   An object of the present invention is to provide a group III nitride laminated substrate that suppresses the occurrence of cracks in a group III nitride semiconductor and has high crystallinity.

上記目的を達成するため、本発明の要旨構成は以下のとおりである。
（１）シリコン基板と、該シリコン基板上に形成した歪超格子積層体と、該歪超格子積層体上に成長したIII族窒化物積層体とを具えるIII族窒化物積層基板であって、
前記歪超格子積層体は、少なくとも前記シリコン基板側から順に第１超格子積層体と第２超格子積層体とを有し、前記第１超格子積層体は、AlN層とGaN層とを交互に積層してなり、前記第２超格子積層体は、AlN層とAlxGa1-xN(0＜x＜1)層とを交互に積層してなり、かつ前記第１超格子積層体の総厚が１μmを超えることを特徴とするIII族窒化物積層基板。 In order to achieve the above object, the gist of the present invention is as follows.
(1) A group III nitride laminated substrate comprising a silicon substrate, a strained superlattice laminate formed on the silicon substrate, and a group III nitride laminate grown on the strained superlattice laminate. ,
The strained superlattice laminate has a first superlattice laminate and a second superlattice laminate in order from at least the silicon substrate side, and the first superlattice laminate has alternating AlN layers and GaN layers. The second superlattice laminate is formed by alternately laminating AlN layers and Al x Ga 1-x N (0 <x <1) layers, and the first superlattice laminate. A group III nitride multilayer substrate characterized by having a total thickness of more than 1 μm.

（２）前記歪超格子積層体は、前記シリコン基板上にバッファ層を介して形成される上記（１）に記載のIII族窒化物積層基板。   (2) The group III nitride laminated substrate according to (1), wherein the strained superlattice laminate is formed on the silicon substrate via a buffer layer.

（３）前記歪超格子積層体は、前記シリコン基板上に直接形成される上記（１）に記載のIII族窒化物積層基板。   (3) The group III nitride multilayer substrate according to (1), wherein the strained superlattice laminate is directly formed on the silicon substrate.

（４）前記第１超格子積層体の前記AlN層および前記GaN層の組数は、50〜120の範囲である上記（１）、（２）または（３）に記載のIII族窒化物積層基板。   (4) The group III nitride laminate according to (1), (2), or (3), wherein the number of sets of the AlN layer and the GaN layer of the first superlattice laminate is in the range of 50 to 120. substrate.

（５）前記第２超格子積層体のAl組成比ｘは、0＜x＜0.4の範囲である上記（１）〜（４）のいずれか一に記載のIII族窒化物積層基板。   (5) The group III nitride multilayer substrate according to any one of (1) to (4), wherein an Al composition ratio x of the second superlattice laminate is in a range of 0 <x <0.4.

（６）前記第２超格子積層体の前記AlN層および前記AlxGa1-xN(0＜ｘ＜1)層の組数は、50〜120の範囲である上記（１）〜（５）のいずれか一に記載のIII族窒化物積層基板。 (6) The number of sets of the AlN layer and the Al x Ga 1-x N (0 <x <1) layer of the second superlattice laminate is in the range of 50 to 120 (1) to (5 3) a group III nitride multilayer substrate according to any one of the above.

本発明によれば、シリコン基板上に適切な歪超格子積層体を設けることにより、その上に積層するIII族窒化物半導体の割れの発生を抑制し、かつ結晶性を向上させることができる。   According to the present invention, by providing an appropriate strained superlattice laminate on a silicon substrate, generation of cracks in a group III nitride semiconductor laminated thereon can be suppressed and crystallinity can be improved.

図１は、本発明に従うIII族窒化物積層基板の実施形態の模式的断面図を示す。FIG. 1 shows a schematic cross-sectional view of an embodiment of a group III nitride multilayer substrate according to the present invention. 図２は、本発明に従うIII族窒化物積層基板の他の実施形態の模式的断面図を示す。FIG. 2 is a schematic cross-sectional view of another embodiment of a group III nitride multilayer substrate according to the present invention. 図３は、本発明に従うIII族窒化物積層基板の他の実施形態の模式的断面図を示す。FIG. 3 is a schematic cross-sectional view of another embodiment of a group III nitride multilayer substrate according to the present invention. 図４は、本発明に従うIII族窒化物積層基板の他の実施形態の模式的断面図を示す。FIG. 4 is a schematic cross-sectional view of another embodiment of a group III nitride multilayer substrate according to the present invention.

次に、本発明のIII族窒化物積層基板の実施形態について図面を参照しながら説明する。図１は、本発明に従うIII族窒化物積層基板の断面構造を模式的に示したものであって、説明の便宜上、厚さ方向が誇張して描かれている。   Next, an embodiment of the group III nitride multilayer substrate of the present invention will be described with reference to the drawings. FIG. 1 schematically shows a cross-sectional structure of a group III nitride laminated substrate according to the present invention, and the thickness direction is exaggerated for convenience of explanation.

本発明に従うIII族窒化物積層基板１００は、一例として図１に示すように、シリコン基板１１０と、このシリコン基板１１０上に形成した歪超格子積層体１２０と、この歪超格子積層体１２０上に成長したIII族窒化物積層体１３０とを具え、歪超格子積層体１２０は、少なくともシリコン基板１１０側から順に第１超格子積層体１２１と第２超格子積層体１２２とを有し、第１超格子積層体１２１は、AlN層１２１ａとGaN層１２１ｂとを交互に積層してなり、第２超格子積層体１２２は、AlN層１２２ａとAlxGa1-xN(0＜x＜1)層１２２ｂとを交互に積層してなり、かつ第１超格子積層体１２１の総厚が１μmを超えることを特徴とし、かかる構成を有することにより、III族窒化物半導体１３０の割れの発生を抑制し、かつ結晶性を向上させることができるものである。 As shown in FIG. 1 as an example, a group III nitride laminated substrate 100 according to the present invention includes a silicon substrate 110, a strained superlattice laminate 120 formed on the silicon substrate 110, and the strained superlattice laminate 120. The strained superlattice laminate 120 includes a first superlattice laminate 121 and a second superlattice laminate 122 in order from at least the silicon substrate 110 side. The first superlattice laminate 121 is formed by alternately laminating AlN layers 121a and GaN layers 121b, and the second superlattice laminate 122 is composed of AlN layers 122a and Al x Ga 1-x N (0 <x <1 ) Layers 122b are alternately stacked, and the total thickness of the first superlattice laminate 121 exceeds 1 μm. With this configuration, the group III nitride semiconductor 130 can be prevented from cracking. To suppress and improve crystallinity. Is shall.

ここで、III族窒化物半導体１３０の結晶性とは、III族窒化物半導体１３０の特定の結晶面のＸ線ロッキングカーブの半値幅で評価されるものとする。特に、III族窒化物半導体１３０がGaN層の場合には、Ｃ軸方向のずれとらせん転位密度を(0004)面のロッキングカーブで評価し、Ａ軸方向のずれと刃状転位密度を(20-24)面のロッキングカーブで評価する。   Here, the crystallinity of the group III nitride semiconductor 130 is evaluated by the half-value width of the X-ray rocking curve of a specific crystal plane of the group III nitride semiconductor 130. In particular, when the group III nitride semiconductor 130 is a GaN layer, the deviation in the C-axis direction and the screw dislocation density are evaluated by a rocking curve on the (0004) plane, and the deviation in the A-axis direction and the edge dislocation density are (20 -24) Evaluate with surface rocking curve.

HEMT等の縦方向に電流を流さないデバイスに対して、歪超格子積層体１２０は、一例として図２に示すように、シリコン基板１１０上にバッファ層１４０を介して形成することができる。シリコン基板上でIII族窒化物半導体層の結晶核生成とその後の平滑なエピタキシャル成長をしやすくするためである。このバッファ層１４０は、例えばAlN層、またはこのAlN層上にAlyGa1-yN(0＜y＜1)層を形成したものとすることができる。これはAlN層がGaとSiの反応を抑制し、いわゆるメルトバックエッチングを抑えやすくし、かつAlN層成長時の凹凸を、その上に形成したAlyGa1-yN(0＜y＜1)層により平滑にするためである。また、上記AlN層の厚さは、５〜200nmの範囲であるのが好ましく、上記AlyGa1-yN層の厚さは100nm以下とするのが好ましい。上記AlN層の厚さが５nm未満だと、上記メルトバックエッチングを引き起こし多結晶化するなど、デバイスの作製に供するには不適切な状態となるおそれがあり、上記AlN層の厚さが200nm超えおよび／または上記AlyGa1-yN層の厚さが100nmを超えると、反りが大きくなったり割れが発生しやすくなったりするおそれがあるためである。 As an example, the strained superlattice laminate 120 can be formed on a silicon substrate 110 via a buffer layer 140 as shown in FIG. This is to facilitate crystal nucleation of the group III nitride semiconductor layer and subsequent smooth epitaxial growth on the silicon substrate. The buffer layer 140 may be, for example, an AlN layer or an Al y Ga 1-y N (0 <y <1) layer formed on the AlN layer. This suppresses the reaction AlN layer is Ga and Si, and easy to suppress a so-called melt-back etching, and Al y Ga 1-y N ( 0 to irregularities during AlN layer grown was formed thereon <y <1 ) To make the layer smoother. The thickness of the AlN layer is preferably in the range of 5 to 200 nm, and the thickness of the Al y Ga 1-y N layer is preferably 100 nm or less. If the thickness of the AlN layer is less than 5 nm, there is a possibility that it will be in an inappropriate state for use in device fabrication, such as causing the melt-back etching and polycrystallizing, and the thickness of the AlN layer exceeds 200 nm. This is because if the thickness of the Al y Ga 1-y N layer exceeds 100 nm, warping may increase or cracks may easily occur.

これに対し、縦方向に電流を流すデバイスに対しては、歪超格子積層体１２０は、シリコン基板１１０上に直接形成することもできる。この場合、成長面に対して垂直方向に余計な抵抗が入らないため、電流降下を抑制することができる。ただし、この場合の第1超格子積層体１２１の最初の層はAlN層１２１ａとする。   On the other hand, the strained superlattice laminate 120 can be directly formed on the silicon substrate 110 for a device that allows current to flow in the vertical direction. In this case, since no extra resistance enters in the direction perpendicular to the growth surface, a current drop can be suppressed. However, the first layer of the first superlattice laminate 121 in this case is the AlN layer 121a.

III族窒化物積層体１３０に割れが発生するのを抑制するため、第１超格子積層体１２１の総厚は１μｍより大きく、第１超格子積層体１２１のAlN層１２１ａおよびGaN層１２１ｂの組数は、50〜120の範囲であるのが好ましい。組数が50未満だと、割れが発生したりIII族窒化物積層体１３０の結晶性が悪化するおそれがあり、組数が120を超えると、積層体中の応力が大きくなることで反りが大きくなったり割れが発生するおそれがあるためである。また、上記AlN層１２１ａの各々の厚さは４〜６nmの範囲であるのがより好ましく、GaN層１２１ｂの各々の厚さは17〜25nmの範囲であるのがより好ましい。上記AlN層１２１ａの厚さが４nm未満および／または上記GaN層１２１ｂの厚さが17nm未満だと、積層体中の応力を十分緩和出来ないことにより転位密度の増大、すなわち結晶性の悪化となるおそれがあり、上記AlN層１２１ａの厚さが６nm超えおよび／または上記GaN層１２１ｂの厚さが25nmを超えると、やはり積層体中の応力を十分緩和出来ずに反りが大きくなったり、積層体中に割れが入ったりするおそれがあるためである。   In order to suppress the occurrence of cracks in group III nitride laminate 130, the total thickness of first superlattice laminate 121 is greater than 1 μm, and the combination of AlN layer 121a and GaN layer 121b of first superlattice laminate 121 The number is preferably in the range of 50-120. If the number of sets is less than 50, cracks may occur or the crystallinity of the group III nitride laminate 130 may be deteriorated. If the number of sets exceeds 120, the stress in the laminate increases and warping occurs. This is because there is a risk that it will become large or crack. The thickness of each of the AlN layers 121a is more preferably in the range of 4 to 6 nm, and the thickness of each of the GaN layers 121b is more preferably in the range of 17 to 25 nm. If the thickness of the AlN layer 121a is less than 4 nm and / or the thickness of the GaN layer 121b is less than 17 nm, the stress in the laminate cannot be sufficiently relaxed, resulting in an increase in dislocation density, that is, a deterioration in crystallinity. If the thickness of the AlN layer 121a exceeds 6 nm and / or the thickness of the GaN layer 121b exceeds 25 nm, the stress in the stacked body cannot be sufficiently relaxed, and warping increases. This is because there is a risk of cracks inside.

また、III族窒化物積層体１３０に割れが発生するのを抑制するため、第２超格子積層体１２２のAl組成比ｘは、0＜x＜0.4の範囲であるのが好ましく、0.05＜ｘ＜0.4の範囲であるのがより好ましい。Al組成比ｘが０だと第１超格子積層を適性組数以上積んだ場合と同じく、積層体中の応力が大きくなることで反りが大きくなったり割れが発生したりするおそれがあり、Al組成比ｘが0.4を超えるとやはり結晶性の悪化、反り増大につながるおそれがあるためである。   In order to suppress the occurrence of cracks in the group III nitride laminate 130, the Al composition ratio x of the second superlattice laminate 122 is preferably in the range of 0 <x <0.4, and 0.05 <x A range of <0.4 is more preferable. If the Al composition ratio x is 0, as in the case where the first superlattice laminate is stacked in an appropriate number or more, the stress in the laminate increases, and there is a risk that warpage will increase or cracks will occur. This is because if the composition ratio x exceeds 0.4, the crystallinity may deteriorate and the warpage may increase.

さらに、III族窒化物積層体１３０に割れが発生するのを抑制するため、第２超格子積層体１２２のAlN層１２２ａおよびAlxGa1-xN(0＜x＜1)層１２２ｂの組数は、50〜120の範囲であるのが好ましい。組数が50未満だと、積層体中の応力を十分緩和出来ないことにより転位密度の増大、すなわち結晶性の悪化となるおそれがあり、組数が120を超えると、やはり積層体中の応力を十分緩和出来ずに反りが大きくなったり、積層体中に割れが入ったりするおそれがあるためである。また、AlN層１２２ａの各々の厚さは５〜15nmの範囲であるのがより好ましく、AlxGa1-xN(0＜x＜1)層１２２ｂの厚さは20〜40nmの範囲であるのがより好ましい。上記AlN層１２２ａの厚さが５nm未満および／または上記AlxGa1-xN(0＜x＜1)層１２２ｂの厚さが20nm未満だと、積層体中の応力を十分緩和出来ないことにより転位密度の増大、すなわち結晶性の悪化となるおそれがあり、上記AlN層１２２ａの厚さが15nm超えおよび／または上記AlxGa1-xN(0＜x＜1)層１２２ｂの厚さが40nmを超えると、やはり積層体中の応力を十分緩和出来ずに反りが大きくなったり、積層体中に割れが入ったりするおそれがあるためである。
上記の第１超格子積層体１２１および第２超格子積層体１２２の構成により、シリコン基板１１０とIII族窒化物積層体１３０との間の格子定数差、熱膨張係数差により積層内に発生する応力を、歪超格子積層体１２０で緩和し、転位の発生・増殖を抑えることにより、結晶性を向上させことができる。 Further, in order to suppress the generation of cracks in the group III nitride laminate 130, a set of the AlN layer 122a and the Al x Ga 1-x N (0 <x <1) layer 122b of the second superlattice laminate 122 is provided. The number is preferably in the range of 50-120. If the number of pairs is less than 50, the stress in the laminate cannot be sufficiently relaxed, which may increase the dislocation density, that is, deteriorate the crystallinity. If the number of pairs exceeds 120, the stress in the laminate will again. This is because there is a possibility that warpage may increase without sufficient relaxation, and cracks may occur in the laminate. The thickness of each AlN layer 122a is more preferably in the range of 5 to 15 nm, and the thickness of the Al x Ga 1-x N (0 <x <1) layer 122b is in the range of 20 to 40 nm. Is more preferable. When the thickness of the AlN layer 122a is less than 5 nm and / or the thickness of the Al x Ga 1-x N (0 <x <1) layer 122b is less than 20 nm, the stress in the laminate cannot be sufficiently relaxed. May increase the dislocation density, that is, the crystallinity, and the thickness of the AlN layer 122a may exceed 15 nm and / or the thickness of the Al x Ga 1-x N (0 <x <1) layer 122b. This is because if the thickness exceeds 40 nm, the stress in the laminate cannot be sufficiently relaxed and warping may increase, or cracks may occur in the laminate.
Due to the configuration of the first superlattice laminate 121 and the second superlattice laminate 122 described above, a lattice constant difference and a thermal expansion coefficient difference between the silicon substrate 110 and the group III nitride laminate 130 are generated in the laminate. The crystallinity can be improved by relaxing the stress by the strained superlattice laminate 120 and suppressing the occurrence and proliferation of dislocations.

シリコン基板１１０は、用途に応じて適宜選択することができるが、GaN系の場合、GaNの高温安定層は六方晶であり、両者の格子定数からみた適合性という点で、(111)面を使用するのがより好ましい。   The silicon substrate 110 can be appropriately selected according to the application, but in the case of GaN, the high temperature stable layer of GaN is a hexagonal crystal, and the (111) plane is in view of compatibility from the viewpoint of both lattice constants. More preferably it is used.

また、上記第１超格子積層体１２１の総厚は、３μm以下であるのが好ましい。総厚が３μmを超えると、積層体中の応力を十分緩和出来ずに、III族窒化物積層体１３０に割れが発生するおそれがあるためである。   The total thickness of the first superlattice laminate 121 is preferably 3 μm or less. This is because if the total thickness exceeds 3 μm, the stress in the laminate cannot be sufficiently relaxed, and the group III nitride laminate 130 may be cracked.

歪超格子積層体１２０上に成長されるIII族窒化物積層体１３０は、GaN層であるのが好ましく、AlGaN層とすることもできる。このIII族窒化物積層体１３０の厚さは、0.25〜2.0μmの範囲であるのが好ましい。   The group III nitride laminate 130 grown on the strained superlattice laminate 120 is preferably a GaN layer, and may be an AlGaN layer. The thickness of the group III nitride laminate 130 is preferably in the range of 0.25 to 2.0 μm.

なお、III族窒化物積層体１３０は、図１および図２に示したように単層でもよく、また、図には示されないが、複数のIII族窒化物層を積層した積層体としてもよい。例えばGaN層の上にAlGaN層を設けた構成とすることができる。   The group III nitride laminated body 130 may be a single layer as shown in FIGS. 1 and 2, or may be a laminated body in which a plurality of group III nitride layers are laminated, although not shown in the drawings. . For example, an AlGaN layer may be provided on the GaN layer.

なお、図１および図２は、代表的な実施形態の例を示したものであって、本発明はこの実施形態に限定されるものではない。例えば、各層の間に本発明の効果に悪影響を与えない程度の中間層を挿入したり、他の超格子層を挿入したり、組成に傾斜をつけたりすることもできる。また、基盤の表面に、窒化膜、炭化膜、Al層などを形成することもできる。   1 and 2 show examples of typical embodiments, and the present invention is not limited to these embodiments. For example, an intermediate layer that does not adversely affect the effects of the present invention can be inserted between the layers, another superlattice layer can be inserted, or the composition can be inclined. Further, a nitride film, a carbide film, an Al layer, or the like can be formed on the surface of the substrate.

（実施例１）
図２に示すように、４インチのシリコン単結晶基板１１０(厚さ:625μm)の(111)面上に、MOCVD法を用いて、バッファ層１４０としてAlN層(厚さ:100nm)およびAl0.3Ga0.7N層(厚さ:３μm)を形成し、歪超格子積層体１２０として、第１超格子積層体１２１(AlN層,厚さ:５nmおよびGaN層,厚さ:20nmを120組、総厚:３μm)および第２超格子積層体１２２(AlN層,厚さ:10nmおよびAl0.15Ga0.85N層,厚さ:30nmを75組、総厚:３μm)を順に形成し、その上に、III族窒化物積層体としてGaN層１３０(厚さ:１μm)を形成してIII族窒化物積層基板１００を作製した。 Example 1
As shown in FIG. 2, an AlN layer (thickness: 100 nm) and Al 0.3 are formed as a buffer layer 140 on a (111) surface of a 4-inch silicon single crystal substrate 110 (thickness: 625 μm) by using MOCVD. Ga 0.7 N layer (thickness: 3 μm) is formed, and the first superlattice laminate 121 (AlN layer, thickness: 5 nm and GaN layer, thickness: 20 nm, 120 pairs, total is formed as the strained superlattice laminate 120 (Thickness: 3 μm) and the second superlattice laminate 122 (AlN layer, thickness: 10 nm and Al 0.15 Ga 0.85 N layer, thickness: 30 nm, 75 pairs, total thickness: 3 μm) are formed in order, A GaN layer 130 (thickness: 1 μm) was formed as a group III nitride multilayer body to produce a group III nitride multilayer substrate 100.

（実施例２）
上記バッファ層１４０を形成しないこと以外は、実施例１と同様の方法によりIII族窒化物積層基板１００を作製した。 (Example 2)
A group III nitride multilayer substrate 100 was produced in the same manner as in Example 1 except that the buffer layer 140 was not formed.

（比較例１）
歪超格子積層体１２０として、第２超格子積層体 (AlN層,厚さ:10nmおよびAl0.15Ga0.85N層,厚さ:30nmを75組、総厚:３μm)および第１超格子積層体 (AlN層,厚さ:５nmおよびGaN層,厚さ:20nmを120組、総厚:３μm)を順に形成したこと以外は、実施例１と同様の方法によりIII族窒化物積層基板を作製した。 (Comparative Example 1)
As the strained superlattice laminate 120, a second superlattice laminate (AlN layer, thickness: 10 nm and Al 0.15 Ga 0.85 N layer, thickness: 30 nm, 75 pairs, total thickness: 3 μm) and the first superlattice laminate A group III nitride multilayer substrate was produced in the same manner as in Example 1 except that (AlN layer, thickness: 5 nm and GaN layer, thickness: 120 pairs of 20 nm, total thickness: 3 μm) were formed in order. .

（比較例２）
歪超格子積層体１２０として、第１超格子積層体１２１(AlN層,厚さ:５nmおよびGaN層,厚さ:20nmを40組、総厚:１μm)および第２超格子積層体１２２(AlN層,厚さ:10nmおよびAl0.15Ga0.85N層,厚さ:30nmを125組、総厚:５μm)を順に形成したこと以外は、実施例１と同様の方法によりIII族窒化物積層基板１００を作製した。 (Comparative Example 2)
As the strained superlattice laminate 120, a first superlattice laminate 121 (AlN layer, thickness: 5 nm and GaN layer, thickness: 40 nm, 40 pairs, total thickness: 1 μm) and second superlattice laminate 122 (AlN Layer, thickness: 10 nm and Al 0.15 Ga 0.85 N layer, thickness: 30 nm, 125 pairs, total thickness: 5 μm) were formed in that order in the same manner as in Example 1 to form a group III nitride multilayer substrate 100 Was made.

（比較例３）
歪超格子積層体１２０として、第２超格子積層体１２２(AlN層,厚さ:10nmおよびAl0.15Ga0.85N層,厚さ:30nmを125組、総厚:５μm)および第１超格子積層体１２１(AlN層,厚さ:5nmおよびGaN層,厚さ:20nmを40組、総厚:１μm)を順に形成したこと以外は、実施例１と同様の方法によりIII族窒化物積層基板を作製した。 (Comparative Example 3)
As the strained superlattice laminate 120, the second superlattice laminate 122 (AlN layer, thickness: 10 nm and Al 0.15 Ga 0.85 N layer, thickness: 125 nm, 125 pairs, total thickness: 5 μm) and the first superlattice laminate A group III nitride multilayer substrate was formed in the same manner as in Example 1 except that the body 121 (AlN layer, thickness: 5 nm and GaN layer, thickness: 40 nm, 40 pairs, total thickness: 1 μm) was formed in order. Produced.

（比較例４）
歪超格子積層体１２０として、第２超格子積層体(AlN層,厚さ:５nmおよびAl0.15Ga0.85N層,厚さ:20nmを240組、総厚:６μm)を形成したこと以外は、実施例１と同様の方法によりIII族窒化物積層基板を作製した。 (Comparative Example 4)
Except for forming a second superlattice laminate (AlN layer, thickness: 5 nm and Al 0.15 Ga 0.85 N layer, thickness: 240 pairs, total thickness: 6 μm) as the strained superlattice laminate 120, A group III nitride laminated substrate was produced in the same manner as in Example 1.

（結晶性評価）
上記実施例１〜２および比較例１〜４について、Ｘ線回折装置(フィリップス社製、X’Peart-MRD)を用い、歪超格子積層体上に形成したGaN層の(0004)面および(20-24)面のＸ線ロッキングカーブを測定した。結果を表１に示す。 (Crystallinity evaluation)
With respect to Examples 1 to 2 and Comparative Examples 1 to 4, the (0004) plane of the GaN layer formed on the strained superlattice laminate using an X-ray diffraction apparatus (manufactured by Philips, X'Peart-MRD) and ( The X-ray rocking curve of the 20-24) plane was measured. The results are shown in Table 1.

Figure 2011100772
Figure 2011100772

表１から、本発明に従う実施例１および実施例２は、（20-24）面の半値幅の値が小さく、結晶性がよいことがわかり、また、割れの発生もないことがわかる。一方、比較例２は、半値幅の値は小さく、結晶性は良いものの、割れが発生してしまっていることがわかる。   From Table 1, it can be seen that in Examples 1 and 2 according to the present invention, the value of the half width of the (20-24) plane is small, the crystallinity is good, and there is no occurrence of cracks. On the other hand, Comparative Example 2 has a small half-value width and good crystallinity, but it can be seen that cracking has occurred.

（評価２）
図３および図４にそれぞれ示すように、上記実施例１および実施例２について、歪超格子積層体２２０上に、ｎ型GaN層２３１、活性層２３２、ｐ型AlGaN層２３３およびｐ型GaN層２３４を形成し、これらを一対の電極２５０ａ，２５０ｂで挟んだ発光素子を作製し、垂直方向の電流-電圧特性を調べた。 (Evaluation 2)
As shown in FIG. 3 and FIG. 4, for Example 1 and Example 2 above, on the strained superlattice laminate 220, an n-type GaN layer 231, an active layer 232, a p-type AlGaN layer 233, and a p-type GaN layer. A light emitting element in which 234 is formed and sandwiched between the pair of electrodes 250a and 250b is manufactured, and current-voltage characteristics in the vertical direction are examined.

実施例１では、注入電流:20mAでの動作電圧が7.0Ｖ、直列抵抗が100Ωであったが、実施例２では、動作電圧が4.0Ｖ、直列抵抗が30Ωとなり、実施例１に比べて実施例２では動作電圧および直列抵抗を低減することができ、電圧ドロップを抑制できることが分かる。   In Example 1, the operating voltage at an injection current of 20 mA was 7.0 V and the series resistance was 100Ω, but in Example 2, the operating voltage was 4.0 V and the series resistance was 30Ω, which was implemented as compared to Example 1. In Example 2, it can be seen that the operating voltage and series resistance can be reduced, and voltage drop can be suppressed.

本発明によれば、シリコン基板上に適切な歪超格子積層体を設けることにより、その上に積層するIII族窒化物半導体の割れの発生を抑制し、かつ結晶性を向上させることができる。   According to the present invention, by providing an appropriate strained superlattice laminate on a silicon substrate, generation of cracks in a group III nitride semiconductor laminated thereon can be suppressed and crystallinity can be improved.

１００ III族窒化物積層基板
１１０ シリコン基板
１２０ 歪超格子積層体
１２１ 第１超格子積層体
１２２ 第２超格子積層体
１３０ III族窒化物半導体 100 Group III nitride laminated substrate 110 Silicon substrate 120 Strained superlattice laminated body 121 First superlattice laminated body 122 Second superlattice laminated body 130 Group III nitride semiconductor

Claims (6)

シリコン基板と、該シリコン基板上に形成した歪超格子積層体と、該歪超格子積層体上に成長したIII族窒化物積層体とを具えるIII族窒化物積層基板であって、
前記歪超格子積層体は、少なくとも前記シリコン基板側から順に第１超格子積層体と第２超格子積層体とを有し、
前記第１超格子積層体は、AlN層とGaN層とを交互に積層してなり、
前記第２超格子積層体は、AlN層とAlxGa1-xN(0＜x＜1)層とを交互に積層してなり、かつ
前記第１超格子積層体の総厚が１μmを超えることを特徴とするIII族窒化物積層基板。 A group III nitride laminated substrate comprising a silicon substrate, a strained superlattice laminate formed on the silicon substrate, and a group III nitride laminate grown on the strained superlattice laminate,
The strained superlattice laminate includes a first superlattice laminate and a second superlattice laminate in order from at least the silicon substrate side,
The first superlattice laminate is formed by alternately laminating AlN layers and GaN layers,
The second superlattice laminate is formed by alternately laminating AlN layers and Al x Ga 1-x N (0 <x <1) layers, and the total thickness of the first superlattice laminate is 1 μm. A group III nitride laminated substrate characterized by exceeding. 前記歪超格子積層体は、前記シリコン基板上に、バッファ層を介して形成される請求項１に記載のIII族窒化物積層基板。   The group III nitride multilayer substrate according to claim 1, wherein the strained superlattice multilayer body is formed on the silicon substrate via a buffer layer. 前記歪超格子積層体は、前記シリコン基板上に、直接形成される請求項１に記載のIII族窒化物積層基板。   The group III nitride multilayer substrate according to claim 1, wherein the strained superlattice laminate is directly formed on the silicon substrate. 前記第１超格子積層体のAlN層およびGaN層の組数は、50〜120の範囲である請求項１、２または３に記載のIII族窒化物積層基板。   4. The group III nitride multilayer substrate according to claim 1, wherein the number of sets of AlN layers and GaN layers in the first superlattice laminate is in the range of 50 to 120. 5. 前記第２超格子積層体のAl組成比ｘは、0＜x＜0.4の範囲である請求項１〜４のいずれか一項に記載のIII族窒化物積層基板。   The group III nitride multilayer substrate according to any one of claims 1 to 4, wherein an Al composition ratio x of the second superlattice laminate is in a range of 0 <x <0.4. 前記第２超格子積層体のAlN層およびAlxGa1-xN(0＜x＜1)層の組数は、50〜120の範囲である請求項１〜５のいずれか一項に記載のIII族窒化物積層基板。 6. The number of sets of the AlN layer and the Al x Ga 1-x N (0 <x <1) layer of the second superlattice laminate is in a range of 50 to 120. 6. Group III nitride laminated substrate.
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Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013074211A (en) * 2011-09-28 2013-04-22 Fujitsu Ltd Semiconductor device
JP2013084957A (en) * 2012-10-05 2013-05-09 Toshiba Corp Semiconductor light-emitting element
JP2013128103A (en) * 2011-11-17 2013-06-27 Sanken Electric Co Ltd Nitride semiconductor device and nitride semiconductor device manufacturing method
JP2013165261A (en) * 2012-01-13 2013-08-22 Dowa Electronics Materials Co Ltd Group iii nitride epitaxial substrate and deep ultraviolet light emitting element including the same
WO2013137476A1 (en) * 2012-03-16 2013-09-19 次世代パワーデバイス技術研究組合 Semiconductor multi-layer substrate, semiconductor element, and production method therefor
JP2014022685A (en) * 2012-07-23 2014-02-03 Nagoya Institute Of Technology Semiconductor laminate structure and semiconductor element using the same
WO2014046527A1 (en) * 2012-09-24 2014-03-27 엘지이노텍 주식회사 Light-emitting element
JP5462377B1 (en) * 2013-01-04 2014-04-02 Ｄｏｗａエレクトロニクス株式会社 Group III nitride epitaxial substrate and manufacturing method thereof
JP2016100508A (en) * 2014-11-25 2016-05-30 サンケン電気株式会社 Epitaxial wafer, semiconductor element, method for manufacturing epitaxial wafer, and method for manufacturing semiconductor element
JP2016149410A (en) * 2015-02-10 2016-08-18 Ｄｏｗａエレクトロニクス株式会社 Epitaxial substrate for electronic device and high electron mobility transistor, and methods of manufacturing them
JP2019208022A (en) * 2018-05-28 2019-12-05 アイメック・ヴェーゼットウェーＩｍｅｃ Ｖｚｗ Iii-n semiconductor structure and formation method of iii-n semiconductor structure

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004048076A (en) * 2003-10-30 2004-02-12 Sanyo Electric Co Ltd Semiconductor element and its manufacturing method
JP2004349387A (en) * 2003-05-21 2004-12-09 Sanken Electric Co Ltd Semiconductor substrate and its manufacturing method
JP2005235911A (en) * 2004-02-18 2005-09-02 Osaka Gas Co Ltd GaN-BASED COMPOUND SEMICONDUCTOR LIGHT RECEIVING ELEMENT
JP2007067077A (en) * 2005-08-30 2007-03-15 Nippon Telegr & Teleph Corp <Ntt> Nitride semiconductor device and method of manufacturing same
JP2007142397A (en) * 2005-11-14 2007-06-07 Palo Alto Research Center Inc Superlattice strain relief layer for semiconductor device
JP2007258230A (en) * 2006-03-20 2007-10-04 Dowa Holdings Co Ltd Semiconductor substrate and semiconductor device
JP2008205117A (en) * 2007-02-19 2008-09-04 Sanken Electric Co Ltd Semiconductor wafer, semiconductor element, and manufacturing method
JP2008251704A (en) * 2007-03-29 2008-10-16 Furukawa Electric Co Ltd:The Silicon board and manufacturing method therefor
WO2009084431A1 (en) * 2007-12-27 2009-07-09 Dowa Electronics Materials Co., Ltd. Semiconductor material, method for manufacturing semiconductor material, and semiconductor element
JP2010251738A (en) * 2009-03-27 2010-11-04 Covalent Materials Corp Nitride semiconductor epitaxial substrate

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004349387A (en) * 2003-05-21 2004-12-09 Sanken Electric Co Ltd Semiconductor substrate and its manufacturing method
JP2004048076A (en) * 2003-10-30 2004-02-12 Sanyo Electric Co Ltd Semiconductor element and its manufacturing method
JP2005235911A (en) * 2004-02-18 2005-09-02 Osaka Gas Co Ltd GaN-BASED COMPOUND SEMICONDUCTOR LIGHT RECEIVING ELEMENT
JP2007067077A (en) * 2005-08-30 2007-03-15 Nippon Telegr & Teleph Corp <Ntt> Nitride semiconductor device and method of manufacturing same
JP2007142397A (en) * 2005-11-14 2007-06-07 Palo Alto Research Center Inc Superlattice strain relief layer for semiconductor device
JP2007258230A (en) * 2006-03-20 2007-10-04 Dowa Holdings Co Ltd Semiconductor substrate and semiconductor device
JP2008205117A (en) * 2007-02-19 2008-09-04 Sanken Electric Co Ltd Semiconductor wafer, semiconductor element, and manufacturing method
JP2008251704A (en) * 2007-03-29 2008-10-16 Furukawa Electric Co Ltd:The Silicon board and manufacturing method therefor
WO2009084431A1 (en) * 2007-12-27 2009-07-09 Dowa Electronics Materials Co., Ltd. Semiconductor material, method for manufacturing semiconductor material, and semiconductor element
JP2010251738A (en) * 2009-03-27 2010-11-04 Covalent Materials Corp Nitride semiconductor epitaxial substrate

Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013074211A (en) * 2011-09-28 2013-04-22 Fujitsu Ltd Semiconductor device
JP2013128103A (en) * 2011-11-17 2013-06-27 Sanken Electric Co Ltd Nitride semiconductor device and nitride semiconductor device manufacturing method
JP2013165261A (en) * 2012-01-13 2013-08-22 Dowa Electronics Materials Co Ltd Group iii nitride epitaxial substrate and deep ultraviolet light emitting element including the same
US9653589B2 (en) 2012-03-16 2017-05-16 Furukawa Electric Co., Ltd. Semiconductor multi-layer substrate, semiconductor device, and method for manufacturing the same
WO2013137476A1 (en) * 2012-03-16 2013-09-19 次世代パワーデバイス技術研究組合 Semiconductor multi-layer substrate, semiconductor element, and production method therefor
JPWO2013137476A1 (en) * 2012-03-16 2015-08-03 古河電気工業株式会社 Semiconductor laminated substrate, semiconductor element, and manufacturing method thereof
JP2014022685A (en) * 2012-07-23 2014-02-03 Nagoya Institute Of Technology Semiconductor laminate structure and semiconductor element using the same
CN104662676A (en) * 2012-09-24 2015-05-27 Lg伊诺特有限公司 Light-emitting element
WO2014046527A1 (en) * 2012-09-24 2014-03-27 엘지이노텍 주식회사 Light-emitting element
US9312433B2 (en) 2012-09-24 2016-04-12 Lg Innotek Co., Ltd. Light emitting element
JP2013084957A (en) * 2012-10-05 2013-05-09 Toshiba Corp Semiconductor light-emitting element
JP5462377B1 (en) * 2013-01-04 2014-04-02 Ｄｏｗａエレクトロニクス株式会社 Group III nitride epitaxial substrate and manufacturing method thereof
CN104885198A (en) * 2013-01-04 2015-09-02 同和电子科技有限公司 Group-iii nitride epitaxial substrate and method for producing same
JP2014132607A (en) * 2013-01-04 2014-07-17 Dowa Electronics Materials Co Ltd Group iii nitride epitaxial substrate and manufacturing method of the same
WO2014106875A1 (en) * 2013-01-04 2014-07-10 Ｄｏｗａエレクトロニクス株式会社 Group-iii nitride epitaxial substrate and method for producing same
JP2016100508A (en) * 2014-11-25 2016-05-30 サンケン電気株式会社 Epitaxial wafer, semiconductor element, method for manufacturing epitaxial wafer, and method for manufacturing semiconductor element
WO2016084311A1 (en) * 2014-11-25 2016-06-02 サンケン電気株式会社 Epitaxial wafer, semiconductor element, epitaxial wafer manufacturing method, and semiconductor element manufacturing method
CN107004579A (en) * 2014-11-25 2017-08-01 三垦电气株式会社 Epitaxial wafer, semiconductor element, the manufacture method of the manufacture method of epitaxial wafer and semiconductor element
JP2016149410A (en) * 2015-02-10 2016-08-18 Ｄｏｗａエレクトロニクス株式会社 Epitaxial substrate for electronic device and high electron mobility transistor, and methods of manufacturing them
JP2019208022A (en) * 2018-05-28 2019-12-05 アイメック・ヴェーゼットウェーＩｍｅｃ Ｖｚｗ Iii-n semiconductor structure and formation method of iii-n semiconductor structure
JP7216615B2 (en) 2018-05-28 2023-02-01 アイメック・ヴェーゼットウェー III-N semiconductor structures and methods of forming III-N semiconductor structures

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